Z80L183AZ020SCRXXXX [ZILOG]
Microcontroller, CMOS, PQFP100, PLASTIC, VQFP-100;
| 型号： | Z80L183AZ020SCRXXXX |
| 厂家： | 
ZILOG, INC. |
| 描述： | Microcontroller, CMOS, PQFP100, PLASTIC, VQFP-100 微控制器 外围集成电路 |
| 文件： | 总170页 (文件大小：1095K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z80S183/Z80L183
GENERAL-PURPOSE INTEGRATED MICROPROCESSOR
PRELIMINARY
PRODUCT SPECIFICATION
PS000501-XMP1299
ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAMILTON AVENUE • CAMPBELL, CA 95008
TELEPHONE: 408.558.8500 • FAX: 408.558.8300 • INTERNET: HTTP://WWW.ZILOG.COM
%
ꢀ2
ꢀ5
ꢀ
<K.1)ꢁ#WVJQTK\GFꢁ&KUVTKDWVKQPꢁ1PN[ꢂ&Qꢁ0QVꢁ&WRNKECVG 25ꢃꢃꢃꢄꢃꢅꢂ:/2ꢅꢀꢆꢆ
Z80S183/Z80L183 PRODUCT SPECIFICATION
DOCUMENT CONVENTIONS
&1%7/'06ꢀ#557/26+105ꢀ#0&ꢀ%108'06+105
The following assumptions and conventions have been adopted to provide clarity and ease
of use:
Use of the Words Set and Clear
The words set and clear imply that a register bit or a condition has the value of logical
1 and logical 0 respectively. When the terms set and clear are followed by a number,
often in parentheses, the word logical may not be included, but it is implied.
Notation for Bits and Similar Registers
A field of bits within a register are designated as: Register (n..n). For example:
PWM_CR (31..20). A field of bits within a bus are designated as: Bus . For example:
PCntl . A range of similar (whole) registers is designated as: Registern..Registern.
For example: OPBCS5..OPBCS0.
Use of the Terms LSB and MSB
In this document, the terms LSB and MSB mean least significant bit and most signifi-
cant bit respectively.
Courier Font
Commands, code lines and fragments, register and other mnemonics, values, equations,
and various executable items are distinguished from general text by the use of the
Courier font. This convention is not used within tables. Where the use of the font is not
possible, as in the Index, the name of the entity is capitalized. For example: The STP
bit in the CNTRregister must be 1.
Hexadecimal Values Designated by H
Hexadecimal values are designated by an upper-case letter H as well as the use of
Courier font. For example: STATis set to F8H.
Use of All Upper-Case Letters
The use of all upper-case letters designates the names of states and commands. For
example: The receiver can force the SCL line to Low for force the transmitter into a
WAIT state. The bus is considered BUSY after the Start condition. A STARTcommand
triggers the processing of the initialization sequence.
Use of Initial Upper-Case Letters
Initial upper-case letters designate settings, modes, and conditions in general text. For
example: The Slave receiver leaves the data line High. In Transmit mode, the byte is sent
most significant bit first. The Master can generate a Stop condition to abort the transfer.
PS002500-DSP1099
iii
Z80S183/Z80L183 PRODUCT SPECIFICATION
Register Access Abbreviations
Register access is designation by the following abbreviations:
Designation
Description
R
Read Only
R/W
W
Read/Write
Write Only
–
Unspecified or indeterminate
Use of Fewer Bits Than in a Register Field
When a register field is comprised of multiple bits, a value for the field may be stated
as a single number. For example: The reset value for an 8-bit field may be described as
0when the register contains 8 bits that each have the value 0.
24'%*#4#%6'4+<#6+10ꢀ241&7%6
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what ZiLOG
knows about this product at this time, but additional features or non-conformance with
some aspects of the document may be found, either by ZiLOG or its customers in the
course of further application and characterization work. In addition, ZiLOG cautions that
delivery may be uncertain at times, due to start-up yield issues.
%12;4+)*6ꢀ#0&ꢀ&+5%.#+/'4
©2000 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the
devices, applications, or technology described is intended to suggest possible uses and may
be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A
REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECH-
NOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME
LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY
MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not
authorized. No licenses are conveyed, implicitly or otherwise, by this document under any
intellectual property rights.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: HTTP://WWW.ZILOG.COM
iv
PS002500-DSP1099
ARCHITECTURAL OVERVIEW
ARCHITECTURAL OVERVIEW
The Z80S183/Z80L183 is a general-purpose integrated microprocessor. It
includes the Z180 processor, 32 bits of general purpose I/O, an Analog-to-Digital
converter with eight multiplexed inputs, a Programmable Output Generator, a
Digital-to-Analog converter, a Watch-Dog Timer, two ASCI channels, two
timers, a CSI/O channel, a Real Time Clock, 2KB of on-chip RAM, and 1KByte
of on-chip ROM. It is packaged in a 100-pin VQFP.
The Z80S183/Z80L183 includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Code-compatible with Z80 & Z180
On-chip wait state generator
Two enhanced UART channels (ASCIs)
Two 16-bit counters
Three interrupt request inputs, two with optional edge-triggering
Real time clock
Two on-chip oscillators
DC-to-33 MHz operating frequency @ 5.0V
DC-to-20 MHz operating frequency @ 3.3V
Clock divide by 2X or 1X
Fully static CMOS design with low-power standby
2 KB of on-chip RAM
1 KB of on-chip ROM
Eight 10-bit A/D channels
One 10-bit D/A
32 bits of general-purpose I/O
Low-power PLL oscillator
Programmable Output Generator (POG)
Watch-Dog Timer (WDT)
Clocked Serial I/O Interface (CSI/O)
ZiLOG Debug Interface (ZDI)
Power-down logic
ASCI Tx complete output
Economical 100-pin VQFP
Interrupts on ports A and D
PS000501-XMP1299
Preliminary Z80S183/Z80L183
5
ARCHITECTURAL OVERVIEW
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
Figure 1 illustrates the block diagram for the Z80S183/Z80L183. In addition to a
Z8S180-compatible processor, it includes the following modules:
32 Bits of General Purpose I/O. Four 8-bit ports are selectively multiplexed
with on-chip peripheral functions (ASCIs, CSI/O, PRT, POG), and are individu-
ally programmable as inputs or outputs. Each I/O pin can source and sink 15mA.
Programmable Output Generator. An engine that is independent of the
processor, that can drive programmable waveforms onto 8 digital outputs, as well
as initiating A/D and D/A conversions
Two ASCI Channels. Asynchronous serial channels with baud rate generators,
modem control, and status.
Two 16-bit Timers. Down-counters with interrupt capability.
CSI/O. Clocked serial I/O can be used for serial memory or peripheral interface.
Watch-Dog Timer. This circuit helps detect code runaway and helps minimize its
negative effects. A range of time-out values is available. The RESET pin can be
forced Low at the terminal count of the Watch-Dog Timer.
Eight Channel Analog-To-Digital Converter. A 10-bit converter with eight
multiplexed inputs.
Digital to Analog Converter. 10-bit resolution.
2KB of On-Chip RAM. Used for stack and other read/write operations.
6
Preliminary Z80S183/Z80L183
PS000501-XMP1299
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
PIN DESCRIPTIONS
10-Bit Analog -
to-Digital
32-Bit General
Purpose I/O
Converter
10-Bit Digital-
to-Analog
Converter
Watch-Dog
Timer
8-Bit POG
2K RAM
1K ROM
Z8S180
Core
Real Time
Clock
ZiLOG Debug
Interface
FIGURE 1. Z80S183/Z80L183 BLOCK DIAGRAM
PIN DESCRIPTIONS
Figure 2 illustrates the Z80S183/Z80L183 pinout. Table 2 describes the processor
and device pins. Table 2 describes the Asynchronous Serial Communications
Interface (ASCI) and Clocked Serial I/O (CSI/O) pins. Table 3 describes the Port
and Programmable Output Generator (POG) pins. Table 4 describes the analog
pins.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
7
PIN DESCRIPTIONS
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
75
70
65
60
55
51
50
2&ꢃꢇ#%ꢃꢇ&4'3ꢃ
+1%5ꢀ
+1%5ꢅ
29459+6%*
6:5
ꢋꢊ
2&ꢅꢇ#%ꢅꢇ&4'3ꢅ
2&ꢀꢇ#%ꢀ
2&ꢈꢇ#%ꢈ
#8
ꢌꢃ
8
2&ꢉꢇ#%ꢉ
2&ꢄꢇ#%ꢄ
2&ꢊꢇ#%ꢊ
2&ꢋꢇ#%ꢋ
.(':6#.
.(:6#.
+194
45
40
35
2$ꢋꢇ4:5
2$ꢊꢇ4:#ꢅ
2$ꢄꢇ6:#ꢅ
2$ꢉꢇ4:#ꢃ
2$ꢈꢇ6:#ꢃ
2$ꢀꢇ%65ꢃꢇ29472
2$ꢅꢇ&%&ꢃ
8
ꢌꢄ
ꢆꢃ
ꢆꢄ
83(2ꢀꢁꢂꢂꢃ2KPꢀ
8
+14&
<&#
<%.
2$ꢃꢇ%-5
4#/94
4#/4&
&ꢋ
2*+
':6#.
:6#.
/ꢅ
&ꢊ
&ꢄ
&ꢉ
8
8
30
26
&ꢈ
&ꢀ
&ꢅ
&ꢃ
0/+
+06ꢃ
+06ꢅ
+06ꢀ
ꢅꢃꢃ
1
5
10
15
20
25
FIGURE 2. Z80S183/Z80L183 PIN DESCRIPTION
TABLE 1. PROCESSOR AND DEVICE PIN DESCRIPTIONS
Symbol
Pin # Function
Type
Description
A19–0
1–4,
Address Bus
Bidirectional, These lines select a location in memory or I/O
6–12,
14–20,
22–23
3-state
space to be read or written. The Z80S183/
Z80L183 does not drive these lines during Reset
nor external bus acknowledge cycles. Drive is
optional during LOW-POWER modes.
8
Preliminary Z80S183/Z80L183
PS000501-XMP1299
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
PIN DESCRIPTIONS
TABLE 1. PROCESSOR AND DEVICE PIN DESCRIPTIONS (CONTINUED)
Symbol
Pin # Function
Type
Description
CE_OUT
69
Chip Enable
Out
Open drain
output
An open-drain output, with no internal pull-up.
Can be used to enable an external RAM, as
described in “Using the Power Control Register”
on page 33.
D7–0
EXTAL
INT0
26–29, Data Bus
31–34
Bidirectional, These lines transfer information to and from I/O
3-state
and memory devices. The Z80S183/Z80L183
drives these lines only during write cycles.
93
98
Oscillator or
Clock In
Input
This pin can be connected to a crystal or to an
external clock. When a crystal is used, this
signal is not a logic level.
Interrupt
Input, active
Low
This signal can be driven Low in an open-drain
fashion by external I/O devices. The processor
responds to this request at the end of the current
instruction cycle if it is enabled, and the NMI and
BUSREQ signals are inactive. This pin can only
be used in Z80/180 Mode 1, in which the
processor acknowledges this request by
interrupting to location 0038H.
Request 0
INT1–2
99, 100 Interrupt
Inputs, active These signals are generated by external
Requests 1–2 Low or edge- devices. The processor acknowledges a request
triggered
on one of these lines at the end of the current
instruction cycle, so long as the NMI, BUSREQ,
and INT0 signals are inactive. The processor
acknowledges one of these requests with an
internal cycle, in which a fixed vector
corresponding to one of the pins is used to
select an interrupt service routine. These pins
may be programmed for active Low level, rising
or falling edge interrupts. The state of the
external INT1 and INT2 pins can be read in the
Interrupt Edge Register.
IOCS1–2
IORD
49, 50 I/O Chip
Selects 1–2
Outputs, active When Bit 2 of the System Control register (SCR)
Low
is 1, IOCS1 goes Low for accesses to I/O
addresses 0080–87H, and IOCS2 goes Low for
accesses to 0088–8FH.
89
I/O Read
Output, active IORD Low indicates that the Z80S183/Z80L183
Low, 3-state
is reading data from a location in I/O space. The
addressed I/O device uses this signal to gate
data onto the processor data bus. The Z80S183/
Z80L183 does not drive this line during Reset,
nor during bus acknowledge cycles.
IOWR
87
I/O Write
Output, active IOWR indicates that Bits D7–0 hold valid data to
Low, 3-state
be stored at the addressed I/O location. The
Z80S183/Z80L183 does not drive this line during
Reset, nor during bus acknowledge cycles.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
9
PIN DESCRIPTIONS
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
TABLE 1. PROCESSOR AND DEVICE PIN DESCRIPTIONS (CONTINUED)
Symbol
Pin # Function
Type
Description
LFExtal
85
Low-
Frequency
Crystal or Clock
Input
A low-frequency crystal or line frequency input
can be connected to this pin, for use by the real
time clock. A low-frequency crystal can be also
used with the FLL for a system clock.
LFXTAL
M1
86
95
97
Low Frequency Output
Crystal
A low-frequency crystal can be connected to this
pin, for use by the Real Time Clock or as the
system clock.
Machine cycle Output, active Together with ROMRD or RAMRD, M1 Low
1
Low
indicates that the current cycle is the fetch cycle
of an instruction execution.
NMI
Nonmaskable Input, falling- NMI has a higher priority than INT0 and is
Interrupt
edge active
always recognized at the end of an instruction,
regardless of the state of the interrupt enable
flip-flops. This signal forces processor execution
to location 0066H. This input includes a Schmitt
trigger to allow RC rise times.
OPMODE0-1 74–75 Operating
Inputs
These pins select the basic operating mode of the
Z80S183/Z80L183. A rising edge on OPMODE1
makes the Z80S183/Z80L183 generate a Power
On Reset (POR), and subsequently enter Boot
mode.
Mode Select
1, 0
OPMODE1 OPMODE0 Operating Mode
L
L
H
H
L
H
L
Normal
Reserved
Internal ROM enabled
BUSREQ is generated
H
PHI
92
System Clock Output
This output is the Z80S183/Z80L183’s master
clock, and is provided for use by external logic.
The frequency of this clock may be equal to or
half of the crystal or input clock frequency,
depending on an internal register bit.
PWRSWITCH 48
Power Switch Output
This pin is a positive logic output controlled by
Bit 5 of the Power Control register. Bit 5 resets to
0, so this pin goes Low at any Reset, including
one initiated by a rising edge on PWRUP or
OPMOD1. See “Using the Power Control
Register” on page 33.
PWRUP
RAMRD
40
35
Power Up
Input
When Bit 6 is 1 in the Power Control Register, a
rising edge on PB2/CTS0/PWRUP resets the
part, as described in “Using the Power Control
Register” on page 33.
RAM Read
Output, active RAMRD Low indicates that the processor reads
Low, 3-state
data from a memory location in the address
range of external RAM. The Z80S183/Z80L183
does not drive this line during Reset, nor during
bus acknowledgment.
10
Preliminary Z80S183/Z80L183
PS000501-XMP1299
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
PIN DESCRIPTIONS
TABLE 1. PROCESSOR AND DEVICE PIN DESCRIPTIONS (CONTINUED)
Symbol
Pin # Function
Type
Description
RAMWR
36
RAM write
Output, active RAMWR Low indicates D7–D0 hold data to be
Low, 3-state
stored at a memory location in the address
range of external RAM. The Z80S183/Z80L183
does not drive this line during Reset, nor during
bus acknowledgement.
RESET
73
Master Reset Input/Output, This signal initializes the Z80S183/Z80L183 and
active Low
other devices in the system. This input must be
Low for a minimum of six system clock cycles,
and is held Low until the clock is stable. RESET
can be programmed as an output, allowing
Z80S183/Z80L183 to reset external devices.
The Power On Reset and Watch-Dog Timer (if
enabled) blocks perform a global reset by
forcing RESET Low. This input includes a
Schmitt trigger to allow RC rise times.
ROMRD
ROMWR
24
25
ROM Read
ROM Write
Output, active ROMRD Low indicates that the processor wants
Low, 3-state
to read data from a memory location in the
address range of external ROM/Flash. The
Z80S183/Z80L183 does not drive this line during
reset, nor during bus acknowledge cycles.
Output, active ROMWR Low indicates that D7–0 hold a byte to
Low, 3-state
be stored at the addressed memory location in
the address range of external Flash memory. The
Z80S183/Z80L183 does not drive this line during
Reset, nor during bus acknowledge cycles.
VDD
13, 30, Power Supply
46, 63,
96
These pins carry power to the device. They must
be tied to the same voltage externally.
VSS
5, 21, Ground
38, 55,
88
These pins are the ground references for the
device. They must be tied to the same voltage
externally.
WDT Enable
70
Watch-Dog
Timer Enable
Input
When this pin is High, the Watch-Dog Timer
cannot be disabled by software nor by Reset.
When this pin is Low at power-up, these three
events occur:
– A Power On Reset disables the Watch-Dog
Timer.
– A WDT Reset does not change the status of
the WDT.
– Software can enable or disable it as needed.
XTAL
ZCL
94
91
Crystal
Input/Output
Input
Crystal oscillator connection. This pin is left
open if an external clock is used instead of a
crystal. This pin does not carry a logic level.
(See “DC Characteristics” on page 155.)
ZDI Clock
The clock for the ZiLOG Debugging Interface.
This input includes a Scmitt trigger.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
11
PIN DESCRIPTIONS
BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
TABLE 1. PROCESSOR AND DEVICE PIN DESCRIPTIONS (CONTINUED)
Symbol
Pin # Function
90 ZDI Data
Type
Description
ZDA
Input/output,
open drain
Data for the ZiLOG Debugging Interface. This
input includes a Schmitt trigger.
TABLE 2. UART AND CSI/O PIN DESCRIPTIONS
Symbol
Pin # Function
Type
Description
CTS0
40
Clear To Send Input, active
Transmit control signal for ASCI channel 0.
0
Low
DCD0
RXA0–1
RXS
39
Data Carrier
Detect 0
Input, active
Low
Receive control signal for ASCI channel 0.
ASCI Receive data.
42, 44 Receive Data Inputs
0, 1
45
CSI/O Receive Input
Data
Receive data for the CSI/O channel.
ASCI Transmit data.
TXA0–1
TXS
41, 43 Transmit Data Outputs
0, 1
47
CSI/O Transmit Output
Data
Transmit data from the CSI/O channel.
TABLE 3. PORT AND POG PIN DESCRIPTIONS
Symbol
Pin # Function
Type
Description
PA7–0
51–54, Port A
56–59
Input/outputs These pins can be configured as inputs or
outputs, with or without level-sensitive, active
Low interrupt request capability, on a bit-by-bit
basis.
PB7–0
PC7–0
37,
39–45
Port B
Input/outputs These pins can be configured as port inputs or
outputs, or ASCI or CSI/O signals, on a bit-by-
bit basis.
60–62, Port C
64–68
Input/outputs These pins can be configured as port inputs or
outputs, or Programmable Output Generator
outputs, on a bit-by-bit basis. Also, PC0 can be
used as a 50 or 60 Hz time base for the real
time Clock.
PD7–0
76–79, Port D
81–84
Input/outputs These pins can be configured as inputs or
outputs, with or without level-sensitive, active
Low interrupt request capability, or as inputs to
the A/D converter, on a bit-by-bit basis. PD0
and PD1 can also act as DREQ0 and DREQ1
respectively.
12
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROCESSOR DESCRIPTION
OPERATIONAL DESCRIPTION
TABLE 4. ANALOG PIN DESCRIPTIONS
Symbol
Pin # Function
Type
Description
AC7–0
76–79, Analog
Inputs
Inputs to the Analog to Digital converter.
81–84 Channels
AGND
AOUT
AVDD
VREF
71
72
80
51
Analog Ground
Reference ground for the analog circuitry.
The output of the Digital to Analog converter.
Power for the analog circuitry.
Analog Output Output
Analog Power
External
Analog
Input
External analog reference voltage, multiplexed
with PA0.
Reference
OPERATIONAL DESCRIPTION
This section describes, using text, tables, and figures, how the various parts of the
Z80S183/Z80L183 operate. This description is presented from the processor
outward to the peripherals. In the latter parts of this section, refer to the corre-
sponding section of “I/O Registers” on page 72 that presents the Z80S183/
Z80L183’s I/O registers. Cross-reference links are included in both sections to aid
these references.
PROCESSOR DESCRIPTION
The Z80S183/Z80L183 is an 8-bit microprocessor that performs certain 16-bit
operations. In both data sizes, the processor includes an accumulator. Register A
is the accumulator for 8-bit operations, and the HL register pair is the accumulator
for 16-bit operations.
Processor Program Registers
In addition to register A, there are six more 8-bit registers named B, C, D, E, H,
and L that can also be operated on as 16-bit register pairs BC, DE, and HL. Flag
register F completes the basic register bank.
Two of these basic register banks are included in all Z80 and Z180 processors.
High-speed exchange between these banks can be used by a program internally, or
one bank can be allocated to the mainline program and the other to interrupt
service routines.
Finally, two Index registers IX and IY allow ‘base and displacement’ addressing
in memory. IX and IY are not included in the register banks on the Z80 and Z180;
there is only one copy of each.
Memory Management Unit (MMU)
To the 16-bit, 64 KB memory addressing capability of the Z80, all Z180 proces-
sors add a Memory Management Unit (MMU) that expands the addressing capa-
bility to 20 bits (1 MB). With the MMU, the 64 KB logical addressing space can
be divided into one to three areas of programmable size and location in the
1-MB physical memory space.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
13
OPERATIONAL DESCRIPTION
PROCESSOR DESCRIPTION
I/O Space
A separate I/O space includes on-chip and off-chip peripheral devices. On the
Z80, I/O space included 8-bit addresses and 256 bytes. All Z180 processors
feature an expanded I/O space with 16-bit addresses and 64 KB. The Z80S183/
Z80L183 includes an extensive set of on-chip peripherals in I/O space that can be
augmented by external peripherals.
Processor Control Registers
In addition to the data-oriented registers described above, the Z80S183/Z80L183
processor includes several other control registers. Unlike the registers in I/O
space, which are described in Section 4, these control registers have no addresses,
but are used implicitly in certain processor operations.
Program Counter (PC). This 16-bit register tracks program execution by the
processor that automatically increments PC while fetching instructions. The
processor stores PC on the stack when it executes a CALLor RSTinstruction, or
an interrupt or TRAPoccurs. The processor loads PC with a new value when it
executes a JUMP, CALL, RST, or RETinstruction, and when an interrupt, Trap, or
Reset occurs. PCresets to 0000.
Stack Pointer (SP). The processor decrements this 16-bit register by 2, and
stores a 16-bit value in memory at this updated address, when it executes a
PUSH, CALL, or RST instruction, and when an interrupt or Trap occurs. The
processor fetches a 16-bit value from memory at the address in SP, and then
increments SP by 2, when it executes a POP, RET, RETI, or RETNinstruction.
Software can store the value in SP in memory, load SP from memory or another
register, or load it with a constant/immediate value. Further, software can add or
subtract the value in SP to or from another register, and can increment or decre-
ment SP. Finally, software can exchange the 16-bit value in memory, to which
SP currently points, with the contents of a 16-bit register. SP resets to 0000B.
Flags (F). The processor includes two Flag registers each containing six bits,
named Zero (Z), Carry (CF), Sign (S), Parity or Overflow (P/V), Half-Carry (HC),
and Add/Subtract (N). Certain flags are automatically updated as part of executing
certain instructions. Subsequent instructions can then use the flags, either as an
operand (ADC, SBC, DAA), or to determine whether to perform a JUMP, CALL, or
REToperation. The flags can be saved on the stack with a PUSHinstruction, or
restored from the stack with a POPinstruction. The two sets of flag registers are
paired with the two (A) accumulators; the current pair is toggled by the
EXAF,AF’instruction.
Interrupt High Address (I). The contents of this register are used as the eight
high-order address bits, when the processor fetches the address of an interrupt
service routine from memory, for an interrupt from the INT1or INT2pin, or
from an on-chip peripheral. The I register points to a table of interrupt service
routine addresses that starts at a 256-byte boundary in the 64 KB logical address
space. The I register resets to 0, and can be read or written by the dedicated
instructions LDA,Iand LDI,A.
14
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROCESSOR DESCRIPTION
OPERATIONAL DESCRIPTION
R Counter (R). On the Z8018x family processors, this register contains a count of
executed fetch cycles. R resets to 0, and can be read or written by the dedicated
instructions LDA,Rand LDR,A.
Observing Read Data from On-Chip Devices
Bit 7 of the Output Control Register (OCR, illustrated on page 78) determines
whether the Z80S183/Z80L183 drives data from on-chip ROM, RAM, and I/O
registers, onto the D7–D0 pins for debugging and monitoring purposes. When this
bit is 0, as it is after a reset, the D7–D0 pins remain in high-impedance state
during read cycles from on-chip devices, saving power.
When software sets this bit to 1during device initialization, the Z80S183/
Z80L183 drives read data from on-chip devices onto D7–D0, allowing it to be
captured by debugging instruments such as logic analyzers.
Illegal Instruction Traps
Like most processors, the defined instruction set for the Z8018x family does not
fully cover all possible sequences of binary values. The Op Code maps, in the
section, “Op Code Map” on page 147, include numerous blank cells. These cells
represent Op Code sequences for which no operation is defined, and are
commonly called illegal instructions.
When a Z80S183/Z80L183 or other Z8018x processor fetches one of these
sequences, it performs a Trap sequence as follows:
1. The Trap bit is set to 1 when an undefined Op Code is fetched.
2. The UFO bit (ITC Bit 6) toggles to indicate the starting address of the
undefined Op Code in the event that the instruction is two or three bytes long.
This is necessary since the Trap may occur on either the second or third byte
of Op Code.
When the UFO bit is set to 0when a Trap interrupt occurs, the first undefined
Op Code should be interrupted as the stacked PC-1. When UFO is 1, the first
undefined Op Code address is stacked PC-2.
3. The processor decrements the Stack Pointer (SP) by 2 and stores the 16-bit
logical address from PC, in memory at the new SP address. This address points
to the last byte of the illegal Op Code sequence.
4. The processor then clears PC and resumes execution at logical address 0000.
Trap Handling. The code at logical address 0000Bcan optionally store the value of
SP in memory, and then set SP to an area of memory dedicated to its private stack.
In all cases, the trap-handling routine stores as many registers among AF, BC, DE,
HL, IX, and IY as it may use, by pushing them onto the stack. A general-purpose
routine stores all of these registers, those in the alternate set, the value of I, and the
state of the Interrupt Enable flag.
Next, the Trap-handling code distinguishes among the four events that can bring
execution to address 0000B:
PS000501-XMP1299
Preliminary Z80S183/Z80L183
15
OPERATIONAL DESCRIPTION
DEVICE AND VERSION ID REGISTERS
•
•
•
•
A Reset
A Trap
An RST0instruction
A program error, such as a JUMPto a null pointer
The code detects a Trap by reading the Interrupt/Trap Control register (ITC) and
checking Bit 7 (Trap). When Bit 7 is 1, a Trap has occurred, and the code handles
it as follows:
1. Clears the Trap bit by writing a 0to Bit 7 of the ITC
2. Fetches the PC value stored on the stack
3. Examines Bit 6 of the ITC (UFO).
4. Decrements the PC value by 1, if the UFO bit is 0; otherwise, decrements it by
2, so that it points to the start of the illegal instruction.
The next action of the trap handling routine depends on the application and its
stage of development.
Extending the Instruction Set. Core software can use illegal instructions as
extensions to the Z8018x instruction set. To accomplish this, the trap handler must
fetch and examine each illegal instruction. When an illegal instruction is an exten-
sion, the trap handler performs the extended operation that the instruction indi-
cates. It then advances the stacked PC value over the instruction, restores the
saved register values, and returns to the next instruction.
Error Message vs. Restart. Except for these extended instructions, the trap
handling software can perform either of the following actions:
•
Output an error message and wait for someone to examine the situation and
restart the application
•
Attempt to restart the application immediately
The former course is more common in the debugging/development stages of an
application, while the latter may be more appropriate in the production/deploy-
ment stage. In the latter case, software may log the event for future readout, using
an external storage medium or just in memory.
DEVICE AND VERSION ID REGISTERS
Three registers (described on page 76), allow software to determine if it is oper-
ating on a Z80S183/Z80L183, as well as the device version. These registers are a
mandatory feature of the ZDI interface that is described in “ZiLOG Debug Inter-
face” on page 166, and are also available in I/O space.
I/O addresses 003BHand 003CHread as 01and 00respectively, indicating that
the Z80S183/Z80L183 is one of the first devices to incorporate a ZDI interface. I/
O address 003DHreads as 00for revision AB, 01for revision BA, and will
feature higher values on future revisions.
16
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INTERRUPTS
OPERATIONAL DESCRIPTION
INTERRUPTS
ZiLOG Z80 and Z180 processors have a rich legacy of sophisticated interrupt
capabilities. Because of the lack of an I/O Request signal on the Z80S183/
Z80L183, its interrupt subsystem is substantially simpler and easier to describe
than those of other 8018x devices.
The following topics, which are significant for other 8018x processors, do not
apply to the Z80S183/Z80L183:
•
•
•
•
INT0 Mode 0 and 2 interrupts
Interrupt acknowledge cycles
Interrupt daisy chains
Interrupt Pending and Interrupt Under Service bits
• RETIinstructions
Interrupt Resources in the Z80S183/Z80L183
IEF1 and IEF2. These bits are internal to the processor and are only affected and
manipulated by certain specific events:
•
•
•
•
•
•
•
A Reset clears IEF1 and IEF2
An EIinstruction sets IEF1 and IEF2
A DIinstruction clears IEF1 and IEF2
An NMIsequence copies IEF1 to IEF2, then clears IEF1
A maskable interrupt clears IEF1 and IEF2
An LDA,Ior LDA,Rinstruction copies IEF2 to the P/V flag
An RETNinstruction copies IEF2 to IEF1
When IEF1 is 1, RESETand BUSREQcondition on the OPMODE pins are both
High, and no falling edge has occurred on NMI, the Z80S183/Z80L183 checks for
maskable interrupt requests from external pins and on-chip peripherals, as it
completes each instruction, or each instruction iteration for HALT, the block I/O
instructions, block move instructions, and block scan instructions.
The I Register. The Z80S183/Z80L183 uses the contents of this register as A15–
8 of the logical address for fetching interrupt service routine addresses from
memory, in response to interrupt requests on INT1and INT2, and from internal
peripherals.
See “Interrupt Registers” that starts on page 80 for other registers associated with
interrupts.
The IL Register. The Z80S183/Z80L183 uses Bits 7-5 of this register as A7–5 of
the logical address for fetching interrupt service routine addresses from memory, in
response to interrupt requests on INT1and INT2, and from internal peripherals.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
17
OPERATIONAL DESCRIPTION
INTERRUPTS
The Interrupt/Trap Control Register (ITC). Bits 2-0 of the ITC are individual
Enable bits for the INT2, INT1, and INT0pins, respectively. They reset to
001B, so that requests on INT0can be enabled by an EIinstruction after Reset.
Interrupt Edge Register (IER). By reading this register, software can detect the
current state of the INT2and INT1pins, and whether an edge has been detected
on each. Other bits in the IER select whether each of these pins is low-level sensi-
tive, or rising- and/or falling-edge sensitive.
Nonmaskable Interrupt (NMI)
The Z80S183/Z80L183 latches falling edges on the NMIpin. A falling edge clears
the DME bit in the DMA Status register (DSTAT), disabling the on-chip DMA
channels. Only a Low on RESETor on BUSREQtakes precedence over NMI.
Unless RESETor BUSREQis Low, the Z80S183/Z80L183 checks for a falling
edge on NMIas it completes each instruction (each instruction iteration of HALT,
the block I/O instructions, block move instructions, and block scan instructions),
and performs an NMIsequence if a falling edge has occurred.
0QVGꢄ BUSREQis a conditional state of the OPMODE0 and OPMODE1 pins.
An NMIsequence includes 4 steps:
1. The processor copies the state of the IEF1 bit to IEF2.
2. It clears IEF1 to prevent maskable interrupts.
3. It decrements SP by 2, and stores the logical address in the PC in memory at
the new address in SP. For most interrupts, this value is the address of the
instruction the processor would have executed next, had no interrupt occurred.
When the processor was stopped by HALTor SLP, this value is the address of
the next instruction. In the event of an incomplete block transfer, block scan,
or block I/O instruction, this value is the address of the instruction.
4. The processor loads 0066Hinto PC, and resumes execution from that logical
address.
NMI Handling. NMI routines fall into two categories, based on whether the
external hardware that drives NMIis capable of producing another falling edge on
the pin, before the NMI service routine has completed its execution and returned
to the interrupted process.The case when the NMI is not capable of producing
another falling edge is called Single Edge Guaranteed. The case when the NMI
can produce another falling edge is called Repeated Edge Possible. Debug moni-
tors, which may display the state of the interrupt process, fall into the Repeated
Edge category.
Single Edge Guaranteed. An NMI routine in this category is similar to other
interrupt service routines. This routine has the option of storing the contents of SP
in memory and loading SP with the address of a memory area that is dedicated for
the stack. In any case, this routine stores as many of the registers as it may use
during its execution.
18
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INTERRUPTS
OPERATIONAL DESCRIPTION
Repeated Edge Possible. An NMI routine in this category starts with a PUSH
AFinstruction, then LOAD Afrom a dedicated location in memory that indicates
whether the interrupted process is the NMI routine. When this location indicates
that the process is the NMI routine, it immediately performs a POPAFand then a
RETNinstruction, to return to its former execution.
When the in NMI location is cleared, software sets it to 1. Then, if the NMI
routine performs either of the following:
•
•
Places a DIinstruction in a Save The Registers routine that it shares with other
means of entry
Displays the I register or the interrupt-enable state of the interrupted process,
and allows a user/programmer to change these (in essence, a debug monitor)
it performs LDA,Iand PUSHAFinstructions. This stores the I register at the
address in SP plus one, and the interrupt enabled state (IEF2) in the
P/V flag and in Bit 2 of the memory location pointed to by SP.
When the NMI routine uses a common Save The Registers subroutine that it
shares with other entry points, the save subroutine can perform a DIinstruction to
prevent interruption by maskable interrupts.
The NMI routine has the option to store the SP value in a dedicated location in
memory, and load SP with the address of a dedicated NMI stack area.
In any case, the NMI routine must PUSH as many other registers as it uses. A
debug monitor typically performs PUSHoperations on all registers in both banks,
so that it can display them.
Reenabling The DMA Channels. In an NMI service routine in an application
that uses the DMA channels, software next reads the DSTAT register and reen-
ables any DMA operation that was in progress, as described in the section “NMI
and DME” on page 45.
Exiting The NMI Routine. On completion of its processing, an NMI routine
restores the saved registers. When the routine used its own stack area, it then
restores the SP value of the interrupted process. When the routine sets an in NMI
memory location on the way in, it clears this location to 0.
NMI routines that did not save the I register and IEF2 state at the start, can
conclude with POPAFand RETNinstructions. RETNcopies the state of IEF2
back into IEF1, restoring the interrupt enable state of the interrupted process.
NMI routines that saved I and IEF2 at the start, conclude with a POPAFfor the
saved I register and IEF2 bit. Then an LDI,A, followed by a JPVto a POPAF,
EI, RETsequence. The JPis followed by LDI,A, POPAF, and RETinstructions.
INT0 Mode 1
The Z80S183/Z80L183 can only handle interrupts requested on the INT0pin in
Mode 1. All Z80S183/Z80L183 applications that enable interrupts and do not tie
INT0High, must include an IM1instruction before the first EIinstruction.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
19
OPERATIONAL DESCRIPTION
INTERRUPTS
The Z80S183/Z80L183 performs an INT0interrupt sequence at the end of an
instruction (each instruction iteration for HALT, the block I/O instructions, block
move instructions, and block scan instructions), if all of the following are true:
• INT0is Low
•
•
Bit 0 of the Interrupt/Trap Control register is 1to enable INT0
The IEF1 bit is set to 1to enable interrupts in general
• RESETand BUSREQare both High, and a negative edge on NMIhas not been
detected.
0QVGꢄ BUSREQis a conditional state of the OPMODE0 and OPMODE1 pins.
When all of these conditions occur simultaneously, the Z80S183/Z80L183
responds as follows:
1. It clears IEF1and IEF2to prevent further interrupts.
2. It decrements SP by 2, and stores the contents of PC in memory at the new
address in SP. This value is typically the address of the instruction the
processor would have executed next, if no interrupt had occurred. When the
processor is stopped by HALTor SLP, this value is the address of the next
instruction. In the event of an incomplete block transfer, block scan, or block
I/O instruction, this value is the address of the instruction.
3. It loads 0038Hinto PC, and resumes execution from that logical address.
Interrupt Handling. Any Interrupt Service Routine (ISR) has the initial option of
saving the contents of SP in memory, and loading SP with the address of a
memory area that is dedicated to its stack. Most interrupt service routines do not
use this option.
An INT0ISR must save the contents of the registers it uses, using PUSH and/or
EX AF,AF’and EXX instructions.
When the application includes a mechanism for allowing nested interrupts, the
ISR can begin as specified by that mechanism, leading to an IEinstruction that
allows the ISR to be interrupted by other interrupts. Most applications do not
allow for nested interrupts.
The ISR next reads status registers from each device that can request an interrupt on
INT0, to identify the cause of the interrupt. The ISR must process each interrupting
device according to this status, and the device and application requirements.
Many ISRs read data from interrupting device(s), or write data to interrupting
device(s). In addition, the ISRs can write registers in these devices, to modify its
mode, status, or operation.
When interrupt processing is complete, if nested interrupts were allowed, the ISR
ends as specified by the nesting mechanism. When nested interrupts were not
allowed, the ISR restores the saved registers and concludes with EIand RET
instructions.
20
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INTERRUPTS
OPERATIONAL DESCRIPTION
0QVGꢄ the Z80 and Z80180 instruction sets include an RETIinstruction that is used for
servicing Z80 peripherals. Since the Z80S183/Z80L183 includes no such peripherals, nor
does it allow them to be connected externally, there is no reason to conclude a Z80S183/
Z80L183 ISR with an RETI. RETis both shorter and faster than RETI, and fills the
same function.
INT1 and INT2
The Z80S183/Z80L183 performs an INT1or INT2interrupt sequence at the end of
an instruction (each instruction iteration for HALT, the block I/O instructions, block
move instructions, and block scan instructions), if all of the following are true:
• INT1and/or INT2meets the condition specified for it in the Interrupt Edge
Control register (low level, rising edge, falling edge),
•
Bit 2 or 1 of the Interrupt/Trap Control register (ITC) is 1to enable this pin
(if both pins are enabled and both pins meet the specified condition, INT1
takes precedence over INT2),
•
IEF1 is 1, to enable interrupts in general,
• INT0is High or Bit 0 of the ITC is 0,
• RESETand BUSREQare High, and
•
A negative edge on NMIhas not been detected.
0QVGꢄ BUSREQis a conditional state of the OPMODE0 and OPMODE1 pins.
When all of these conditions occur simultaneously, the Z80S183/Z80L183
responds as follows:
1. It clears IEF1 and IEF2 to prevent further interrupts.
2. It decrements SP by 2, and stores the contents of PC in memory at the new
address in SP. Typically, this value is the address of the instruction the
processor would have executed next, if no interrupt had occurred. When the
processor was stopped by HALTor SLP, this value is the address of the next
instruction. In the event of an incomplete block transfer, block scan, or block
I/O instruction, this value is the address of the instruction.
3. Next, the processor forms a logical memory address using the contents of the
I register as A15–8, Bits 7–5 of the IL register as A7–5, and 0 as A4–0 for
INT1or 2 in A4–0 for INT2.
4. Finally, the processor fetches a 16-bit logical address from memory at that
logical address, loads it into PC, and resumes instruction execution from there.
INT1–2 Handling. All of the considerations noted for INT0ISRs in “Interrupt
Handling” on page 20, also apply to ISRs for INT1and INT2. One additional
step is required when the pin is edge-triggered: read the INT2-1 Interrupt Edge
Register (IECR), and write the value (including 1in Bit 5 or 4) back to the IECR
to clear the edge-detection logic.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
21
OPERATIONAL DESCRIPTION
INTERRUPTS
On-Chip Interrupts
The Z80S183/Z80L183 performs an interrupt sequence for an on-chip device at the
end of an instruction (each instruction iteration for HALT, the block I/O instruc-
tions, block move instructions, and block scan instructions), if all of the following
are true:
•
•
•
•
An interrupting condition has occurred in the device
That condition is interrupt-enabled in the device’s registers
IEF1 is 1, to enable interrupts in general
No higher-priority internal device is requesting an interrupt (see Table 5 below
for the relative priorities of internal devices)
•
Neither INT1nor INT2is interrupting
• INT0is High or Bit 0 of the ITC is 0
• RESETand BUSREQare both High
•
A negative edge on NMIhas not been detected.
0QVGꢄ BUSREQis a conditional state of the OPMODE0 and OPMODE1 pins.
When all of these conditions occur simultaneously, the Z80S183/Z80L183
responds as follows:
1. It clears IEF1 and IEF2 to prevent further interrupts.
2. It decrements SP by 2, and stores the contents of PC in memory at the new
address in SP. Typically, this value is the address of the instruction the
processor would have executed next, if no interrupt had occurred. When the
processor was stopped by a HALTor SLPinstruction, this value is the address
of the next instruction. For an incomplete block transfer, block scan, or block
I/O instruction, this value is the address of the instruction.
3. Next, the processor forms a logical memory address using the contents of the
I register as A15–8, Bits 7–5 of the IL register as A7–5, and the value
corresponding to the interrupting device as A4–0.
4. Finally, the processor fetches a 16-bit logical address from memory at that
logical address, loads it into PC, and resumes instruction execution from there.
On-Chip Interrupt Handling. The only difference between handling an on-chip
interrupt, and the considerations noted for INT0ISRs in “Interrupt Handling” on
page 20, is that the ISR for an on-chip device never needs to differentiate among
several devices connected to an INTpin, only among interrupt sources within
the device.
TABLE 5. INTERRUPT OFFSETS AND PRIORITIES
Device
Priority A4–0 Offset
INT1 pin
INT2 pin
highest
0
2
22
Preliminary Z80S183/Z80L183
PS000501-XMP1299
MEMORY
OPERATIONAL DESCRIPTION
TABLE 5. INTERRUPT OFFSETS AND PRIORITIES (CONTINUED)
Device
Priority A4–0 Offset
PRT0
4
PRT1
6
DMA0
8
DMA1
10 = 0AH
12 = 0CH
14 = 0EH
16 = 10H
18 = 12H
20 = 14H
22 = 16H
24 = 18H
26 = 1AH
28 = 1CH
CSI/O
ASCI0
ASCI1
Programmable Output Generator (POG)
Port A
Port D
A/D Converter
Real Time Clock (RTC)
Reserved
ZiLOG Debug Interface (ZDI)
lowest
30 = 1EH
NOTE: Devices are ordered identically with respect to interrupt priority and offset value
MEMORY
Z8018x family processors include a 64 KB logical memory space in which soft-
ware operates, and a 1 MB physical memory address space in which on-chip and
external memory reside. The Memory Management Unit (MMU) translates 16-bit
logical addresses to 20-bit physical addresses dynamically, as part of each
memory access.
Memory Structure
On the Z80S183/Z80L183, memory is divided into four categories:
•
•
•
•
1 KB of on-chip ROM
2 KB of on-chip RAM
External ROM or Flash memory using on-chip decoding
External RAM using on-chip decoding
Table 30 on page 80 describes the System Configuration Register (SCR) that
includes bits that enable or disable each of these four memory categories. Soft-
ware designers must be cautious when programming this register, to not disable
the memory in which the current code sequence resides.
On-chip ROM can be enabled or disabled at Reset time, by the state of the
OPMODE1–0pins. These pins control the initial state of the on-chip ROM Enable
bit in the SCR. When on-chip ROM is enabled, it occupies physical addresses
00000–003FFH.
The last 256 bytes of on-chip RAM are always accessible to the Programmable
Output Generator (POG) module. When processor access to on-chip RAM is
PS000501-XMP1299
Preliminary Z80S183/Z80L183
23
OPERATIONAL DESCRIPTION
MEMORY
enabled, another bit in the SCR controls whether A19–16 are included in address
decoding for on-chip RAM.
The on-chip address decoder for external ROM or Flash memory decodes from
physical address 00000through a programmable upper limit. When external
ROM is enabled, memory accesses at addresses below the upper limit, drive the
ROMRDor ROMWRpin Low. (Among the capabilities of the ROMWRpin are
programming of Flash memories.)
The on-chip address decoder for external RAM decodes between programmable
lower and upper limits. When external RAM is enabled, memory accesses at
addresses between these two limits, drive the RAMRDor RAMWRpin Low.
0QVGꢄ When software programs the Memory Chip Select Logic and System Configura-
tion Register so that some addresses do not match either the ROM or RAM chip selection,
accesses to these addresses do not appear on the external bus. Avoid this possibility by
programming the active chip selects to cover the entire memory address space.
Addressing Modes
Instructions can specify a memory address in several ways. Z80S183/Z80L183
addressing modes include:
Relative Addressing. JRand DJNZinstructions include a signed 8-bit displace-
ment that specifies a range of addresses –126to +129from the Op Code, to
which program control can be transferred.
Direct Addressing. In this mode, instructions include a 16-bit logical address.
Register Indirect Addressing. In this mode, the address is taken from one of the
register pairs BC, DE, or HL.
Indexed Addressing. In this mode, instructions include an 8-bit signed displace-
ment from the address in an index register IX or IY.
Other contexts in which memory is accessed include instruction fetching, inter-
rupts, and DMA operations.
Memory Management Unit (MMU)
The MMU translates the 16-bit addresses used by software, called logical
addresses, into 20-bit physical addresses, as part of all memory accesses
performed by the processor. The MMU has no effect on accesses performed by
the DMA channels that include 20-bit address registers. It also has no effect on
addresses in I/O space that always have A19–16 0.
The MMU resets to a state in which it has no effect on addresses in processor
cycles, passing A15–0 through without change and keeping A19–16 0. When an
application needs 64 KB of memory or less, it ignores the MMU.
Even when the MMU has been programmed to perform active address transac-
tions, it passes A11 0from the logical to the physical address. The MMU
manages memory in 4 KB blocks.
24
Preliminary Z80S183/Z80L183
PS000501-XMP1299
MEMORY
OPERATIONAL DESCRIPTION
The section titled “MMU Registers” on page 82, describes the registers associated
with the MMU.
MMU Operation. The MMU compares Bits 15–12 of each logical address to two
4-bit fields in its Common/Base Address Register (CBAR), in an unsigned
manner.
When Bits 15–12 of a logical address are less than the value in Bits 3–0 of the
CBAR, the MMU considers the address to be in Common Area 0. For these
addresses, it passes Bits 15–12 to the A15-12 pins unchanged, and sets pins
A19–16 to 0.
When Bits 15–12 of a logical address are greater than or equal to the value in Bits
3–0 of the CBAR, but are less than the value in Bits 7–4 of the CBAR, the MMU
considers the address to be in the Bank Area. For such addresses, it adds the value
in its 8-bit Bank Base Register (BBR) to Bits 15–12 of the logical address, and
outputs the 8-bit sum on pins A19–12.
When Bits 15–12 of a logical address are greater than or equal to the value in Bits
7–4 of the CBAR, the MMU considers the address to be in Common Area 1. For
such addresses, it adds the value in its 8-bit Common Base Register (CBR) to Bits
15–12 of the logical address, and outputs the 8-bit sum on A19–12.
0QVGꢄ The value in Bits 7–4 of the CBAR must never be less than the value in Bits 3–0 of
the CBAR.
MMU Configurations. In the general case, the MMU divides the 64 KB logical
memory space into three parts, with Common Area 0 located at the start of the
1 MB physical address space, and the Bank Area and Common Area 1 relocatable
to other parts of the physical address space. These three parts are under control of
the Bank Base Register and Common Base Register, respectively.
Certain combinations of values in the CBAR result in the logical address space
being divided into fewer active areas:
•
When the CBAR contains 0, all logical addresses fall into Common Area 1,
and are relocated to a contiguous 64 KB area starting at the address in the CBR
times 4096.
•
When CBAR3–0 are 0but CBAR7–4 are non-zero, the Bank Area and
Common Area 1 are active. Logical addresses less than (CBAR7–4)*4096
are relocated by the Bank Base Register, while other addresses are related by
the Common Base Register.
•
When CBAR7–4and CBAR3–0are equal and not 0, Common Area 0 and
Common Area 1 are active. Logical addresses less than (CBAR3–0)*4096
are not relocated, and map to the start of physical memory. Other addresses are
relocated by the Common Base Register.
The MMU After Reset. Because the CBAR resets to 11110000B, logical
addresses 0000–EFFFHare in the Bank Area and F000–FFFFHare in Common
Area 1 after Reset. But since the BBR and CBR both reset to 0, the MMU passes
all logical addresses through without change, with A19–16 all 0.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
25
OPERATIONAL DESCRIPTION
MEMORY
On-Chip ROM
On-Chip RAM
Bit 7 in the System Configuration Register (page 80) controls whether physical
addresses 00000–003FFHaccess on-chip ROM or external memory. A 1in this
bit enables on-chip ROM. At reset, this bit is set to 1if the OPMOD1pin is High
and the OPMOD2pin is Low. Otherwise, this bit is cleared to 0.
Bits 6–5 in the System Configuration Register control processor access to on-chip
RAM. When Bit 6 is 0, on-chip RAM is disabled. When Bits 6–5 are 10, on-chip
RAM does not decode Bits 19–16 of physical addresses, and responds to all phys-
ical addresses with A15–11 all 1: xF800 through xFFFFH. When Bits 6–5 are
11B, on-chip RAM responds to physical addresses with A19–11 all 1: addresses
FF800–FFFFFH.
The Programmable Output Generator (POG) can always read the last 256 bytes of
on-chip RAM, regardless of Bits 6–5 in the SCR.
External ROM/Flash Decoding
Bit 4 of the System Configuration Register enables or disables an on-chip address
decoder for external ROM or Flash memory. When this bit is 1, memory accesses
at physical addresses less than the upper limit programmed in the ROM Boundary
Register (ROMBR, page 84), drive the ROMRDor ROMWRpin Low. (The ROMWR
pin can be used to program Flash memories.)
When SCR Bit 4 is 1, ROMRDor ROMWRgoes Low for addresses with A19–12
less than or equal to the contents of ROMBR, that is, for addresses less than
(ROMBR+1)*4096.
External RAM Decoding
Bit 3 of the System Configuration Register (page 80) enables or disables an on-
chip address decoder for external RAM. When this bit is 1, memory accesses at
physical addresses between the lower limit programmed in the RAM Lower
Bound Register (RAMLBR), and the upper limit programmed in the RAM Upper
Bound Register (RAMUBR), drive the RAMRDor RAMWRpin Low. These regis-
ters are described on page 85.
When SCR Bit 3 is 1, RAMRDor RAMWRgoes Low for addresses with A19–12
greater than or equal to the contents of RAMLBR, and less than or equal to the
contents of RAMUBR, that is, for addresses A in the range
(RAMLBR)*4096 < A < (RAMUBR+1)*4096
Wait State Generators
The Z80S183/Z80L183 includes two registers that control automatic insertion of
wait states into memory and I/O accesses.
The DMA/Wait Control register (DCNTL) is shown on page 103, and is present
on all 8018x family members. DCNTL is one of the DMA registers, but the wait
states that it controls apply to processor cycles as well as to those generated by the
DMA channels.
26
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INPUT/OUTPUT
OPERATIONAL DESCRIPTION
Bits 7–6 select the number of wait states for all memory accesses.
Bits 5–4 select the number of wait states for I/O accesses other than those to 180
registers. The Z80S183/Z80L183 interprets both fields as a binary number of wait
states:
Bit 5
Bit 4
Wait State
0
0
1
1
0
1
0
1
No wait states
1 wait state
2 wait states
3 wait states
The Wait State Generator Control register (WSGCR) is described on page 83, and
is unique to the Z80S183/Z80L183.
Bits 7–6 control the number of wait states for memory accesses in the ROMRD/
ROMWRaddress range.
Bits 5–4 control the number of wait states for memory accesses in the RAMRD/
RAMWRaddress range.
Bits 3–2 control the number of wait states for other memory accesses, but these
cycles do not appear on the external bus.
The Z80S183/Z80L183 interprets these fields as follows:
Bit 3
Bit 2
Wait State
0
0
1
1
0
1
0
1
No wait states
1 wait state
2 wait states
4 wait states
No DRAM Refresh
ZiLOG’s Z80 and Z8018x families have traditionally included dynamic RAM
refresh logic. This logic is identical on all Z8018x devices including the Z80S183/
Z80L183, but the Z80S183/Z80L183 does not have a RFSHpin with which to
signal refresh cycles, nor a Refresh Control Register.
INPUT/OUTPUT
The Z80S183/Z80L183 includes an I/O space that is distinct from memory space.
I/O space is accessed by means of INand OUTinstructions rather than LD, PUSH,
POP, and other instructions that access memory space. The MMU passes
addresses in I/O space through without change; such addresses always have
A19–16 all 0.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
27
OPERATIONAL DESCRIPTION
INPUT/OUTPUT
I/O Instructions
The original Z80 featured a 256-byte I/O space. The following instructions are
specific to the Z80’s 256-byte I/O space, and should not be used on the Z80S183/
Z80L183 except to access external I/O devices that do not decode A15–8:
OUT (port), A
IND
INDR
INI
INIR
OTDR
OTIR
OUTD
OUTI
The following instructions ensure that A15–8 are all 0, and can be used to access
the Z80S183/Z80L183’s on-chip I/O registers, as well as external devices that
decode A15–8 as all 0:
IN0 r, (port)
OUT0 (port), r
OTDM
OTDMR
OTIM
OTIMR
The following instructions drive A15–0 from the BC register pair, and can be used
to access the full 64 Kbyte I/O space:
IN r, (C)
OUT (C), r
The following instruction can access the entire 64 Kbyte I/O space, by pre-loading
the MS 8 bits of the address into A. (This step is unnecessary for external devices
that do not decode A15-8.)
IN A, (port)
Relocating the 80180 Registers
The section, “Registers Summary” on page 72, describes how the Z80S183/
Z80L183’s I/O registers are divided into 80180-registers and Z80S183/Z80L183-
specific registers. The latter registers are always located in the range 0040–
007FH. After a reset, the 80180 Registers are located in the range 0000–003FH,
but Bits 7–6 of the I/O Control Register (page 78) allow software to relocate the
80180 Registers to higher addresses:
IOCR 7–6 180 Register Addresses
00
01
10
11
0000–003FH
Reserved, do not program
0080–00BFH
00C0–00FFH
28
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INPUT/OUTPUT
OPERATIONAL DESCRIPTION
Relocating the 180 registers is included to ease porting of Z80 applications to the
Z8018x family.
%CWVKQPꢄ Use this facility with caution because certain tools may assume that the 80180
Registers are located in the 0000– 003FHrange. Those tools need to be reconfigured
(reassembled, recompiled) to allow for relocated 180 Registers.
Write Enable/Lock for Critical Registers
Some registers are protected from inadvertent modification by software. Writing a
0BHto the Watch-Dog Timer Command Register (WDTCR, page 106) sets Bit 0
of the Watch-Dog Timer Master register to 1(WDTMR, page 105) and enables
writing to these registers. Writing any other value to WDTCR clears Bit 0 of the
WDTMR to 0and prevents writing to these registers.
The Write Enable state has no effect on reading the registers protected by this
mechanism that include.
•
•
•
•
System Configuration register (SCR, page 80)
Power Control register (PCR, page 79)
Port A-D Data Direction registers (DDRA–D, pages 86–92)
All Real Time Clock registers (pages 112–117)
I/O Chip Selects
When Bit 2 in the System Control Register (SCR) is 1, the Z80S183/Z80L183
drives the IOCS1pin for accesses to I/O addresses 0080–87H, and drives the
IOCS2pin Low for accesses to 0088–8FH. When SCR Bit 2 is 0, IOCS1and
IOCS2remain High at all times.
I/O Waits
Bits 5–4 of the DMA/Wait Control Register can be used to insert wait states into
I/O cycles with the Z80S183/Z80L183-specific registers at addresses 0040–
007FH, and into I/O cycles with external devices. This field is interpreted as a
binary number of wait states:
Bit 5
Bit 4
Wait State
0
0
1
1
0
1
0
1
No wait states
1 wait state
2 wait states
3 wait states
IORD Timing
Bit 5 in the Operating Mode Control Register (OMCR, shown on page 77)
controls the timing of the IORDsignal when software reads from an external I/O
device. When this bit is 1, as it is after a reset, the Z80S183/Z80L183 drives
IORDLow from the falling edge of PHIin the T1 clock cycle. When this bit is 0,
PS000501-XMP1299
Preliminary Z80S183/Z80L183
29
OPERATIONAL DESCRIPTION
CLOCK CIRCUITS
it drives IORDLow one-half clock cycle later, from the rising edge of PHIat the
start of T2. Both cases are illustrated in Figure 3.
0QVGꢄ On other Z8018x family members, Bits 7 and 6 in the OMCR control how the M1
signal affects Z80 peripheral devices. Since the Z80S183/Z80L183 does not have an
IORQ pin, it cannot be used with Z80 peripherals, and OMCR Bits 7–6 do not matter.
T1
T2
Tw
T3
PHI
IORD (OMCR5=1)
IORD (OMCR5=0)
FIGURE 3. IORD TIMING
CLOCK CIRCUITS
The Z80S183/Z80L183 can be clocked in any of three ways:
•
•
•
By an external TTL- or CMOS-level clock on the EXTALpin
By a crystal connected to its XTALand EXTALpins
By a low-frequency crystal (typically 32.768 KHz) connected to its LFXTAL
and LFEXTALpins
An external clock signal must be free of overshoot or ringing, must make contin-
uous, monotonic, and rapid transitions in both directions, and must meet the
minimum High and Low times specified in “AC Characteristics” on page 159.
Clock Selection
Bits 1–0 of the System Configuration Register, which is shown on page 80, select
the source of the main device clock (PHI) between the XTAL/EXTALpins and
the LFXTAL/LFEXTALpins, and in the latter case, a multiplier for the clock:
SCR 1–0
PHI source
00
01
10
11
XTAL/EXTAL
LFXTAL/LFEXTAL
LFXTAL/LFEXTAL times 1004
LFXTAL/LFEXTAL times 502
Because these bits reset to 00, an application that requires LFXTALand
LFEXTALmust start up using XTALand EXTAL. The circuit in Figure 6 includes
a connection that satisfies this need.
Divide-by-2 vs. Direct Option
Regardless of the source of PHI, Bit 7 of the CPU Control Register (CCR,
described on page 75) controls whether the Z80S183/Z80L183 uses the signal
30
Preliminary Z80S183/Z80L183 PS000501-XMP1299
CLOCK CIRCUITS
OPERATIONAL DESCRIPTION
selected by Bits 1–0 of the SCR directly as PHI, or whether it divides the signal by
2 to obtain PHI.
When CCR Bit 7 is 0, as it is after a reset, the part divides the selected signal by 2.
This mode insulates the part against an asymmetric waveform on the selected
signal. When CCR Bit 7 is 1, the Z80S183/Z80L183 uses the selected signal
directly. In this case, if an external clock is connected to EXTAL, the clock must
meet the minimum High and Low times specified in “AC Characteristics” on
page 159.
Circuits
When using a crystal connected to XTALand EXTAL, locate the crystal as close as
possible to the pins. This placement minimizes the trace lengths between the
crystal, the pins, and the two capacitors shown in Figure 4, which illustrates the
connection of a fundamental mode crystal up to and including 20 MHz. C1 and
C2 are 20–30 pF, with 22 pF a typical value.
C1
XTAL
Crystal
Inputs
GND
GND
C2
EXTAL
FIGURE 4. FUNDAMENTAL MODE CRYSTAL CIRCUIT < 20 MHZ
For frequencies above 20 MHz, use a third-overtone crystal and include an LC
tank circuit to filter the fundamental frequency, as shown in Figure 5. Again, it is
essential to minimize trace lengths by locating all of the components as close as
possible to the XTALand EXTALpins.
XTAL
Crystal
Inputs
EXTAL
C
L
GND
GND
FIGURE 5. THIRD-OVERTONE CRYSTAL > 20 MHZ
A low-frequency crystal can be connected between the LFXTALand LFEXTAL
pins without any other components (see Figure 6). When the LF crystal is used as
the clock source for the Real Time Clock, it must be exactly 32.768 KHz.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
31
OPERATIONAL DESCRIPTION
RESET CONDITIONS
150 W
85
LFEXTAL
22pF
18MW
37.268 KHz
Z80S183/Z80S183
86
93
94
LFXTAL
EXTAL
XTAL
22pF
(nc)
FIGURE 6. LOW-FREQUENCY CRYSTAL CIRCUIT
Crystal Specifications
The following specifications apply to fundamental mode crystals up to 20 MHz:
•
•
•
•
Fundamental, parallel type (AT cut recommended)
Load capacitance: C = C1 = C2 = 20–30 pF (22 pF typical)
L
Equivalent Resistance R < 60 ohms
S
C
= C
= 15–22 pF
OUT
IN
Reduced Oscillator Drive Option
Bit 6 in the Clock Control Register, described on page 74, controls the gain of the
XTAL/EXTALoscillator. When Bit 6 is 0, as it is after a reset, a crystal connected
to XTALand EXTALis driven strongly, to guarantee that oscillation always starts.
This drive is suitable for traditional crystals packaged in HC–49-type packages,
but may be too powerful for crystals packaged for miniaturized applications such
as PCMCIA.
To reduce the gain of the oscillator, write a 1to Bit 6 of the Clock Control Register.
This action reduces the drive to about 25% of normal mode, and reduces the
maximum oscillator frequency from 33 to 20 MHz.
RESET CONDITIONS
The effects of Reset on each of the registers in I/O space is described in Tables
18–133 in the section describing “I/O Registers” on page 72. Among processor
registers, the following registers and state bits are cleared to 0: PC, SP, I, IEF1,
IEF2, R, and F. The following are not changed by Reset: A, B, C, D, E, H, L, IX,
and IY.
The Z80S183/Z80L183 resets itself on power-up. When power is applied, the
device detects power rising. When the oscillator starts, the Power On Reset
16
circuitry holds the Z80S183/Z80L183 in reset for 2 clock cycles, driving
RESETLow to provide a reset to external peripherals. This Power On Reset
sequence also occurs in response to a rising edge on OPMOD1pin. When Bit 6 of
the Power Control Register (PCR) is 1, a reset is generated in response to a rising
edge on PB2/CTS0/PWRUP.
32
Preliminary Z80S183/Z80L183
PS000501-XMP1299
POWER MANAGEMENT
OPERATIONAL DESCRIPTION
Another possible source of Reset is the Watch-Dog Timer (WDT). See the section
“Watch-Dog Timer” on page 45, for more information on the WDT.
POWER MANAGEMENT
The Z80S183/Z80L183’s low-power modes are controlled by the Standby and
Idle/Quick bits in the CPU Control Register (page 75), the IOSTOP bit in the I/O
Control Register (page 78), and execution of SLPand HALTinstructions.
The section titled “LOW-POWER Modes” on page 34 describes the low-power
modes.
Using the Power Control Register
The Power Control Register (PCR, page 79) is unique to the Z80S183/Z80L183,
and offers additional power control options to the board designer and programmer.
CE_OUT. This pin can be connected to the CEor CSpin(s) of external RAM, and
to an external pullup resistor. The Z80S183/Z80L183 drives this pin Low when
Bit 7 of the Power Control Register is 1. Software sets this bit before trying to
access external RAM. When PCR Bit 7 is 0, the Z80S183/Z80L183 does not
drive CE_OUT, and the external resistor pulls it High, which helps safeguard the
RAM against modification. Software clears PCR Bit 7 to 0before entering a
LOW-POWER mode.
The RAM and the external pullup can be powered from a supply that is active
when the Z80S183/Z80L183 is not powered, for example, from standby power or
from a battery.
PB2/CTS0/PWRUP. This pin can be connected to a rising-edge-active wake up
signal from external logic. To use this feature, software sets Bit 6 of the Power
Control Register to 1before entering a LOW-POWER mode. When PCR Bit 6 is
1, a rising edge on PB2/CTS0/PWRUP causes a Reset that is identical to a Power
On Reset. This reset brings the Z80S183/Z80L183 out of the LOW-POWER
mode and into normal operation. When Bit 6 of the PCR is 0, PB2/CTS0/
PWRUPcannot cause a reset, and can be used for other purposes.
0QVGꢄ A rising edge on the OPMOD1pin also causes a Power On Reset. Assuming that
OPMOD1 remains High, the device executes code from on-chip ROM after the Reset.
After a Power On Reset caused by the PWRUP pin, execution starts in on-chip ROM or
external memory, depending on the state of OPMOD1.
PWRSWTCH. This pin can be connected to a Low-active power switch that
controls power to external devices (for example, a P-channel FET). It is a direct
positive-logic output controlled by Bit 5 of the Power Control Register, which resets
to 0, making PWRSWTCHLow, which in turn applies power to the external devices.
Before entering a LOW-POWER mode, software can write a 1to Bit 5 of the PCR,
making PWRSWTCHHigh and removing power from the external devices.
Tristate A19–0, RAMRD, RAMWR, ROMRD, ROMWR, IORD, IOWR, IOCS1-2,
TXS. When Bit 4 of the Power Control Register is 1, these pins are 3-stated
when the Z80S183/Z80L183 is in a LOW-POWER mode. This action completes
PS000501-XMP1299
Preliminary Z80S183/Z80L183
33
OPERATIONAL DESCRIPTION
POWER MANAGEMENT
the PWRSWTCH power control mechanism, in that it keeps external memories
and peripherals from drawing power from these signals. PCR Bit 4 resets to 0.
To use this facility, software sets PCR Bits 5 and 4 to 1before entering a LOW-
POWER mode.
LOW-POWER Modes
The IOSTOP bit in the I/O Control Register (page 78) controls operation of the
ASCIs, PRTs, and CSI/O. When this bit is 0, these peripherals operate normally.
When this bit is 1, they are disabled, reducing power use.
The Standby and Idle/Quick bits in the CPU Control Register (page 75) control
what mode the Z80S183/Z80L183 enters when it executes an SLPinstruction.
When the application uses the XTAL/EXTAL oscillator and Standby is 1, an SLP
instruction stops the oscillator. This mode uses less power than any other mode,
but requires time to restart the oscillator in response to a reset, an interrupt
request, or optionally a bus request.
When Standby is 1, the Idle/Quick bit controls the number of PHIclocks the
device waits after reenabling the oscillator and before restarting operation
17
(0selects 2 (128K) clocks, and 1selects 64 clocks).
When Standby is 0, the oscillator runs for the duration of the SLPinstruction, but
clocking is blocked to most of the Z80S183/Z80L183. The Idle/Quick bit controls
whether the oscillator output is driven onto the PHIpin. A 1in Idle/Quick
disables clocking on PHI.
When Standby is 1, the BREXT bit, Bit 5 in the CPU Control Register (page 75),
controls whether the Z80S183/Z80L183 restarts the oscillator in response to a
Low on BUSREQ, with a 1enabling this response.
0QVGꢄ BUSREQis a conditional state of the OPMODE0 and OPMODE1 pins.
Table 6 below details the interaction of these various bits and states, including the
conditions that make the Z80S183/Z80L183 leave each LOW-POWER mode and
resume normal operation.
TABLE 6. LOW-POWER MODES
Instruction Standby Idle/Quick IOSTOP Mode: Operation
other than
HALT
or SLP
X
X
0
NORMAL: The processor fetches instructions and executes
them, possibly sharing the bus with on–chip DMAs and
external masters. On-chip peripherals operate under software
control.
other than
HALT
or SLP
X
X
1
I/O STOP: The processor, MMU, DMAs, and external
masters operate normally, but the ASCIs, PRTs, and CSI/O
are disabled to reduce power consumption. All the ASCIs,
PRTs, and CSI/O can do is generate an interrupt
combinatorially. Software can switch the Z80S183/Z80L183
between NORMAL and I/O STOP mode as appropriate
34
Preliminary Z80S183/Z80L183
PS000501-XMP1299
POWER MANAGEMENT
OPERATIONAL DESCRIPTION
TABLE 6. LOW-POWER MODES (CONTINUED)
Instruction Standby Idle/Quick IOSTOP Mode: Operation
HALT
X
X
0
HALT: The processor continually fetches the Op Code
following the Halt, but does not execute it, possibly sharing
the bus with on-chip DMAs and external masters. Halt mode
reverts to Normal mode if:
– RESET or NMI is Low,
– INT0 is Low and enabled, or
– An enabled interrupt is requested from an ASCI, PRT,
CSI/O, DMA or INT21.
HALT
SLP
X
0
X
0
1
0
HALT and I/O STOP: Similar to HALT mode except that the
ASCIs, PRTs, and CSI/O are disabled.
SLEEP: Clocking is blocked to the, processor and DMAs,
and, refresh logic, so that bus activity is they are not
generated active on the bus. The bus can be granted to
external masters. I/O operates except for DMA. SLEEP mode
reverts to Normal mode under the same conditions as for
HALT mode, except that the DMAs cannot interrupt.
SLP
0
0
1
SYSTEM STOP: The oscillator continues running and
generating PHI, but clocking is blocked to most of the chip.
Bus granting can occur. SYSTEM STOP mode reverts to
Normal mode if:
– RESET or NMI is Low,
– INT2–0 is Low
– An enabled interrupt is requested by an on-chip peripheral
that can generate an interrupt combinatorially.
SLP
SLP
0
1
1
0
1
1
IDLE: The oscillator continues running but PHI is blocked, as
is clocking to most of the chip. Bus granting can occur if the
BREXT bit (CCR5) is 1. IDLE mode can revert to NORMAL
mode under the same circumstances as from SYSTEM
STOP mode.
STANDBY: The XTAL/EXTAL oscillator is stopped. This
mode does not apply to applications that use LFXTAL/
LFEXTAL. Bus granting can occur if the BREXT bit (CCR5) is
1, in which case the device reactivates the oscillator, waits for
217 (128K) clocks, grants the bus, and deactivates the
oscillator again after the bus request is negated. STANDBY
mode can revert to NORMAL mode under the same
circumstances as from System Stop mode. When one of
these stimuli occur while the Z80S183/Z80L183 is waiting for
128K clocks before responding to an enabled bus request, or
while the bus is granted, it re-enters Normal mode when the
bus request is negated. Otherwise, the Z80S183/Z80L183
reactivates the oscillator and wait for 217 (128K) clocks before
commencing normal operation.
SLP
1
1
1
STANDBY WITH QUICK RECOVERY: Similar to STANDBY
mode, except that the Z80S183/Z80L183 waits only 64 clocks
after enabling the oscillator, before granting the bus or
resuming normal operation.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
35
OPERATIONAL DESCRIPTION
REDUCED DRIVE/LOW NOISE FEATURES
In SLEEP, SYSTEM STOP, IDLE, or either STANDBY mode, if the Z80S183/
Z80L183 exits the mode because of NMIor an enabled interrupt with the IEF1 flag
1, the device resumes operation by performing the interrupt, with the return address
as the instruction after the SLPinstruction. When the device exits the LOW-
POWER mode because of an individually-enabled interrupt request, but IEF1 is 0,
the Z80S183/Z80L183 resumes by executing the instruction after the SLP.
REDUCED DRIVE/LOW NOISE FEATURES
Reduced drive is available on many of the outputs of the Z80S183/Z80L183.
These options reduce power consumption for applications that do not need the full
drive and slew rate capability provided in normal mode. Even more importantly
for some applications, invoking these features results in less noise induced onto
power and ground.
The following register bits govern the drive strength on various output pins. Each
of these bits resets to 0, which selects normal/full drive strength for the outputs.
To save power and reduce noise for outputs that do not need the maximum drive
and slew rate, software sets the associated bit to 1during device initialization.
This action reduces the drive to about 25% of full strength.
TABLE 7. REDUCED DRIVE/LOW NOISE CONTROL BITS
Shown
Register
on
Bit Output Pins
CPU Control Register (CCR)
page 75 4
PHI
1
0
IORD, IOWR
A19–0, D7–0
PA7–0
Output Control Register (OCR) page 78 3
2
1
0
PB7–0
PC7–0
PD7–0
I/O PORTS
The Z80S183/Z80L183 includes four 8-bit I/O ports called A through D. All four
ports feature the same basic capabilities. The ports are controlled by three registers
for each port: a Data Register, a Data Direction Register, and an Output Control
Register.
The ports differ primarily in interrupt capability and in pin-multiplexing with other
functions, controlled by an Alternate Function Select (AFS) Register for each port.
The next two sections describe the common characteristics shared by all the ports,
then the unique capabilities controlled by the AFS register for each port
The section titled, “I/O Port Registers” on page 86, describes the registers associ-
ated with the I/O ports.
36
Preliminary Z80S183/Z80L183
PS000501-XMP1299
I/O PORTS
OPERATIONAL DESCRIPTION
Data Registers
Writing to a Data Register affects the data that is driven onto pins that are desig-
nated as outputs in the Data Direction and Output Control Registers. Reading
from the Data Register returns the states of the pins, for both inputs and outputs.
The output latches cannot be read separately.
Data Direction Registers and Output Control Registers
These registers determine which pins in each port are inputs and which are
outputs, and for outputs, select one of three output modes. The following table
shows the four possible states for each pin:
DDR OCR FUNCTION
0
0
1
1
0
1
0
1
Totem pole output (active pullup)
Open-drain output (no internal pullup)
Input
Open-drain output with internal pullup resistor
The totem pole outputs actively drive both High and Low. The classic open-drain
output only drives Low, and relies on an external pull-up resistor to ensure a High
voltage when no open-drain driver is driving Low. (This external pull-up also
avoids excessive current draw by the Z80S183/Z80L183’s receiver and any other
CMOS receivers that may be connected to the signal. The 11Bstate is similar but
connects an internal pull-up resistor of about 15K Ohms, eliminating the need for
an external pullup.
All four DDRs reset to all 1s and all four OCRs reset to all 0s, so Reset configures
all port pins as inputs.
The Data Direction Registers can only be written if the Register Write Enable bit
is 1in the WDT registers.
Port A Alternate Function Select (AFSA)
This register controls interrupts from port A. AFSA resets to all zeroes, disabling
all interrupts from port A. Setting any of these bits to 1enables the corresponding
pin to interrupt. When an interrupt is requested by the port and interrupts are
enabled, the Z80S183/Z80L183 fetches the address of the Interrupt Service
Routine (ISR) from memory at address (I : IL : 20). The ISR must read the Data
Register to determine which pin(s) caused the interrupt. Pins selected for inter-
rupts are level-sensitive and active Low. Regardless of how this register is
programmed, software must set DDRA for each port pin. Setting a pin as an
output, and enabling interrupt for it, allows software to force an interrupt.
Port B Alternate Function Select (AFSB)
This register controls alternate functions for the port B pins. AFSB resets to all 0s,
so that all of the pins are assigned to port B. Setting a bit to 1selects the following
alternate function for the pin:
PS000501-XMP1299
Preliminary Z80S183/Z80L183
37
OPERATIONAL DESCRIPTION
I/O PORTS
PB0: CKS
PB1: DCD0
PB2: CTS0 or PWRUP
PB3: TXA0
PB4: RXA0
PB5: TXA1
PB6: RXA1
PB7: RXS
Selecting the alternate function for a pin disables any control of the pin by the
DDRB register, but the corresponding bit in OCRB must be 0.
Port B Weak Latch Disable Feature
Most of the inputs on the Z80S183/Z80L183 have weak latch circuits to reduce
power consumption if an input is not driven by an external device. A weak latch
can come up in either state at Power On, and thereafter is easily over-driven by an
external driver, or for bidirectional pins like the Port pins, by an internal driver.
Typically, the only effect of weak latches is to prevent an input voltage from
floating in the threshold region that makes the receiver circuit draw high current.
For the PB7–0pins only, the weak latches can be disabled by setting Bit 4 of the
Output Control Register to 1, (described on page 78). When this Bit 4 is 0, as it is
after a Reset, weak latches are enabled on Port B.
Port C Alternate Function Select (AFSC)
AFSC resets to all 0s, so that all of the pins are assigned to port C. Setting a bit to 1
assigns that pin to the Programmable Output Generator (POG). In this
ALTERNATE FUNCTION mode, the DDRC and OCRC registers determine the
output drive on the pin. This feature allows the POG to be used with any of the
output modes of the normal port function. To use PC0 as a 50 or 60 Hz time base for
the Real Time Clock, leave AFSC Bit 0 at 0, DDRC Bit 0 at 1, and OCRC Bit 0 at 0.
Port D Alternate Function Select (AFSD)
This register controls interrupts from Port D. AFSD resets to all 0, disabling all
interrupts from port D. Setting any of these bits to 1enables the corresponding pin
to interrupt. When an interrupt is generated by the port and interrupts are enabled,
the Z180 fetches the address of the Interrupt Service Routine (ISR) from memory
at (I: IL: 22). The ISR must read the Data Register to determine which pin(s)
caused the interrupt. Pins selected for interrupts are level-sensitive and active
Low. Regardless of how this register is programmed, software must set DDRD for
each port pin. Setting a pin as an output, and enabling interrupt for it, allows soft-
ware to force an interrupt.
0QVGꢄ PD0 and PD1 also function as DREQ0and DREQ1respectively. The DMA
section describes how to take DMA Requests from these pins, which programmed inputs
in this case. To use the A/D capability of Port D, leave the Alternate Function Select
Register in PORT mode and set the DDRD and OCRD for input.
38
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA CHANNELS
OPERATIONAL DESCRIPTION
TABLE 8. REGISTER REFERENCE
Register
On Page Bit Output Pins
CPU Control Register (CRC)
68
4
1
0
3
2
1
0
PHI
IORD, IOWR
A19–0, D7–0
PA7–0
Output Control Register (OCR)
71
PB7–0
PC7–0
7–0
DMA CHANNELS
The Z80S183/Z80L183 includes two DMA channels called DMA0 and DMA1.
Both channels can transfer data between memory and a peripheral in I/O space. In
addition, DMA0 can perform memory-to-memory block transfers, and transfers
between memory and memory-mapped I/O devices.
Both DMA channels are of the flowthrough type, in which each byte transferred
requires two bus cycles—the first to read the source and the second to write the
destination. As a result, neither memory nor peripherals are subject to any special
considerations for bus cycles controlled by the DMA channels, because such
cycles are identical to processor bus cycles.
DMA transfer can occur as fast as 6 clocks/byte. At 33 MHz, this speed corre-
sponds to 5.5 MBPS. Destination/output devices require Edge-Sensitive request
mode, in which the maximum rate is 9 clocks/byte, or 3.67 MBPS at33 MHz.
The section, “DMA Registers” on page 94, describes the registers associated with
the DMA channels.
DMA Basics
Each channel has two 20-bit address registers and a 16-bit byte count. For DMA0
the address registers are called the Source and Destination Address Registers
(SAR and DAR). DMA1’s address registers are called the Memory and I/O
Address Registers (MAR and IAR).
Each address register is divided into three Z80S183/Z80L183 I/O registers, called
L (Low), H (High), and B.
When a DMA channel is operating, it drives A7–0 from the L register and A15–8
from the H register. For memory addresses (always for MAR), the channel drives
A19–16 from the least-significant four bits of the B register. For I/O addresses
(always for IAR), the channel uses the least-significant three bits of the B register
to select the source of the DMA Request signal that controls data transfer.
Each byte count register is divided into two Z80S183/Z80L183 I/O registers,
called L (Low) and H (High).
After programming a DMA channel’s address and byte count registers, software
starts the channel by setting the Enable bit in the DSTAT register (DE0 or DE1).
PS000501-XMP1299
Preliminary Z80S183/Z80L183
39
OPERATIONAL DESCRIPTION
DMA CHANNELS
When the channel transfers each byte, it decrements the byte count register. When
a channel has decremented the byte count to 0, it goes inactive by clearing its
Enable bit to 0.
Software can select whether a channel increments or decrements a memory address
when it transfers each byte. DMA0 also features an option to keep a memory
address fixed. This fixed address option is intended for use with a memory-mapped
I/O device that provides a DMA Request signal on the PD0/AC0/DREQ0pin.
DMA Requests
An external peripheral, which needs a DMA channel to transfer data for it, must
provide a DMA request signal to the PD0/AC0/DREQ0pin for DMA0, and/or to
the PD1/AC1/DREQ1pin for DMA1. A DMA request can be connected directly
to one of these pins if only one external peripheral is serviced by that DMA
channel. When more than one external device uses a DMA channel, external
selection logic must be included in the application to route the current device’s
request to the channel’s DREQpin.
The otherwise-unused Bits 19–16 of the I/O address of a peripheral, select either
the external DREQpin or an internal peripheral as the source of each DMA
channel’s request. For a memory-mapped peripheral (a source or destination of a
DMA0 memory-to-memory operation that is programmed to use a fixed address),
the PD0/AC0/DREQ0pin is always used as the Request signal.
The DMA request signal indicates when an input or source peripheral has a byte
to be transferred to memory, or when an output or destination peripheral needs a
byte from memory.
Edge- vs. Level-Sensitive Requests
DMA requests can be programmed to be low-level sensitive or falling-edge sensi-
tive. For an output/destination peripheral, the timing requirements on the DMA
Request signal dictate falling-edge mode. An input/source peripheral can use
either an edge- or level-sensitive DMA Request.
Figure 7 illustrates the timing of a level-sensitive DMA Request. DMA operation
is triggered when the channel samples the DMA request line Low. The channel
samples the Request line again, at the rising PHIedge that begins the second-last
clock cycle of the write cycle to the destination. When the Request line is Low at
that time, as it is at the rightmost down-arrow below, the channel continues on to
transfer another byte. When the Request is High, as at the leftmost down-arrow
below, the DMA channel relinquishes use of the bus (to the processor, the other
DMA channel, or an external master) after completing the write cycle.
40
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA CHANNELS
OPERATIONAL DESCRIPTION
DMA Write Cycle
TW TW T3
CPU Cycle
T2 T3
DMA Read Cycle
T1 T2 T3
DMA Write Cycle (I/O)
DMA Read Cycle
T1
T1
T2
TW TW T3
T2
T1
* *
* *
* *
Request
* * Request is sampled at
DMA Write Cycle
TW TW T3
CPU Cycle
T2 T3
DMA Read Cycle
T1 T2 T3
DMA Write Cycle (I/O)
DMA Read Cycle
T1
T1
T2
TW TW T3
T2
T1
* *
* *
* *
Request
* * Request is sampled at
FIGURE 7. PROCESSOR/DMA OPERATION WITH LEVEL- SENSE REQUEST
Figure 8 illustrates the timing of an edge-sensitive request. At the first down-
arrow, the DMA channel writes a byte to the destination. However, a new falling
edge has not occurred by the second-to-last rising PHIedge of the cycle. The
channel relinquishes the bus to the processor.
By the same sampling point in the subsequent processor cycle, a new falling edge
has occurred on the Request line, so the DMA channel assumes control of the bus,
and reads and then writes a byte.
At the same point in the DMA write cycle, a new falling edge has not yet
occurred, so the channel returns bus control to the processor. The channel does not
operate again until the Request line goes High and then Low again, some time
after the right edge of Figure 8.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
41
OPERATIONAL DESCRIPTION
DMA CHANNELS
DMA Write
Cycle
CPU Machine
Cycle
DMA Read
Cycle
DMA Write Cycle
CPU Machine
Cycle
TW T3
T1
T2
T3
T1
T2
T3
T1
T2
TW T3
T1
T2
T3
* *
* *
* *
* *
Request
* * Request is sampled at
DMA Write
Cycle
CPU
Cycle
DMA Read
Cycle
DMA Write Cycle
CPU
Cycle
TW T3
T1
T2
T3
T1
T2
T3
T1
T2
TW T3
T1
T2
T3
* *
* *
* *
* *
Request
* * Request is sampled at
FIGURE 8. PROCESSOR/DMA OPERATION WITH EDGE-SENSE REQUEST
Memory-to-Memory Modes
In a DMA0 memory-to-memory operation, in which both the source and destina-
tion are programmed for address incrementing or decrementing, there is no
peripheral to supply a request signal to control the transfer. In this case, software
can select between two modes of operation by programming MMOD, Bit 1 of the
DMA mode register.
When MMOD is 0, the processor and DMA channel alternate bus cycles until the
DMA completes the block transfer and decrements the byte count to 0. This
sequence is called CYCLE STEAL mode.
When MMOD is 1, the DMA channel performs continuous cycles until the block
transfer is complete. The processor can perform no other actions during this time.
This sequence is called BURST mode.
DMA Interrupts
Software can enable interrupts from each DMA channel, which then requests an
interrupt after decrementing its byte count to 0. When the processor acknowl-
edges this interrupt, it fetches the address of the interrupt service routine from
memory at (I : IL : 8) for DMA0, or (I : IL : 10) for DMA1.
When the interrupt service routine does not have another block of data for the
DMA channel to transfer, it prevents further interrupts by clearing the interrupt
enable bit (DSTAT Bit 2 for DMA0, Bit 3 for DMA1), before it reenables inter-
42
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA CHANNELS
OPERATIONAL DESCRIPTION
rupts with an EIinstruction. When the ISR programs the DMA channel for
another transfer, interrupts can be reenabled with an EIinstruction, after
restarting the DMA by writing to DCNTL.
Setting Up a DMA Transfer
Write the Address Registers. For DMA0, this process includes registers
SAR0L, SAR0H, SAR0B, DAR0L, DAR0H, and DAR0B. When the source is in
I/O space, write SAR0B with a code to select the source of the DMA Request for
DMA0, as described in Table 9:
TABLE 9. SAR0B VALUE FOR A SOURCE IN I/O SPACE
SAR0B Bits 2–0
DMA Request Source
000
001
010
011
1xx
PD0/AC0/DREQ0 pin
ASCI0 RDRF
ASCI1 RDRF
Reserved, do not program
Reserved, do not program
When the DMA destination is in I/O space, write DAR0B with a code to select the
source of the DMA Request for DMA0, as described in Table 10:
TABLE 10. DAR0B VALUE FOR A DESTINATION IN I/O SPACE
DAR0B Bits 2–0
DMA Request Source
000
001
010
011
1xx
PD0/AC0/DREQ0 pin
ASCI0 TDRE
ASCI1 TDRE
Reserved, do not program
Reserved, do not program
For DMA1, software must write registers MAR1L, MAR1H, MAR1B, IAR1L,
IAR1H, and IAR0B. Write IAR1B with a code to select (with the DIM1 bit in the
DCNTL) the source of the DMA Request for DMA1, as described in Table 11:
TABLE 11. IAR1B VALUE
IAR1B Bits 2–0
DIM1
DMA Request Source
000
001
X
PD1/AC1/ DREQ1 pin
ASCI0 TDRE
0 (mem→I/O)
1 (I/O→mem)
0 (mem→I/O)
1 (I/O→mem)
X
ASCI0 RDRF
010
ASCI1 TDRE
ASCI1 RDRF
011
1xx
Reserved, do not program
Reserved, do not program
X
Write the Byte Count Registers. Write the less-significant byte to BCR0L or
BCR1L, and the more-significant byte to BCR0H or BCR1H. An all-0value
causes the DMA to transfer 65,536 bytes.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
43
OPERATIONAL DESCRIPTION
DMA CHANNELS
For DMA0, Write the DMA Mode Register. Bits 3–2 select the operating mode
for the source, as described in Table 12. Bits 5–4 select the operating mode for the
destination, as described in Table 13. For memory-to-memory block transfers, Bit
1 (MMOD) selects between Cycle Steal and Burst modes, as described in
“Memory-to-Memory Modes” on page 42.
TABLE 12. DMA0 SOURCE MODE
DMODE 3–2 Mode
00
01
10
11
Increment Memory Address
Decrement Memory Address
Fixed Memory Address (request on PD0/AC0/DREQ0 pin)
Fixed I/O Address
TABLE 13. DMA0 DESTINATION MODE
DMODE 5–4 Mode
00
01
10
11
Increment Memory Address
Decrement Memory Address
Fixed Memory Address (request on PD0/AC0/DREQ0 pin)
Fixed I/O Address
Write the DCNTL Register. When both DMA channels can be used simulta-
neously, software reads DCNTL, modifies the bits noted below for the current DMA
channel, and writes back the result. Otherwise, software can simply write DCNTL.
Bits 7–4 select the number of waits to insert for Memory and I/O accesses, as
described in the section “Wait State Generators” on page 26. For DMA0, Bit 2
selects between edge- and level-sensitivity on the DMA Request. For DMA1,
Bit 3 selects between edge- and level-sensitivity, and Bits 1–0 select the operating
mode as described in Table 14:
TABLE 14. DMA1 OPERATING MODE
DCNTL 1–0
Mode
00
01
10
11
Increment Memory Address → Fixed I/O Address
Decrement Memory Address → Fixed I/O Address
Fixed I/O Address → Increment Memory Address
Fixed I/O Address → Decrement Memory Address
Write the DSTAT Register to Enable the DMA Channel. When both DMA
channels can be used simultaneously, software reads DSTAT, modifies the bits
noted below for the current DMA channel, and writes back the result. Otherwise,
software can simply write DSTAT.
For DMA0, write 110to Bits 6–4, and write a 1to Bit 2 if DMA0 interrupts
when it has decremented its byte count to 0, or a 0if not.
For DMA1, write a 1to Bit 7, 01to Bits 5–4, and a 1to Bit 3 if DMA1 interrupts
when it has decremented its byte count to 0, or a 0if not.
44
Preliminary Z80S183/Z80L183
PS000501-XMP1299
WATCH-DOG TIMER
OPERATIONAL DESCRIPTION
NMI and DME
When software writes to DSTAT to enable either DMA channel, this action also
sets the DMA Master Enable (DME) bit (Bit 0 in DSTAT). A 1in this bit enables
operation by either or both DMA channels.
To guarantee that a Non Maskable Interrupt (NMI) is handled promptly when it
detects NMILow, the Z80S183/Z80L183 sets DME to 1to suspend DMA operation.
The NMI service routine reads DSTAT immediately after saving the registers. For
each DMA channel, if the DE bit (DSTAT7 or 6) is 1, and the associated device (if
any) has not overrun or underrun, the service routine clears that channel’s DWE bit
(DSTAT5 or 4) to 0. Then, if either DWE bit is 0, the routine writes the result back
to DSTAT. This sequence sets DME again and reenables DMA operation.
DMA Channel Completion
While a DMA channel is operating, software can stop it by reading DSTAT,
clearing bits 6 and 4 for DMA0, or 7 and 5 for DMA1, and writing the result back
to DSTAT.
Otherwise, if software enabled the channel to interrupt when the channel has
decremented its byte count to 0, an interrupt is requested.
When software does not enable the DMA channel to interrupt, it can read the
Enable bit in DSTAT (Bit 6 for DMA0, Bit 7 for DMA1) to determine whether/
when the DMA channel finishes transferring the current block of data. In some
applications, software can use status or an interrupt from the associated peripheral
device to determine completion of the block transfer.
Handling DMA Interrupts
When the conditions noted in “On-Chip Interrupt Handling” on page 22 are met
with respect to a DMA interrupt request, the processor fetches the interrupt
service routine (ISR) address from memory at (I : IL : 8) for DMA0 or (I : IL : 10)
for DMA1. The ISR performs the following functions, as a minimum:
•
Reads the DSTAT to verify that the DE bit is 0for the DMA channel corre-
sponding to the service routine entry point. When a common ISR is used for
both DMAs, the DSTAT value indicates which DMA channel(s) has (have)
completed operation.
•
•
•
Reprograms the channel’s registers and restarts it if the channel is to continue
operation.
Clears the DIE bit for the channel, in the DSTAT register, to prevent another
interrupt for the same DMA completion.
Concludes with EIand RETinstructions, to return to the interrupted process.
WATCH-DOG TIMER
The Watch-Dog Timer (WDT) helps protect against unreliable software, power line
faults that put the processor into unusual states, and other system-level problems.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
45
OPERATIONAL DESCRIPTION
PROGRAMMABLE RELOAD TIMERS (PRTS)
When the WDT is enabled, software must periodically reload it, to prevent it from
resetting the processor or the entire application. The time period, within which
18 22 25
27
software must reload the WDT, is programmable among 2 , 2 , 2 , or 2
system clocks.
The registers in the WDT are detailed in “Watch-Dog Timer Registers” on
page 104.
Several provisions of the WDT enhance its integrity against runaway execution.
The WDT can only be reloaded by writing the specific value 4EHto the WDT
Command register. The WDT can only be disabled by:
•
•
•
Setting Bit 1 of the WDT Master register to 1
Writing the value 40Hto the WDT Command register
Clearing Bit 1 to 0in the Master register.
Core code at logical address 0000Btypically identifies a Reset if the SP contains
0000B. At reset, two bits in the WDT Master register (WDTMR) help identify
the cause of the reset. Bit 3 is 1for a Power On Reset, while Bit 2 is 1for a WDT
Reset. Reading The WDTMR clears these bits for subsequent reads.
PROGRAMMABLE RELOAD TIMERS (PRTS)
The Z80S183/Z80L183 includes two Programmable Reload Timers called PRT0
and PRT1. Each includes a 16-bit down-counter that can be read at any time, and
a reload value that can be dynamically programmed. Each PRT can interrupt the
processor when it counts down to 0 and reloads.
0QVGꢄ On other 8018x family devices, PRT1 has waveform-generation capability on a
pin called TOUT, but on the Z80S183/Z80L183 this function is superseded by the more
capable Programmable Output Generator (POG).
“Programmable Reload Timer (PRT) Registers” on page 107, details the PRT
registers. Reset clears both Timer Downcount Enable bits (TDE1, TDE0) in the
Timer Control register to 0, which prevents PRT operation.
Starting a PRT
To start a PRT:
1. Write the initial down-count value to the Timer Data Registers (TMDR0L and
TMDR0H, or TMDR1L and TMDR1H)
2. Write the second (and possibly constant) down-count value to the Timer
Reload Registers (RLDR0L and RLDR0H, or RLDR1L and RLDR1H)
3. Read the Timer Control Register (TCR)
4. Set the appropriate Timer Downcount Enable bit (TDE0 or TDE1) to 1.
5. Set or clear the corresponding Timer Interrupt Enable bit (TIE0 or TIE1)
depending on whether an interrupt is desired when the count is decremented
to 0.
6. Write the result value back to the TCR.
46
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROGRAMMABLE RELOAD TIMERS (PRTS)
OPERATIONAL DESCRIPTION
The read-modify-write procedure of steps 3-6 ensures that starting one PRT does
not affect the operation of the other. Applications that only use one PRT can
simply write the desired value to the TCR instead.
Stopping a PRT
To stop a running PRT:
1. Read the TCR.
2. Clear the PRT’s TDE bit.
3. Write the result value back to the TCR.
A PRT may be stopped when its timing function is no longer needed, or before
rewriting the RLDR value as described in the next section.
PRT Operation
While a PRT is running, it decrements the down-counter every 20 PHIclocks.
When it counts down to 0, a PRT automatically performs the following actions:
1. Reloads the TMDR from the RLDR.
2. Sets the TIE bit in the TCR to 1.
3. Requests an interrupt if the TIE bit in the TCR is 1.
After reading a TIF bit as 1in the TCR, software clears it by reading either half of
that PRT’s TMDR. However, reading a TMDR, without first reading a TIF bit as
1in the TCR, does not clear the TIF bit.
Software can read a down-counter, from TMDR0L and TMDR0H or TMDR1L
and TMDR1H at any time. The PRTs ensure that the two 8-bit values read by IN0
instructions are consistent, provided that software reads TMDR0L or TMDR1L
first. Reading one of these registers captures the more-significant byte of the
down-counter in a separate 8-bit latch, from which the value is provided when
software subsequently reads TMDR0H or TMDR1H.
Writing an RLDR. Software can write a new reload value to RLDR0L and
RLDR0H or RLDR1L and RLDR1H, while a PRT is running, but there is no
hardware safeguard against the down-counter decrementing to 0between the two
8-bit OUT0instructions needed to write the new reload value. When this occurs,
the value loaded into the down-counter may be incorrect.
When a new reload value is written in response to a PRT interrupt or to detecting
a TIF Bit 1 in the TCR, and the count values are large enough to prevent this
problem, software can write the RLDR. Otherwise software must perform the
following steps to load an RLDR:
1. Reads the Timer Control Register (TCR).
2. Clears the PRT’s TDE bit.
3. Writes the result back to the TCR.
4. Writes the PRT’s RLDR (L and H, in either order).
PS000501-XMP1299
Preliminary Z80S183/Z80L183
47
OPERATIONAL DESCRIPTION
REAL TIME CLOCK (RTC)
5. Writes the value from step 1 (with the TDE Bit 1) back to the TCR.
Handling PRT Interrupts
When the conditions noted in “On-Chip Interrupt Handling” on page 22 are met
with respect to an interrupt request from a PRT, the processor reads the address of
the interrupt service routine from memory at address (I : IL : 4) for PRT0, or
(I : IL : 6) for PRT1. The PRT ISR performs the following actions:
1. Save as many registers of the interrupted process as it may use (worst case), by
means of PUSH, EXAF,AF’, and/or EXXinstructions.
2. Read the TCR, verifying that the TIF bit is set to 1.
3. Read the PRT’s TMDRL register to clear the TIF bit, preventing another
interrupt for the same zero-count.
4. When the RLDR value must be changed for the next down count sequence, the
ISR proceeds as described in “Writing an RLDR”, described previously.
5. Next, the ISR performs any necessary time-periodic functions in service to the
overall application.
6. When these timer functions are completed, the ISR restores the saved registers,
and returns to the interrupt process using EIand RETinstructions.
When both PRTs are active and both are started and stopped, either at interrupt or
mainline level, the mainline code that reads, modifies, and writes the TCR must
protect against conflicts with an ISR for the other PRT. It surrounds the read-
modify-write sequence (steps 1–5 in “Writing an RLDR” on page 47) with DIand
EIinstructions.
PRTs and Reset. Both TMDRs and both RLDRs reset to FFFFH, and the TCR
resets to all 0, which inhibits PRT operation until a TDE bit is set.
REAL TIME CLOCK (RTC)
The Real Time Clock module operates like a watch chip, maintaining readable
registers ranging from seconds to centuries. An application that uses the RTC
must provide it with one of several specific time bases. A 32.768 crystal can be
connected to the LFXTALand LFEXTALpins, or a 50- or 60-Hz clock derived
from AC power can be connected to the PC0pin.
The RTC also includes an alarm function. Programmable registers containing
alarm seconds, minutes, and hours are continually compared to the corresponding
clock values. When all three registers match, the RTC can interrupt the processor.
When a Snooze function is required, it must be implemented by software.
The section titled, “Real Time Clock (RTC) Registers” on page 111, describes the
registers in the RTC. All of them are read/write. After software sets these regis-
ters, the RTC maintains the time provided there is Power On the VDD pins. Reset
has no effect on the RTC.
0QVGꢄ The Register Write Enable bit must be set as described on page 29, before any of
the RTC registers can be written.
48
Preliminary Z80S183/Z80L183
PS000501-XMP1299
REAL TIME CLOCK (RTC)
OPERATIONAL DESCRIPTION
Configuring the RTC
First, software must select the time base for the RTC: a 32.768 KHz crystal on the
EXTALand LFEXTALpins, or a 50- or 60-Hz clock on the PC0pin, in Bits 4–3 of
the RTC Command/Status register. The RTC divides the selected base clock by
32768, 50, or 60 to produce a 1 Hz clock that increments the Seconds register.
Setting the Time and Date.
The first step in setting the time and date is to determine them from a user inter-
face or a network or serial link. Next, software must convert the time and date to
the BCD format used in the RTC registers. The RTC does not include any hard-
ware support for deriving the day of the week from the other values. Finally, soft-
ware writes these values to the RTC Seconds, Minutes, Hours, Day of the Week,
Date, Month, Year, and Century registers.
0QVGꢄ the RTC registers increment in Binary Coded Decimal (BCD) format, and values
written to these registers must be encoded in this format. In most of the RTC registers,
Bits 7-4 contain a tens digit and Bits 3-0 contain a units digit. Neither field may contain
any of the values 1010Bthrough 1111B. Most of the RTC registers have further
restrictions on the range of values that can be written to them, which are noted later in
“RTC Incrementing”.
Writing the RTC registers. While writing a new time and date into the RTC
registers, there is a slight chance that a 1 Hz clock edge that causes a rollover will
occur between writes, so that the registers contain the wrong value. To protect
against this possibility:
1. Write all of the registers starting with the Seconds register.
2. Read the Seconds register.
When the value from step 2 is less than the value written to the Seconds register in
step 1, a rollover occurred and the RTC registers may be wrong: Return to step 1.
Reading the RTC registers. When reading the RTC registers, there is a slight
chance that a 1Hz clock edge that causes a rollover will fall between reads, so that
the set of values read is wrong. To protect against this possibility:
3. Read all the registers, starting with the Seconds register.
4. Read the Seconds register again.
When the Seconds value from step 2 is less than the Seconds value from step 1, a
rollover occurred: return to step 1.
RTC Operation
RTC Incrementing. This section describes the functions of clocks and calendars.
1. The Seconds register rolls over from 59 to 0, at which time the Minutes
registers is incremented.
2. The Minutes register rolls over from 59 to 0, at which time the Hours register
is incremented.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
49
OPERATIONAL DESCRIPTION
REAL TIME CLOCK (RTC)
3. The Hours register rolls over from 23 to 0, at which time the Day of the Week
and Date registers are incremented. The RTC is a 24-hour clock.
4. The Day of the Week register rolls over from 7 to 1.
5. The contents of the Month, Year, and Century registers determine how the
Date register rolls over. When the Date register rolls over, the Month register
is incremented.
–
When the Month is 1, 3, 5, 7, 8, 10, or 12, the Date register rolls over from
31 to 1.
–
–
When the Month is 4, 6, 9, or 11, the Date register rolls over from 30 to 1.
When the Month is 2 and the Year and Century registers indicate a leap
year, the Date register rolls over from 29 to 1. Otherwise it rolls over from
28 to 1.
6. The Month Register rolls over from 12 to 1, at which time the Year register is
incremented.
7. The Year register rolls over from 99 to 0, at which time the Century register is
incremented.
Setting and Polling the Alarm. To set an alarm, write the Alarm Seconds, Alarm
Minutes, and Alarm Hours registers. The RTC continually compares these values
with those in the Seconds, Minutes, and Hours registers, and sets the Alarm bit
(Bit 7) in the RTC Control/Status register (RTCCS) whenever all of these regis-
ters are equal. When the RTC Alarm interrupt is disabled, software can poll Bit 7
in the RTCCS periodically to detect an Alarm.
Handling an Alarm Interrupt. When an interrupt is desired when the RTC sets the
Alarm bit, set Bit 6 (IE) in the RTC Control/Status register after writing the three
Alarm registers. Thereafter, when the Alarm bit (RTCCS7) is 1and the conditions
in “On-Chip Interrupt Handling” on page 22 have been met with respect to the RTC
request, the Z80S183/Z80L183 responds by fetching the RTC interrupt service
routine (ISR) address from memory at address (I : IL : 26). Most of this ISR is appli-
cation-dependent, but as a minimum the ISR performs the following actions:
1. Save as many registers of the interrupted process as it may use, using PUSH,
EXAF, AF’, and/or EXXinstructions.
2. Check that the Alarm bit (Bit 7) of the RTC Control/Status (RTCCS) register
is 1. When Bit 7 is 0, the ISR may log this unknown interrupt, before restoring
the saved register values and returning to the interrupted process using EIand
RETinstructions.
When a future alarm at a different time is desired, the ISR must reprogram the
Alarm registers with that time. When no future Alarm is required, clear the IEbit
in the value read in step 2. When an Alarm is required at the same time tomorrow,
increment the Alarm time by 1 second, and write that value to the Alarm registers.
This action prevents a continuing match from setting the Alarm bit immediately.
3. Clear Bit 7 in the value read in step 2, and write it back to RTCCS.
50
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DIGITAL/ANALOG CONVERTER (DAC)
OPERATIONAL DESCRIPTION
4. Restore the saved registers after application-dependent processing is complete,
and return to the interrupted process by means of EIand RETinstructions.
When an Alarm at the same time tomorrow was needed in step 2, when the next
RTC Alarm interrupt occurs (1 second later) repeat steps 1–4, decrementing the
Alarm registers back to their original value.
DIGITAL/ANALOG CONVERTER (DAC)
The Digital-to-Analog Converter converts 10-bit digital values to analog voltages
using a 10-stage resistor ladder. The DAC output is protected against latch-up and
can drive output loads.
The AV and AGNDpins provide the analog power for both the ADC and DAC
DD
modules. To achieve the specified accuracy, the voltages must be within the spec-
ified tolerances of V and V respectively. For maximum accuracy, isolate and
DD
SS
filter AV and AGNDfrom power supply noise.
DD
“Digital-to-Analog Converter (DAC) Registers” on page 117, describes the I/O
registers associated with the D/A Converter. These registers include a Data
register containing the eight most-significant bits of the digital value, and a
Control register (DACCR) that holds the two least-significant bits plus configura-
tion and enable bits.
Reference Voltage Selection
Bits 5–4 of the Control register select the reference voltage, which is multiplied
by the binary fraction represented by the digital value to be converted, to obtain
the voltage produced on the AOUTpin.
DACCR5–4
Reference Voltage
0X
10
11
PA0/VREF pin
internal 4.2 V
internal 2.6 V
Notes:
1. The DAC and A/D Converter share the PA0/VREFpin as an external analog
reference voltage.
2. The reference voltage selected by Bits 5–4 must be less than AV and
DD
V
.
DD
'ZCORNGꢄꢀWhen the 10-bit binary value in the Data and Control registers is
1000000000B, and Bits 5–4 are 00B, the voltage on the AOUTpin is 2.1 volts.
Programming the DAC. To convert a 10-bit value to an analog voltage:
1. Write the eight most-significant bits of the value to the DAC data register.
2. Write the two least-significant bits of the value to Bits 7–6 of the DAC Control
register, along with the reference voltage selection in Bits 5–4, and a 1in Bit
2 to enable analog voltage drive on the AOUTpin.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
51
OPERATIONAL DESCRIPTION
ANALOG/DIGITAL CONVERTER (ADC)
The voltage on AOUTsettles to the programmed value within 1 microsecond after
step 2.
Conversion Time Waffle. At the time this document was written, there is concern
about the DAC conversion time in one case. When the selected reference voltage,
times the fraction represented by the digital value, is within 0.5 volts of AV and
DD
V
, settling may take longer than 1 microsecond. This issue will be character-
DD
ized and clarified when silicon is available.
ANALOG/DIGITAL CONVERTER (ADC)
The Analog-to-Digital Converter is a 10-bit successive-approximation converter
with 8 input pins. Conversion time is 64 PHIclocks, or about 1.92 microseconds
at 33 MHz. Software determines the completion of a conversion using an interrupt
or by polling.
The AV and AGND pins provide the analog power for both the ADC and DAC
DD
modules. To achieve the specified accuracy, the voltages on these pins must be
within the specified tolerances from V and GND respectively. For maximum
DD
accuracy, isolate and filter AV and AGND from power supply noise.
DD
Though the ADC can operate with small analog reference voltages, noise and
offset are independent of the reference. Accuracy is maximized for reference volt-
ages close to AV and V
.
DD
DD
“Analog to Digital Converter (ADC) Registers” on page 118, describes the I/O
registers associated with the A/D Converter. They include two Control registers,
ADCC0 and ADCC1, and a Data register from which the software can read the
most-significant eight bits of the digital value when a conversion is complete.
Channel Selection
The ADC can divide the voltage on any of the pins in Port D by the reference
voltage, to produce a 10-bit binary fraction. This fraction can be read from the
Data register and ADCC1, when the conversion is complete. Bits 2–0 of ADCC1
select the port pin for each conversion:
ADCC1 2–0
Selected Channel
000
001
010
011
100
101
110
111
PD0/AC0/DREQ0
PD1/AC1/DREQ1
PD2/AC2
PD3/AC3
PD4/AC4
PD5/AC5
PD6/AC6
PD7/AC7
52
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ANALOG/DIGITAL CONVERTER (ADC)
OPERATIONAL DESCRIPTION
Reference Voltage Selection
Bits 1–0 of ADCC0 select the reference voltage by which the voltage on the
selected channel is divided, to produce the 10-bit binary fraction.
ADCC0 1–0
Reference Voltage
0X
10
11
PA0/VREF pin
internal 4.2 V
internal 2.6 V
Notes:
1. The D/A Converter and ADC share the PA0/VREFpin as an external analog
reference voltage.
2. The reference voltage selected by Bits 1–0 must be less than AV
DD
and V
.
DD
Programming the ADC
To convert the voltage on one of the Port D pins to a 10-bit binary fraction:
1. Write ADCC0 Bits 1–0 to select the desired reference voltage, with a 1in Bit
2 to enable the A/D converter.
2. Write ADCC1 Bits 2–0 to select the desired Port D pin, with a 1in Bit 3 to start
the conversion. Include a 1in Bit 5 if an interrupt at the end of the conversion
is desired. If so, refer to the next section, “Handling an ADC Interrupt”.
3. Read ADCC1 until Bit 4 is 1, indicating polled operation. This operation
indicates that the conversion is complete. Because the conversion always takes
64 clocks, 21 NOPinstructions can be substituted for reading ADCC1, but
NOPsrequire more memory.
4. Read the ADC Data register to obtain the eight most-significant bits of the
result. When all 10 bits of the result are needed, read ADCC1 (Bits 7–6 are the
two least-significant bits).
Handling an ADC Interrupt
An interrupt takes at least 18 PHIclocks, plus the overhead of saving and restoring
registers, reenabling interrupts, and returning to the interrupted process. Because a
complete ADC conversion takes 64 clocks, many Z80S183/Z80L183 applications
use polling rather than ADC interrupts, for A/D conversions initiated by the
processor.
A/D interrupts are more useful for A/D conversions initiated by the POG module,
described in “Programmable Output Generator (POG)” on page 54.
Regardless of the initiator, when the conditions noted in “On-Chip Interrupt
Handling” on page 22 are met with respect to an ADC interrupt request, the
Z80S183/Z80L183 fetches the address of the ADC interrupt service routine (ISR)
from memory at (I : IL : 24). This ISR is application-dependent, but at a minimum
it must:
PS000501-XMP1299
Preliminary Z80S183/Z80L183
53
OPERATIONAL DESCRIPTION
PROGRAMMABLE OUTPUT GENERATOR (POG)
1. Save as many registers of the interrupted process as it may use, using of PUSH,
EXAF,AF’, and/or EXXinstructions.
2. Read the Data register into H and ADCC1 into L when all 10 bits are required.
When only the most-significant eight bits of the result are required, the ISR
reads ADCC1 into A to clear the conversion complete flag and prevent further
interrupts for the same conversion, and then read the Data register into A.
3. Process the resulting value. This step is application-dependent.
4. Start another conversion, if desired, as in steps 1–2 of “Programming the ADC”.
5. Restore the registers using POP, EXAF, AF’and/or EXXinstructions.
6. Return to the interrupted process using EIand RETinstructions.
Sampling and Conversion
During the first 3 PHIPHIclocks of the 64 required for a complete conversion,
the ADC samples the voltage on the selected pin. To ensure the accuracy of the
conversion, the voltage must remain constant during this time. During the last 61
clocks of the conversion, the pin voltage can change without affecting the result.
Restarting Conversion
An A/D conversion can be started at any time. When a conversion is in progress
and a new start command is written to ADCC1, the conversion in progress is
aborted and a new conversion is initiated. Software must not change Bits 2–0 of
ADCC1 while a conversion is in progress, unless the write that changes these bits
also includes a 1in Bit 3 to start a new conversion.
Saving Power
When the ADC is not needed, a small amount of power can be saved by clearing
Bit 2 of ASCC0, shutting down the ADC.
PROGRAMMABLE OUTPUT GENERATOR (POG)
The Programmable Output Generator can be used to create multiple complex
digital waveforms and trigger A/D and D/A conversions without processor inter-
vention. In addition the POG can generate processor interrupts at selected points
during its operation.
The last 256 bytes of on-chip RAM can be read by the POG and can be read and
written by the processor. Depending on the value of Bit 5 in the System Control
Register, the processor may locate these bytes at addresses FFF00–FFFFFHor
xFF00–xFFFFH, that is, with or without decoding A19–16.
To the POG, this memory area is organized as 64 4-byte entries, each containing:
•
•
•
•
A 14- or 16-bit delay value
A 2-bit entry type
An 8- or 10-bit data value
A 6-bit address of the next entry
54
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROGRAMMABLE OUTPUT GENERATOR (POG)
OPERATIONAL DESCRIPTION
When the POG fetches an entry from RAM, it stops processing if the next-address
field in the entry is zero. Otherwise it loads the entry into internal registers and
begins counting down the delay value. When the POG has counted the delay down
to zero, it performs the action specified by the rest of the entry. The POG then
fetches a new entry using the Next Address value as A7–2 of the memory address.
The section, “Programmable Output Generator (POG) Registers” on page 120,
details the I/O registers in the POG that include:
•
•
A Control register that software can use to configure the POG
An Address/Type register into which the POG fetches control information
from each entry
•
Timer Low and High registers, into which the POG fetches a 16-bit delay value
from each entry, and then counts it down to zero.
Configuring the POG
Bits 1–0 of the Control register select the clock used to count down the delay
value in each POG entry, among PHI, PHI/256, PHI/1024, or PHI/4096.
Software must not change these bits while the POG is running. To ensure an accu-
rate delay in the first entry, software set Bits 1–0 to the desired value before
setting Bit 7 to enable POG operation.
Bit 6 of the Control register enables or disables interrupts from the POG, if and
when it encounters interrupt entries.
Other registers that affect the POG include:
•
•
•
The AFSC (“Port C Alternate Function Select (AFSC)” on page 38) controls
which Port C pins are controlled by the POG.
The DDRC and OCRC (“Data Direction Registers and Output Control Regis-
ters” on page 37) control Port C pin functions.
The System Configuration Register (SCR, page 80) controls whether the proces-
sor as well as the POG can access on-chip RAM, and if so, at what addresses.
Creating POG Entries in On-Chip RAM
Bit 6 of the System Control Register must be 1to allow the processor to set up
POG entries in on-chip RAM. Each entry includes four bytes and starts at an
address that is a multiple of 4.
When the processor first enables the POG, the POG always processes the entry at
xFF00–3Hor FFF00–3Hfirst.
When a new POG sequence is needed in the future, software can build the next
sequence in on-chip RAM while the POG is still running its current sequence,
provided that the total length of both sequences is 64 entries or less.
To accomplish this task, software builds the next sequence in those parts of the
POG RAM that are not used by the current sequence. Next, software can store the
first entry of the next sequence at location xFF00–3Hor FFF00–3H. When the
PS000501-XMP1299
Preliminary Z80S183/Z80L183
55
OPERATIONAL DESCRIPTION
PROGRAMMABLE OUTPUT GENERATOR (POG)
POG has completed its current sequence, software can start the next sequence as
described in “Starting and Polling the POG” on page 57.
Digital Data Output Entries. Figure 9 illustrates the format of a POG Digital
Data Output entry. The first two bytes contain a delay value, in the units selected
by Bits 1–0 of the POG Control register. As with all Z80/180 multi-byte binary
values, the least-significant byte is stored first, at the lower address. An all-0 delay
value indicates 65,536 clocks. The third byte holds a value that the POG is to
output to Port C after the specified delay. Bits 7–2 of the fourth and last byte hold
a non-zero address of the next entry, with 00in Bits 1–0 to identify this entry as a
Digital Data entry.
Address A1-0
00
01
10
11
7
2 1 0
00
Delay LSB
Next Address
Delay MSB
Port C Data
FIGURE 9. POG DIGITAL DATA OUTPUT ENTRY
Analog Data Output Entries. Figure 10 illustrates the format of a POG Analog
Data Output entry. The first byte, and Bits 5–0 of its second byte, contain a delay
value in the units selected by Bits 1–0 of the POG Control register. As with all
Z80/180 multibyte binary values, the least-significant byte is stored first, at the
lower address. An all-zero delay value indicates 65,536 clocks. The third byte
holds Bits 9-2, and Bits 7-6 of the second byte contain Bits 1-0, of a 10-bit value
that the POG is to output to the D/A Converter after the specified delay. Bits 7-2
of the fourth and last byte hold a non-zero address of the next entry, with 10in
Bits 1-0 identifying this entry as an Analog Data Output entry.
Address A1-0
00
01
10
11
7 6 5
0
2 1 0
10
D
1-0
Delay LSB
Delay 13-8
Data 9-2
Next Address
FIGURE 10. POG ANALOG DATA OUTPUT ENTRY
Analog Data Input Entries. Figure 11 describes the format of a POG Analog
Data Input entry. The first two bytes contain a delay value, in the units selected by
Bits 1-0 of the POG Control register. As with all Z80/180 multibyte binary values,
the least-significant byte is stored first, at the lower address. An all-0 delay value
indicates 65,536 clocks. After the specified delay, Bits 2-0 of the third byte hold a
channel (port D pin) number, the voltage on which is to be converted to a digital
value. Bits 7-2 of the fourth byte contain the non-zero address of the next entry,
and 01in Bits 1-0 identify this entry as an Analog Data Input entry.
56
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROGRAMMABLE OUTPUT GENERATOR (POG)
OPERATIONAL DESCRIPTION
Address A1-0
00
01
10
3 2 1 0
11
7
2 1 0
01
chan
(AC)
Delay LSB
Next Address
Delay MSB
not used
FIGURE 11. POG ANALOG DATA INPUT ENTRY
Interrupt Entries. Figure 12 illustrates the format of a POG Interrupt entry. The
first two bytes contain a delay value, in the units selected by Bits 1-0 of the POG
Control register. As with all Z80/180 multibyte binary values, the least-significant
byte is stored first, at the lower address. An all-0delay value indicates 65,536
clocks. The third byte of an Interrupt entry is not used. Bits 7-2 of the fourth byte
hold the non-zero address of the next entry, with 11in Bits 1-0 identifying this
entry as an Interrupt entry.
Address A1-0
00
01
10
11
7
2 1 0
11
Delay LSB
Next Address
Delay MSB
not used
FIGURE 12. POG INTERRUPT ENTRY
End of Sequence Entry. Figure 13 illustrates the format of an entry that identi-
fies the end of a POG sequence. This type of entry is 0in Bits 7-2 of its fourth
byte. The other bits in the entry can be any value. When the POG fetches such an
entry, it stops processing immediately, clearing Bit 7 of its Control register.
Address A1-0
00
01
10
11
7
2 1 0
XX
not used
not used
not used
0 0 0 0 0 0
FIGURE 13. POG END-OF-SEQUENCE ENTRY
Starting and Polling the POG
After software has built a complete POG sequence in POG RAM, including the
first entry in addresses xFF00-3Hor FFF00-3H, and the POG has completed any
previous sequence, software proceeds as follows:
1. When a change is required to the clock selection, write the new value to the
Control register as a separate step. This action ensures accuracy of the delay
associated with the first entry.
2. Write a 1to Bit 7 of the Control register, maintaining the prior clock selection
in Bits 1-0. When the sequence contains one or more Interrupt entries, enable
POG interrupts by writing a 1in Bit 6 of this value.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
57
OPERATIONAL DESCRIPTION
PROGRAMMABLE OUTPUT GENERATOR (POG)
3. The POG fetches all bits of each entry simultaneously. While the POG runs,
the software can track its progress through the sequence by reading the POG
Address/Type register.
4. When the Next Address field of an entry is non-zero, the POG counts down the
delay value specified in the first two bytes, using the clock selected by Bits 1-
0 of the Control register.
0QVGꢄ For a D/A entry, the POG automatically loads zeroes into the two most-significant
bits of the delay counter. D/A entries are limited to a 16,383 clock delay, or 65,536 for an
all-zero value.
5. After the POG has counted the delay value down to zero, it performs the action
specified by Bits 1-0 of the last byte of the entry:
–
–
–
–
Writes an 8-bit value to Port C.
Writes a 10-bit value to the D/A converter.
Starts an A/D conversion on a particular channel.
Requests an interrupt.
6. Software can stop POG operation at any time, by clearing Bit 7 of the Control
register. Otherwise, when the POG reaches an entry with 0in its Next Address
field, it clears Bit 7 of the Control register and stops. Software polls the Control
register to detect when this occurs, or the last active entry in the sequence can
be an interrupt entry.
Handling POG Interrupts
When Bit 6 of the POG Control register is 1and the POG fetches an Interrupt
entry, it requests an interrupt. When the conditions noted in “On-Chip Interrupts”
on page 22 have been met for this request, the processor fetches the address of the
POG interrupt service routine from memory at address (I : IL : 18) The ISR
performs the following operations:
1. Save as many registers of the interrupted process as it may use (worst case),
using PUSH, EXAF, AF’, and/or EXXinstructions.
2. Read the POG Status register and verify that Bit 5 (Interrupt Pending), is 1.
If not, the ISR can store logging information in memory if desired, before
restoring the registers and using EIand RETinstructions to return to the
interrupted process.
3. Clear Bit 5 if IP is 1, in the value read in step 2, and write the result back to the
Control register. This action clears the IP bit and prevents further interrupts for
the same POG event.
4. Read the Address/Type register, if there is more than one Interrupt entry in the
POG sequence, read the Address/Type register to determine which entry
caused this interrupt.
5. Reads ADC Control Register 1 and checks the conversion complete bit if this
interrupt follows the start of an A/D conversion by the POG. Assuming that the
delay in the interrupt entry has guaranteed that the conversion is complete, read
58
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
OPERATIONAL DESCRIPTION
the result value from the ADC Result register and, if desired, the two least-
significant bits from Control Register 1.
0QVGꢄ Software can use either an A/D interrupt or a POG interrupt to signal the comple-
tion of an A/D conversion initiated by the POG.
6. Other processing is application-dependent. When the interrupt marks the end
of a sequence, and another sequence must be run immediately, the ISR can start
that sequence as described above.
7. Restore the saved registers, then use EIand RETinstructions to reenable
interrupts and return to the interrupted process.
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
The ASCIs are asynchronous full-duplex UARTs with the following features:
•
•
•
•
•
•
•
7- or 8-bit data
Odd, even, or no parity
One or two Tx Stop bits
Checking for Parity, Framing, and Overrun errors
Break Generation and Detection
Choice of two Baud Rate Generators (BRGs)
Rx and Tx interrupts
• DCDand CTSpins on ASCI0
•
•
Operation with the on-chip DMA channels
A MULTIPROCESSOR mode with an extra bit designating address vs. data
characters
The registers associated with the ASCIs are described in section “Async Serial
Communications Interface (ASCI) Registers” on page 122. Control registers A
and B (CNTLA0, CNTLA1, CNTLB0, and CNTLB1) and the Extension Control
registers (ASEXT0, ASEXT1) are typically written one time each, to configure an
ASCI. The Status registers (STAT0 and STAT1) indicate the current state of each
ASCI’s Receiver and Transmitter. Under control of this status, software can write
bytes to be transmitted to the Transmit Data Registers (TDR0 and TDR1), and
read received bytes from the Receiver Data Registers (RDR0 and RDR1).
Basic Clocking
Each ASCI uses the same clock for both transmitting and receiving. Because the
Z80S183/Z80L183 does not include CKApins for either channel, clocking for
each ASCI must be derived from one of its two baud rate generators (BRG).
Furthermore, Bits 2-0 of each CNTLB register must not be left 111, as they are
after a reset.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
59
OPERATIONAL DESCRIPTION
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
To use the older version of the BRG that is compatible with the original ZiLOG
Z80180:
•
Clear Bit 3 (BRG Mode) of the Extension Control register, to select the old
BRG.
•
Write Bit 5 (PS) and Bits 2-0 (SS) in the CNTLB register to select the value by
which the old BRG divides the PHIclock to obtain the Basic Clock, as
described in Table 15.
TABLE 15. OLD BRG DIVISION FACTORS
PS (CNTLB5) SS (CNTLB2-0) Basic Clock = PHI Divided By
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
10
20
40
80
160
320
640
No clock
30
1
60
120
240
480
960
1920
No clock
To use the newer BRG that is compatible with the ZiLOG SCC family:
•
•
Set Bit 3 (BRG mode) of the Extension Control register, to select the new BRG.
Write a 16-bit time constant to the Time Constant Low and High registers. This
value is the factor by which the PHIis divided to produce the basic clock,
divided by 2, minus 2. The new BRG calculates the basic clock as:
basic clock = PHI / (2 (TC+2)
Clock Mode. Since neither ASCI has a clock pin on the Z80S183/Z80L183, the
1X ISOCHRONOUS mode that can be used on other 8018x family members,
cannot be used on the Z80S183/Z80L183, and Bit 4 (X1 clock) in the Extension
Control register must be 0.
When the DR bit (Bit 3) in the CNTLB register is 0, the ASCI divides its basic
clock by 16 to obtain the serial bit rate. When DR is 1, the ASCI divides the basic
clock by 64.
60
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
OPERATIONAL DESCRIPTION
Async Transmission
Figure 14 illustrates a single asynchronous character on the TXAor RXApin.
When a transmitter is disabled, or when it has completed sending all characters
that the software or a DMA channel has provided, the transmitter maintained a
High on the TxDpin. This state is also called 1 or Mark.
TXA
or RXA
Start bit
Data bits
First Stop bit
Stop/idle
FIGURE 14. AN ASYNCHRONOUS CHARACTER
When software or a DMA channel provides a character to an idle ASCI transmitter:
1. It drives TXALow on the next falling edge of the basic clock, to begin a start
bit, and maintains TXALow for 16 or 64 basic clocks depending on the value
of DR.
2. It switches TXAto the state of the least-significant bit (Bit 0) of the character,
and holds that for 16 or 64 clocks.
3. It repeats step 2 for each next-more-significant bit of the character, through the
most-significant bit (Bit 6 or 7) of the character, and for a parity or MP bit if
one of these is enabled.
4. It drives TXAHigh (1, Mark) again for a Stop bit, and maintains it High for at
least 16 or 64 clocks.
5. It continues this High of another 16 or 64 clocks if Bit 0 of its CNTLA register
is 1to select two Tx Stop bits.
The Tx character is now complete. When software or a DMA channel has provided
another character to send, the transmitter begins another Start bit as described
above. Otherwise, it maintains a High on TXAHigh until a character is provided.
Async Reception
The Receiver has a more complex task. When it is first enabled, or after a char-
acter has been received the receiver samples the RXApin on the rising edge of
each basic clock.
1. When RXAis High, it remains in this state of waiting for a Start bit.
2. When the receiver samples RXALow, it counts off half a bit time (8 basic
clocks if DR is 0, or 32 basic clocks if DR is 1) then samples RXAagain. When
RXAis High, the receiver rejects the transient Low state on RXAas not
representing a Start bit, and returns to step 1. The RXApin is sampled again.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
61
OPERATIONAL DESCRIPTION
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
3. When RXAis still Low after half a bit time, it validates the Start bit. The
receiver then counts off the number of basic clocks in a bit—16 if DR is 0, 64
if it is 1, — and samples RXAfor the Least Significant data bit (Bit 0). It
continues this routine for each progressively significant data bit (through Bit 6
or 7), and for a Parity or MP bit if either is enabled.
Finally, the receiver counts off 16 or 64 more basic clocks and samples the first
Stop bit. When the receiver’s basic clock is close to the clock that the transmitter
used to send the character, this occurs near the middle of the first Stop bit. When
there is no noise or other error on the line, the receiver samples the Stop bit as
High/1/Mark. However, if the receiver’s and transmitter’s clocks were sufficiently
different, or if there is noise or an error on the line, the receiver samples the Stop
bit as Low/0/Space. This latter situation is called a framing error. When a
framing error occurs, the receiver sets an error bit that accompanies the character
through the receiver FIFO. The receiver then sets the FE bit in the STAT register
when the character becomes the oldest one in the FIFO.
The received character is now complete, and the receiver returns to step 1 and
samples the line for a new Start bit.
Combined Effect of BRG and Clock Mode
Combining the operation of the BRGs and the division by 16 or 64 performed by
the transmitter and receiver, where:
•
•
•
•
•
•
•
Serial rate is in bits/second
PHI is the system clock frequency
PS is the value written to Bit 5 of CNTLB (0or 1)
^ indicates exponentiation (2 to the power)
SS is the binary value of Bits 2-0 of CNTLB (0 thru 6)
DR is Bit 3 of CNTLB (0or 1)
TC is the 16-bit value in the ASTCL and ASTCH registers:
Old BRG: serial rate = PHI / ((10 + 20*PS) * (2 ^ SS) * (16 + 48*DR))
New BRG: serial rate = PHI / (2 * (TC+2) * (16 + 48*DR))
TC = (PHI / (serial rate * (32 + 96*DR))) - 2
Options
7 or 8 Data Bits. When Bit 2 of CNTLA is 0, the transmitter sends, and the
receiver accumulates, 7 data bits per character. When CNTLA2 is 1, the trans-
mitter sends, and the receiver accumulates, 8 data bits per character.
Parity. When Bit 1 of CNTLA is 1, the transmitter accumulates and sends a Parity
bit after the data bits, and the receiver samples and checks these bits. When
CNTLA1 is 1, a 1in Bit 4 of CNTLB selects odd parity and 0in Bit 4 selects
even parity. Odd Parity means that a correct character includes an odd number of
62
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
OPERATIONAL DESCRIPTION
1 bits, including the Parity bit. Even Parity means that a correct character includes
an even number of 1bits.
When the receiver samples the Parity bit in the incorrect state for a character, it
sets an error bit that accompanies the character through the receiver FIFO. The
receiver then sets the PE bit in the STAT register when the character becomes the
oldest one in the FIFO.
Transmit Stop Bits. When Bit 0 of CNTLA is 0, the transmitter sends a
minimum of one Stop bit between characters. When CNTLA0 is 1, it sends at
least two Stop bits between characters. Selecting two Stop bits has been known to
work around timing mismatches between a transmitter and a receiver.
0QVGꢄ The ASCI receivers on the Z80S183/Z80L183 check only one Stop bit, regardless
of Bit 0 of CNTLA. This is also true of ASCI receivers on other current 8018x family
members, as well as other UARTs, but on the original Z80180, the ASCIs actually
checked two Stop bits if CNTLA0 was 1.
Status
Break Conditions. Break conditions date back to the early days of async commu-
nications using Teletypewriters that were functionally half-duplex in that text
could only flow in one direction at a time.
When the operator of a receiving Teletype had a condition, or something to say,
and wanted to interrupt the data from the other machine, the operator could press a
Break key. Pressing this key drove the line to the 0/Space state for several char-
acter-times, which switched on a light at the other machine, and stopped its paper
tape reader if it had been in use.
A Break is still defined as at least two character times of consecutive zeroes on the
line. A receiver sees this as one or more all-0 characters with Framing errors.
Software can send a Break by setting Bit 0 of the Extension Control register.
Before doing this, software can ensure that any characters previously written to
the Transmit Data Register have been sent, by monitoring Bit 0 of the Extension
Control register. The duration of a transmitted Break is under software control—
the Break is terminated by clearing the ASEXT Bit to 0.
While receiving an all-zero character with a Framing error indicates a Break, Bit 1
of the Extension Control register provides more specific break detection. When
the receiver detects an all-zero character with a framing error, it sets a Break
status bit that accompanies the character through the receiver FIFO. The receiver
sets Bit 1 in the ASEXT register to 1when such a character becomes the oldest
one in the FIFO.
After detecting a Break, the receiver does not assemble any further characters until
the RXApin returns to High/1/Mark, signalling the end of the Break condition.
Rx Overrun. The ASCIs in the Z80S183/Z80L183 contain 4-character Rx FIFOs
between the Rx Shift registers and Receive data registers. When a receiver
receives a character and there are already 4 characters in the FIFO, an overrun
status bit is set that accompanies the preceding character through the FIFO. The
PS000501-XMP1299
Preliminary Z80S183/Z80L183
63
OPERATIONAL DESCRIPTION
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
receiver then sets the OVRN bit (Bit 6 in the STAT register) to 1when that char-
acter becomes the oldest in the FIFO.
The receiver discards the character that triggers the overrun condition, and subse-
quent characters, until the last good character has come to the top of the FIFO so
that OVRNis 1, and software writes a 0to the EFR bit to clear OVRN.
Receive Status. There are four receive status bits in the STAT register and one in
the Extension Control register. RDRF, Bit 7 of STAT, is 1whenever there is at
least one received character in the Rx FIFO. RDRF is cleared:
•
•
•
•
When the software or a DMA channel has read all characters out of the Rx FIFO
By a reset
In I/O STOP mode
On ASCI0, when the DCD0pin is autoenabled and is High.
FE, PE, and OVRNin the STAT register are 1when a character with a framing
error or parity error, or the last character before an Rx Overrun, comes to the top
of the receive FIFO. Similarly, Bit 1 in the Extension Control register is 1when a
Break character comes to the top of the FIFO.
Any of these bits remain 1even if the character associated with the condition is
read out of the receive FIFO. That is, these bits latch an error or exception condi-
tion. All four of these bits are cleared to 0by reading CNTLA, clearing Bit 3
(Error Flag Reset, or EFR) to 0, and writing the result back to CNTLA.
This action also allows the receiver to put subsequent characters into the receive
FIFO after an Overrun, and if the receiver is handled by a DMA channel, allows
the channel to service the receiver again.
Modem Control/Status. The only ASCI modem control or status signals on the
Z80S183/Z80L183 are DCD0 and CTS0. The state of the DCD0 pin can be read
as Bit 2 of the STAT0 register, and that of CTS0 as Bit 5 of CNTLB0. Both bits
read as 1if the pin is High/inactive.
Bit 6 in the Extension Control register controls whether DCD0 automatically
enables and disables the receiver. Bit 5 controls whether CTS0 automatically
enables and disables the transmitter.
In each case, if one of these ASEXT bits is 0, as it is after a reset, then a Low on
the pin allows the module to operate. However, a High disables the module. When
one of these ASEXT bits is 1, software can read the state of the pin, but the pin
does not enable or disable the transmitter or receiver.
When ASEXT0 Bit 6 is 0, a High on DCD0 forces the status bits RDRF, PE, FE,
OVRN, and RxBreakto 0. When DCD0 goes Low thereafter, the next read of the
STAT register still contains a 1in Bit 2 (DCD0). Subsequent reads of STAT indi-
cate current status.
When ASEXT0 Bit 5 is 0, a High on CTS0 clears the TDRE bit in STAT. This
action prevents software or a DMA channel from putting further Tx data into
64
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
OPERATIONAL DESCRIPTION
TDR. As many as three characters (one from the Tx shift register, two from the
2-stage Tx FIFO) can appear on TDA0 after CTS0goes High.
DMA Operation
On the Z80S183/Z80L183, data can be transferred to or from either ASCI by
either DMA channel. Setup for these operations is covered in the following ASCI
and DMA topics:
“Starting a Transmitter” later on this page,
“Starting a Receiver” on page 66,
“Handling ASCI Interrupts” on page 66, and
“Setting Up a DMA Transfer” on page 43.
A DMA channel used with an ASCI transmitter must be programmed to use the
appropriate TDRE flag as its DMA request, and must be set up for edge-sensitive
DMA request.
A DMA channel used with an ASCI receiver must be programmed to use the
appropriate RDRF flag as its DMA request, and can be used in either edge- or
level-sensitive mode. In this application, software sets both the RIE bit in the
STAT register, and Bit 7 of the Extension Control register, enabling ASCI receive
interrupts in the event of errors, but not for every received character.
0QVGꢄ The signal that an ASCI receiver provides as a Request to a DMA channel, is not
simply RDRF but rather (RDRF and not PE and not FE and not OVRN and not RxBreak).
DMA operation will be suspended if any of these errors or exceptional conditions occurs.
This operation is performed so that software can determine the point in the receive data
stream at which the error or condition occurred.
Programming Techniques
Starting a Transmitter. A Software can enable a transmitter at the same time as
its associated receiver, or separately, as follows:
1. Write the CNTLB register to set the clocking and basic options.
2. Write the Extension Control register to select the BRG mode and, on ASCI0,
the mode of the CTS0pin.
3. Set Bit 0 (TIE) in the STAT register to enable transmit interrupts, otherwise,
clear it.
4. Set Bit 5 to 1of CNTLA to enable the transmitter.
The TDRE flag is set immediately. When transmit interrupts were enabled in step
3, an interrupt occurs immediately.
0QVGꢄ When a DMA channel is to provide data to the transmitter, software can set it up
whenever transmit data is available, including selecting TDRE as the DMA Request.
Edge-sensitivity is required on the DMA request for transmit/output devices. When TDRE
is set before the DMA channel is started, device software sets up the DMA to not include
the first Tx character, and then write first character to the TDR, to initialize the ASCI-
DMA handshake.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
65
OPERATIONAL DESCRIPTION
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
Starting a Receiver. A Software can enable a receiver at the same time as its
associated transmitter, or separately, as follows:
1. Write the CNTLB register to set the clocking and basic options.
2. Write the Extension Control register to select the BRG mode and, on ASCI0,
the mode of the DCD0pin. When the receiver is to be handled by a DMA
channel, set Bit 7 of the Extension Control register to 1 to block the RDRF flag
from requesting a receive interrupt.
3. Set Bit 3 (RIE) in STAT to 1if receive interrupts are desired, otherwise clear it.
4. Set up the DMA channel if the receiver is to be handled by a DMA channel.
Select the channel, including selecting RDRF as the DMA Request signal.
5. Set the Bit 6 in CNTLA to enable the receiver.
RDRF is 1when there is data in the Rx FIFO. When RDRF interrupts are enabled,
an interrupt occurs at that time.
Polled Transmission. After starting a transmitter without interrupts enabled,
while there is data to send:
1. Read the STAT register (preferably more often than once per character-time)
until Bit 1 (TDRE) is 1.
2. Write the next character to be transmitted to the TDR. When there is more data
to transmit, return to step 1.
Polled Reception. After starting a receiver without interrupt enabled:
1. Read the STAT register, at least once per character time, until it detects Bit 7
(RDRF).
2. Read a received character from the RDR.
3. Process process the received character, then return to step 1.
Handling ASCI Interrupts. A 1in Bit 0 (TIE) of an ASCI’s STAT register
enables transmit interrupts, and a 1in Bit 3 (RIE) enables receive interrupts.
When any of following are true:
•
•
•
•
TIE and TDRE are both 1
RIE is 1and any of OVRN, PE, FE, or RxBreak(ASEXT Bit 1) are 1
RIE is 1, Bit 7 of the Extension Control register is 0, and RDRF is 1
RIE is 1, Bit 6 in the Extension Control register is 0, and the DCD0pin is High
for ASCI0
then an ASCI requests an interrupt from the processor. When the conditions listed
in “On-Chip Interrupt Handling” on page 22 are met with respect to this request,
the processor fetches the address of the interrupt service routine (ISR) from
(I : IL : 14) for ASCI0, or from (I : IL : 16) for ASCI1.
An ASCI ISR that handles both kinds of interrupts must:
66
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
OPERATIONAL DESCRIPTION
1. Save as many registers as it may use, by means of PUSH, EXEXAF, AF’, and/
or EXXinstructions.
2. Read the STAT register for this ASCI.
3. When TIE and TDRE in STAT are both 1:
a. If another Transmit character is available, write it to the TDR.
b. If not, clear the TIE bit until another Tx character is available.
4. When RIE in STAT is 1and any of OVRN, PE, FE, or RxBreak(ASEXT Bit 1)
are 1:
a. When Bit 7 of the Extension Control register is 1, indicating that a DMA
channel is handling receive data, read the DSTAT register, clear the DE
and DWE bits for that DMA channel, and write the result back to DSTAT.
b. Read the CNTLA register, clear Bit 3 (EFR) to 0and write the result back
to CNTLA
c. Read the associated character from the RDR
d. For PEor FEconditions, applications can discard the character, replace it
with a standard error character, or treat it like other characters.
e. For an OVRNcondition (without any other error), most applications process
this last good character normally, as in step 5. An application may then post
an overrun occurred here notification in the received-data stream.
f. For Break, most applications discard the all-0 character. An application
may post a Break occurred here notification in the received-data stream.
The receiver does not assemble more all-0 characters, but waits for RDA
to go High before searching for a new Start bit.
5. When no errors are found in step 4, but RIE is 1, Bit 7 of the Extension Control
register is 0, and RDRF is 1, read the next received character from the RDR.
Process it; the simplest method is storing it at the next memory location in a
buffer.
6. When ASCI0, RIE is 1, Bit 6 in the Extension Control register is 0, and Bit 2
of STAT is 1, carrier has been lost, and the ASCI receiver does nothing until
the carrier returns. In this case, either clear RIEor set Bit 6 in the Extension
Control register, to prevent further interrupts when DCD0is High.
7. Optionally, at this point software can read STAT again, and return to step 3 if
RIE and RDRF are both 1, or TIE and TDRE are both 1. This option saves on
interrupt overhead.
8. When the ISR disabled the receive DMA channel in step 4a, it restarts the channel.
9. Finally, the ISR must restore the saved registers, and return to the interrupted
process by means of EIand RETinstructions.
Multiprocessor Mode
In this mode, the transmitter sends, and the receiver expects, an extra bit between
the data and Stop bits, which differentiates address from data characters. Other
manufacturers’ devices have a similar mode called NINE-BIT mode. To enable
PS000501-XMP1299
Preliminary Z80S183/Z80L183
67
OPERATIONAL DESCRIPTION
ASYNC SERIAL COMMUNICATIONS INTERFACES (ASCIS)
this mode for both the transmitter and receiver, set Bit 6 of the CNTLB register as
part of initializing the ASCI.
0QVGꢄ MULTIPROCESSOR mode cannot be used with parity generation and checking.
In MULTIPROCESSOR mode, data is grouped into frames or messages, each
preceded by an address character, which differs from data characters in that its
extra bit is 1.
To send a frame:
1. Wait, if necessary, for the TDRE bit (Bit 1 of the STAT register) to be 1,
indicating that a new Tx character can be written to the TDR. The next two
steps can be performed in an ASCI Interrupt Service Routine.
2. Read the CNTLB register, set Bits 7-6 to 11, and write the result back to
CNTLB. This action sets up the transmitter to send the first character of the
frame with the extra Bit 1.
3. Write the address value for the intended destination device to the TDR.
4. For each data character in the frame, again wait, if necessary, for the TDRE bit
(Bit 1 of the STAT register) to be 1. The following two steps can be performed
in an ASCI ISR.
5. Read CNTLB, clear Bit 7, and write the result back. These actions cause the
transmitter to send the next character with the extra Bit 0.
6. Write the next data character to the TDR. When there are more characters in
the frame, return to Step 4.
When Bit 6 of CNTLB is 1, to receive a frame in MULTIPROCESSOR mode:
1. Read CNTLA, set Bit 7, and write the result back to CNTLA. This process
conditions the receiver to ignore data characters, that contain a 0in the extra bit.
2. Wait for the RDRF bit in the STAT register to be 1. The following steps can
be done in an ASCI ISR.
3. Read CNTLA and verify that Bit 3 is 1, specifically that the next available
character is an address character. If not, read the RDR, discard the data
character, and return to step 2.
4. Read the RDR and check whether the value obtained indicates a frame destined
for this processor (there may be one or more unique addresses for this node,
plus a broadcast and/or group address). If not, discard the character and return
to step 2. The hardware ignores the data characters in the frame.
5. Optionally, store the address character in memory. (The following steps may
vary depending on the address.)
6. Read CNTLA, clear Bit 7, and write the result back to CNTLA. This process
conditions the receiver to assemble the following data characters.
7. For each data character in the frame, wait for the RDRF bit in the STAT
register to be 1. The following steps can be processed in an ASCI interrupt
service routine.
68
Preliminary Z80S183/Z80L183
PS000501-XMP1299
CLOCKED SERIAL INPUT/OUTPUT MODULE (CSI/O)
OPERATIONAL DESCRIPTION
8. Read the data character from the RDR and store it in memory. (When frames
are not a fixed length, software determines the frame length from its content.)
When the frame is not complete, return to step 7.
9. Check the frame for checking or validation information. Most protocols specify
that a receiving node ignores a frame that fails checking/validation.
10. Process the frame based on its content. This routine is application-dependent.
CLOCKED SERIAL INPUT/OUTPUT MODULE (CSI/O)
The CSI/O allows synchronous communication with serial memories, peripherals,
and other processors that include compatible interfaces. The CSI/O is a half-
duplex interface that sends or receives 8-bit bytes, but not simultaneously.
The CSI/O includes separate receive and transmit data pins, RXSand TXS, plus a
clock pin, CKS, that can be either an input or an output. In either direction, CKS
switches only during active data characters on the RXSand TXSpins.
The bit rate for the CSI/O can be up to PHI/20 for an internally-generated clock,
and faster with an externally-generated clock.
The CSI/O Control (CNTR) and Data (TRDR) registers are described in section
“Clocked Serial Input/Output Module (CSI/O)” on page 69.
Clock Selection
After Reset, Bits 2-0 of the CNTR are 111B, which conditions the CKSpin to be an
input. When this Z80S183/Z80L183 is to provide the clock to the other station(s),
write Bits 2-0 with one of the values 000–110Bdepicted in Table 16. This value
determines the factor by which the CSI/O divides PHIto produce the clock it drives
onto CKS.
TABLE 16. CSI/O CLOCK RATE SELECTION
CNTR 2-0
CKS Bit Rate
000
001
010
011
100
101
110
111
PHI/20
PHI/40
PHI/80
PHI/160
PHI/320
PHI/640
PHI/1280
Input from external source
0QVGꢄ Wait at least one bit time after the transmitter clears the TE bit, or the receiver
clears the RE bit, before changing the baud rate.
Operation
The clock signal on CKSand the data signals on TXSand RXSfeature the same
basic relationship whether this Z80S183/Z80L183 is driving or receiving the
clock on CKS, and whether it is sending on TXSor receiving on RXS.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
69
OPERATIONAL DESCRIPTION
CLOCKED SERIAL INPUT/OUTPUT MODULE (CSI/O)
Figure 15 illustrates this relationship, along with the state of the flags in the CNTR.
CKS
LS bit
MS bit
TXS/RXS
TE/RE
EF
FIGURE 15. CSI/O OPERATION
CKS is High between bytes. The CSI/O operates as follows in the four possible
cases of clock and data sourcing:
Output Clock, Output Data. After software writes a byte to be transmitted to the
TRDR and sets the TE bit in the CNTR, the CSI/O drives CKSLow, and shortly
thereafter drives Bit 0 of the byte onto TXS.
Then, it toggles CKSat the selected clock rate, driving each next-more-significant
bit from each falling edge on TXS, until it has driven Bit 7 onto TXS. Then the
CSI/O clears the TE bit and sets the EF bit in the CNTR. The CSI/O drives CKS
High to complete the operation.
Input Clock, Output Data. Software must write the byte to be transmitted to the
TRDR, and then set the TE bit in the CNTR, before the external clock source
drives the CKSpin Low for the first bit of the byte.
At each falling edge of CKS, CSI/O drives a bit onto TXS, beginning with Bit 0. After
driving Bit 7 onto TXS, the CSI/O clears the TE bit and sets the EF bit in the CNTR.
Output Clock, Input Data. After software sets the RE bit in the TRDR, the CSI/O
drives CKS Low, and thereafter toggles CKSat the selected clock rate, for a total
of eight falling and eight rising edges. At each rising edge on CKS, the CSI/O
samples one bit of the byte into the TRDR, starting with Bit 0. After sampling Bit
7, the CSI/O clears the RE bit and sets the EF bit in the CNTR.
Input Clock, Input Data. Software must set the RE bit in the CNTR, before the
external clock source drives CKSLow for the first bit of the byte. At each rising
edge on CKS, the CSI/O samples one bit of the byte into the TRDR, starting with Bit
0. After sampling Bit 7, the CSI/O clears the RE bit and sets the EF bit in the CNTR.
Transmitting a Byte. Both the TE and RE bits in the CNTR must be 0 before
another byte can be sent. At that point, software must:
1. Write the byte to be transmitted into the TRDR.
2. Write a 1to the TE bit (Bit 4) in the CNTR, with the selected clock control
value in Bits 2-0. When no interrupt is necessary when the byte has been sent,
write a 0in Bit 6 (EIE) of this register. Otherwise, write a 1for the interrupt
service routine.
70
Preliminary Z80S183/Z80L183
PS000501-XMP1299
CLOCKED SERIAL INPUT/OUTPUT MODULE (CSI/O)
OPERATIONAL DESCRIPTION
Receiving a Byte. Both the TE and RE bits in the CNTR must be 0before soft-
ware can condition the CSI/O to receive another byte. At that point software must:
1. Write a 1to the RE bit (Bit 5) in the CNTR, with the selected clock control value
in Bits 2–0. For polled operation, write a 0in Bit 6 (EIE) of this value.
Otherwise, write a 1and clear the transmit flag for the Interrupt Service Routine.
2. Read the CNTR (for polled operation) periodically or in a tight loop, until RE
is 0and EF is 1. For interrupt-driven operation, the following step is
performed in the interrupt service routine, as described in the next topic.
3. Read the TRDR to acquire the byte and clear the EF flag. When the sending
station is to send more data, return to step 1.
Cancelling Transmission or Reception. Software can cancel a byte transmis-
sion or reception in progress, by writing 0s to the TE and RE bits. Avoid cancella-
tion when the Z80S183/Z80L183 is sourcing CKS, because this action may hang
the remote station’s hardware in mid-byte. When operating with an external clock,
software may cancel byte transmission or reception after a time-out period
expires, indicating that the remote station has nothing more to send, or cannot
accept further data.
Handling CSI/O Interrupts
When software sets Bit 6 (EIE) in the CNTR when it starts a transmit or receive
operation, the CSI/O requests an interrupt when it completes the operation and
sets the EF bit. When the conditions listed in “On-Chip Interrupt Handling” on
page 22 are met with respect to this request, the processor responds by fetching
the address of the CSI/O interrupt service routine (ISR) from memory at address
(I : IL : 12). The ISR then:
1. Saves as many registers as it may use, using PUSH, EXAF, AF’, or EXX
instructions.
2. Reads the CNTR. When the EF bit is 0, the ISR may log this unknown
interrupt, before restoring the registers and returning to the interrupted process
using EIand RETinstructions.
0QVGꢄ If the Transmit flag is cleared, read the TRDR.
3. Process the byte.
a. When further reception is necessary, write a 1to RE as described in step 1
of “Receiving a Byte”, previously.
b. When data is to be sent, write the first byte to the TRDR (this action clears
the EF flag). Then set TE in the CNTR, as described in steps 1–2 of
“Transmitting a Byte”, previously. Set the Transmit flag for the next
interrupt.
4. If the Transmit flag is set:
a. Write the next byte to the TRDR (this clears EF).
b. Then set TE in the CNTR, as described steps 1-2 of “Transmitting a Byte”,
previously.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
71
I/O REGISTERS
REGISTERS SUMMARY
5. When there is data to be received, perform a dummy read of the TRDR to clear
the EF flag, then write a 1to RE as described in step 1 of “Receiving a Byte”,
previously. Clear the Transmit flag.
a. When no further data is to be sent or received, perform a dummy read of
the TRDR to clear the EF flag.
6. Restore the saved registers and return to the interrupted process using EIand
RETinstructions.
I/O REGISTERS
“Processor Description” describes the processor registers and the Z80S183/
Z80L183’s programming model. This section describes the registers in I/O space
that control the operation of the overall device and its on-chip peripherals.
REGISTERS SUMMARY
I/O registers on the Z80S183/Z80L183 are divided into two classes, the 80180
registers and other on-chip registers.
The 80180 registers:
•
Are located at addresses between 0000and 003FH
Can be relocated to 0080–00BFHor 00C0–00FFH
Require three cycles per I/O instruction
•
•
Other on-chip registers:
•
•
Are located at addresses between 0040and 007FH, and
Require four cycles per I/O instruction.
All the on-chip registers on the Z80S183/Z80L183 decode 16-bit I/O addresses
and require A15-8 to be all 0. These registers must be accessed using IN0and
OUT0instructions.
The following table includes all on-chip registers in both classes. I/O addresses
not described are not used.
TABLE 17. ON-CHIP REGISTERS
Register Name
Addr (hex) Register Name
Addr (hex)
ASCI0 Control Register A
ASCI0 Control Register B
ASCI0 Status Register
00
02
04
06
08
0A
0C
0E
10
ASCI1 Control Register A
01
03
05
07
09
0B
0D
0F
ASCI1 Control Register B
ASCI1 Status Register
ASCI0 Tx Data Register
ASCI0 Rx Data Register
CSI/O Control Register
ASCI1 Tx Data Register
ASCI1 Rx Data Register
CSI/O Data Register
PRT0 Timer Data Register Low
PRT0 Timer Reload Register Low
Timer Control Register
PRT0 Timer Data Register High
PRT0 Timer Reload Register High
72
Preliminary Z80S183/Z80L183
PS000501-XMP1299
REGISTERS SUMMARY
I/O REGISTERS
TABLE 17. ON-CHIP REGISTERS (CONTINUED)
ASCI0 Extension Control Reg
PRT1 Timer Data Register Low
PRT1 Timer Reload Register Low
Free Running Counter
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
30
32
34
36
38
3A
3C
3E
40
42
44
46
48
4A
4C
4E
60
62
64
66
68
6A
6C
6E
70
72
74
76
ASCI1 Extension Control Reg
PRT1 Timer Data Register High
PRT1 Timer Reload Register High
13
15
17
ASCI0 Time Constant Low
ASCI1 Time Constant Low
Clock Control Register
ASCI0 Time Constant High
ASCI1 Time Constant High
CPU Control Register
1B
1D
1F
21
23
25
27
29
2B
2D
2F
31
33
35
DMA0 Source Addr Register L
DMA0 Source Addr Register B
DMA0 Dest Addr Register H
DMA0 Byte Count Register L
DMA1 Memory Addr Register L
DMA1 Memory Addr Register B
DMA1 I/O Addr Register H
DMA1 Byte Count Register L
DMA Status Register
DMA0 Source Addr Register H
DMA0 Dest Addr Register L
DMA0 Dest Addr Register B
DMA0 Byte Count Register H
DMA1 Memory Addr Register H
DMA1 I/O Addr Register L
DMA1 I/O Addr Register B
DMA1 Byte Count Register H
DMA Mode Register
DMA/Wait Control Register
Interrupt/Trap Control Register
Refresh Control Register
MMU Common Base Register
MMU Common/Bank Area Register
Device ID High
Interrupt Vector Low Register
Interrupt Edge Register
MMU Bank Base Register
Device ID Low
39
3B
3D
3F
41
43
45
47
49
4B
4D
4F
61
63
65
67
69
6B
6D
6F
71
73
75
77
Revision ID
Operating Mode Control Register
Port A Data Register
I/O Control Register
Port A Data Direction Register
Port A Output Control Register
Port B Data Direction Register
Port B Output Control Register
Port C Data Direction Register
Port C Output Control Register
Port D Data Direction Register
Port D Output Control Register
POG Address/Type Register
POG Counter High
Port A Alternate Function Register
Port B Data Register
Port B Alternate Function Register
Port C Data Register
Port C Alternate Function Register
Port D Data Register
Port D Alternate Function Register
POG Control Register
POG Counter Low
WDT Master Register
WDT Command Register
ADC Control Register 1
DAC Control Register
WSG Control Register
RAM Lower Bound Register
RTC Control/Status
ADC Control Register 0
ADC Result Register
DAC Data Register
ROM Boundary Register
RAM Upper Bound Register
RTC Seconds
RTC Minutes
RTC Hours
RTC Day of the Week
RTC Month
RTC Date
RTC Year
RTC Century
PS000501-XMP1299
Preliminary Z80S183/Z80L183
73
I/O REGISTERS
BASIC DEVICE REGISTERS
TABLE 17. ON-CHIP REGISTERS (CONTINUED)
RTC Alarm Seconds
RTC Alarm Hours
78
7A
7E
RTC Alarm Minutes
79
7D
7F
Output Control Register
System Control Register
Power Control Register
BASIC DEVICE REGISTERS
In these register tables, the abbreviation ‘Resvd’ denotes Reserved bits that must
not be programmed.
TABLE 18. FREE RUNNING COUNTER (0018H)
Bit
7
6
5
4
1
3
1
2
1
1
1
0
1
Bit/Field
R/W
Count
R
Reset
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Bit/
Position Field
R/W Value Description
7-0 Count
R
This value is counted down by 1 every 10 PHI
clocks, including during I/O Stop mode.
TABLE 19. CLOCK CONTROL REGISTER (001EH) CLKCR
Bit
7
6
5
4
3
2
1
0
Bit/Field
Resvd Low
Noise
Resvd
?
XTAL
R/W
?
R/W
0
Reset
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
Low Noise R/W
XTAL
R/W Value Description
6
1
When this bit is 1, the oscillator operates in
a Low Noise mode, in which the gain is
reduced and the output drive is reduced to
about 30% of normal operation. This mode
can be used for PCMCIA applications, in
which the crystal would otherwise be
driven with too much power. This mode
limits the crystal frequency to 20 MHz at
V
=4.5V and 10 MHz at V =3.0V.
74
Preliminary Z80S183/Z80L183
PS000501-XMP1299
BASIC DEVICE REGISTERS
I/O REGISTERS
TABLE 20. CPU CONTROL REGISTER (001FH) CCR
Bit
7
6
5
4
3
2
1
0
Bit/Field
X1
XTAL
Stand- BREXT LNPHI
by
Idle/
Quick
Resvd LNCTL LNA/D
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
?
R/W
0
R/W
0
Reset
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W Value Description
7
X1 XTAL R/W
0
1
The crystal frequency is divided by 2.
The crystal frequency is used directly.
6,3
Standby, R/W
Idle/Quick
00 SLP instruction enters Sleep or System Stop
mode
01 IOSTOP+SLP enters Idle mode
10 IOSTOP+SLP enters Standby mode
11 IOSTOP+SLP enters Quick Recovery
Standby mode
5
BREXT
R/W
1
Z80S183/Z80L183 honors Bus Requests in
Standby mode
4
1
LNPHI
LNCTL
R/W
R/W
1
1
PHI Low noise mode: 30% of normal drive
IORD and IOWR Low noise mode: 30% of
normal drive
0
LNA/D
R/W
1
A19-0/D7-0 Low noise mode: 30% of normal
drive
TABLE 21. REFRESH CONTROL REGISTER (0036H) RCR
Bit
7
6
5
4
3
2
1
0
0
0
Bit/Field
R/W
REFE REFW
Resvd
?
Cycle
R/W
R/W
1
R/W
1
Reset
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W Value Description
7
REFE
REFW
Cycle
R/W
R/W
R/W
1
The Z80S183/Z80L183 generates Refresh
cycles
6
0
1
2-clock Refresh cycles
3-clock Refresh cycles
1-0
00 Refresh cycle every 10 PHI clocks
01 Refresh cycle every 20 PHI clocks
10 Refresh cycle every 40 PHI clocks
11 Refresh cycle every 80 PHI clocks
PS000501-XMP1299
Preliminary Z80S183/Z80L183
75
I/O REGISTERS
BASIC DEVICE REGISTERS
Bit
Position Bit/Field R/W Value Description
Note:Because the Z80S183/Z80L183 has no RFSH pin, always program this register
with all 0s.
TABLE 22. DEVICE ID LOW (003BH)
Bit
7
6
5
4
3
2
0
1
0
0
1
Bit/Field
R/W
LS byte of Device ID
R
Reset
0
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7-0
Device ID R/W 01H LSB of the Device ID value used to identify a
LS byte Z80S183/Z80L183 via the ZDI interface
TABLE 23. DEVICE ID HIGH (003CH)
Bit
7
6
5
4
3
2
0
1
0
0
Bit/Field
R/W
MS byte of Device ID
Reset
0
0
0
0
0
10
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7-0
Device ID R/W
MS byte
00 MSB of the Device ID value used to identify a
Z80S183/Z80L183 via the ZDI interface
76
Preliminary Z80S183/Z80L183
PS000501-XMP1299
BASIC DEVICE REGISTERS
I/O REGISTERS
TABLE 24. REVISION ID (003DH)
Bit
7
6
5
0
4
3
2
0
1
0
0
0
Bit/Field
R/W
Revision ID
R
Reset
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7-0
Revision
ID
R
00 Identifies revision AB of the Z80S183/
01 Z80L183.Identifies revision BA.
TABLE 25. REVISION ID (003DH)
Bit
7
6
5
0
4
3
2
0
1
0
0
0
Bit/Field
R/W
Revision ID
R
Reset
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7-0
Revision
ID
R
00 Identifies the revision of the Z80S183/
Z80L183.
TABLE 26. OPERATING MODE CONTROL REGISTER (003EH) OMCR
Bit
7
6
M1TE
W
5
4
3
2
1
0
Bit/Field
R/W
M1E
R/W
1
IOC
R/W
1
Reserved
?
Reset
1
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W Value Description
7
M1E
R/W
0
M1 is driven Low during refetch of RETI
instructions and INT0 acknowledge cycles
(Z80 peripheral compatible).
1
M1 is driven Low in all Op Code fetches,
INT0 acknowledge cycles, and first cycle of
NMI acknowledge.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
77
I/O REGISTERS
BASIC DEVICE REGISTERS
Bit
Position Bit/Field R/W Value Description
6
M1TE
W
0
After a 0 is written to this bit, the next Op
Code fetch asserts M1 Low. (Automatically
returns to 1 state.)
1
0
M1E governs operation of M1
5
IOC
R/W
IORD is driven Low from rising edge at
start of T2 cycle (Z80 compatible)
IORD is driven Low from falling edge in T1
cycle (64180 compatible)
1
TABLE 27. I/O CONTROL REGISTER (003FH) IOCR
Bit
7
6
5
IOSTP
R/W
0
4
3
2
1
0
Bit/Field
R/W
IOA
Reserved
R/W
?
Reset
0
0
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field R/W Value Description
7-6
IOA
R/W
R/W
00 180 registers are located at 0000-003FH
Do not program this value
01 180 registers are located at 0080-00BFH
10 180 registers are located at 00C0-00FFH
11 Do not program this value
5
IOSTP
0
1
Normal operation
Clocking is blocked to the ASCIs, PRTs, and
CSI/O, disabling these units.
TABLE 28. OUTPUT CONTROL REGISTER (007DH) OCR
Bit
7
6
5
4
3
2
1
0
Bit/Field ROME
Reserved
Port B Port A Port B Port C Port D
Weak Low Low Low Low
Latch Noise Noise Noise Noise
Disable
R/W
R/W
0
?
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not applicable
78
Preliminary Z80S183/Z80L183
PS000501-XMP1299
BASIC DEVICE REGISTERS
I/O REGISTERS
Bit
Position Bit/Field R/W Value Description
7
ROM
Emulator
mode
R/W
0
Read data from internal devices does not
appear on D7-0. This feature saves power.
Read data from internal devices is driven
onto D7-0, for monitoring by an external logic
analyzer or other instrumentation.
1
5
Port B
Weak
Latch
R/W
0
Weak latches on Port B are enabled, as they
are on other pins with input capability. Weak
latches save power by preventing floating
voltage levels.
Disable
1
1
Weak latches on Port B are disabled, to allow
quasi-analog use of these pins.
3-0
Port A-D
Low Noise
R/W
Drive on the corresponding Port is reduced to
25% of its current capability. This setting
saves power and reduces system noise,
while slightly increasing switching times.
TABLE 29. POWER CONTROL REGISTER (007EH) PCR
Bit
7
6
5
4
3
2
1
0
Bit/Field CEOUT Reset
PWR
SWCH Addr
Ctrl
LPM
Resvd
?
on ↑ of
PWRUP
R/W
R/W
0
R/W
0
R/W
0
R/W
0
Reset
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field R/W Value Description
7
CEOUT
R/W
0
1
CEOUT pin is not driven
CEOUT pin is driven Low
6
Reset on R/W
↑ of
PWRUP
0
1
PWRUP pin cannot Reset
Rising edge on PWRUP Resets the
Z80S183/Z80L183
5
4
PWR
SWCH
R/W
R/W
Direct positive-logic output
LPM
Address
Control
0
1
LOW-POWER modes do not affect A19-0,
RAMRD, RAMWR, ROMRD, ROMWR,
IORD, IOWR, IOCS1-2, TXS
These pins are 3-stated in any LOW-POWER
mode
PS000501-XMP1299
Preliminary Z80S183/Z80L183
79
I/O REGISTERS
INTERRUPT REGISTERS
TABLE 30. SYSTEM CONFIGURATION REGISTER (007FH) SCR
Bit
Bit/Field Onchip Onchip RAM ROMCS RAMCS IOCS
ROM RAM High Enable Enable Enable
Enable Enable Enable
7
6
5
4
3
2
1
0
Clock Select
R/W
R/W
R/W
1
R/W
0
R/W
1
R/W
0
R/W
0
R/W
Reset
OPMO
D1
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field R/W Value Description
7
6
5
On-chip
ROM
Enable
R/W
0
1
Addresses 00000–003FFH are off-chip
Addresses 00000–003FFH are in on-chip
ROM.
On-chip
RAM
Enable
R/W
0
1
On-chip RAM is not accessible to the
processor
On-chip RAM is accessible to the processor
RAM High R/W
Enable
0
1
On-chip RAM is at xF800–xFFFFH;
addresses A19-16 are not decoded for on-
chip RAM
On-chip RAM is at FF800–FFFFFH
4
ROMCS
Enable
R/W
R/W
R/W
R/W
1
1
1
ROMCS pin is enabled/active
3
RAMCS
Enable
RAMCS pin is enabled/active
2
IOCS
Enable
The IOCS1 and IOCS2 pins are enabled/
active
1-0
Clock
00 PHI taken from EXTAL
Select
01 PHI taken from LFEXTAL
10 PHI = LFEXTAL times 1004
11 PHI = LFEXTAL times 502
INTERRUPT REGISTERS
See the Interrupts section, which starts on page 17, for more about these registers.
TABLE 31. INTERRUPT VECTOR LOW REGISTER (0033H) IL
Bit
7
6
IL7-5
R/W
0
5
4
3
2
Resvd
?
1
0
Bit/Field
R/W
Reset
0
0
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
80
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INTERRUPT REGISTERS
I/O REGISTERS
Bit
Bit/
Position
Field
R/W Value Description
7-5
IL7-5
R/W
The processor uses these bits as A7-5
(along with the contents of the I register
as A15-8) when fetching an interrupt
service routine address for INT1-2,
ASCI0-1, PRT0-1, DMA0-1, or the CSI/O.
TABLE 32. INTERRUPT/TRAP CONTROL REGISTER (0034H) ITC
Bit
7
6
5
4
3
2
1
0
Bit/Field
Trap UFO IEF1
Resvd
INT2 INT1 INT0
en
R/W
0
en
R/W
0
en
R/W
1
R/W
RW0C
0
R
X
R
0
?
Reset
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W Value Description
7
Trap
RW0C
1
Illegal Instruction Trap. Writing a 0 to this
bit clears it; writing a 1 has no effect.
6
UFO
R
0
1
Inst started at stacked PC-1
Inst started at stacked PC-2
5
2
1
0
IEF1
R
Current state of interrupt enable
INT2 interrupt enable
INT2 en
INT1 en
INT0 en
R/W
R/W
R/W
INT1 interrupt enable
INT0 interrupt enable
TABLE 33. INT2-1 INTERRUPT EDGE REGISTER (0035H) IECR
Bit
7
6
5
4
3
2
1
0
Bit/Field
INT2
INT1
INT2
Edge
INT1 INT2 Mode Sel INT1 Mode Sel
Edge
R/W
R
X
R
X
RW1C RW1C
RW
RW
Reset
0
0
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7
6
5
INT2
R
R
INT2 pin state, 0 is Low
INT1 pin state, 0 is Low
INT1
INT2 Edge
RW1C
0
1
R: edge not detected, W: no effect
R: edge detected, W: clear this bit
PS000501-XMP1299
Preliminary Z80S183/Z80L183
81
I/O REGISTERS
MMU REGISTERS
Bit
Position Bit/Field
R/W Value Description
4
INT1 Edge
RW1C
0
1
R: edge not detected, W: no effect
R: edge detected, W: clear this bit
3-2
INT2 Mode
RW
00 Low-Level Interrupt
01 Rising Edge Interrupt
10 Falling Edge Interrupt
11 Both Edges Interrupt
1-0
INT1 Mode
RW
00 Low-Level Interrupt
01 Rising Edge Interrupt
10 Falling Edge Interrupt
11 Both Edges Interrupt
MMU REGISTERS
See “Memory Management Unit (MMU)” on page 13, for more about these regis-
ters.
TABLE 34. COMMON BASE REGISTER (0038H) CBR
Bit
7
6
5
4
3
2
0
1
0
0
0
Bit/Field
R/W
Base of Common Area 1
R/W
Reset
0
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W
7-0
Common 1
Area Base
When the comparison of Bits 15-12 of a
logical address indicates that the
address is in Common Area 1, this value
(shifted left 12 bits, times 4096) is added
to the logical address to form the
physical address.
TABLE 35. BANK BASE REGISTER (0039H) BBR
Bit
7
6
5
4
3
2
0
1
0
0
0
Bit/Field
R/W
Base of Bank Area
R/W
Reset
0
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
82
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ROM/RAM CHIP SELECT AND WAIT REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W
7-0
Bank Area
Base
When the comparison of Bits 15–12 of a
logical address indicates that the
address is in the Bank Area, this value
(shifted left 12 bits, times 4096) is added
to the logical address to form the
physical address.
TABLE 36. COMMON/BANK AREA REGISTER C(003AH) CBAR
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Bank/Common 1 Boundary
R/W
Common 0/Bank Boundary
R/W
Reset
1
1
1
1
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-4
Bank/
Common 1
Boundary
R/W
When Bits 15–12 of a logical address
are greater than or equal to this value,
the address is in Common Area 1.
3-0
Common 0/
Bank
Boundary
R/W
When Bits 15–12 of a logical address
are less than this value, the address is in
Common Area 0.
0QVGꢄꢀWhen Bits 3-0 of this reg < Bits 15-12 of a logical address < Bits 7-4 of this reg, the
address is in the Bank Area. Do not program this register so that Bits 3-0 > Bits 7-4. All
comparisons are unsigned.
ROM/RAM CHIP SELECT AND WAIT REGISTERS
See “Memory”, which starts on page 23, for more detail about these registers.
TABLE 37. WAIT STATE GENERATOR CONTROL REGISTER (006BH) WSGCR
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
ROM Waits
R/W
RAM Waits
R/W
Other Waits
R/W
Reserved
?
Reset
1
1
1
1
1
1
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
83
I/O REGISTERS
ROM/RAM CHIP SELECT AND WAIT REGISTERS
Bit
Position Bit/Field
R/W Value Description
7-6
5-4
3-2
ROM Waits
RAM Waits
Other Waits
R/W
R/W
R/W
This field determines how many wait
states are inserted for memory
addresses that activate ROMCS:
00 No Wait states
01 1 Wait state
10 2 Wait states
11 4 Wait states
This field determines how many wait
states are inserted for memory
addresses that activate RAMCS:
00 No Wait states
01 1 Wait state
10 2 Wait states
11 4 Wait states
This field determines how many wait
states are inserted for memory
addresses that do not activate either
ROMCS nor RAMCS. (These cycles do
not activate any control signals and thus
are not visible.)
00 No Wait states
01 1 Wait state
10 2 Wait states
11 4 Wait states
TABLE 38. ROM BOUND REGISTER (006CH) ROMBR
Bit
7
6
5
4
3
2
1
1
1
0
1
Bit/Field
R/W
ROM Upper Bound
R/W
Reset
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit Bit/
Position Field
R/W
Value Description
7-0
ROM
Upper
Bound
R/W
When Bit 4 of the System Configuration
Register is 1, as it is after a reset, memory
accesses at addresses with A19-12 less
than or equal to this value, activate
ROMRD or ROMWR
84
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ROM/RAM CHIP SELECT AND WAIT REGISTERS
I/O REGISTERS
TABLE 39. RAM LOWER BOUND REGISTER (006DH) RAMLBR
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
RAM lower Bound
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W
7-0
RAM lower
Bound
When Bit 3 of the System Configuration
Register is1, memory accesses at
addresses with A19–12 greater than or
equal to this value, less than or equal to
the value in RAMUBR, and greater than
the value in ROMBR, activate RAMRD
or RAMWR.
TABLE 40. RAM UPPER BOUNDARY REGISTER (006EH) RAMUBR
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
RAM Upper Bound
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W
7-0
RAM lower
Bound
When Bit 3 of the System Configuration
Register is 1, memory accesses at
addresses with A19–12 greater than or
equal to this value, less than or equal to
the value in RAMUBR, and greater than
the value in ROMBR, activate RAMRD
or RAMWR.
TABLE 41. RAM UPPER BOUND REGISTER (006EH) RAMUBR
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
RAM Upper Bound
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
85
I/O REGISTERS
I/O PORT REGISTERS
Bit
Position Bit/Field
R/W Value Description
7-0
RAM Upper
Bound
R/W
When Bit 3 of the System Configuration
Register is 1, as it is after a reset,
memory accesses at addresses with
A19-12 less than or equal to this value,
greater than or equal to the value in
RAMLBR, and greater than the value in
ROMBR, activate RAMRD or RAMWR.
I/O PORT REGISTERS
See “I/O Ports” on page 36, for more about these registers.
TABLE 42. PORT A DATA REGISTER (0040H) DRA
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
PA7
R/W
X
PA6
R/W
X
PA5
R/W
X
PA4
R/W
X
PA3
R/W
X
PA2
R/W
X
PA1
R/W
X
PA0
R/W
X
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0 PA7-0
R/W
Writing to this register sets the data that
is driven onto those pins among PA7-0,
that are designated as outputs in the
Data Direction and Output Control
Registers. Reading from the Data
Register returns the state of pins PA7-0,
for both inputs and outputs. The output
latches cannot be read back separately.
TABLE 43. PORT A DATA DIRECTION REGISTER (0041H) DDRA
Bit
7
6
5
4
3
2
1
0
Bit/Field PA7 dir PA6 dir PA5 dir PA4 dir PA3 dir PA2 dir PA1 dir PA0 dir
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
86
Preliminary Z80S183/Z80L183
PS000501-XMP1299
I/O PORT REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PA7-0 dir
Together with Output Control Register
A, these bits determine which pins
among PA7-0 are inputs and which are
outputs, and for outputs, one of three
output modes. The 4 possible settings
for each pin are:
0
0
1
1
With 0 in the corresponding OCR bit, 0
selects totem pole output.
With 1 in the corresponding OCR bit, 0
selects open drain output.
With 0 in the corresponding OCR bit, 1
selects input.
With 1 in the corresponding OCR bit, 1
selects open drain output with an
internal pullup resistor.
TABLE 44. PORT A ALTERNATE FUNCTION SELECT REGISTER (0042H) AFSA
Bit
7
6
5
4
3
2
1
0
Bit/Field PA7 int PA6 int PA5 int PA4 int PA3 int PA2 int PA1 int PA0 int
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W A 1 in one of these bits makes the
7-0 PA7-0 int
corresponding pin a Low-active interrupt
request line.
TABLE 45. PORT A OUTPUT CONTROL REGISTER (0043H) OCRA
Bit
7
6
5
4
3
2
1
0
Bit/Field PA7 oc PA6 oc PA5 oc PA4 oc PA3 oc PA2 oc PA1 oc PA0 oc
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
87
I/O REGISTERS
I/O PORT REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PA7-0 oc
Together with Data Direction Register A,
these bits determine which pins among
PA7-0 are inputs and which are outputs,
and for outputs, one of three output
modes. The four configurations for each
pin are described in Table 43.
TABLE 46. PORT B DATA REGISTER (0044H) DRB
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
PB7
R/W
X
PB6
R/W
X
PB5
R/W
X
PB4
R/W
X
PB3
R/W
X
PB2
R/W
X
PB1
R/W
X
PB0
R/W
X
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0 PB7-0
R/W
Writing to this register sets the data that
is driven onto those pins among PB7-0,
that are designated as outputs in the
Data Direction and Output Control
Registers. Reading from the Data
Register returns the state of pins PB7-0,
for both inputs and outputs. The output
latches cannot be read separately.
TABLE 47. PORT B DATA DIRECTION REGISTER (0045H) DDRB
Bit
7
6
5
4
3
2
1
0
Bit/Field PB7 dir PB6 dir PB5 dir PB4 dir PB3 dir PB2 dir PB1 dir PB0 dir
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
88
Preliminary Z80S183/Z80L183
PS000501-XMP1299
I/O PORT REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PB7-0 dir
Together with Output Control Register
B, these bits determine which pins
among PB7-0 are inputs and which are
outputs, and for outputs, one of three
output modes. The four possible
settings for each pin are:
0
0
1
1
With 0 in the corresponding OCR bit, 0
selects totem pole output.
With 1 in the corresponding OCR bit, 0
selects open drain output.
With 0 in the corresponding OCR bit, 1
selects input.
With 1 in the corresponding OCR bit, 1
selects open drain output with an
internal pullup resistor.
TABLE 48. PORT B ALTERNATE FUNCTION SELECT REGISTER (0046H) AFSB
Bit
7
6
5
4
3
2
1
0
Bit/Field PB7 alt PB6 alt PB5 alt PB4 alt PB3 alt PB2 alt PB1 alt PB0 alt
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7
6
5
4
3
2
PB7 alt
PB6 alt
PB5 alt
PB4 alt
PB3 alt
PB2 alt
R/W
R/W
R/W
R/W
R/W
R/W
0
1
The PB7/RXS pin is PB7
The PB7/RXS pin is RXS
0
1
The PB6/RXA1 pin is PB6
The PB6/RXA1 pin is RXA1
0
1
The PB5/TXA1 pin is PB5
The PB5/TXA1 pin is TXA1
0
1
The PB4/RXA0 pin is PB4
The PB4/RXA0 pin is RXA0
0
1
The PB3/TXA0 pin is PB3
The PB3/TXA0 pin is TXA0
0
1
The PB2/CTS0/PWRUP pin is PB2
The PB2/CTS0/PWRUP pin is CTS0 or
PWRUP
1
0
PB1 alt
PB0 alt
R/W
R/W
0
1
The PB1/DCD0 pin is PB1
The PB1/DCD0 pin is DCD0
0
1
The PB0/CKS pin is PB0
The PB0/CKS pin is CKS
PS000501-XMP1299
Preliminary Z80S183/Z80L183
89
I/O REGISTERS
I/O PORT REGISTERS
Bit
Position Bit/Field
R/W Value Description
0QVGꢄꢀA 1 in any of these bits disables control of the pin by the DDRB register, but the
corresponding bit in OCRB is 0 in this case.
TABLE 49. PORT B OUTPUT CONTROL REGISTER (0047H) OCRB
Bit
7
6
5
4
3
2
1
0
Bit/Field PB7 oc PB6 oc PB5 oc PB4 oc PB3 oc PB2 oc PB1 oc PB0 oc
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PB7-0 oc
Together with Data Direction Register B,
these bits determine which pins among
PB7-0 are inputs and which are outputs,
and for outputs, one of three output
modes. The four configurations for each
pin are described in Table 47.
TABLE 50. PORT C DATA REGISTER (0048H) DRC
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
PC7
R/W
X
PC6
R/W
X
PC5
R/W
X
PC4
R/W
X
PC3
R/W
X
PC2
R/W
X
PC1
R/W
X
PC0
R/W
X
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0 PC7-0
R/W
Writing to this register sets the data that
is driven onto those pins among PC7-0,
that are designated as outputs in the
Data Direction and Output Control
Registers. Reading from the Data
Register returns the state of pins PC7-0,
for both inputs and outputs. The output
latches cannot be read separately.
90
Preliminary Z80S183/Z80L183
PS000501-XMP1299
I/O PORT REGISTERS
I/O REGISTERS
TABLE 51. PORT C DATA DIRECTION REGISTER (0049H) DDRC
Bit
7
6
5
4
3
2
1
0
Bit/Field PC7 dir PC6 dir PC5 dir PC4 dir PC3 dir PC2 dir PC1 dir PC0 dir
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PC7-0 dir
Together with Output Control Register
C, these bits determine which pins
among PC7-0 are inputs and which are
outputs, and for outputs, one of three
output modes. The four possible
settings for each pin are:
0
0
1
1
With 0 in the corresponding OCR bit, 0
selects totem pole output.
With 1 in the corresponding OCR bit, 0
selects open drain output.
With 0 in the corresponding OCR bit, 1
selects input.
With 1 in the corresponding OCR bit, 1
selects open drain output with an
internal pullup resistor.
TABLE 52. PORT C ALTERNATE FUNCTION SELECT REGISTER R(004AH) AFSC
Bit
7
6
5
4
3
2
1
0
Bit/Field PC7 alt PC6 alt PC5 alt PC4 alt PC3 alt PC2 alt PC1 alt PC0 alt
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0 PC7-0 alt
R/W
Writing a 1 to any of these bits assigns
the corresponding pin to the
Programmable Output Generator (POG).
In this mode the DDRC and OCRC
registers still determine the output drive
of the port, so that the POG can use any
of the port output modes. To use PC0 as
a 50 or 60 Hz time base for the Real
Time Clock, leave AFSC Bit 0 zero,
DDRC Bit 0 one, and OCRC Bit 0 zero.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
91
I/O REGISTERS
I/O PORT REGISTERS
TABLE 53. PORT C OUTPUT CONTROL REGISTER (004BH) OCRC
Bit
7
6
5
4
3
2
1
0
Bit/Field PC7 oc PC6 oc PC5 oc PC4 oc PC3 oc PC2 oc PC1 oc PC0 oc
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PC7-0 oc
Together with Data Direction Register C,
these bits determine which pins among
PC7-0 are inputs and which are outputs,
and for outputs, one of three output
modes. The four configurations for each
pin are described in Table 51.
TABLE 54. PORT D DATA REGISTER (004CH) DRD
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
PD7
R/W
X
PD6
R/W
X
PD5
R/W
X
PD4
R/W
X
PD3
R/W
X
PD2
R/W
X
PD1
R/W
X
PD0
R/W
X
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PD7-0
Writing to this register sets the data that
is driven onto pins among PD7-0, that
are designated as outputs in the Data
Direction and Output Control Registers.
Reading from the Data Register returns
the states of pins PD7-0, for both inputs
and outputs. There is no way to read
back the output latches separately.
TABLE 55. PORT D DATA DIRECTION REGISTER (004DH) DDRD
Bit
7
6
5
4
3
2
1
0
Bit/Field PD7 dir PD6 dir PD5 dir PD4 dir PD3 dir PD2 dir PD1 dir PD0 dir
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
92
Preliminary Z80S183/Z80L183
PS000501-XMP1299
I/O PORT REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
7-0 PD7-0 dir
R/W
Together with Output Control Register
D, these bits determine which pins
between PD7-0 are inputs and which
are outputs, and for outputs, one of
three output modes. The four possible
settings for each pin are:
0
0
1
1
With 0 in the corresponding OCR bit, 0
selects totem pole output.
With 1 in the corresponding OCR bit, 0
selects open drain output.
With 0 in the corresponding OCR bit, 1
selects input.
With 1 in the corresponding OCR bit, 1
selects open-drain output with an
internal pullup resistor.
TABLE 56. PORT D ALTERNATE FUNCTION SELECT REGISTER (004EH) AFSD
Bit
7
6
5
4
3
2
1
0
Bit/Field PD7 int PD6 int PD5 int PD4 int PD3 int PD2 int PD1 int PD0 int
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W A 1 in one of these bits makes the
7-0 PD7-0 int
corresponding pin a Low-active interrupt
request line.
TABLE 57. PORT D OUTPUT CONTROL REGISTER (004FH) OCRD
Bit
7
6
5
4
3
2
1
0
Bit/Field PD7 oc PD6 oc PD5 oc PD4 oc PD3 oc PD2 oc PD1 oc PD0 oc
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
93
I/O REGISTERS
DMA REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W
7-0 PD7-0 oc
Together with Data Direction Register D,
these bits determine which pins among
PD7-0 are inputs and which are outputs,
and for outputs, one of three output
modes. The four configurations for each
pin are described in Table 54.
DMA REGISTERS
See section “DMA Channels” on page 39, for more about these registers.
TABLE 58. DMA0 SOURCE ADDRESS REGISTER LOW (0020H) SAR0L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS byte of DMA0 Source Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA0
R/W
LSB of the Source Address for DMA
channel 0.
Source
Address LS
byte
TABLE 59. DMA0 SOURCE ADDRESS REGISTER LOW (0020H) SAR0L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS byte of DMA0 Source Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA0
R/W
LSB of the Source Address for DMA
channel 0.
Source
Address LS
byte
94
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA REGISTERS
I/O REGISTERS
TABLE 60. DMA0 SOURCE ADDRESS REGISTER HIGH (0021H) SAR0H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Middle byte of DMA0 Source Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA0
Source
R/W
Bits 15-8 of the Source Address for
DMA channel 0.
Address
middle byte
TABLE 61. DMA0 SOURCE ADDRESS REGISTER B (0022H) SAR0B
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Reserved
MS part of DMA0 Source Addr
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W When the Source Mode field in the
3-0
MS part of
DMA0
DMODE register is 11, indicating an
I/O source, these bits select which
source device handshake line controls
data transfer, as follows:
Source
Address
X000 DREQ0 pin
X001 ASCI0 RDRF
X010 ASCI1 RDRF
other Reserved, do not program
Otherwise, these bits contain A19-16 of
the DMA0 Source address.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
95
I/O REGISTERS
DMA REGISTERS
TABLE 62. DMA0 DESTINATION ADDRESS REGISTER LOW (0023H) DAR0L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS byte of DMA0 Destination Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA0
R/W
LSB of the Destination Address for DMA
channel 0.
Destination
Address LS
byte
TABLE 63. DMA0 DESTINATION ADDRESS REGISTER HIGH (0024H) DAR0H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Middle byte of DMA0 Destination Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA0
Destination
Address
R/W
Bits 15-8 of the Destination Address for
DMA channel 0.
middle byte
TABLE 64. DMA0 DESTINATION ADDRESS REGISTER B (0025H) DAR0B
Bit
7
6
5
4
3
2
1
0
Bit/Field
Reserved
MS part of DMA0 Destination
Address
R/W
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
96
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W When the Dest Mode field in the
3-0
MS part of
DMA0
DMODE register is 11, indicating an I/O
destination, these bits select which
destination device handshake line
controls data transfer, as follows:
Destination
Address
DREQ0 pin
X000 ASCI0 TDRE
X001 ASCI1 TDRE
X010 Reserved, do not program
other
Otherwise these bits contain A19-16 of
the DMA 0 Destination address.
TABLE 65. DMA0 BYTE COUNT REGISTER LOW (0026H) BCR0L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS byte of DMA0 Byte Count
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA0 Byte
Count LS
byte
R/W
LS byte of the Byte Count for DMA
channel 0.
TABLE 66. DMA0 BYTE COUNT REGISTER HIGH (0027H) BCR0H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
MS byte of DMA0 Byte Count
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA0 Byte
Count MS
byte
R/W
MS byte of the Byte Count for DMA
channel 0.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
97
I/O REGISTERS
DMA REGISTERS
TABLE 67. DMA1 MEMORY ADDRESS REGISTER LOW (0028H) MAR1L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS byte of DMA1 Memory Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA1
R/W
LS byte of the Memory Address for DMA
channel 1.
Memory
Address LS
byte
TABLE 68. DMA1 MEMORY ADDRESS REGISTER HIGH (0029H) MAR1H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Middle byte of DMA1 Memory Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA1
R/W
Bits 15-8 of the Memory Address for
DMA channel 1.
Memory
Address
middle byte
TABLE 69. DMA1 MEMORY ADDRESS REGISTER B (002AH) MAR1B
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Reserved
DMA1 Memory Address 19-16
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
98
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W Bits 19-16 of the DMA1 Memory
address.
3-0
DMA1
Memory
Address 19-
16
TABLE 70. DMA1 I/O ADDRESS REGISTER LOW (002BH) IAR1L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS byte of DMA1 I/O Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA1 I/O
Address LS
byte
R/W
LS byte of the I/O Address for DMA
channel 1.
TABLE 71. DMA1 I/O ADDRESS REGISTER HIGH (002CH) IAR1H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
MS byte of DMA1 I/O Address
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA1 I/O
Address MS
byte
R/W
Bits 15-8 of the I/O Address for DMA
channel 1.
TABLE 72. DMA1 I/O ADDRESS REGISTER B (002DH) IAR1B
Bit
7
6
5
4
3
2
1
0
Bit/Field
AltE
AltC
Reserved
DMA1 I/O Handshake
Select
R/W
R/W
X
R/W
X
?
R/W
Reset
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
99
I/O REGISTERS
DMA REGISTERS
Bit
Position Bit/Field
R/W Value Description
Set this bit only when both DMA
7
AltE
R/W
R/W
R/W
1
channels are programmed for the same
I/O source or I/O destination. In this
case, a channel end condition (byte
count = 0) on channel 0 sets Bit 6 (AltC),
which then enables channel 1’s request
and blocks channel 0’s. Similarly, a
channel end condition on channel 1
clears Bit 6 (AltC), which then enables
channel 0’s request and blocks channel
1’s. To use this feature with external
requests, the request from the device
must be routed or connected to both the
DREQ0 and DREQ1 pins.
6
AltC
When Bit 7 (AltE) is 0, this bit has no
effect. When Bit 7 (AltE) is 1 and this bit
is 0, the Request signal selected by Bits
2-0 is not presented to channel 1, but
channel 0’s Request operates normally.
When AltE is 1 and this bit is 1, the
Request selected by SAR18-16 or
DAR18-16 is not presented to channel
0, but channel 1’s request operates
normally. This bit can be written to
select which channel operates first, but
perform this operation only when both
channels are stopped (both DE1 and
DE0 are 0).
2-0
DMA1 I/O
Handshake
Select
When bit DIM1 in the DCNTL register is
1, indicating an I/O source, these bits
select which source handshake signal
controls the transfer.
DREQ1 pin
000 ASCI0 RDRF
001 ASCI1 RDRF
010 Reserved, do not program
other
When DIM1 is 0, indicating an I/O
destination, these bits select which
destination handshake signal controls
the transfer, as follows:
DREQ1 pin
ASCI0 TDRE
000 ASCI1 TDRE
001 Reserved, do not program
010
other
100
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA REGISTERS
I/O REGISTERS
TABLE 73. DMA1 BYTE COUNT REGISTER LOW (002EH) BCR1L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS byte of DMA1 Byte Count
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA1 Byte
Count LS
byte
R/W
LS byte of the Byte Count for DMA
channel 1.
TABLE 74. DMA1 BYTE COUNT REGISTER HIGH (002FH) BCR1H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
MS byte of DMA1 Byte Count
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
DMA1 Byte
Count MS
byte
R/W
MS byte of the Byte Count for DMA
channel 1.
TABLE 75. DMA STATUS REGISTER (0030H) DSTAT
Bit
7
6
5
4
3
2
1
0
Bit/Field
DE1
DE0
DWE1 DWE0 DIE1
DIE0 Reserv DME
ed
R/W
R/W
0
R/W
0
W
X
W
X
R/W
0
R/W
0
?
R/W
0
Reset
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7
DE1
R/W
DMA channel 1 enable. This bit can only
be written when DWE1 is 0 in a write
operation. DMA channel 1 clears this bit
when it counts its byte count down to 0.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
101
I/O REGISTERS
DMA REGISTERS
Bit
Position Bit/Field
R/W Value Description
6
DE0
R/W
DMA channel 0 enable. This bit can only
be written when DWE0 is 0 in a write
operation. DMA channel 0 clears this bit
when it counts its byte count down to 0.
5-4
DWE1-0
W
0
1
Writing a 0 to one of these bits makes
the Z80S183/Z80L183 capture the value
of the corresponding DE bit.
Writing a 1 to one of these bits does not
affect the state of the corresponding
DMA channel. These bits always read
as 11.
3-2
0
DIE1-0
DME
R/W
R
Interrupt enable for DMA channels 1-0.
When one of these bits is 1, that DMA
channel interrupts when it decrements
its byte count to 0.
0
1
Operations of both DMA channels are
disabled. Reset and a nonmaskable
interrupt both clear this bit.
Operation of a DMA channel that has its
DE Bit 1 is enabled. This bit is set when
a 1 is written to a DE bit, and a 0 is
written to the corresponding DWE bit in
the same write operation.
TABLE 76. DMA MODE REGISTER (0031H) DMODE
Bit
7
6
5
4
3
2
1
0
Bit/Field
Reserved
DMA0 Dest
Mode
DMA0 Source MMOD Resvd
Mode
R/W
?
R/W
R/W
R/W
0
?
Reset
X
X
0
0
0
0
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit Bit/
Position Field
R/W
Value Description
5-4
DMA0
Dest
Mode
R/W
This field controls operation of the
destination side of DMA channel 0:
Memory write, address increment
Memory write, address decrement
Memory (or memory mapped I/O) write,
fixed address
00
01
10
11
I/O write, fixed address
102
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DMA REGISTERS
I/O REGISTERS
TABLE 77. DMA MODE REGISTER (0031H) DMODE
Bit
7
6
5
4
3
2
1
0
Bit/Field
Reserved
DMA0 Dest
Mode
DMA0 Source MMOD Reserv
Mode
ed
R/W
R/W
R/W
R/W
0
Reset
X
X
0
0
0
0
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit Bit/ Description
Position Field Value Bit
R/W
5-4
3-2
1
DMA0
Dest
Mode
R/W
This field controls operation of the
destination side of DMA channel 0:
Memory write, address increment
Memory write, address decrement
Memory (or memory mapped I/O) write,
fixed address
00
01
10
11
I/O write, fixed address
DMA0
Source
Mode
R/W
R/W
This field controls operation of the source
side of DMA channel 0:
Memory read, address increment
Memory read, address decrement
Memory (or memory mapped I/O) read,
fixed address
00
01
10
11
I/O read, fixed address
MMOD
When the Source and Dest Mode fields
above are both 0x, indicating memory to
memory operation, no device request (that
is, DREQ0) controls data transfer on DMA
channel 0. In this case, this bit selects
between two modes:
0
1
Cycle Steal mode: the DMA(s) and
processor alternate bus cycles.
Burst mode: DMA0 uses the bus
continuously to complete the block transfer.
TABLE 78. DMA/WAIT CONTROL REGISTER (0032H) DCNTL
Bit
7
6
5
4
3
2
1
0
Bit/Field
Memory Waits
I/O Waits
Request Sense
1-0
DMA1 Mode
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
0
0
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
103
I/O REGISTERS
WATCH-DOG TIMER REGISTERS
Bit
Position Bit/Field
R/W Value Description
7-6
5-4
3-2
Memory
Waits
R/W
R/W
R/W
This field controls how many wait states
are injected into DMA and processor
memory cycles:
00 None
01
10
11
1
2
3
I/O Waits
This field controls how many wait states
are injected into DMA and processor I/O
cycles:
00 None
01
10
11
1
2
3
Request
Sense 1-0
Each of these bits controls how the
corresponding DMA channel samples its
Request signal (except when DMA 0’s
Source and Dest Mode fields are both
0x)
0
1
Level sense: the DMA samples its
Request again during the second cycle
for each byte
Edge sense: another falling edge is
needed on the Request line before the
DMA channel transfers another byte
See section, which starts on page 40,
for timing of both cases.
1-0
DMA1 Mode R/W
This field controls the direction of both
transfer and address stepping on DMA
channel 1:
00 Incrementing Memory addrs to I/O
01 Decrementing Memory addrs to I/O
10 I/O to incrementing Memory addrs
11 I/O to decrementing Memory addrs
WATCH-DOG TIMER REGISTERS
See “Watch-Dog Timer” on page 45, for more about these registers.
TABLE 79. WATCH-DOG TIMER MASTER REGISTER (0064H) WDTMR
Bit
7
6
5
4
3
2
1
0
Bit/Field Enable Period Select
Drive Power WDT
State
Reg
Reset
On
Reset
Reset Change Write
Enable Enable
R/W
R
1
R/W
R/W
RC
RC
R/W
1
R
1
Reset
1
1
POR=1 POR=1 WDT
0QVGꢄꢀR = Read W = Write X = Indeterminate
104
Preliminary Z80S183/Z80L183
PS000501-XMP1299
WATCH-DOG TIMER REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
7
WDT
R
When this read-only bit is 1the Watch-
Enabled
Dog Timer is enabled.
6-5
Period Select R/W
The field selects how long software can
leave the Watch-Dog Timer unattended,
before it resets the part:
00 218 (262,144) PHI clocks
01 222 (4,194,304) PHI clocks
10 225 (33,554,432) PHI clocks
11 227 (134,217,728) PHI clocks
4
3
Drive Reset
R/W
When this bit is 1, as it is after a Power
On Reset, expiration of the WDT drives
the Reset pin Low, to reset external
devices. WDT expiration resets the
Z80S183/Z80L183 regardless of this bit.
Power On
Reset
RC
RC
A Power On Reset sets this bit. (This
includes a POR sequence caused by a
rising edge on the OPMOD1 or PWRUP
pin.) Reading this register clears this bit.
2
1
WDT Reset
WDT expiration sets this bit. Reading
this register clears it.
StateChange R/W
Enabled
When this bit is 1, writing 40H to the
WDT Command register disables the
WDT, and writing B0H to it enables the
WDT. Such changes only become
effective after this bit is cleared.
0
Register
Write Enable
R
When this read-only bit is 1, as it is after
a reset, the System Configuration
Register, port Data Direction Registers,
the Power Control Register, and all of
the Real Time Clock registers can be
written. When this bit is 0, these
registers are read-only.
TABLE 80. WATCH-DOG TIMER MASTER REGISTER (0064H) WDTMR
Bit
7
6
5
4
3
2
1
0
Bit/Field Enable Period Select
Drive Power WDT
State
Reg
Reset
On
Reset
Reset Change Write
Enable Enable
R/W
R
1
R/W
R/W
RC
RC
R/W
1
R
1
Reset
1
1
POR=1 POR=1 WDT
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
105
I/O REGISTERS
WATCH-DOG TIMER REGISTERS
Bit
Position Bit/Field
R/W Value Description
7
WDT
Enabled
R
When this read-only bit is 1 the Watch-
Dog Timer is enabled.
6-5
Period Select R/W
This field selects how long software can
leave the Watch-Dog Timer unattended,
before it resets the part:
00 218 (262,144) PHI clocks
01 222 (4,194,304) PHI clocks
10 225 (33,554,432) PHI clocks
11 227 (134,217,728) PHI clocks
4
3
Drive Reset
R/W
When this bit is 1, as it is after a Power
On Reset, expiration of the WDT drives
the RESET pin Low, to reset external
devices. WDT expiration resets the
Z80S183/Z80L183 regardless of this bit.
Power On
Reset
RC
RC
A Power On Reset sets this bit. (This
includes a POR sequence caused by a
rising edge on the OPMOD1 or PWRUP
pin.) Reading this register clears this bit.
2
1
WDT Reset
WDT expiration sets this bit. Reading
this register clears it.
StateChange R/W
Enabled
When this bit is 1, writing 40H to the
WDT Command register disables the
WDT, and writing 0B0H to it enables the
WDT.
0
Register
Write Enable
R
When this read-only bit is 1, as it is after
a reset, the System Configuration
Register, port Data Direction Registers,
the Power Control Register, and all of
the Real Time Clock registers can be
written. When this bit is 0, these
registers are read-only.
TABLE 81. WATCH-DOG TIMER COMMAND REGISTER (0065H) WDTCR
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
WDT Command
W
Reset
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
0QVGꢄꢀR = Read W = Write X = Indeterminate
106
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROGRAMMABLE RELOAD TIMER (PRT) REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
7-0
WDT
Command
W
Software can write the following values
to this register, to affect the status of the
WDT and Z80S183/Z80L183:
0BH Set Register Write Enable (WDTMR Bit 0)
Disables WDT if WDTMR Bit 1 is 1
40H Reloads/Restarts WDT
4EH Enables WDT if WDTMR Bit 1 is 1
B0H
Writing any value other than 0BH to this
register clears the Register Write Enable
bit.
PROGRAMMABLE RELOAD TIMER (PRT) REGISTERS
See section “Programmable Reload Timers (PRTs)” on page 46, for more about
these registers.
TABLE 82. PRT0 TIMER DATA REGISTER LOW (000CH) TMDR0L
Bit
7
6
5
4
3
2
1
1
1
0
1
Bit/Field
R/W
LS Byte of PRT0 Counter
R/W
Reset
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
LS byte of
PRT0
R/W
The LS 8 bits of the PRT0 down-
counter.
Counter
TABLE 83. PRT0 TIMER DATA REGISTER HIGH (000DH) TMDR0H
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
MS Byte of PRT0 Counter
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
MS byte of
PRT0
R/W
The MS 8 bits of the PRT0 down-
counter.
Counter
PS000501-XMP1299
Preliminary Z80S183/Z80L183
107
I/O REGISTERS
PROGRAMMABLE RELOAD TIMER (PRT) REGISTERS
TABLE 84. PRT0 RELOAD REGISTER LOW (000EH) RLDR0L
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
LS Byte of PRT0 Reload Value
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
LS byte of
PRT0 Reload
Value
R/W
The LS 8 bits of the value that is loaded
into the PRT0 down-counter, when it is
decremented to 0.
TABLE 85. PRT0 TIMER DATA REGISTER LOW (000CH) TMDR0L
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
LS Byte of PRT0 Counter
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
LS byte of
PRT0
R/W
The LS 8 bits of the PRT0 down-
counter.
Counter
TABLE 86. PRT0 TIMER DATA REGISTER HIGH (000DH) TMDR0H
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
MS Byte of PRT0 Counter
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
MS byte of
PRT0
R/W
The MS 8 bits of the PRT0 down-
counter.
Counter
108
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROGRAMMABLE RELOAD TIMER (PRT) REGISTERS
I/O REGISTERS
TABLE 87. PRT0 RELOAD REGISTER LOW (000EH) RLDR0L
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
LS Byte of PRT0 Reload Value
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
LS byte of
PRT0 Reload
Value
R/W
The LS 8 bits of the value that is loaded
into the PRT0 down-counter, when it is
decremented to 0.
TABLE 88. PRT0 RELOAD REGISTER HIGH (000FH) RLDR0H
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
MS Byte of PRT0 Reload Value
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
MS byte of
PRT0 Reload
Value
R/W
The MS 8 bits of the value that is loaded
into PRT0’s down-counter, when it is
decremented to 0.
TABLE 89. TIMER CONTROL REGISTER (0010H) TCR
Bit
7
TIF1
R
6
TIF0
R
5
4
3
2
1
0
Bit/Field
R/W
TIE1
R/W
0
TIE0
R/W
0
Resvd
?
TDE1 TDE0
R/W
0
R/W
0
Reset
0
0
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W Value Description
7-6 TIF1,0
R
One of these status bits is set when a
PRT decrements its down-counter to 0.
It is cleared when software has read this
register and either byte of the TMDR.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
109
I/O REGISTERS
PROGRAMMABLE RELOAD TIMER (PRT) REGISTERS
Bit
Position Bit/Field
R/W Value Description
5-4
TIE1,0
R/W
When one of these bits is 1, the
corresponding PRT requests an
interrupt when its down-counter has
counted down to 0 and it has set the TIF
bit.
1-0
TDE1,0
R/W
0
1
The corresponding PRT is stopped.
The corresponding PRT is running.
TABLE 90. PRT1 TIMER DATA REGISTER LOW (0014H) TMDR1L
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
LS Byte of PRT1 Counter
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W The LS 8 bits of PRT1’s down-counter.
7-0
LS byte of
PRT1
Counter
TABLE 91. PRT1 TIMER DATA REGISTER HIGH (0015H) TMDR1H
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
MS Byte of PRT1 Counter
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
R/W The MS 8 bits of PRT1’s down-counter.
7-0
MS byte of
PRT1
Counter
110
Preliminary Z80S183/Z80L183
PS000501-XMP1299
REAL TIME CLOCK (RTC) REGISTERS
I/O REGISTERS
TABLE 92. PRT1 RELOAD REGISTER LOW (0016H) RLDR1L
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
LS Byte of PRT1 Reload Value
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
LS byte of
PRT1 Reload
Value
R/W
The LS 8 bits of the value that is loaded
into PRT1’s down-counter, when it is
decremented to 0.
TABLE 93. PRT1 RELOAD REGISTER HIGH (0017H) RLDR1H
Bit
7
6
5
4
3
2
1
1
0
1
Bit/Field
R/W
MS Byte of PRT1 Reload Value
R/W
Reset
1
1
1
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
MS byte of
PRT1 Reload
Value
R/W
The MS 8 bits of the value that is loaded
into PRT1’s down-counter, when it is
decremented to 0.
REAL TIME CLOCK (RTC) REGISTERS
See the section titled “Real Time Clock (RTC)” on page 48, for more about these
registers.
TABLE 94. RTC CONTROL/STATUS REGISTER (006FH) RTCCS
Bit
7
Alarm
R/W
0
6
IE
5
Resvd
?
4
3
2
1
Resvd
?
0
Bit/Field
R/W
Clock Select
R/W
R/W
0
Reset
X
0
0
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
111
I/O REGISTERS
REAL TIME CLOCK (RTC) REGISTERS
Bit
Position Bit/Field
R/W Value Description
7
Alarm
R/W
The RTC sets this bit when the hours,
minutes, and seconds registers equal
the programmed alarm value. Software
can set this bit to 0, but either:
– wait a second before doing so or
– change the Alarm value before doing
so, to prevent the continuing match from
resetting Alarm.
6
IE
R/W
When this bit is 1, the RTC requests an
interrupt when the Alarm bit is 1. When
the service routine for this interrupt
clears Alarm by method a) above, it
clears this bit during the match second
to avoid further interrupts.
4-3
Clock Select R/W
0x The RTC takes its clock from the
LFXTAL and LFEXTAL pins that must
be connected to a 32.768 KHz crystal.
The RTC takes its clock from the PC0
10 pin that must be programmed as an
input and connected to a 60 Hz line
frequency.
The RTC takes its clock from the PC0
11 pin that must be programmed as an
input and connected to a 50 Hz line
frequency.
TABLE 95. RTC CONTROL/STATUS REGISTER (006FH) RTCCS
Bit
7
Alarm
R/W
0
6
IE
5
Resvd
?
4
3
2
1
Resvd
?
0
Bit/Field
R/W
Clock Select
R/W
R/W
0
Reset
X
0
0
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
7
6
Alarm
R/W
The RTC sets this bit when the hours,
minutes, and seconds registers equal
the programmed alarm value. Software
can write a 0 to this bit to 0, but should
change the Alarm value before doing so,
to prevent the continuing match from
setting Alarm again.
IE
R/W
When this bit is 1, the RTC requests an
interrupt when the Alarm bit is 1.
112
Preliminary Z80S183/Z80L183
PS000501-XMP1299
REAL TIME CLOCK (RTC) REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
4-3
Clock Select R/W 0x The RTC takes its clock from the
LFXTAL and LFEXTAL pins that must
be connected to a 32.768 KHz crystal.
The RTC takes its clock from the PC0
10 pin that must be programmed as an
input and connected to a 60 Hz line
frequency.
The RTC takes its clock from the PC0
11 pin that must be programmed as an
input and connected to a 50 Hz line
frequency.
TABLE 96. RTC SECONDS REGISTER (0070H) RTCSEC
Bit
7
0
6
5
4
3
Seconds
R/W
2
1
0
Bit/Field
R/W
R
0
Reset
NC
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC once per
second. BCD 59H is followed by 0.
6-0 Seconds
TABLE 97. RTC MINUTES REGISTER (0071H) RTCMIN
Bit
7
0
6
5
4
3
Minutes
R/W
2
1
0
Bit/Field
R/W
R
0
Reset
NC
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC when the
6-0 Minutes
Seconds register increments from 59H
to 0. This BCD register also increments
from 59H to 0.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
113
I/O REGISTERS
REAL TIME CLOCK (RTC) REGISTERS
TABLE 98. RTC HOURS REGISTER 0072H) RTCHR
Bit
7
0
6
0
5
4
3
2
1
0
Bit/Field
R/W
Hours
R/W
R
R
Reset
NC
NC
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC when the
5-0 Hours
Minutes register increments from 59H to
0. This BCD register increments from
23H to 0.
TABLE 99. RTC DAY OF THE WEEK REGISTER (0073H) RTCDAY
Bit
7
0
6
0
5
0
4
0
3
0
2
1
0
Bit/Field
R/W
Day
R/W
NC
R
0
R
0
R
0
R
0
R
0
Reset
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC when the
2-0 Day
Hours register increments from 23H to
0. This register increments from 7 to 1.
TABLE 100. RTC DATE REGISTER (0074H) RTCDAT
Bit
7
0
6
0
5
4
3
2
1
0
Bit/Field
R/W
Date
R/W
R
0
R
0
Reset
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
114
Preliminary Z80S183/Z80L183
PS000501-XMP1299
REAL TIME CLOCK (RTC) REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC when the
5-0
Date
Hours register increments from 23H to
0. This BCD register increments from
28H, 30H, or 31H to 1, depending on the
month and (for February) the year and
century.
TABLE 101. RTC MONTH REGISTER (0075H) RTCMO
Bit
7
0
6
0
5
0
4
3
2
1
0
Bit/Field
R/W
Month
R/W
NC
R
0
R
0
R
0
Reset
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
4-0 Month
R/W
Incremented by the RTC when the Date
register increments to 1. This BCD
register increments from 12H to 1.
TABLE 102. RTC YEAR REGISTER (0076H) RTCYR
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Year
R/W
Reset
NC
NC
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC when the
7-0 Year
Month register increments from 12H to
1. This BCD register increments from
99H to 0.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
115
I/O REGISTERS
REAL TIME CLOCK (RTC) REGISTERS
TABLE 103. RTC CENTURY REGISTER (0077H) RTCC
Bit
7
0
6
0
5
4
3
2
1
0
Bit/Field
R/W
Century
R/W
R
0
R
0
Reset
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC in a BCD
5-0 Century
fashion, when the Years register
increments from 99H to 0.
TABLE 104. RTC ALARM SECONDS REGISTER (0078H) ALARMS
Bit
7
0
6
5
4
3
2
1
0
Bit/Field
R/W
Alarm Seconds
R/W
R
0
Reset
NC
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
6-0
Alarm
Seconds
R/W
The seconds component of the Alarm
time (BCD).
TABLE 105. RTC ALARM MINUTES REGISTER (0079H) ALARMM
Bit
7
0
6
5
4
3
Minutes
R/W
2
1
0
Bit/Field
R/W
R
0
Reset
NC
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
R/W Incremented by the RTC when the
6-0 Year
Month register increments from 12 to 1.
This register increments from 99 to 0.
116
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DIGITAL-TO-ANALOG CONVERTER (DAC) REGISTERS
I/O REGISTERS
TABLE 106. RTC ALARM HOURS REGISTER (007AH) ALARMH
Bit
7
0
6
0
5
4
3
2
1
0
Bit/Field
R/W
Alarm Hours
R/W
R
0
R
0
Reset
NC
NC
NC
NC
NC
NC
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register can only be written if the Register Write Enable bit (WDTMR 0) is 1.
Bit
Position Bit/Field
R/W Value Description
4-0
Alarm Hours R/W
The hours component of the Alarm time
(BCD).
DIGITAL-TO-ANALOG CONVERTER (DAC) REGISTERS
See “Digital/Analog Converter (DAC)” on page 51, for more about these registers.
TABLE 107. DAC CONTROL REGISTER (0069H) DACCR
Bit
7
6
5
4
3
2
1
0
Bit/Field
Data 1-0
Ref Select
Resvd Output
Enable
Resvd
?
R/W
R/W
R/W
?
R/W
0
Reset
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W Value Description
7-6
5-4
2
Data 1-0
R/W
R/W
R/W
This field contains the 2 LS bytes of the
10-bit digital value that the DAC
converts to analog.
Reference
Voltage
Select
0X DAC reference voltage is PA0 pin
10 Internal 4.2V
11 Internal 2.6V
Output
Enable
A 1 in this bit enables the DAC to drive
its analog result voltage onto the AOUT
pin.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
117
I/O REGISTERS
ANALOG TO DIGITAL CONVERTER (ADC) REGISTERS
TABLE 108. DAC DATA REGISTER (006AH) DAC
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Data 9-2
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0 Data 9-2
R
Writing to this register sets Bits 9-2 of
the digital value the DAC is to convert.
With Bits 7-6 of the DACCR, this value is
a 10-bit binary fraction of the selected
reference voltage. For example,
1000000000B means that the DAC
outputs half of the reference voltage.
The DAC continuously converts this
value, so rewriting this register produces
the corresponding voltage on AOUT
within the specified conversion time.
ANALOG TO DIGITAL CONVERTER (ADC) REGISTERS
See section “Analog/Digital Converter (ADC)” on page 52, for more about these
registers.
TABLE 109. ADC CONTROL REGISTER 0 (0066H) ADCC0
Bit
7
6
5
Resvd
?
4
3
2
Enable
R/W
0
1
0
Bit/Field
R/W
Ref Select
R/W
Reset
X
X
X
X
X
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W Value Description
2
Enable
R/W
This bit enables the ADC and must be
set prior to starting an ADC conversion.
When this bit is 0, the ADC powers
down.
1-0
Reference
Voltage
Select
R/W
0x ADC Reference voltage is PA0 pin
10 Internal Reference 4.2 V
11 Internal Reference 2.6 V
118
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ANALOG TO DIGITAL CONVERTER (ADC) REGISTERS
I/O REGISTERS
TABLE 110. ADC CONTROL REGISTER 1 (0067H) ADCC1
Bit
7
6
5
IE
4
CC
R
3
Start
W
2
0
1
0
0
Bit/Field
R/W
Result 1-0
R
Channel Select
R/W
0
R/W
0
Reset
X
X
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-6
Result 1-0
R
When a conversion is completed, these
bits hold the LS bits of the digital value
5
IE
R/W
When this bit is 1 when the ADC
completes a conversion, an interrupt is
requested.
4
Conversion
Complete
(CC)
R
W
The ADC sets this bit when it completes
a conversion. This bit is cleared when
software writes a 1 to the Start bit, to
begin a new conversion.
3
Start
Writing a 1 to this bit causes the ADC to
start a new conversion. When the ADC
had a conversion in progress, it is
aborted.
2-0
Channel
Select
R/W
These bits select which pin is sampled
for a conversion.
000 Pin PD0
001 Pin PD1
010 Pin PD2
011 Pin PD3
100 Pin PD4
101 Pin PD5
110 Pin PD6
111 Pin PD7
TABLE 111. ADC RESULT REGISTER (0068H) ADC
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Result 9-2
R
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
119
I/O REGISTERS
PROGRAMMABLE OUTPUT GENERATOR (POG) REGISTERS
Bit
Position Bit/Field
R/W Value Description
7-0 Result 9-2
R
After the ADC has completed a
conversion, this register contains Bits
9-2 of the result digital value. With Bits
7-6 of the ADCC1, this value is a 10-bit
binary fraction of the selected reference
voltage. For example, 1000000000B
means that the voltage on the selected
pin was half of the reference voltage.
PROGRAMMABLE OUTPUT GENERATOR (POG) REGISTERS
See section “Programmable Output Generator (POG)” on page 54, for more about
these registers.
TABLE 112. POG CONTROL REGISTER (0060H) POGCR
Bit
7
6
IE
5
IP
4
3
Resvd
?
2
1
0
Bit/Field Enable
Clock Select
R/W
R/W
R/W
0
R/W
0
R/W
0
Reset
X
X
X
0
0
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W Value Description
7
6
Enable
IE
R/W
R/W
A 1 in this bit enables the POG.
A 1 in this bit allows the POG to request
an interrupt when it encounters an entry
in its RAM, directing it to do so.
5
IP
R/W
The POG sets this bit when it
encounters an “interrupt” entry in its
RAM. Interrupt service routines write a 0
to this bit to clear the POG interrupt
request.
1-0
Clock Select R/W
This field determines the POG clock
frequency
00 PHI
01 PHI/256
10 PHI/1024
11 PHI/4096
120
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROGRAMMABLE OUTPUT GENERATOR (POG) REGISTERS
I/O REGISTERS
TABLE 113. POG ADDRESS/TYPE REGISTER (0061H) POGAT
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Next Address
R
Entry Type
R
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-2
Next Address
R
Software can read the Next Address
value from the RAM entry most recently
fetched by the POG, in this field.
1-0
Entry Type
R
Software can read the Entry Type value
from the RAM entry most recently
fetched by the POG, in this field.
TABLE 114. POG COUNTER LOW (0062H) POGCL
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS Byte of POG Counter
R
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7-0
Counter LS
byte
R
Software can read the LS 8 bytes of the
current POG Counter value from this
register.
TABLE 115. POG COUNTER HIGH (0063H) POGCH
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
MS Byte of POG Counter
R
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
121
I/O REGISTERS
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
Bit
Position Bit/Field
R/W Value Description
7-0
Counter MS
byte
R
Software can read the MS 8 bytes of the
POG Counter value, at the time that
POGCL was last read, from this register.
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
See section “Clocked Serial Input/Output Module (CSI/O)” on page 69, for more
detail about these registers.
TABLE 116. ASCI0 CONTROL REGISTER A (0000H) CNTLA0
Bit
7
6
5
4
3
2
1
0
Bit/Field
MPE
RE
TE
Reserv MPBR/ MOD2 MOD1 MOD0
ed
R/W
1
EFR
R/W
X
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7
Multi-
processor
Mode Enable
R/W
When this bit and the MP bit in CNTLB
are both 1, only received characters
having a 1 in an additional bit between
the last data bit and the Stop bit are
placed in the Rx FIFO. When either the
MP bit or this bit is 0, all received
characters are placed in the Rx FIFO.
6
5
4
3
Receive
Enable
R/W
R/W
R/W
R/W
A 1 in this bit enables the receiver.
Writing a 0 stops reception.
Transmit
Enable
A 1 in this bit enables the transmitter.
Writing a 0 stops transmission.
Reserved
On other 180 devices this bit controlled
the RTS0 output.
MP Bit Rcv/
Error Flag
Reset
Reading this bit returns the value of the
multiprocessor (MP) bit. Read this
register before reading the RDR. Writing
a 0 to this bit clears the OVRN, FE, PE,
and Break Detect bits. Writing a 1 has
no effect.
2
1
0
MOD2
MOD1
MOD0
R/W
R/W
R/W
0
1
7 bit data (Tx and Rx)
8 bit data
0
1
No parity (Tx and Rx)
Parity generated (Tx), checked (Rx)
0
1
1 Stop bit transmitted
2 Stop bits transmitted
122
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
I/O REGISTERS
TABLE 117. ASCI1 CONTROL REGISTER A (0001H) CNTLA1
Bit
7
6
5
4
3
2
1
0
Bit/Field
MPE
RE
TE
Resvd MPBR/ MOD2 MOD1 MOD0
EFR
R/W
R/W
0
R/W
0
R/W
0
?
R/W
1
R/W
0
R/W
0
R/W
0
Reset
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
All bits in this register are as described in Table 116.
TABLE 118. ASCI0 CONTROL REGISTER B (0002H) CNTLB0
Bit
7
6
5
4
3
2
1
0
1
Bit/Field
MPBT
MP
CTS/
PS
PEO
DR
Speed Select
R/W
R/W
X
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
Reset
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7
Multi-
Processor Bit
Tx
R/W
When the MP bit (Bit 6) is 1, this bit
defines the value to send in the MP bit
with the next character written to the
Transmit Data Register.
6
Multi-
processor
Mode
R/W
When this bit is 1, the ASCI sends, and
expects to receive, an extra bit after the
last data bit. The extra bit is 1 in address
characters that begin frames and 0 in
following data characters.
5
CTS/PS
R/W
Reading this pin returns the state of the
CTS pin (0 is Low, 1 is High). For
writing, this bit is PS. When Bits 2–0 in
this register are not 111 and the BRG
Mode bit in the Extension Control
register is 0, PS determines whether the
PHI clock is prescaled by 10 (for 0) or 30
(for 1) as the first stage in ASCI
clocking.
4
3
Parity Even/
Odd
R/W
R/W
When MOD1 (CNTLA Bit 1) is 1, this bit
selects whether parity is generated and
checked as even (for 0) or odd (for 1).
DR
0
1
The ASCI divides its basic clock by 16 to
obtain its bit rate.
The ASCI divides its basic clock by 64 to
obtain its bit rate.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
123
I/O REGISTERS
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
Bit
Position Bit/Field
R/W Value Description
2–0
Speed Select R/W
111 Do not program this value.
(other) When the BRG0 Mode bit is 1, the
output of the new BRG is the basic clock
of the ASCI. When BRG0 Mode is 0,
these bits determine what the output of
the Prescaler is divided by, to obtain
basic clock for the ASCI:
used as is
000 Divide by 2
001 Divide by 4
010 Divide by 8
011 Divide by 16
100 Divide by 32
101 Divide by 64
110 The ASCI divides the basic clock by 16
or 64 to obtain the bit rate.
TABLE 119. ASCI1 CONTROL REGISTER B (0003H) CNTLB1
Bit
7
MPBT
R/W
X
6
MP
R/W
0
5
PS
R/W
0
4
3
DR
R/W
0
2
1
0
1
Bit/Field
R/W
PEO
R/W
0
Speed Select
R/W
1
Reset
1
0QVGꢄꢀR = Read W = Write X = Indeterminate
All bits in this register are as described in Table 118, except that Bit 5 has no func-
tion in write operations on the Z80S183/Z80L183 ASCI1.
TABLE 120. ASCI0 STATUS REGISTER (0004H) STAT0
Bit
7
6
5
PE
R
4
FE
R
3
RIE
R/W
0
2
1
0
TIE
R/W
0
Bit/Field
R/W
RDRF OVRN
DCD0 TDRE
R
0
R
0
R
R
0
Reset
0
0
pin
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7
RDRF
R
The Z80S183/Z80L183 sets this bit
when a character is received. Reading
the last received byte from the Rx FIFO
clears this bit. See Note below.
124
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
6
5
4
OVRN
R
R
R
This bit is set when the last character
received before an Overrun condition
comes to the top of the Rx FIFO. It is
cleared when a 0 is written to the EFR
bit in CNTL0. See Note below.
PE
This bit is set if parity is enabled, and a
character with a Parity Error comes to
the top of the Rx FIFO. It is cleared
when a 0 is written to the EFR bit in
CNTL0. See Note below.
FE
This bit is set if a character with a
Framing Error (one in which the Stop bit
was sampled as 0) comes to the top of
the Rx FIFO. It is cleared when a 0 is
written to the EFR bit in CNTL0. See
Note below.
3
RIE
R/W
When this bit is 1, the ASCI requests an
interrupt when any of the flags OVRN,
PE, FE, or Break Detect is set, or if Bit 7
of the Extension Control register is 0
and RDRFis 1, or if Bit 6 of the
Extension Control register is 0 and
DCD0 is Low.
2
1
DCD0
TDRE
R
R
This bit is 1 whenever the DCD0pin is
High. When DCD0 goes Low, the next
read of this register returns a 1. The next
read returns a 0 if DCD0 is still Low.
This bit is cleared when software writes
a character to the TDR. It is set when
the character leaves the TDR for
transmission, by Reset, and in I/O Stop
mode. It is cleared if Bit 5 of the
Extension Control register is 0 and
CTS0 is High.
0
TIE
R/W
When this bit is 1, the ASCI requests an
interrupt when TDRE is 1.
0QVGꢄꢀThe RDRF, OVRN, PE, and FE bits are cleared by Reset, during I/O Stop mode, and
for ASCI0, if the DCD Disable bit in the Extension Control register is 0 and DCD0 is High.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
125
I/O REGISTERS
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
TABLE 121. ASCI1 STATUS REGISTER (0005H) STAT1
Bit
7
6
5
4
3
2
1
0
Bit/Field
RDRF OVRN
PE
FE
RIE
Reserv TDRE
ed
TIE
R/W
R
0
R
0
R
0
R
0
R/W
0
R
R
0
R/W
0
Reset
pin
0QVGꢄꢀR = Read W = Write X = Indeterminate
This register is as described in Table 120, except that Bit 2 has no function for
Z80S183/Z80L183 ASCI1.
TABLE 122. ASCI0 TX DATA REGISTER (0006H) TDR0
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Character to Tx
W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0 Tx character R/W
Software can write a character to be
transmitted to this register, when the
TDRE flag in STAT0 is 1.
TABLE 123. ASCI1 TX DATA REGISTER (0007H) TDR1
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Character to Tx
W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0 Tx character R/W
Software can write a character to be
transmitted to this register, when the
TDRE flag in STAT1 is 1.
126
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
I/O REGISTERS
TABLE 124. ASCI0 RX DATA REGISTER (0008H) RDR0
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Received Character
R
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0 Rx character R/W
When the RDRF flag in STAT0 is 1,
software can read a received character
from this register.
TABLE 125. ASCI1 RX DATA REGISTER (0009H) RDR1
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Received Character
R
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0 Rx character R/W
When the RDRF flag in STAT1 is 1,
software can read a received character
from this register.
TABLE 126. ASCI0 EXTENSION CONTROL REGISTER (0012H) ASEXT0
Bit
7
6
5
4
3
2
1
0
Bit/Field
RDID DCD0 CTS0
X1
BRG Start IE
Rx
Tx
Disable Disable Clock Mode
Break Break/
TxEnd
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
Reset
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
127
I/O REGISTERS
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
Bit
Position Bit/Field
R/W Value Description
7
Rx Data
Interrupt
Disable
R/W
When RIE (STAT Bit 3) and this bit are
both 1, the ASCI requests receive
interrupts only when OVRN, PE, or FE is
set. When RIE is 1 and this bit is 0, the
ASCI also requests interrupts when
RDRF is set (for each received
character). When RIE is 0, this bit has no
effect.
6
5
DCD0
Disable
R/W
R/W
0
1
DCD0 auto-enables the receiver
DCD0 has no effect on the receiver
CTS0
Disable
0
1
CTS0 auto-enables the transmitter
CTS0 has no effect on the transmitter
4
3
X1 Clock
R/W
R/W
0
0
Always 0 on the Z80S183/Z80L183.
BRG Mode
The SS bits in Control Register B
determine the factor by which the
Prescaler output is divided, to obtain the
ASCI’s basic clock.
1
The ASCI’s basic clock comes from the
new BRG.
2
1
Start IE
R/W
R
When this bit and RIE are both 1, the
ASCI requests an interrupt when the
start of a start bit is detected, for auto-
bauding. Writing a 0 to this bit clears the
interrupt request.
RxBreak
This bit is 1 if the receiver has detected a
Break condition, that is, if all bits in a
character, including the Stop bit, are 0.
The all-0 character is placed in the Rx
FIFO if there is room, but the receiver
does not assemble any more characters
until the RXA pin has returned High.
0
TxBreak/
TxEnd
R/W
Writing a 1 to this bit makes the
transmitter drive TXA Low to send a
Break condition, until software writes a 0
to this bit. This bit reads as 0 while a
character is transmitted, but becomes 1
when the number of Stop bits selected
by MOD0 in CNTLA have been sent.
128
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASYNC SERIAL COMMUNICATIONS INTERFACE (ASCI) REGISTERS
I/O REGISTERS
TABLE 127. ASCI1 EXTENSION CONTROL REGISTER (0013H) ASEXT1
Bit
7
6
5
4
3
2
1
0
Bit/Field
RDID
Resvd
?
X1
BRG Start IE
Rx
Tx
Clock Mode
Break Break/
TxEnd
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
Reset
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate ? = Not Applicable
This register is as described in the previous table, except that Bits 6–5 have no
function for Z80S183/Z80L183 ASCI1.
TABLE 128. ASCI0 TIME CONSTANT LOW (001AH) ASTC0L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS Byte of Time Constant
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0
LS byte of
Time
R/W
The Least Significant 8 bits of the ASCI0
Baud Rate Generator’s Time Constant.
Constant
TABLE 129. ASCI0 TIME CONSTANT HIGH (001BH) ASTC0H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS Byte of Time Constant
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0
MS byte of
Time
R/W
The Most Significant 8 bits of the ASCI0
Baud Rate Generator’s Time Constant.
Constant
PS000501-XMP1299
Preliminary Z80S183/Z80L183
129
I/O REGISTERS
CLOCKED SERIAL I/O (CSI/O) REGISTERS
TABLE 130. ASCI1 TIME CONSTANT LOW (001CH) ASTC1L
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS Byte of Time Constant
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0
LS byte of
Time
R/W
The Least Significant 8 bits of the ASCI1
Baud Rate Generator’s Time Constant.
Constant
TABLE 131. ASCI0 TIME CONSTANT HIGH (001DH) ASTC1H
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
LS Byte of Time Constant
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
Bit
Position Bit/Field
R/W Value Description
7–0
MS byte of
Time
R/W
The Most Significant 8 bits of the ASCI1
Baud Rate Generator’s Time Constant.
Constant
CLOCKED SERIAL I/O (CSI/O) REGISTERS
See section , which starts on page 69, for more about these registers.
TABLE 132. CSI/O CONTROL REGISTER (000AH) CNTR
Bit
7
EF
R
6
EIE
R/W
0
5
RE
R/W
0
4
TE
R/W
0
3
Resvd
?
2
1
0
Bit/Field
R/W
Speed Select (SS)
R/W
Reset
0
X
1
1
1
0QVGꢄꢀR = Read W = Write X = Indeterminate? = Not Applicable
130
Preliminary Z80S183/Z80L183
PS000501-XMP1299
CLOCKED SERIAL I/O (CSI/O) REGISTERS
I/O REGISTERS
Bit
Position Bit/Field
R/W Value Description
The CSI/O sets this bit to 1 when it
7
End Flag
(EF)
R
finishes sending or receiving a byte. It
clears this bit when software reads or
writes the TRDR, on Reset, and during
I/O Stop mode.
6
5
End Interrupt R/W
Enable (EIE)
When this bit is 1, the CSI/O requests an
interrupt when it completes sending or
receiving a byte and sets EF.
Receive
R/W
Write a 1 to this bit to start a CSI/O
receive operation. When the SS bits are
111, the CSI/O waits for 8 clock pulses
on CKS. Otherwise, it outputs 8 clock
pulses on CKS. In either case, it clocks
data on RXS into the TRDR at each
rising edge on CKS. After capturing the
8th bit, it clears this bit and sets EF.
Enable (RE)
4
Transmit
Enable (TE)
R/W
Write a 1 to this bit to start CSI/O
transmission. When the SS bits are 111,
the CSI/O waits for 8 clock pulses on
CKS. Otherwise, it outputs 8 clock
pulses on CKS. In either case, it clocks
data from the TRDR onto TXS at each
falling edge on CKS. After sending 8
bits, the CSI/O clears this bit and sets
EF.
2–0
Speed Select R/W
(SS)
When these bits are 111, as they are
after a Reset, the CSI/O takes external
clocking from the CKS pin. Otherwise, it
drives a clock onto CKS, that it derives
from PHI as follows:
000 PHI/20
001 PHI/40
010 PHI/80
011 PHI/160
100 PHI/320
101 PHI/640
110 PHI/1280
TABLE 133. CSI/O DATA REGISTER (000BH) TRDR
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Byte to Send (W) or Received Byte (R)
R/W
Reset
X
X
X
X
X
X
X
X
0QVGꢄꢀR = Read W = Write X = Indeterminate
PS000501-XMP1299
Preliminary Z80S183/Z80L183
131
INSTRUCTION SET
CLASSES OF INSTRUCTIONS
Bit
Position Bit/Field
R/W Value Description
R/W
7–0
Software writes a byte to this register,
before setting the TE bit, allowing the
CSI/O to send it. Software reads a
received byte from this register, after the
CSI/O sets the EF bit in response to
software setting the RE bit.
INSTRUCTION SET
The Z80S183/Z80L183 includes the 8S180 processor that descended from the
ZiLOG Z80. The 8-bit data bus and 20-bit address space fit well into a wide
variety of mid-range embedded processing applications. This processor provides
significantly more computing power than a microcontroller, at a fraction of the
system cost of a larger microprocessor.
For details of these instructions see the Z80S183/Z80L183 User Manual, or the
Z8S180 or Z80185 User Manuals until the Z80S183/Z80L183 User Manual is
available.
CLASSES OF INSTRUCTIONS
TABLE 134. LOAD INSTRUCTION
Mnemonic
Operands
Instruction
LD
dst,src
dst
Load
Pop
POP
PUSH
src
Push
TABLE 135. ARITHMETIC INSTRUCTIONS
Mnemonic
Operands
Instruction
ADC
ADD
CP
dst,src
dst,src
A,src
Add with Carry
Add
Compare
CPD(R)
CPI(R)
DAA
DEC
INC
Block Scan, decrementing (and Repeat)
Block Scan, incrementing (and Repeat)
Decimal Adjust Accumulator
Decrement
dst
dst
rr
Increment
MLT
NEG
SBC
SUB
Multiply
Negate Accumulator
Subtract with Carry
Subtract
dst,src
A,src
132
Preliminary Z80S183/Z80L183
PS000501-XMP1299
CLASSES OF INSTRUCTIONS
INSTRUCTION SET
TABLE 136. LOGICAL INSTRUCTIONS
Mnemonic
Operands
Instruction
AND
CPL
OR
A,src
Logical AND
Complement accumulator
Logical OR
A,src
A,src
A,src
TST
XOR
Test accumulator
Logical Exclusive OR
TABLE 137. EXCHANGE INSTRUCTIONS
Mnemonic
Operands
Instruction
EX
AF,AF’
DE,HL
(SP),rr
Exchange Accumulator and Flags
Exchange DE and HL
EX
EX
Exchange register and top of stack
Exchange register banks
EXX
TABLE 138. PROGRAM CONTROL INSTRUCTIONS
Mnemonic
Operands
Instruction
CALL
CALL
DJNZ
JP
cc,dst
dst
Conditional Call
Call
dst
Decrement and Jump if Non-Zero
Conditional Jump
Jump
cc,dst
dst
JP
JR
cc’,dst
dst
Conditional Jump Relative
Jump Relative
JR
RET
RET
RETI
RETN
RST
cc
Conditional Return
Return
Return from Interrupt
Return from Nonmaskable interrupt
Restart
dst
TABLE 139. BIT MANIPULATION INSTRUCTIONS
Mnemonic
Operands
Instruction
BIT
n,src
n,dst
n,dst
Bit test
Reset bit
Set bit
RES
SET
PS000501-XMP1299
Preliminary Z80S183/Z80L183
133
INSTRUCTION SET
CLASSES OF INSTRUCTIONS
TABLE 140. BLOCK TRANSFER INSTRUCTIONS
Mnemonic
Operands
Instruction
LDD(R)
LDI(R)
Block Move, decrementing (and Repeat)
Block Move, incrementing (and Repeat)
TABLE 141. ROTATE AND SHIFT INSTRUCTIONS
Mnemonic
Operands
Instruction
RL
dst
Rotate Left
RLA
RLC
RLCA
RLD
RR
Rotate Left Accumulator
Rotate Left Circular
Rotate Left Circular Accumulator
Rotate Left Decimal
Rotate Right
dst
dst
dst
RRA
RRC
RRCA
RRD
SLA
SRA
SRL
Rotate Right Accumulator
Rotate Right Circular
Rotate Right Circular Accumulator
Rotate Right Decimal
Shift Left
dst
dst
dst
Shift Right Arithmetic
Shift Right Logical
TABLE 142. INPUT/OUTPUT INSTRUCTIONS
Mnemonic
Operands
Instruction
IN
A, (n)
r, (C)
r, (n)
Input to A from port n
IN
Input to register from port in BC
IN0
Input to r from port n in page 0
IND(R)
INI(R)
Block Input, decrementing (and Repeat)
Block Input, incrementing (and Repeat)
Block Output, page 0, decrementing (and Repeat)
Block Output, page 0, incrementing (and Repeat)
Output from A to port n
OTDM(R)
OTIM(R)
OUT
(n), A
(C), r
(n), r
OUT
Output from register to port in BC
Output from register to port n in page 0
Block Output, decrementing (and Repeat)
Block Output, incrementing (and Repeat)
Test port (0,C) under mask
OUT0
OUTD (OTDR)
OUTI (OTIR)
TSTIO
n
134
Preliminary Z80S183/Z80L183
PS000501-XMP1299
PROCESSOR FLAGS
INSTRUCTION SET
TABLE 143. PROCESSOR CONTROL INSTRUCTIONS
Mnemonic
Operands
Instruction
CCF
DI
Complement Carry Flag
Disable Interrupts
Enable Interrupts
Halt
EI
HALT
IM
0/1/2
Interrupt Mode
No Operation
Set Carry Flag
Sleep
NOP
SCF
SLP
PROCESSOR FLAGS
Table 144 describes the Flag register. Bits in this register are set and cleared by
instructions described in the Z80S183/Z80L183 User Manual. Some of the Flags
are tested by conditional JR, JP, CALL, and RETinstructions, and some are used
by subsequent instructions such as ADC, SBC, and DAA. Accumulator A can also
perform PUSHand POPinstructions on the Flags.
TABLE 144. FLAG REGISTER F
Bit
7
S
0
6
Z
0
5
x
x
4
HC
0
3
x
x
2
P/V
0
1
N
0
0
CF
0
Name
Reset
0QVGꢄꢀX = Indeterminate
Bit/
Bit
Field Position Description
S
Z
7
6
5
4
3
2
1
0
Sign Flag
Zero Flag
Reserved, do not program
Half-carry Flag
HC
Reserved, do not program
Parity or Overflow Flag
Add/Subtract Flag
Carry Flag
P/V
N
CF
CONDITION CODES
Table 145 describes the codes used in the Flags Affected columns of the Instruc-
tion Summary Table, Table 148, to indicate how each flag is affected by each type
of instruction.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
135
INSTRUCTION SET
NOTATION
TABLE 145. FLAG SETTINGS DEFINITIONS
Symbol
Definition
0
Cleared to 10
Set to 1
1
*
Set or cleared according to the result of the operation
Unaffected
–
X
V
P
NZ
Undefined
Set if Overflow or Underflow
Set if Parity or result is Even
Set if the count in B or BC is non-zero
Table 146 describes the condition codes that can be used in conditional JP, CALL,
and RETinstructions in assembly language. A subset of these codes can also be
used in JRinstructions, which are shorter and faster than JPs.
TABLE 146. CONDITION CODES
Mnemonic Definition
Flag Settings
Valid in JR?
C
Carry
CF = 1
CF = 0
Z = 1
Y
Y
Y
Y
N
N
N
N
N
N
NC
Z
No Carry
0
NZ
M
Non-Zero
Minus
Z = 0
S = 1
P
Positive or 0
Parity Even
Parity Odd
Overflow
No Overflow
S = 0
PE
PO
V
P/V = 1
P/V = 0
P/V = 1
P/V = 0
NV
NOTATION
Table 147 describes other notation used in the subsequent Instruction Summary table.
TABLE 147. SYMBOLS
Symbol
Definition
(aa)
(mn), (IX±d), (IY±d), (BC), (DE), or (HL).
(BC), (DE), (HL) The 8-bit contents of memory, at the address pointed to by a
register pair.
(IX±d), (IY±d)
The 8-bit content of memory at the address formed by adding
the contents of the index register and the signed displacement
d in the instruction.
(mn)
(SP)
The 8-bit content of memory at the direct address mn.
The 16-bit contents of memory at the address pointed to by
SP, and the next higher address.
136
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ASSEMBLY LANGUAGE SYNTAX
INSTRUCTION SET
TABLE 147. SYMBOLS (CONTINUED)
Symbol
Definition
±d
Since d is signed, it would be more correct to just write +
instead. But we write ± to emphasize that d is signed.
AF
b
A concatenated with F, with A as the more-significant byte
A bit number 0–7
cc
A condition code C, NC, Z, NZ, S, M, PE, PV, V, or NV
A condition code C, NC, Z, or NZ
cc’
d
An 8-bit signed displacement –128 to +127
A 16-bit register BC, DE, HL, SP, IX, or IY
ee
IEF1,2
The processor’s two Interrupt Enable Flags. See the “Interrupt
Registers” on page 80 section for more detail.
mn
A 16-bit immediate data value or direct address
n
A 8-bit immediate value or port number, 0–255 or 0–FFH
op1–op2
A range of Op Code values, that includes some of the values
between the Low and High values. See the Note.
PC
Program Counter
pp
A 16-bit register BC, DE, HL, SP, IX, IY, or AF
An 8-bit register A, B, C, D, E, H, or L.
A 16-bit register HL, IX, or IY.
r, r’
rr
s
An 8-bit register or memory location
Stack Pointer
SP
ss
A 16-bit register BC, DE, HL, or SP.
The more- and less-significant eight bits of a register pair
ssH, ssL
tt
A 16-bit register like ss, except that the value that designates
HLin the ssencoding, here means same as the destination
register HL, IX, or IY.
0QVGꢄ The symbol – between Op Codes (op1–op2), in the Op Codes column of the
Instruction Summary table, indicates all the binary values between the lower and upper
limits inclusive, that can be formed by incrementing the set of bits that differ between the
lower and upper value.
'ZCORNGꢄꢀ00–C0 represents 00, 40, 80, and C0, while 40–BF represents all the values in
that range.
ASSEMBLY LANGUAGE SYNTAX
For two-operand instructions, Z80 assembly language syntax puts the destination
operand before the source operand.
'ZCORNGꢄꢀLDA,(1234)is a Load instruction, while LD(1234),Ais a Store
instruction.
Past Z80 assemblers allowed the destination operand to be omitted (implicit) if the
Op Code mnemonic only allowed one destination operand, for example, ANDL
instead of ANDA,L. Use of these short forms is discouraged because they are a
source of possible error (the programmer thinks that the implicit destination is
PS000501-XMP1299
Preliminary Z80S183/Z80L183
137
INSTRUCTION SET
INSTRUCTION SUMMARY
other than it really is). For the sake of legacy code, all known Z80 assemblers still
accept the short form.
%CWVKQPꢄ the assembly language uses C ambiguously, to designate one of the 8-bit regis-
ters as well as a condition code to test the Carry flag. This Product Specification uses CF
to designate the Carry flag, and HC to designate the Half-Carry flag (as opposed to the
8-bit register H).
INSTRUCTION SUMMARY
The following table describes each type or class of instruction, using the notation
described in the preceding sections. In cases where the Address Mode information
can be both Destination (Dest) and Source code, this information spans both the
Dest and Source columns (for example, the DECinstruction). The table is sorted
by the assembly language mnemonics.
.
TABLE 148. INSTRUCTION SUMMARY
Address Mode
Op Code(s) (Hex)
Flags Affected
HC P/V
Instruction and Operation
Dest
Source
S
Z
N
CF
ADC A,s
A ← A + s + CF
r
n
88–8F
CE
*
*
*
V
0
*
(HL)
(IX/Y±d)
8E
DD/FD 8E
ED 4A–7A
ADC HL,ss
HL ← HL+ ss + CF
*
*
*
*
*
*
V
V
0
0
*
*
ADD A,s
A ← A + s
r
n
80–87
C6
(HL)
(IX/Y±d)
86
DD/FD 86
09–39
ADD rr,tt
rr ← rr + tt
HL
–
*
–
*
*
–
0
0
*
IX/Y
DD/FD 09–39
A0–A7
E6
AND A,s
A ← A and s
r
n
1
P
0
(HL)
(IX/Y±d)
r
A6
DD/FD A6
CB 40–7F
CB 46–7E
BIT b,m
Z ← not (bit b of m)
X
–
*
1
–
X
–
0
–
–
–
(HL)
(IX/Y±d) DD/FD CB d 46–7E
C4–FC
CALL cc,mn
IF cc {SP ← SP – 2
(SP) ← PC
–
PC ← mn}
138
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INSTRUCTION SUMMARY
INSTRUCTION SET
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
Dest
Source
S
Z
HC P/V
N
CF
CALL mn
SP ← SP – 2
(SP) ← PC
PC ← mn
CD
–
–
–
–
–
–
CCF
CF ← not CF
3F
–
*
–
*
*
*
–
0
1
*
*
CP A,s
A – s
r
n
B8–BF
FE
V
(HL)
(IX/Y±d)
BE
DD/FD BE
ED A9
CPD
A − (HL)
HL ← HL – 1
BC ← BC – 1
*
*
*
*
*
*
NZ
NZ
1
1
–
–
CPDR
ED B9
repeat {A − (HL)
HL ← HL – 1
BC ← BC – 1
} while (not Z and BC!=0)
CPI
A − (HL)
HL ← HL + 1
BC ← BC – 1
ED A1
ED B1
*
*
*
*
*
*
NZ
NZ
1
1
–
–
CPIR
repeat {A − (HL)
HL ← HL + 1
BC ← BC – 1
} while (not Z and BC!=0)
CPL
A ← not A
2F
27
–
*
–
*
1
*
–
P
–
1
–
–
–
*
DAA
A ← decimal adjust (A,F)
DEC ee
ee ← ee – 1
ss
0B–3B
DD/FD 2B
05–3D
35
–
–
–
–
IX/Y
r
DEC m
m ← m – 1
*
*
*
V
–
1
–
–
–
(HL)
(IX/Y±d)
DD/FD 35
F3
DI
–
–
–
IEF1,2 ← 0
PS000501-XMP1299
Preliminary Z80S183/Z80L183
139
INSTRUCTION SET
INSTRUCTION SUMMARY
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
Dest
Source
S
Z
HC P/V
N
CF
DJNZ d
10
–
–
–
–
–
–
B← B – 1
if B != 0 {PC ← PC±d}
EI
FB
08
–
*
–
*
–
*
–
*
–
*
–
*
IEF1,2 ← 1
EX AF,AF’
AF ↔ AF’
EX (SP),rr
(SP) ↔ rr
HL
E3
DD/FD E3
D9
–
–
–
–
–
–
IX/Y
EXX
–
–
–
–
–
–
BC ↔ BC’
DE ↔ DE’
HL ↔ HL’
HALT
IM n
76
ED 40–58
DB
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
IN A,(n)
A ← (n)
IN r,(C)
r ← (BC)
ED 40–78
ED 00–38
*
*
*
*
0
0
–
P
P
–
0
0
–
–
–
–
IN0 r,(n)
r ← (0,n)
INC ee
ee ← ee + 1
ss
IX/Y
r
03–33
DD/FD 23
04–3C
–
–
INC m
m ← m + 1
*
*
*
*
V
X
0
1
–
–
(HL)
IX/Y
34
DD/FD 34
ED AA
IND
X
X
(HL) ← (C)
B ← B – 1
HL ← HL – 1
INDR
do {(HL) ← (C)
B ← B – 1
HL ← HL – 1
} while B != 0
ED BA
ED A2
X
X
1
*
X
X
X
X
1
1
–
–
INI
(HL) ← (C)
B ← B – 1
HL ← HL + 1
140
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INSTRUCTION SUMMARY
INSTRUCTION SET
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
Dest
Source
S
Z
HC P/V
N
CF
INIR
ED B2
X
1
X
X
1
–
do {(HL) ← (C)
B ← B – 1
HL ← HL + 1
} while B != 0
JP (rr)
PC ← rr
(HL)
(IX/Y)
E9
–
–
–
–
–
–
DD/FD E9
C2–FA
JP cc,mn
if cc {PC ← mn}
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
JP mn
PC ← mn
C3
10–38
18
JR cc’,d
if cc’ {PC ← PC ± d}
JR d
PC ← PC ± d
LD (aa),A
(aa) ← A
(BC)
(DE)
(HL)
(mn)
02
12
77
32
(IX/Y±d)
DD/FD 77
22
LD (mn),ee
(mn) ← ee
HL
ss
–
–
–
–
–
–
–
–
–
–
–
–
ED 43–73
DD/FD 22
0A
IX/Y
LD A,(aa)
(BC)
(DE)
(HL)
A ← (aa)
1A
7E
(mn)
(IX/Y±d)
3A
DD/FD 7E
ED 57
LD A,I
A ← I
*
*
*
*
0
0
–
IEF2
IEF2
–
0
0
–
–
–
–
LD A,R
A ← R
ED 5F
LD ee,mn
ee ← mn
ss
IX/Y
HL
01–31
DD/FD 21
2A
–
–
LD ee,(mn)
–
–
–
–
–
–
ee ← (mn)
ss
ED 4B–7B
DD/FD 2A
IX/Y
PS000501-XMP1299
Preliminary Z80S183/Z80L183
141
INSTRUCTION SET
INSTRUCTION SUMMARY
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
Dest
Source
S
Z
HC P/V
N
CF
LD I,A
ED 47
–
–
–
–
–
–
I ← A
LD m,n
m ← n
r
06–3E
36
–
–
–
–
–
–
–
–
–
–
(HL)
(IX/Y±d)
r’
DD/FD 36
40–7F
LD m,r
–
–
m ← r
(HL)
70–77
(IX/Y±d)
DD/FD 70–77
ED 4F
LD R,A
R ← A
–
–
–
–
–
–
–
–
–
–
–
–
LD r,s
r ← s
r’
n
40–7F
06–3E
(HL)
(IX/Y±d)
HL
46–7E
DD/FD 46–7E
F9
LD SP,rr
SP ← rr
–
–
–
–
–
0
–
–
0
–
–
IX/Y
DD/FD F9
ED A8
LDD
NZ
(DE) ← (HL)
DE ← DE – 1
HL ← HL – 1
BC ← BC – 1
LDDR
ED B8
–
–
0
0
0
–
do {(DE) ← (HL)
DE ← DE – 1
HL ← HL – 1
BC ← BC – 1
} while BC != 0
LDI
ED A0
ED B0
–
–
–
–
0
0
NZ
0
0
0
–
–
(DE) ← (HL)
DE ← DE + 1
HL ← HL + 1
BC ← BC – 1
LDIR
do {(DE) ← (HL)
DE ← DE + 1
HL ← HL + 1
BC ← BC – 1
} while BC != 0
MLT ss
ED 4C–7C
–
–
–
–
–
–
ss ← ssL * ssH
142
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INSTRUCTION SUMMARY
INSTRUCTION SET
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
Dest
Source
S
Z
HC P/V
N
CF
NEG
ED 44
*
*
*
V
1
*
A ← 0 – A
NOP
00
B0–B7
F6
–
*
–
*
–
0
–
–
0
–
0
OR A,s
A ← A OR s
r
n
P
(HL)
(IX/Y±d)
B6
DD/FD B6
ED 8B
OTDM
*
*
*
P
1
*
*
*
(0,C) ← (HL)
B ← B – 1
C ← C – 1
HL ← HL – 1
OTDMR
ED 8B
0
1
0
0
do {(0,C) ← (HL)
B ← B – 1
C ← C – 1
HL ← HL – 1
} while B != 0
OTDR
do {(C) ← (HL)
B ← B – 1
HL ← HL – 1
} while B != 0
ED BB
ED 83
ED 93
X
*
1
*
X
*
X
P
1
1
*
–
*
OTIM
(0,C) ← (HL)
B ← B – 1
C ← C + 1
HL ← HL + 1
OTIMR
0
1
0
*
0
do {(0,C) ← (HL)
B ← B – 1
C ← C + 1
HL ← HL + 1
} while B != 0
OTIR
ED B3
X
1
X
X
1
–
do {(C) ← (HL)
B ← B – 1
HL ← HL + 1
} while B != 0
OUT (C),r
(BC) ← r
ED 41–79
D3
–
–
–
–
–
–
–
–
–
–
–
–
OUT (n),A
(n) ← A
PS000501-XMP1299
Preliminary Z80S183/Z80L183
143
INSTRUCTION SET
INSTRUCTION SUMMARY
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
Dest
Source
S
Z
HC P/V
N
CF
OUT0 (n),r
(0,n) ← r
ED 01–79
ED AB
–
–
–
–
–
–
OUTD
X
X
*
*
X
X
1
1
–
–
(C) ← (HL)
B ← B – 1
HL ← HL – 1
OUTI
ED AB
X
X
(C) ← (HL)
B ← B – 1
HL ← HL + 1
POP pp
qq
C1–F1
(no change unless operand is AF)
pp ← (SP)
SP ← SP + 2
IX/Y
DD/FD E1
PUSH pp
SP ← SP–2
(SP) ← pp
qq
C5–F5
–
–
–
–
–
–
–
–
–
–
–
–
IX/Y
DD/FD E5
RES b,m
m ← m and not (2^b)
r
CB 80–BF
CB 86–BE
(HL)
(IX/Y±d)
DD/FD CB d 86–BE
C9
RET
PC ← (SP)
SP ← SP + 2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RET cc
if cc {PC ← (SP)
SP ← SP + 2}
C0–F8
ED 4D
RETI
PC ← (SP)
SP ← SP + 2
+ recognition by Z80
peripherals
RETN
ED 45
–
–
–
–
–
–
PC ← (SP)
SP ← SP + 2
IEF1 ← IEF2
RL m
r
CB 10–17
CB 16
*
*
0
0
P
–
0
0
*
*
(HL)
7
0
C
(CF,m) ← rotL(CF,m)
(IX/Y±d)
DD/FD CB d 16
17
RLA
–
–
7
0
C
(CF,A) ← rotL(CF,A)
144
Preliminary Z80S183/Z80L183
PS000501-XMP1299
INSTRUCTION SUMMARY
INSTRUCTION SET
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
RLC m
Dest
Source
S
Z
HC P/V
N
CF
r
CB 00–07
CB 06
*
*
0
0
0
P
0
*
(HL)
7
0
C
(CF,m) ← rotL(m)
(IX/Y±d)
DD/FD CB d 06
07
RLCA
–
*
–
*
–
0
0
*
7
0
C
(CF,A) ← rotL(A)
RLD
ED 6F
P
–
tmp ← A[3:0]
A[3:0] ← (HL)[7:4]
(HL)[7:4] ← (HL)[3:0]
(HL)[3:0] ← tmp
RR m
r
(HL)
(IX/Y±d)
r
CB 18–1F
CB 1E
*
*
0
P
0
*
7
0
C
(CF,m) ← rotR(CF,m)
DD/FD CB d 1E
1F
RRA
–
*
–
*
0
0
–
0
0
*
*
7
0
C
(CF,A) ← rotR(CF,A)
RRC m
r
CB 08–0F
CB 0E
P
7
0
(HL)
C
(CF,m) ← rotR(m)
(IX/Y±d)
DD/FD CB d 0E
0F
RRCA
–*
*
–
*
0
0
–
0
0
*
7
0
C
(CF,A) ← rotR(A)
RRD
ED 67
C7–FF
P
–
tmp ← (HL)[3:0]
(HL)[3:0] ← (HL)[7:4]
(HL)[7:4] ← A[3:0]
A[3:0] ← tmp
RST p
*
*
*
*
*
*
0
*
P
V
V
0
1
1
–
*
SP ← SP – 2
(SP) ← PC
PC ← 0,p
note p=0,8,10,18,...38H
SBC A,s
r
98–9F
DE
A ← A – s – CF
n
(HL)
(IX/Y±d)
r
9E
DD/FD 9E
ED 42–72
SBC HL,ss
*
*
HL ← HL – ss – CF
PS000501-XMP1299
Preliminary Z80S183/Z80L183
145
INSTRUCTION SET
INSTRUCTION SUMMARY
TABLE 148. INSTRUCTION SUMMARY (CONTINUED)
Address Mode
Op Code(s) (Hex)
Flags Affected
Instruction and Operation
Dest
Source
S
Z
HC P/V
N
CF
SCF
37
–
–
0
–
0
1
CF ← 1
SET b,m
m ← m or (2^b)
r
CB C0–FF
CB C6–FE
DD/FD CB d C6–FE
CB 20–27
CB 26
–
*
–
*
–
–
–
0
–
*
(HL)
(IX/Y±d)
r
SLA m
0
P
(HL)
0
7
0
C
(CF,m) ← m + m
SLP
(IX/Y±d)
DD/FD CB d 26
ED 76
–
*
–
*
–
0
–
–
0
–
*
SRA m
r
CB 28–2F
CB 2E
P
7
0
(HL)
C
(m,CF) ← arith_shR(m)
(IX/Y±d)
r
DD/FD CB d 2E
CB 38–3F
CB 3E
SRL m
0
*
*
*
0
*
P
V
0
1
*
*
0
7
0
C
(HL)
(m,CF) ← logic_shR(m)
(IX/Y±d)
DD/FD CB d 3E
90–97
SUB A,s
r
A ← A – s
n
D6
(HL)
96
(IX/Y±d)
DD/FD 96
ED 04–3C
ED 64
TST A,s
r
n
*
*
1
P
0
0
A AND s
(HL)
ED 34
TSTIO n
(0,C) AND n
ED 34
*
*
*
*
1
0
P
P
0
0
0
0
XOR A,s
A ← A XOR s
r
n
A8–AF
EE
(HL)
(IX/Y±d)
AE
DD/FD AE
146
Preliminary Z80S183/Z80L183
PS000501-XMP1299
OP CODE MAP
INSTRUCTION SET
OP CODE MAP
TABLE 149. OP CODE MAP (FIRST OP CODE)
LOWER NIBBLE (HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
LD
LD
INC
INC
B
DEC
B
LD
B,n
RLCA
EX
ADD
LD
DEC
INC
C
DEC
C
LD RRCA
C,n
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
BC,nn (BC),A BC
LD LD INC
DE,nn (DE),A DE
LD LD INC
AF,AF’ HL,BC A,(BC) BC
DJNZ
d
INC
D
DEC
D
LD
D,n
RLA
DAA
SCF
LD
JR
d
ADD
HL,DE A,(DE) DE
ADD LD DEC
LD
DEC
INC
E
DEC
E
LD
E,n
RRA
CPL
CCF
LD
JR
INC
H
DEC
H
LD
H,n
JR
INC
L
DEC
L
LD
L,n
NZ,d HL,nn (nn),HL HL
Z,d HL,HL (HL),nn HL
JR
LD
LD
INC
SP
INC
(HL)
DEC
(HL) (HL),n
LD
JR
ADD
LD
DEC
SP
INC
A
DEC
A
LD
A,n
NC,d SP,nn (nn),A
C,d HL,SP A,(nn)
LD
B,B
LD
B,C
LD
B,D
LD
B,E
LD
B,H
LD LD
LD
C,B
LD
C,C
LD
C,D
LD
C,E
LD
C,H
LD
LD
B,L B,(HL) C,A
LD LD LD
D,L D,(HL) D,A
LD LD LD
H,L H,(HL) H,A
LD HALT LD
C,L C,(HL) C,A
LD LD LD
E,L E,(HL) E,A
LD LD LD
L,L L,(HL) L,A
LD LD LD
A,L A,(HL) A,A
LD
D,B
LD
D,C
LD
D,D
LD
D,E
LD
D,H
LD
E,B
LD
E,C
LD
E,D
LD
E,E
LD
E,H
LD
H,B
LD
H,C
LD
H,D
LD
H,E
LD
H,H
LD
L,B
LD
L,C
LD
L,D
LD
L,E
LD
L,H
LD
LD
LD
LD
LD
LD
LD
A,C
LD
A,D
LD
A,E
LD
A,H
(HL),B (HL),C (HL),D (HL),E (HL),H (HL),L
(HL),A A,B
ADD ADD ADD ADD ADD ADD ADD ADC ADC ADC ADC ADC ADC ADC ADC ADC
A,B A,C A,D A,E A,H A,L A,(HL) A,A A,B A,C A,D A,E A,H A,L A,(HL) A,A
SUB SUB SUB SUB SUB SUB SUB SUB SBC SBC SBC SBC SBC SBC SBC SBC
A,B A,C A,D A,E A,H A,L A,(HL) A,A A,B A,C A,D A,E A,H A,L A,(HL) A,A
AND AND AND AND AND AND AND AND XOR XOR XOR XOR XOR XOR XOR XOR
A,B
A,C
A,D
A,E
A,H
A,L A,(HL) A,A
OR OR OR
A,L A,(HL) A,A
A,B
A,C
A,D
A,E
A,H
A,L A,(HL) A,A
CP CP CP
A,L A,(HL) A,A
OR
A,B
OR
A,C
OR
A,D
OR
A,E
OR
A,H
CP
A,B
CP
A,C
CP
A,D
CP
A,E
CP
A,H
RET POP
NZ
RET POP
NZ DE NC,nn (n),A NC,nn DE
RET POP JP EX
JP
JP
nn
CALL PUSH ADD RST
NZ,nn BC
RET
Z
RET
EXX
JP
JP
Z,nn
(Table CALL CALL ADC RST
150)
BC NZ,nn
A,n
0
Z,nn
CALL (Table SBC
A,n
nn
A,n
8
JP
OUT CALL PUSH SUB
A,n
RST
10H
RET
C
JP
IN
RST
18H
C,nn A,(n) C,nn 151)
CALL PUSH AND RST
RET
PE
JP EX
CALL (Table XOR RST
PO
HL PO,nn (SP),H PO,nn HL
L
A,n
20
(HL) PE,nn DE,HL PE,nn 152)
A,n
28H
RET POP
JP
P,nn
DI
CALL PUSH OR
RST
30H
RET
M
LD
JP
EI
CALL (Table CP
RST
38H
F
P
AF
P,nn
AF
A,n
SP,HL M,nn
M,nn 153)
A,n
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Notes:
lower Op Code Nibble
4
n = 8-bit data
nn = 16-bit addr or data
d = signed 8-bit
Upper
Op Code
Nibble
displacement
Mnemonic
AND
A,H
A
First Operand
Second Operand
PS000501-XMP1299
Preliminary Z80S183/Z80L183
147
INSTRUCTION SET
OP CODE MAP
TABLE 150. OP CODE MAP (SECOND OP CODE AFTER 0CBH)
LOWER NIBBLE (HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC RLC
RLC
D
RLC
E
RLC
H
RLC
L
RLC
(HL) RRCA
RLC RRC RRC RRC RRC RRC RRC RRC RRC
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
B
C
B
C
D
E
H
L
(HL)
A
RL
B
RL
C
RL
D
RL
E
RL
H
RL
L
RL
(HL)
RL
A
RR
B
RR
C
RR
D
RR
E
RR
H
RR
L
RR
(HL)
RR
A
SLA
B
SLA
C
SLA
D
SLA
E
SLA
H
SLA
L
SLA
(HL)
SLA
A
SRA SRA SRA SRA SRA SRA SRA SRA
B
C
D
E
H
L
(HL)
A
SRL
B
SRL
C
SRL
D
SRL
E
SRL
H
SRL
L
SRL
(HL)
SRL
A
BIT
0,B
BIT
0,C
BIT
0,D
BIT
0,E
BIT
0,H
BIT
BIT
BIT
BIT
1,B
BIT
1,C
BIT
1,D
BIT
1,E
BIT
1,H
BIT
BIT
BIT
0,L 0,(HL) 0,A
BIT BIT BIT
2,L 2,(HL) 2,A
BIT BIT BIT
4,L 4,(HL) 4,A
BIT BIT BIT
6,L 6,(HL) 6,A
1,L 1,(HL) 1,A
BIT BIT BIT
3,L 3,(HL) 3,A
BIT BIT BIT
5,L 5,(HL) 5,A
BIT BIT BIT
7,L 7,(HL) 7,A
BIT
2,B
BIT
2,C
BIT
2,D
BIT
2,E
BIT
2,H
BIT
3,B
BIT
3,C
BIT
3,D
BIT
3,E
BIT
3,H
BIT
4,B
BIT
4,C
BIT
4,D
BIT
4,E
BIT
4,H
BIT
5,B
BIT
5,C
BIT
5,D
BIT
5,E
BIT
5,H
BIT
6,B
BIT
6,C
BIT
6,D
BIT
6,E
BIT
6,H
BIT
7,B
BIT
7,C
BIT
7,D
BIT
7,E
BIT
7,H
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
0,B 0,C 0,D 0,E 0,H 0,L 0,(HL) 0,A 1,B 1,C 1,D 1,E 1,H 1,L 1,(HL) 1,A
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
2,B 2,C 2,D 2,E 2,H 2,L 2,(HL) 2,A 3,B 3,C 3,D 3,E 3,H 3,L 3,(HL) 3,A
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
4,B 4,C 4,D 4,E 4,H 4,L 4,(HL) 4,A 5,B 5,C 5,D 5,E 5,H 5,L 5,(HL) 5,A
RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES RES
6,B
6,C
6,D
6,E
6,H
6,L 6,(HL) 6,A
SET SET SET
0,L 0,(HL) 0,A
SET SET SET
2,L 2,(HL) 2,A
SET SET SET
4,L 4,(HL) 4,A
SET SET SET
6,L 6,(HL) 6,A
7,B
7,C
7,D
7,E
7,H
7,L 7,(HL) 7,A
SET SET SET
1,L 1,(HL) 1,A
SET SET SET
3,L 3,(HL) 3,A
SET SET SET
5,L 5,(HL) 5,A
SET SET SET
7,L 7,(HL) 7,A
SET
0,B
SET
0,C
SET
0,D
SET
0,E
SET
0,H
SET
1,B
SET
1,C
SET
1,D
SET
1,E
SET
1,H
SET
2,B
SET
2,C
SET
2,D
SET
2,E
SET
2,H
SET
3,B
SET
3,C
SET
3,D
SET
3,E
SET
3,H
SET
4,B
SET
4,C
SET
4,D
SET
4,E
SET
4,H
SET
5,B
SET
5,C
SET
5,D
SET
5,E
SET
5,H
SET
6,B
SET
6,C
SET
6,D
SET
6,E
SET
6,H
SET
7,B
SET
7,C
SET
7,D
SET
7,E
SET
7,H
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
lower Nibble of Second Op Code
Upper
4
Nibble
of Second
Op Code
Mnemonic
RES
4,H
A
First Operand
Second Operand
148
Preliminary Z80S183/Z80L183
PS000501-XMP1299
OP CODE MAP
INSTRUCTION SET
TABLE 151. OP CODE MAP (SECOND OP CODE AFTER 0DDH)
LOWER NIBBLE (HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ADD
IX,BC
0
1
2
ADD
IX,DE
LD
LD
INC
IX
ADD
IX,IX
LD
IX,
DEC
IX
IX,nn (nn),IX
(nn)
INC
DEC LD (IX
ADD
IX,SP
3
4
5
6
7
(IX±d) (IX±d) ±d),n
LD B,
(IX±d)
LD C,
(IX±d)
LD D,
(IX±d)
LD E,
(IX±d)
LD H,
(IX±d)
LD L,
(IX±d)
LD (IX
LD
LD (IX LD (IX LD (IX LD (IX
±d),B (IX±d), ±d),D ±d),E ±d),H ±d),L
C
LD (IX+
±d),A
LD A,
(IX±d)
ADD A,
(IX±d)
ADC A,
(IX±d)
8
9
SUB A,
(IX±d)
SBC A,
(IX±d)
AND A,
(IX±d)
XOR A,
(IX±d)
A
B
C
D
E
OR A,
(IX±d)
CP A,
(IX±d)
(Table
154)
POP
IX
EX
(SP),
IX
PUSH
IX
JP
(IX)
LD
SP,IX
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Notes:
n = 8-bit data
nn = 16-bit addr or data
d = signed 8-bit
lower Nibble of Second Op Code
9
Upper
displacement
Nibble
of Second
Op Code
Mnemonic
LD
F
SP,IX
First Operand
Second Operand
PS000501-XMP1299
Preliminary Z80S183/Z80L183
149
INSTRUCTION SET
OP CODE MAP
TABLE 152. OP CODE MAP (SECOND OP CODE AFTER 0EDH)
LOWER NIBBLE (HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IN0 OUT0
B,(n) (n),B
TST
A,B
IN0 OUT0
C,(n) (n),C
TST
A,C
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IN0 OUT0
D,(n) (n),D
TST
A,D
IN0 OUT0
E,(n) (n),E
TST
A,E
IN0 OUT0
H,(n) (n),H
TST
A,H
IN0 OUT0
L,(n) (n),L
TST
A,L
IN0
F,(n)
TST
A,(HL)
IN0 OUT0
A,(n) (n),A
TST
A,A
IN
OUT SBC
LD
NEG RETN IM 0
LD
I,A
IN
OUT ADC
LD
MLT RETI
LD
R,A
B,(C) (C),B HL,BC (nn),BC
IN OUT SBC LD
D,(C) (C),D HL,DE (nn),DE
IN OUT SBC LD
H,(C) (C),H HL,HL (nn),HL A,n
C,(C) (C),C HL,BC BC,(nn) BC
IN OUT ADC LD MLT
E,(C) (C),E HL,DE DE,(nn) DE
IN OUT ADC LD MLT
L,(C) (C),L HL,HL HL,(nn) HL
IN OUT ADC LD MLT
IM 1
LD
A,I
IM 2
LD
A,R
TST
RRD
RLD
IN
F,(C)
SBC
LD TSTIO
SLP
HL,SP (nn),SP
n
A,(C) (C),A HL,SP SP,(nn) SP
OTIM
OTDM
OTIMR
OTDM
R
LDI
CPI
INI
OUTI
LDD CPD
IND OUTD
LDIR CPIR INIR OTIR
LDDR CPDR INDR OTDR
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Notes:
n = 8-bit data
nn = 16-bit addr or data
d = signed 8-bit
lower Nibble of Second Op Code
2
Upper
displacement
Nibble
of Second
Op Code
Mnemonic
SBC
4
HL,BC
First Operand
Second Operand
150
Preliminary Z80S183/Z80L183
PS000501-XMP1299
OP CODE MAP
INSTRUCTION SET
TABLE 153. OP CODE MAP (SECOND OP CODE AFTER 0FDH)
LOWER NIBBLE (HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ADD
IY,BC
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ADD
IY,DE
LD
LD
INC
IY
ADD
IY,IY IY,(nn)
LD
DEC
IY
IY,nn (nn),IY
INC
DEC LD (IY
ADD
IY,SP
(IY±d) (IY±d) ±d),n
LD B,
(IY±d)
LD C,
(IY±d)
LD D,
(IY±d)
LD E,
(IY±d)
LD H,
(IY±d)
LD L,
(IY±d)
LD (IY LD (IY LD (IY LD (IY LD (IY LD (IY
±d),B ±d),C ±d),D ±d),E ±d),H ±d),L
LD (IY
±d),A
LD A,
(IY±d)
ADD A,
(IY±d)
ADC A,
(IY±d)
SUB A,
(IY±d)
SBC A,
(IY±d)
AND A,
(IY±d)
XOR A,
(IY±d)
OR A,
(IY±d)
CP A,
(IY±d)
(Table
155)
POP
IY
EX
(SP),IY
PUSH
IY
JP
(IY)
LD
SP,IY
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Notes:
n = 8-bit data
nn = 16-bit addr or data
d = signed 8-bit
lower Nibble of Second Op Code
9
Upper
displacement
Nibble
of Second
Op Code
Mnemonic
LD
F
SP,IY
First Operand
Second Operand
PS000501-XMP1299
Preliminary Z80S183/Z80L183
151
INSTRUCTION SET
OP CODE MAP
TABLE 154. OP CODE MAP (FOURTH BYTE, AFTER 0DDH, 0CBH, AND d)
LOWER NIBBLE (HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC
(IX±d)
RRC
(IX±d)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RL
(IX±d)
RR
(IX±d)
SLA
(IX±d)
SRA
(IX±d)
SRL
(IX±d)
BIT 0,
(IX±d)
BIT 1,
(IX±d)
BIT 2,
(IX±d)
BIT 3,
(IX±d)
BIT 4,
(IX±d)
BIT 5,
(IX±d)
BIT 6,
(IX±d)
BIT 7,
(IX±d)
RES 0,
(IX±d)
RES 1,
(IX±d)
RES 2,
(IX±d)
RES 3,
(IX±d)
RES 4,
(IX±d)
RES 5,
(IX±d)
RES 6,
(IX±d)
RES 7,
(IX±d)
SET 0,
(IX±d)
SET 1,
(IX±d)
SET 2,
(IX±d)
SET 3,
(IX±d)
SET 4,
(IX±d)
SET 5,
(IX±d)
SET 6,
(IX±d)
SET 7,
(IX±d)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Note:
d = signed 8-bit
lower Nibble of Fourth Byte
displacement
6
Upper
Nibble
of Fourth
Byte
BIT
0,(IX+d)
Mnemonic
Second Operand
4
First Operand
152
Preliminary Z80S183/Z80L183
PS000501-XMP1299
OP CODE MAP
INSTRUCTION SET
TABLE 155. OP CODE MAP (FOURTH BYTE, AFTER 0FDH, 0CBH, AND d)
LOWER NIBBLE (HEX)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC
(IY±d)
RRC
(IY±d)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RL
(IY±d)
RR
(IY±d)
SLA
(IY±d)
SRA
(IY±d)
SRL
(IY±d)
BIT 0,
(IY±d)
BIT 1,
(IY±d)
BIT 2,
(IY±d)
BIT 3,
(IY±d)
BIT 4,
(IY±d)
BIT 5,
(IY±d)
BIT 6,
(IY±d)
BIT 7,
(IY±d)
RES 0,
(IY±d)
RES 1,
(IY±d)
RES 2,
(IY±d)
RES 3,
(IY±d)
RES 4,
(IY±d)
RES 5,
(IY±d)
RES 6,
(IY±d)
RES 7,
(IY±d)
SET 0,
(IY±d)
SET 1,
(IY±d)
SET 2,
(IY±d)
SET 3,
(IY±d)
SET 4,
(IY±d)
SET 5,
(IY±d)
SET 6,
(IY±d)
SET 7,
(IY±d)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Note:
d = signed 8-bit
lower Nibble of Fourth Byte
displacement
Upper
Nibble
of Fourth
Byte
6
BIT
0,(IY+d)
Mnemonic
Second Operand
4
First Operand
PS000501-XMP1299
Preliminary Z80S183/Z80L183
153
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This rating is a stress rating only. Operation of
the device at any condition outside those indicated in the operational sections of
these specifications is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
TABLE 156. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Units
Notes
Ambient Temperature under Bias
Storage Temperature
–40
–65
+105
+150
+12
C
C
1
Voltage on any Pin with Respect to VSS
Voltage on VDD Pin with Respect to VSS
Total Power Dissipation
–0.7
–0.3
V
2
+7
V
TBD
TBD
TBD
+TBD
TBD
mW
mA
mA
µA
mA
Maximum Current out of VSS
Maximum Current into VDD
Maximum Current on Input and/or Inactive Output Pin
Maximum Output Current
–TBD
–TBD
Notes:
1. Operating temperature is specified in DC Characteristics
2. This applies to all pins except where noted otherwise. Maximum current through a pin is specified below.
STANDARD TEST CONDITIONS
Unless otherwise noted, the DC and AC characteristics in this document are
measured under standard test conditions that include the load circuit illustrated in
Figure 16. This circuit closely mimics the loading presented by active devices
such as memories and peripheral devices.
All voltages are referenced to the V pins (ground, 0V). Positive current flows
SS
into the referenced pin.
All AC parameters assume a load capacitance of 100 pF. See “Characteristic
Curves” on page 165 for the effect of lesser or greater total capacitance on the
timing. AC timing measurements are referenced to the High and low voltage
thresholds given in the DC specifications, as indicated in Figures 17 through 25.
154
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DC CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
IOL
VOL max + VOH min
2
From Pin
CL
100 pF
IOH
FIGURE 16. TEST CONDITION LOAD CIRCUIT
DC CHARACTERISTICS
Table 157 describes the DC Characteristics of the Z80S183/Z80L183, for temper-
ature ranges T = 0°C to +70°C.
A
TABLE 157. DC CHARACTERISTICS, TA = 0°C to +70°C
Symbol Parameter
Condition
Min
Typ
Max Units
VIH1
Input High Voltage
V
DD–0.6
VDD+0.3
V
(RESET, EXTAL, NMI, INT0, INT1,
INT2, OPMODE0, OPMODE1,
PWRSWITCH, ZDA, ZCL)
VIH2
Input High Voltage
2.0
VDD+0.3
V
(Except RESET, EXTAL, NMI, CKS,
INT0, INT1, INT2, OPMODE0,
OPMODE1, PWRSWITCH, ZDA,
ZCL)
VIH3
VIL1
Input High Voltage (CKS)
2.4
VDD+0.3
0.4
V
V
Input Low Voltage
–0.3
(RESET, EXTAL, NMI, INT0, INT1,
INT2, OPMODE0, OPMODE1,
PWRSWITCH, ZDA, ZCL)
VIL2
Input Low Voltage
–0.3
0.6
V
V
(except RESET, EXTAL, NMI, INT0,
INT1, INT2, OPMODE0, OPMODE1,
PWRSWITCH, ZDA, ZCL)
VOH
Output High Voltage
IOH = –200 uA
OH = –20 uA
2.4
I
VDD–1.2
VOL
IIL
Output Low Voltage
IOL = 2.2 mA
VIN = 0.5 to
0.45
1.0
V
Input Leakage (All inputs except
uA
XTAL, EXTAL, LFXTAL, LFEXTAL)
V
DD–0.5
PS000501-XMP1299
Preliminary Z80S183/Z80L183
155
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
TABLE 157. DC CHARACTERISTICS, TA = 0°C to +70°C (CONTINUED)
Symbol Parameter
Condition
Min
Typ
Max Units
IOL
Output Leakage
VIN = 0.5 to
1.0
uA
VDD–0.5
VICR
IDD
Comparator Input
Common Mode Voltage Range
Supply Current (Normal Operation)
20 MHz (note 1)
33 MHz (note 1)
20 MHz (note 1)
33 MHz (note 1)
55
TBD
TBD
TBD
TBD
TBD
mA
mA
uA
TBD
TBD
TBD
TBD
IDD1
Standby Current
(System Stop Mode)
IDD2
Standby Current (Standby Mode)
Note:
1. VIH > VDD–1.0 V, VIL < 0.8 V, VDD = 5.0 V, no outputs loaded.
TABLE 158. AC CHARACTERISTICS, TA = 0°C TO +70°C, CL = 100 PF
No Symbol Parameter
20 MHz
ꢅꢅꢀ/*\
Min
Max
Min
Max Units
1
2
3
4
5
6
7
8
9
fOSC
Crystal Frequency
20
DC
15
15
10
10
33.33 MHz
tEXCYC External Clock Cycle Time (EXTAL)
50
30
DC
10
10
5
ns
ns
ns
ns
ns
tEXH
tEXL
tEXr
tEXf
tCHW
tCLW
t
External Clock High Time (EXTAL)
External Clock Low Time (EXTAL)
External Clock Rise Time (EXTAL)
External Clock Fall Time (EXTAL)
PHI High Time
5
20
20
50
10
5
12
12
30
8
PHI Low Time
PHI Cycle Time
DC
50
DC
50
ns
ns
10 tRES
11 tREH
12 tRr
RESET Setup to PHI Fall2
RESET Hold from PHI Fall2
RESET Fall Time1
5
ns
ms
tCYC
13 tRL
RESET Low Time
6
6
14 tRf
15 tIr
16 t
RESET Rise Time1
50
50
50
15
50
50
50
5
ms
ns
ns
ns
Input Fall Time (except EXTAL, RESET)1
Input Rise Time (except EXTAL, RESET)1
PHI Rise to Address Valid
17 tAV
Memory Read
18 tM1L
PHI Rise to M1 Fall
15
15
ns
19 tASMR Address Valid to (ROMRD or RAMRD) Fall
tCHW–5
tCHW–10
ns
20 tMRL
PHI Fall to (ROMRD or RAMRD) Fall
15
15
ns
156
Preliminary Z80S183/Z80L183
PS000501-XMP1299
DC CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
TABLE 158. AC CHARACTERISTICS, TA = 0°C TO +70°C, CL = 100 PF (CONTINUED)
20 MHz
ꢅꢅꢀ/*\
No Symbol Parameter
Min
Max
Min
Max Units
21 tWTS
22 tWTH
23 tMRPL
WAIT Setup to PHI Fall2
WAIT Hold from PHI Fall2
15
5
15
5
ns
ns
ns
(ROMRD or RAMRD) Width Low
2t
–15
2t
–10
24 tRDS
25 tM1H
26 tRWH
27 tRDH
Read Data Setup to PHI Rise1
15
15
ns
PHI Rise to M1 Rise
15
15
15
15
ns
ns
ns
ns
PHI Fall to (ROMRD or RAMRD) Rise
Read Data Hold from (ROMRD or RAMRD) Rise1
0
0
28 tMRHAC (ROMRD or RAMRD) Rise to Address Change
tCLW–10
tCLW–10
Memory Write
29 tASMW Address Valid to (ROMWR or RAMWR) Fall
t
–10
t
–10
30 tWDV
31 tMWDS Write Data Valid to (ROMWR or RAMWR) Fall
32 tMRL PHI Rise to (ROMWR or RAMWR) Fall
33 tMWPL (ROMWR or RAMWR) Width Low
PHI Fall to Write Data Valid
20
15
20
15
ns
ns
tCLW–15
tCLW–15
ns
ns
t
t
tCHW–10
tCHW–10
34 tWRH
35 tWDH
PHI Fall to (ROMWR or RAMWR) Rise
15
10
15
10
ns
ns
(ROMWR or RAMWR) Rise to Write Data Change tCLW–20
PHI Rise to Write Data Float
tCLW–12
tCLW–12
36 tWDZ
ns
ns
37 tMWHAC (ROMWR or RAMWR) Rise to Address Change
tCLW–20
I/O Read
38 tASIR
39
Address Valid to IORD Fall (IOC=1)
Address Valid to IORD Fall (IOC=0)
tCHW–10
tCYC–10
tCHW–10
tCYC–10
40 tIRL
41
PHI Fall to IORD Fall (IOC=1)
PHI Rise to IORD Fall (IOC=0)
IORD Width Low (IOC=1)
15
15
15
15
ns
ns
42 tIRPL
3tCYC–15
2tCYC+
3tCYC–10
2tCYC+
43
IORD Width Low (IOC=0)
t
–15
t
–10
44 tRWH
45 tRDH
PHI Fall to IORD Rise
Read Data Hold from IORD Rise1
15
15
ns
ns
ns
0
0
46 tIRHAC IORD Rise to Address Change
tCLW–20
tCLW–12
PS000501-XMP1299
Preliminary Z80S183/Z80L183
157
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
TABLE 158. AC CHARACTERISTICS, TA = 0°C TO +70°C, CL = 100 PF (CONTINUED)
20 MHz
ꢅꢅꢀ/*\
No Symbol Parameter
Min
Max
Min
Max Units
I/O Write
47 tASOW Address Valid to IOWR Fall
48 tOWDS Write Data Valid to IOWR Fall
tCYC–10
tCYC–10
tCLW–10
tCLW–10
49 tWRL
PHI Rise to IOWR Fall
15
15
15
15
ns
ns
50 tOWPL IOWR Width Low
2tCYC+
2tCYC+
t
–15
t
–10
51 tWRH
52 tWDH
PHI Fall to IOWR Rise
ns
ns
IOWR Rise to Write Data Change
tCLW–20
tCLW–20
tCLW–12
tCLW–12
53 tOWHAC IOWR Rise to Address Change
ns
Bus Exchange Timing
54 tBRS
55 tBRH
56 t
BUSREQ Setup to PHI Fall2
BUSREQ Hold after PHI Fall2
BUSREQ Low to BUSACK Low
10
10
10
10
ns
ns
t
t
+t
+t
57 tBAL
58 tBZ
59 t
PHI Rise to BUSACK Fall
PHI Rise to Bus Float
15
10
2
15
10
2
ns
ns
BUSREQ High to BUSACK High
1
1
t
60 tBAH
61 t
PHI Fall to BUSACK Rise
PHI Rise to Bus Valid
15
30
15
20
ns
ns
Interrupt Timing
62 tINTS
63 tINTH
64 tINTS
65 tINTH
66 tINTL
67 tNMIL
INT0 Setup to PHI Fall2
INT0 Hold after PHI Fall2
INT1–2 Setup to PHI Fall (level sense)2
INT1–2 Hold after PHI Fall (level sense)2
INT1–2 Pulse Width (edge sense)1
NMI Width low1
15
5
15
5
ns
ns
ns
ns
ns
ns
15
5
15
5
15
35
15
25
DMA Timing
68 tDRQS DREQ0–1 Setup to PHI Rise (level sense)2
69 tDRQH DREQ0–1 Hold from PHI Rise (level sense)2
15
15
ns
ns
5
t
5
t
70 t
71 t
DREQ0–1 Low Width (edge sense)1
DREQ0–1 High Width (edge sense)1
t
t
158
Preliminary Z80S183/Z80L183
PS000501-XMP1299
AC CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
TABLE 158. AC CHARACTERISTICS, TA = 0°C TO +70°C, CL = 100 PF (CONTINUED)
20 MHz
ꢅꢅꢀ/*\
Min Max Units
No Symbol Parameter
Min
Max
CSI/O Timing
72 tSTDI
73 tSRSI
74 tSRHI
Notes:
CKS Low to TXS Valid
10
10
ns
ns
ns
RXS Valid to CKS high1
CKS High to RXS Invalid1
15
5
15
5
1. These timing requirements must be met to assure correct device operation.
2. These Setup and Hold times must be met to guarantee recognition at the clock edge in question. If they are not
met with respect to a clock edge, the Z80S183/Z80L183 may or may not recognize the new state of the signal at
that edge. If it does not, and the signal remains in the same state, the Z80S183/Z80L183 recognizes the new state
1 clock period later.
AC CHARACTERISTICS
Table 158 gives the AC Characteristics of the Z80S183/Z80L183 for the tempera-
ture range of T = 0°C to +70°C and for the parameters described in Figures 17
A
through 25.
CAPACITANCE
The capacitance of each pin on the Z80S183/Z80L183 depends on whether the pin
is an input, output, or both. The total capacitance associated with outputs affects
their AC characteristics (switching time) as described in “Characteristic Curves”
on page 165.
Input
Output
I/O
5 pF
10 pF
15 pF
PS000501-XMP1299
Preliminary Z80S183/Z80L183
159
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
3
4
EXTAL
5
6
2
PHI
8
7
11
10
9
12
13
12
RESET
14
15
Any
Other
Input
FIGURE 17. BASIC TIMING
160
Preliminary Z80S183/Z80L183
PS000501-XMP1299
TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
T1
T2
Tw
T3
PHI
17
18
19
A19-0
28
25
High in other memory reads
M1
Low in Op Code fetches
20
26
ROMRD
or
23
RAMRD
22
22
21
21
9#+6
27
24
D7–0
FIGURE 18. MEMORY READ TIMING (ONE WAIT STATE)
T1 T2
T3
PHI
17
29
37
A19-0
30
36
31
35
34
D7-0
32
33
ROMWR
or
RAMWR
21
22
WAIT
FIGURE 19. MEMORY WRITE TIMING (NO WAIT STATES)
PS000501-XMP1299
Preliminary Z80S183/Z80L183
161
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
T1
38
T2
Tw
T3
PHI
17
39
46
A19-0
41
40
44
42
43
IORD
21
22
24
WAIT
D7-0
45
FIGURE 20. I/O READ TIMING (AUTO WAIT STATE)
T1 T2
Tw
Tw
T3
PHI
17
47
53
A19-0
36
52
30
48
D7-0
51
49
50
IOWR
WAIT
22
22
21
21
FIGURE 21. I/O WRITE TIMING (AUTO+ONE WAIT STATE)
162
Preliminary Z80S183/Z80L183
PS000501-XMP1299
TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
PHI
BUSREQ
BUSACK
54
55
54
56
59
57
58
60
61
A19-0,IORD,IOWR,
RAMRD,RAMWR,
ROMRD,ROMWR
PHI
54
54
55
BUSREQ
BUSACK
59
56
57
58
60
61
A19-0,IORD,IOWR,
RAMRD,RAMWR,
ROMRD,ROMWR
Notes:
1. BUSREQ is a conditional state of the OPMODE0 and OPMODE1.
2. BUSACK is strictly shown to indicate when the MPU address and Data Bus have entered their High
impedance state.
3. BUSACK is not pinned outside of the Z80S183/Z80L183.
FIGURE 22. BUS EXCHANGE TIMING
PS000501-XMP1299
Preliminary Z80S183/Z80L183
163
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
PHI
62
64
63
65
62
64
INT0
66
66
INT1-2
NMI
67
FIGURE 23. INTERRUPT TIMING
PHI
68
69
68
DREQ1-0
(level)
70
71
DREQ1-0
(edge)
FIGURE 24. DMA TIMING
CKS
72
TXS
RXS
74
73
FIGURE 25. CSI/O TIMING
164
Preliminary Z80S183/Z80L183
PS000501-XMP1299
CHARACTERISTIC CURVES
SYSTEM DESIGN CONSIDERATIONS
CHARACTERISTIC CURVES
10
8
6
4
2
0
-2
-4
25
50
75
100
125
150
175
200
225
250
275 pF
FIGURE 26. CAPACITIVE LOAD CL VS. SWITCHING TIME
SYSTEM DESIGN CONSIDERATIONS
ERRATA
The following precautions apply to devices marked Z80S183XXYYYZZ with
date code 9941 or later. The date code is formatted as ‘yyww’. For example,
‘9941’ is the forty-first week of 1999.
Sleep Mode. The current draw in sleep mode is between 6 and 10 mA. Prior to
executing the sleep mode instruction, users should clear the ADC and DAC
enable bits.
ADC. The least-significant bit of the ADC result (ADCC1 Bit 6) is always read
as a 1.
32 Mhz FLL. When a 32.768 KHz crystal is running on LFEXTAL and LFXTAL
pins, and the FLL is activated in the multiply-by-502 mode, the resulting PHI
frequency is approximately 11 Mhz. Similarly, when the FLL is operating in
multiply-by-1004 mode, the resulting PHI frequency is approximately 22 Mhz.
Watch-Dog Timer (WDT). The Watch-Dog timer only works with the time
18
22
period set to 2 or 2 system clocks.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
165
APPLICATION NOTES/DEVELOPMENT TOOLS
ZILOG DEBUG INTERFACE
Watch-Dog Timer. When the Drive Reset function (set with Bit 4 of the Watch-
Dog Timer Master Register) is enabled, and a WDT timeout reset occurs, Bit 2 of
the Watch-Dog Timer Master Register is not set following the WDT reset. When
the Drive Reset function is disabled and a WDT timeout reset occurs, Bit 2 of the
Watch-Dog Timer Master Register functions normally and indicates that a WDT
reset has occurred.
Workarounds: a) Program the WDT not to export an external reset, so that
following a WDT reset the software detects that Bit 2 of the WDT Master Register
is set. Then, software sets up and enables a WDT timeout to occur with the
external reset enabled. b) Alternatively, software exports an external reset through
any available I/O pin.
Power Up. On power-up, the Z80S183/Z80L183 goes into test mode.
Workaround: Use an external pull-up resistor (suggest 47 Kohm) on ROMRD pin 24.
APPLICATION NOTES/DEVELOPMENT TOOLS
ZILOG DEBUG INTERFACE
The Z80S183/Z80L183 includes this serial interface to allow ZiLOG and Third-
party development systems and emulators to control and monitor the processor and
other on-chip resources, during application development and debugging. This 2-wire
interface is intended to be a standard feature of ZiLOG processors, obviating the
need for expensive and cumbersome pods and clip-on emulation equipment.
To use the ZiLOG Developer Studio (ZDS) or equivalent equipment with an
application or target board, include a standard right angle, 0.1 in spaced, 0.025 in
square post, six pin header on the board (Berg P/N 75867-131 or equivalent).
Connect the ZCL and ZDA pins of the Z80S183/Z80L183 to pins 4 and 6 of this
header as illustrated in Figure 27, which is a top view.
Vdd
Z80S183/Z80L183
1
3
5
4
6
ZCL
ZDA
10K
GND
90
91
ZDA
ZCL
FIGURE 27. ZDI CONNECTOR ON TARGET BOARD
166
Preliminary Z80S183/Z80L183
PS000501-XMP1299
ZILOG DEBUG INTERFACE
PACKAGING
PACKAGING
FIGURE 28. 100-PIN VQFP PACKAGE DIAGRAM
ORDERING INFORMATION
Z80S183 (33 MHz)
5VCPFCTFꢀ6GORGTCVWTG
100 Pin VQFP
Z80S183AZ033SCRxxxx
Z80L183 (20 MHz)
5VCPFCTFꢀ6GORGTCVWTG
100 Pin VQFP
Z80L183AZ033SCRxxxx
For fast results, contact your nearest ZiLOG sale office or the ZiLOG Customer
Support Center at 877-945-6427 (web site: www.zilog.com) for assistance in
ordering parts.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
167
ORDERING INFORMATION
PART NUMBER DESCRIPTION
PART NUMBER DESCRIPTION
ZiLOG part numbers consist of a number of components.
'ZCORNGꢄꢀ
Part number Z80S183 AZ 033 SCR4567, a Z80S183, 33 MHz, VQFP, 0 to 70 C,
Plastic Standard Flow, is made up of the codes described in the following table.
Z
ZiLOG prefix
Product Number
Package
80S183
AZ
033
S
Speed
Temperature
Environmental Flow
ROM Code
C
R
Note:
ROM 4567 is a standard part available to all customers.
ROM CODE SUBMISSION
ROM Code Submission Instructions
Outlook Public Folders: All Public Folders: ZiLOG Corporate:
ROM Submission Forms: Z8S183-4.2.
ZiLOG Z8S183 Code Submission Form
To submit a ROM Code:
1. Complete ROM Code submission form.
2. Send this form and the hex file (in Intel Hex format) as separate attachments in
an E-mail to: codes@zilog.com.
Company Name:
Disty/Subcon:
Date:
___________________________
______________________
______
ZiLOG P/N:
Package Code Legend:
__________________________
Checksum
Rev. (input by ZiLOG)
___________________________
Company P/N:
_____________________________
File P Input: (input by ZiLOG)
____________________
Expected Annual volume in Units: __________
Application:
_________________________________________________________________________________
168 Preliminary Z80S183/Z80L183 PS000501-XMP1299
ROM CODE SUBMISSION
ORDERING INFORMATION
SPECIAL INSTRUCTIONS: (Optional)
ZiLOG Sales Office (or your City and Country:
_________________________________________________
Send ROM Verification to:
____________________________________________________________________
Phone:
E-mail:
Fax:
_______________________
_______________________
_________________________
TOPMARK OF PARTS
To submit a topmark:
1. Check box for default or custom for the preferred package.
2. On default, ‘9999’ indicates ROM number assigned to part by ZiLOG.
3. When custom topmark is selected, enter characters in the space provided.
ZiLOG adds the date code (XXYY BB) as bottom line and align as shown on
default topmark.
4. When you do not use all the lines on a custom topmark, you must leave the top
line blank.
5. For ™ (Trademark) symbol, place lowercase ‘tm’. For © (Copyright) symbol,
place lowercase ‘c’ followed by a space.
6. For custom logo, attach BMP, JPEG, or GIF file to this form.
7. To use ZiLOG in a custom topmark, type: pZiLOG. The pis a placemark
for the ZiLOG name.
PS000501-XMP1299
Preliminary Z80S183/Z80L183
169
DISCLAIMER
PRECHARACTERIZATION PRODUCT
DISCLAIMER
©2000 by ZiLOG, Inc. All rights reserved. Information in this publication
concerning the devices, applications, or technology described is intended to suggest
possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME
LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTEL-
LECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO
USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG,
use of information, devices, or technology as critical components of life support
systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this
document under any intellectual property rights.
PRECHARACTERIZATION PRODUCT
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or nonconfor-
mance with some aspects of the document may be found, either by ZiLOG or its
customers, in the course of further application and characterization work. In addi-
tion, ZiLOG cautions that delivery may be uncertain at times, because of start-up
yield issues.
ZiLOG, Inc.
910 East Hamilton Avenue
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: HTTP://WWW.ZILOG.COM
DOCUMENT INFORMATION
CHANGE LOG
Rev
Date
Purpose
By
00
01
09/13/99
12/01/99
Original issue
ggamble
dzattiero
Add preliminary test data and errata
170
Preliminary Z80S183/Z80L183
PS000501-XMP1299
相关型号：
©2020 ICPDF网 联系我们和版权申明