Z80S18333AECRXXXX [ZILOG]
Microprocessor, 8-Bit, 33MHz, CMOS, PQFP100, TQFP-100;
| 型号： | Z80S18333AECRXXXX |
| 厂家： | 
ZILOG, INC. |
| 描述： | Microprocessor, 8-Bit, 33MHz, CMOS, PQFP100, TQFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总202页 (文件大小：1080K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applica-
tions, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC.
DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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The Z80S183 is a general-purpose integrated microprocessor. It includes the
Z8S180 processor, 32 bits of general purpose I/O, an Analog-to-Digital converter
with eight multiplexed inputs, a Programmable I/O Sequencer, a Digital-to-
Analog converter, a Watch-Dog Timer, two ASCI channels, two timers, a CSI/O
channel, a Real Time Clock, 2KB of on-chip RAM, and 1KByte of on-chip ROM.
It is packaged in a 100-pin VQFP.
The Z80S183 includes the following features:
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Code-compatible with Z80 & Z180
On-chip wait state generator
Two enhanced UART channels (ASCIs)
Two 16-bit counters
Three interrupt request inputs, two with optional edge-triggering
Real time clock
Two on-chip oscillators
DC-to-33 MHz operating frequency @ 5.0V
DC-to-20 MHz operating frequency @ 3.3V
Clock divide by 2X or 1X
Fully static CMOS design with low-power standby
2 KB of on-chip RAM
1 KB of on-chip ROM
Eight 10-bit A/D channels
One 10-bit D/A
32 bits of general-purpose I/O
Low-power PLL oscillator
Programmable Input/Output Sequencer (PIOS)
Watch-Dog Timer (WDT)
Clocked Serial I/O Interface (CSI/O)
ZiLOG Debug Interface (ZDI)
Power-down logic
ASCI Tx complete output
Economical 100-pin VQFP
Interrupts on ports A and D
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Figure 1 illustrates the block diagram for the Z8S183. In addition to a Z8S180-
compatible processor, it includes the following modules:
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Figure 2 illustrates the Z8S183 pinout. Table 2 describes the processor and device
pins. Table 2 describes the Asynchronous Serial Communications Interface
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Programmable I/O Sequencer (PIOS)pins. Table 4 describes the analog pins.
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This section describes, using text, tables, and figures, how the various parts of the
Z80S183 operate. This description is presented from the processor outward to the
peripherals. In the latter parts of this section, refer to the corresponding section of
“I/O Registers” on page 70, which present the Z80S183’s I/O registers. Cross-
reference links are included in both sections to aid these references.
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The Z80S183 is an 8-bit microprocessor that performs certain 16-bit operations.
In both data sizes, the processor includes an accumulator. Register A is the accu-
mulator for 8-bit operations, and the HL register pair is the accumulator for 16-bit
operations.
2TQEGUUQTꢁ2TQITCOꢁ4GIKUVGTU
In addition to register A, there are six more 8-bit registers named B, C, D, E, H,
and L, which can also be operated on as 16-bit register pairs BC, DE, and HL.
Flag register F completes the basic register bank.
Two of these basic register banks are included in all Z80 and Z180 processors.
High-speed exchange between these banks can be used by a program internally, or
one bank can be allocated to the mainline program and the other to interrupt
service routines.
Finally, two Index registers IX and IY allow base and displacement addressing in
memory. IX and IY are not included in the register banks on the Z80 and Z180;
there is only one copy of each.
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To the 16-bit, 64 KB memory addressing capability of the Z80, all Z180 proces-
sors add a Memory Management Unit (MMU) that expands the addressing capa-
bility to 20 bits (1 MB). With the MMU, the 64 KB logical addressing space can
be divided into one to three areas of programmable size and location in the
1-MB physical memory space.
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A separate I/O space includes on-chip and off-chip peripheral devices. On the
Z80, I/O space included 8-bit addresses and 256 bytes. All Z180 processors
feature an expanded I/O space with 16-bit addresses and 64 KB. The Z80S183
includes an extensive set of on-chip peripherals in I/O space, which can be
augmented by external peripherals.
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In addition to the data-oriented registers described above, the Z80S183 processor
includes several other control registers. Unlike the registers in I/O space that are
described in Section 4, these control registers have no addresses, but are used
implicitly in certain processor operations.
2TQITCOꢁ%QWPVGTꢁꢎ2%ꢏꢆꢁThis 16-bit register tracks program execution by the
processor, which automatically increments PC while fetching instructions. The
processor stores PC on the stack when it executes a CALLor RSTinstruction, or
an interrupt or TRAPoccurs. The processor loads PC with a new value when it
executes a JUMP, CALL, RST, or RETinstruction, and when an interrupt, Trap, or
Reset occurs. PCresets to 0000.
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a 16-bit value in memory at this updated address, when it executes a PUSH, CALL,
or RSTinstruction, and when an interrupt or Trap occurs. The processor fetches a
16-bit value from memory at the address in SP, and then increments SP by 2, when
it executes a POP, RET, RETI, or RETNinstruction. Software can store the value
in SP in memory, load SP from memory or another register, or load it with a
constant/immediate value. Further, software can add or subtract the value in SP to
or from another register, and can increment or decrement SP. Finally, software can
exchange the 16-bit value in memory, to which SP currently points, with the
contents of a 16-bit register. SP resets to 0000B.
(NCIUꢁꢎ(ꢏꢆꢁThe processor includes two Flag registers each containing six bits,
named Zero (Z), Carry (CF), Sign (S), Parity or Overflow (P/V), Half-Carry (HC)
and Add/Subtract (N). Certain flags are automatically updated as part of executing
certain instructions. Subsequent instructions can then use the flags, either as an
operand (ADC, SBC, DAA), or to determine whether to perform a JUMP, CALL, or
REToperation. The flags can be saved on the stack with a PUSHinstruction, or
restored from the stack with a POPinstruction. The two sets of flag registers are
paired with the two A accumulators; the current pair is toggled by the
EXAF,AF’instruction.
+PVGTTWRVꢁ*KIJꢁ#FFTGUUꢁꢎ+ꢏꢆꢁThe contents of this register are used as the eight
high-order address bits, when the processor fetches the address of an interrupt
service routine from memory, for an interrupt from the INT1or INT2pin, or
from an on-chip peripheral. The I register points at a table of interrupt service
routine addresses, that starts at a 256-byte boundary in the 64 KB logical address
space. The I register resets to 0, and can be read or written by the dedicated
instructions LDA,Iand LDI,A.
4ꢁ%QWPVGTꢁꢎ4ꢏꢆꢁOn the Z8018x family processors this register contains a count of
executed fetch cycles. R resets to 0, and can be read or written by the dedicated
instructions LDA,Rand LDR,A.
1DUGTXKPIꢁ4GCFꢁ&CVCꢁHTQOꢁ1Pꢀ%JKRꢁ&GXKEGU
Bit 7 of the Output Control Register (OCR, illustrated on page 77) determines
whether the Z80S183 drives data from on-chip ROM, RAM, and I/O registers,
onto the D7–D0 pins for debugging and monitoring purposes. When this bit is 0,
as it is after a reset, the D7–D0 pins remain in high-impedance state during read
cycles from on-chip devices, saving power.
If software sets this bit to 1during device initialization, the Z80S183 drives read
data from on-chip devices onto D7–D0, allowing it to be captured by debugging
instruments such as logic analyzers.
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Like most processors, the defined instruction set for the Z8018x family does not
fully cover all possible sequences of binary values. The Op Code maps, in the
section, “Op Code Map” on page 157, include numerous blank cells. These cells
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represent Op Code sequences for which no operation is defined, and are
commonly called illegal instructions.
When a Z80S183 or other Z8018x processor fetches one of these sequences, it
performs a Trap sequence as follows:
1. The Trap bit is 1in the Interrupt/Trap Control register.
2. The UFO bit in the Interrupt/Trap If the register is set to 0if the processor
detected the condition while fetching the second byte of the instruction. The,
UFO bit clears to 1if in the Interrupt/Trap Control register. If the condition
was detected while fetching the third byte, UFO is 1.
3. The processor decrements the Stack Pointer (SP) by 2 and stores the 16-bit
logical address from PC, in memory at the new SP address. This address points
to the last byte of the illegal Op Code sequence.
4. The processor then clears PC and resumes execution at logical address 0000.
6TCRꢁ*CPFNKPIꢆꢁThe code at logical address 0000Bcan optionally store the value
of SP in memory, and then set SP to an area of memory dedicated to its private
stack.
In all cases, the trap-handling routine stores as many registers among AF, BC, DE,
HL, IX, and IY as it may use, by pushing them onto the stack. A general-purpose
routine stores all of these registers, those in the alternate set, the value of I and the
state of the Interrupt Enable flag.
Next, the Trap-handling code distinguishes among the four events that can bring
execution to address 0000B:
•
•
•
•
A Reset
A Trap
An RST0instruction
A program error, such as a JUMPto a null pointer
The code detects a Trap by reading the Interrupt/Trap Control register (ITC) and
checking bit 7 (Trap). If bit 7 is 1, a Trap has occurred, and the code handles it as
follows:
1. Clears the Trap bit by writing a 0to bit 7 of the ITC
2. Fetches the PC value stored on the stack
3. Examines bit 6 of the ITC (UFO).
4. Decrements the PC value by 1, if the UFO bit is 0; otherwise, decrements it by
2, so that it points to the start of the illegal instruction.
The next action of the trap handling routine depends on the application and its
stage of development.
'ZVGPFKPIꢁVJGꢁ+PUVTWEVKQPꢁ5GVꢆꢁCore software can use illegal instructions as
extensions to the Z8018x instruction set. To accomplish this, the trap handler must
fetch and examine each illegal instruction. If an illegal instruction is an extension,
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the trap handler performs the extended operation that the instruction indicates. It
then advances the stacked PC value over the instruction, restores the saved
register values, and returns to the next instruction.
'TTQTꢁ/GUUCIGꢁXUꢆꢁ4GUVCTVꢆꢁExcept for these extended instructions, the trap
handling software can perform either of the following actions:
•
Output an error message and wait for someone to examine the situation and re-
start the application
•
Attempt to restart the application immediately
The former course is more common in the debugging/development stages of an
application, while the latter may be more appropriate in the production/deploy-
ment stage. In the latter case, software may log the event for future readout, using
an external storage medium or just in memory.
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Three registers (described on page 74), allow software to determine if it is oper-
ating on a Z80S183, as well as the device version. These registers are a mandatory
feature of the ZDI interface that is described in “ZiLOG Debug Interface” on
page 180, and are also available in I/O space.
I/O addresses 003BHand 003CHread as 01and 00respectively, indicating that
the Z80S183 was one of the first devices to incorporate a ZDI interface. I/O
address 003DHreads as 00for revision AB, 01for revision BA, and will feature
higher values on future revisions.
+06'447265
ZiLOG Z80 and Z180 processors have a rich legacy of sophisticated interrupt
capabilities. Because of the ack of an I/O Request signal on the Z80S183, its inter-
rupt subsystem is substantially simpler and easier to describe than those of other
8018x devices.
The following topics that are significant for other 8018x processors, do not apply
to the Z80S183:
•
•
•
•
•
INT0 Mode 0 and 2 interrupts,
Interrupt acknowledge cycles,
Interrupt daisy chains,
Interrupt Pending and Interrupt Under Service bits, and
RETIinstructions.
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+'(ꢄꢁCPFꢁ+'(ꢌꢆꢁThese bits are internal to the processor and can only be affected
and manipulated by certain specific events:
•
A Reset clears IEF1 and IEF2
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•
•
An EIinstruction sets IEF1 and IEF2
A DIinstruction clears IEF1 and IEF2
An NMIsequence copies IEF1 to IEF2, then clears IEF1
A maskable interrupt clears IEF1 and IEF2
An LDA,Ior LDA,Rinstruction copies IEF2 to the P/V flag
An RETNinstruction copies IEF2 to IEF1
When IEF1 is 1, RESETand BUSREQare both High, and no falling edge has
occurred on NMI, the Z80S183 checks for maskable interrupt requests from
external pins and on-chip peripherals, as it completes each instruction, or each
instruction iteration for HALT, the block I/O instructions, block move instructions,
and block scan instructions.
6JGꢁ+ꢁ4GIKUVGTꢆꢁThe Z80S183 uses the contents of this register as A15–8 of the
logical address for fetching interrupt service routine addresses from memory, in
response to interrupt requests on INT1and INT2, and from internal peripherals.
See “Interrupt Registers”, which starts on page 80, for other registers associated
with interrupts.
6JGꢁ+.ꢁ4GIKUVGTꢆꢁThe Z80S183 uses bits 7-5 of this register as A7–5 of the logical
address for fetching interrupt service routine addresses from memory, in response
to interrupt requests on INT1and INT2, and from internal peripherals.
6JGꢁ+PVGTTWRVꢇ6TCRꢁ%QPVTQNꢁ4GIKUVGTꢁꢎ+6%ꢏꢆꢁ2-0 of the ITC are individual Enable
bits for the INT2, INT1, and INT0pins, respectively. They reset to 001B, so
that requests on INT0can be enabled by an EIinstruction after Reset.
+PVGTTWRVꢁ'FIGꢁ4GIKUVGTꢁꢎ+'4ꢏꢆꢁBy reading this register, software can sense the
current state of the INT2and INT1pins, and whether an edge has been detected
on each. Other bits in the IER select whether each of these pins is low-level sensi-
tive, or rising- and/or falling-edge sensitive.
0QPOCUMCDNGꢁ+PVGTTWRVꢁꢎ0/+ꢏ
TheZ80S183 latches falling edges on the NMIpin. A falling edge clears the DME
bit in the DMA Status register (DSTAT), disabling the on-chip DMA channels.
Only a Low on RESETor on BUSREQtakes precedence over NMI. Unless RESET
or BUSREQis Low, the Z80S183 checks for a falling edge on NMIas it completes
each instruction (each instruction iteration of HALT, the block I/O instructions,
block move instructions, and block scan instructions), and performs an NMI
sequence if a falling edge has occurred.
An NMI sequence includes 4 steps:
1. The processor copies the state of the IEF1 bit to IEF2.
2. It clears IEF1 to prevent maskable interrupts.
3. It decrements SP by 2, and stores the logical address in the PC in memory at
the new address in SP. For most interrupts, this value is the address of the
ꢂꢉ
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instruction the processor would have executed next, had no interrupt occurred.
If the processor was stopped by HALTor SLP, this value is the address of the
next instruction. In the event of an incomplete block transfer, block scan, or
block I/O instruction, this value is the address of the instruction.
4. The processor loads 0066Hinto PC, and resumes execution from that logical
address.
0/+ꢁ*CPFNKPIꢆꢁNMI routines fall into two categories, based on whether the
external hardware that drives NMIis capable of producing another falling edge on
the pin, before the NMI service routine has completed its execution and returned
to the interrupted process.The case when the NMI is not capable of producing
another falling edge is called Single Edge Guaranteed. The case when the NMI
can produce another falling edge is called Repeated Edge Possible. Debug moni-
tors, which may display the state of the interrupt process, fall into the Repeated
Edge category.
5KPINGꢁ'FIGꢁ)WCTCPVGGFꢆꢁꢁAn NMI routine in this category is similar to other
interrupt service routines. This routine has the option of storing the contents of SP
in memory and loading SP with the address of a memory area that is dedicated for
the stack. In any case, this routine stores as many of the registers as it may use
during its execution.
4GRGCVGFꢁ'FIGꢁ2QUUKDNGꢆꢁAn NMI routine in this category starts with a PUSHAF
instruction, then LOAD Afrom a dedicated location in memory that indicates
whether the interrupted process is the NMI routine. If this location indicates that
the process is the NMI routine, it immediately performs a POPAFand then a
RETNinstruction, to return to its former execution.
If the in NMI location is cleared, software sets it to 1. Then, if the NMI routine
performs either of the following:
•
•
Places a DIinstruction in a Save The Registers routine that it shares with other
means of entry, or
Displays the I register or the interrupt-enable state of the interrupted process,
and allows a user/programmer to change these (in essence, a debug monitor)
it performs LDA,Iand PUSHAFinstructions. This stores the I register at the
address in SP plus one, and the interrupt enabled state (IEF2) in the
P/V flag and in bit 2 of the memory location pointed to by SP.
If the NMI routine uses a common Save The Registers subroutine that it shares
with other entry points, the save subroutine can perform a DIinstruction to
prevent interruption by maskable interrupts.
The NMI routine has the option to store the SP value in a dedicated location in
memory, and load SP with the address of a dedicated NMI stack area.
In any case, the NMI routine must PUSH as many other registers as it uses. A
debug monitor typically performs PUSHoperations on all registers in both banks,
so that it can display them.
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
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+
4GGPCDNKPIꢁ6JGꢁ&/#ꢁ%JCPPGNUꢆꢁIn an NMI service routine in an application that
uses the DMA channels, software next reads the DSTAT register and reenables
any DMA operation that was in progress, as described in the in “NMI and DME”
on page 42.
'ZKVKPIꢁ6JGꢁ0/+ꢁ4QWVKPGꢆꢁOn completion of its processing, an NMI routine
restores the saved registers. If the routine used its own stack area, it then restores
the SP value of the interrupted process. If the routine set an in NMI memory loca-
tion on the way in, it clears this location to 0.
NMI routines that did not save the I register and IEF2 state at the start, can
conclude with POPAFand RETNinstructions. RETNcopies the state of IEF2
back into IEF1, restoring the interrupt enable state of the interrupted process.
NMI routines which saved I and IEF2 at the start, conclude with a POPAFfor the
saved I register and IEF2 bit. Then an LDI,A, followed by a JPVto a POPAF,
EI, RETsequence. The JPis followed by LDI,A, POPAF, and RETinstruc-
tions.
+06ꢃꢁ/QFGꢁꢄ
The Z80S183 can only handles interrupts requested on the INT0pin in Mode 1.
All Z80S183 applications that enable interrupts and do not tie INT0High, must
include an IM1instruction before the first EIinstruction.
The Z80S183 performs an INT0interrupt sequence at the end of an instruction
(each instruction iteration for HALT, the block I/O instructions, block move
instructions, and block scan instructions), if all of the following are true:
•
•
•
•
INT0is Low
Bit 0 of the Interrupt/Trap Control register is 1 to enable INT0
The IEF1 bit is set to 1 to enable interrupts in general general
RESETand BUSREQare both High, and a negative edge on NMIhas not been
detected
When all of these conditions occur simultaneously, the Z80S183 responds as
follows:
1. It clears IEF1and IEF2to prevent further interrupts.
2. It decrements SP by 2, and stores the contents of PC in memory at the new
address in SP. This value is typically the address of the instruction the
processor would have executed next, if no interrupt had occurred. If the
processor was stopped by HALTor SLP, this value is the address of the next
instruction. In the event of an incomplete block transfer, block scan, or block
I/O instruction, this value is the address of the instruction.
3. It loads 0038Hinto PC, and resumes execution from that logical address.
+PVGTTWRVꢁ*CPFNKPIꢆꢁAny Interrupt Service Routine (ISR) has the initial option of
saving the contents of SP in memory, and loading SP with the address of a
ꢂꢏ
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memory area that is dedicated to its stack. Most interrupt service routines do not
use this option.
An INT0ISR must save the contents of the registers it uses, using PUSHand/or
EX AF,AF’and EXXinstructions.
If the application includes a mechanism for allowing nested interrupts, the ISR
can begin as specified by that mechanism, leading to an IEinstruction that allows
the ISR to be interrupted by other interrupts. Most applications do not allow for
nested interrupts.
The ISR next reads status registers from each device that can request an interrupt
on INT0, to identify the cause of the interrupt. The ISR must process each inter-
rupting device according to this status, and the device and application require-
ments.
Many ISRs read data from interrupting device(s), or write data to interrupting
device(s). In addition, the ISRs can write registers in these devices, to modify its
mode, status, or operation.
When interrupt processing is complete, if nested interrupts were allowed, the ISR
ends as specified by the nesting mechanism. If nested interrupts were not allowed,
the ISR restores the saved registers and concludes with EIand RETinstructions.
0QVGꢐ the Z80 and Z80180 instruction sets include an RETIinstruction, that is used for
servicing Z80 peripherals. Since the Z80S183 includes no such peripherals, nor does it
allow them to be connected externally, there is no reason to ever conclude a Z80S183 ISR
with an RETI. RETis both shorter and faster than RETI, and fills the same function.
+06ꢄꢁCPFꢁ+06ꢌ
The Z80S183 performs an INT1or INT2interrupt sequence at the end of an
instruction (each instruction iteration for HALT, the block I/O instructions, block
move instructions, and block scan instructions), if all of the following are true:
•
INT1and/or INT2meets the condition specified for it in the Interrupt Edge
Control register (low level, rising edge, falling edge),
•
Bit 2 or 1 of the Interrupt/Trap Control register (ITC) is 1 to enable this pin (if
both pins are enabled and both pins meet the specified condition, INT1takes
precedence over INT2),
•
•
•
•
IEF1 is 1, to enable interrupts in general,
INT0is High or bit 0 of the ITC is 0,
RESETand BUSREQare High, and
A negative edge on NMIhas not been detected.
When all of these conditions occur simultaneously, the Z80S183 responds as
follows:
1. It clears IEF1 and IEF2 to prevent further interrupts.
2. It decrements SP by 2, and stores the contents of PC in memory at the new
address in SP. Typically, this value is the address of the instruction the
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
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+
processor would have executed next, if no interrupt had occurred. If the
processor was stopped by HALTor SLP, this value is the address of the next
instruction. In the event of an incomplete block transfer, block scan, or block
I/O instruction, this value is the address of the instruction.
3. Next, the processor forms a logical memory address using the contents of the
I register as A15–8, bits 7–5 of the IL register as A7–5, and 0 as A4–0 for
INT1or 2 in A4–0 for INT2.
4. Finally, the processor fetches a 16-bit logical address from memory at that
logical address, loads it into PC, and resumes instruction execution from there.
+06ꢄ ꢌꢁ*CPFNKPIꢆꢁAll of the considerations noted for INT0ISRs in “Interrupt
Handling” on page 16, also apply to ISRs for INT1and INT2. One additional
step is required if the pin is edge-triggered: read the INT2-1 Interrupt Edge
Register (IECR), and write the value (including 1 in bit 5 or 4) back to the IECR
to clear the edge-detection logic.
1Pꢀ%JKRꢁ+PVGTTWRVU
The Z80S183 performs an interrupt sequence for an on-chip device at the end of
an instruction (each instruction iteration for HALT, the block I/O instructions,
block move instructions, and block scan instructions), if all of the following are
true:
•
•
•
•
An interrupting condition has occurred in the device,
That condition is interrupt-enabled in the device’s registers,
IEF1 is 1, to enable interrupts in general,
No higher-priority internal device is requesting an interrupt (see Table 5 below
for the relative priorities of internal devices),
•
•
•
•
Neither INT1nor INT2is interrupting,
INT0is High or bit 0 of the ITC is 0,
RESETand BUSREQare both High, and
A negative edge on NMIhas not been detected.
When all of these conditions occur simultaneously, the Z80S183 responds as
follows:
1. It clears IEF1 and IEF2 to prevent further interrupts.
2. It decrements SP by 2, and stores the contents of PC in memory at the new
address in SP. Typically, this value is the address of the instruction the
processor would have executed next, if no interrupt had occurred. If the
processor was stopped by a HALTor SLPinstruction, this value is the address
of the next instruction. For an incomplete block transfer, block scan, or block
I/O instruction, this value is the address of the instruction.
ꢂꢇ
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3. Next the processor forms a logical memory address using the contents of the I
register as A15–8, bits 7–5 of the IL register as A7–5, and the value
corresponding to the interrupting device as A4–0.
4. Finally, the processor fetches a 16-bit logical address from memory at that
logical address, loads it into PC, and resumes instruction execution from there.
1Pꢀ%JKRꢁ+PVGTTWRVꢁ*CPFNKPIꢆꢁThe only difference between handling an on-chip
interrupt, and the considerations noted for INT0ISRs in “Interrupt Handling” on
page 16, is that the ISR for an on-chip device never needs to differentiate among
several devices connected to an INTpin, only among interrupt sources within the
device.
6
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016'ꢐꢀ&GXKEGUꢀCTGꢀQTFGTGFꢀKFGPVKECNN[ꢀYKVJꢀTGURGEVꢀVQꢀKPVGTTWRVꢀRTKQTKV[ꢀCPFꢀQHHUGVꢀ
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/'/14;
Z8018x family processors include a 64 KB logical memory space in which soft-
ware operates, and a 1 MB physical memory address space in which on-chip and
external memory reside. The Memory Management Unit (MMU) translates 16-bit
logical addresses to 20-bit physical addresses dynamically, as part of each
memory access.
/GOQT[ꢁ5VTWEVWTG
On the Z80S183, memory is divided into four categories:
•
1 KB of on-chip ROM
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1
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/
•
•
•
2 KB of on-chip RAM
External ROM or Flash memory using on-chip decoding
External RAM using on-chip decoding
Table 28 on page 79 describes the System Configuration Register (SCR), which
includes bits that enable or disable each of these four memory categories. Soft-
ware designers must be cautious when programming this register, to not disable
the memory in which the current code sequence resides.
On-chip ROM can be enabled or disabled at Reset time, by the state of the
OPMODE1–0pins. These pins control the initial state of the on-chip ROM Enable
bit in the SCR. If on-chip ROM is enabled, it occupies physical addresses
00000–003FFH.
The last 256 bytes of on-chip RAM are always accessible to the Programmable
I/O Sequencer (PIOS) module. If processor access to on-chip RAM is enabled,
another bit in the SCR controls whether A19–16 are included in address decoding
for on-chip RAM.
The on-chip address decoder for external ROM or Flash memory decodes from
physical address 00000through a programmable upper limit. When external
ROM is enabled, memory accesses at addresses below the upper limit, drive the
ROMRDor ROMWRpin Low. (Among the capabilities of the ROMWRpin are
programming of Flash memories.)
The on-chip address decoder for external RAM decodes between programmable
lower and upper limits. When external RAM is enabled, memory accesses at
addresses between these two limits, drive the RAMRDor RAMWRpin Low.
0QVGꢐ If software programs the Memory Chip Select Logic and System Configuration
Register so that some addresses do not match either the ROM or RAM chip selection,
accesses to these addresses do not appear on the external bus. Avoid this possibility by
programming the active chip selects to cover the entire memory address space.
ꢍꢃ
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#FFTGUUKPIꢁ/QFGU
Instructions can specify a memory address in several ways. Z80S183 addressing
modes include:
4GNCVKXGꢁ#FFTGUUKPIꢆꢁJRand DJNZinstructions include a signed 8-bit displace-
ment that specifies a range of addresses –126to +129from the Op Code, to
which program control can be transferred.
&KTGEVꢁ#FFTGUUKPIꢆꢁIn this mode, instructions include a 16-bit logical address.
4GIKUVGTꢁ+PFKTGEVꢁ#FFTGUUKPIꢆꢁIn this mode, the address is taken from one of the
register pairs BC, DE or HL.
+PFGZGFꢁ#FFTGUUKPIꢆꢁIn this mode, instructions include an 8-bit signed displace-
ment from the address in an index register IX or IY.
Other contexts in which memory is accessed include instruction fetching, inter-
rupts, DMA operations, and cycles generated by external masters while BUSACK
is Low.
/GOQT[ꢁ/CPCIGOGPVꢁ7PKVꢁꢎ//7ꢏ
The MMU translates the 16-bit addresses used by software, called logical
addresses, into 20-bit physical addresses, as part of all memory accesses
performed by the processor. The MMU has no effect on accesses performed by the
DMA channels, which include 20-bit address registers. It also has no effect on
addresses in I/O space, which always have A19–16 0.
The MMU resets to a state in which it has no effect on addresses in processor
cycles, passing A15–0 through without change and keeping A19–16 0. If an
application needs 64 KB of memory or less, it ignores the MMU.
Even when the MMU has been programmed to perform active address transac-
tions, it passes A11 0from the logical to the physical address. The MMU manages
memory in 4 KB blocks.
The section titled “MMU Registers” on page 82, describes the registers associated
with the MMU.
//7ꢁ1RGTCVKQPꢆꢁThe MMU compares bits 15–12 of each logical address to two
4-bit fields in its Common/Base Address Register (CBAR), in an unsigned
manner.
If bits 15–12 of a logical address are less than the value in bits 3–0 of the CBAR,
the MMU considers the address to be in Common Area 0. For these addresses, it
passes bits 15–12 to the A15-12 pins unchanged, and sets pins A19–16 to 0.
If bits 15–12 of a logical address are greater than or equal to the value in bits 3–0
of the CBAR, but are less than the value in bits 7–4 of the CBAR, the MMU
considers the address to be in the Bank Area. For such addresses, it adds the value
in its 8-bit Bank Base Register (BBR) to bits 15–12 of the logical address, and
outputs the 8-bit sum on pins A19–12.
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
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If bits 15–12 of a logical address are greater than or equal to the value in bits 7–4
of the CBAR, the MMU considers the address to be in Common Area 1. For such
addresses, it adds the value in its 8-bit Common Base Register (CBR) to bits 15–
12 of the logical address, and outputs the 8-bit sum on A19–12.
0QVGꢐ The value in bits 7–4 of the CBAR must never be less than the value in bits 3–0 of
the CBAR.
//7ꢁ%QPHKIWTCVKQPUꢆꢁIn the general case, the MMU divides the 64 KB logical
memory space into three parts, with Common Area 0 located at the start of the
1 MB physical address space, and the Bank Area and Common Area 1 relocatable
to other parts of the physical address space. These three parts are under control of
the Bank Base Register and Common Base Register, respectively.
Certain combinations of values in the CBAR result in the logical address space
being divided into fewer active areas:
•
If the CBAR contains 0, all logical addresses fall into Common Area 1, and
are relocated to a contiguous 64 KB area starting at the address in the CBR
times 4096.
•
If CBAR3–0 are 0but CBAR7–4 are non-zero, the Bank Area and Common
Area 1 are active. Logical addresses less than (CBAR7–4)*4096are relocat-
ed by the Bank Base Register, while other addresses are related by the Com-
mon Base Register.
•
If CBAR7–4and CBAR3–0are equal and not 0, Common Area 0 and Common
Area 1 are active. Logical addresses less than (CBAR3–0)*4096are not re-
located, and map to the start of physical memory. Other addresses are relocated
by the Common Base Register.
6JGꢁ//7ꢁ#HVGTꢁ4GUGVꢆꢁBecause the CBAR resets to 11110000B, logical
addresses 0000–EFFFHare in the Bank Area and F000–FFFFHare in Common
Area 1 after Reset. But since the BBR and CBR both reset to 0, the MMU passes
all logical addresses through without change, with A19–16 all 0.
1Pꢀ%JKRꢁ41/
1Pꢀ%JKRꢁ4#/
Bit 7 in the System Configuration Register (page 79) controls whether physical
addresses 00000–003FFHaccess on-chip ROM or external memory. A 1 in this
bit enables on-chip ROM. At reset, this bit is set to 1 if the OPMOD1pin is High
and the OPMOD2pin is Low. Otherwise, this bit is cleared to 0.
Bits 6–5 in the System Configuration Register control processor access to on-chip
RAM. If bit 6 is 0, on-chip RAM is disabled. If bits 6–5 are 10, on-chip RAM
does not decode bits 19–16 of physical addresses, and responds to all physical
addresses with A15–11 all 1: xF800 through xFFFFH. If bits 6–5 are 11B, on-
chip RAM responds to physical addresses with A19–11 all 1: addresses FF800–
FFFFFH.
ꢍꢍ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
/
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ꢁ&
The Programmable I/O Sequencer (PIOS) can always read the last 256 bytes of
on-chip RAM, regardless of bits 6–5 in the SCR.
'ZVGTPCNꢁ41/ꢇ(NCUJꢁ&GEQFKPI
Bit 4 of the System Configuration Register enables or disables an on-chip address
decoder for external ROM or Flash memory. When this bit is 1, memory accesses
at physical addresses less than the upper limit programmed in the ROM Boundary
Register (ROMBR, page 84), drive the ROMRDor ROMWRpin Low. (The ROMWR
pin can be used to program Flash memories.)
When SCR bit 4 is 1, ROMRDor ROMWRgoes Low for addresses with A19–12 less
than or equal to the contents of ROMBR, that is, for addresses less than
(ROMBR+1)*4096.
'ZVGTPCNꢁ4#/ꢁ&GEQFKPI
Bit 3 of the System Configuration Register (page 79) enables or disables an on-
chip address decoder for external RAM. When this bit is 1, memory accesses at
physical addresses between the lower limit programmed in the RAM Lower
Bound Register (RAMLBR), and the upper limit programmed in the RAM Upper
Bound Register (RAMUBR), drive the RAMRDor RAMWRpin Low. These regis-
ters are described on page 86.
When SCR bit 3 is 1, RAMRDor RAMWRgoes Low for addresses with A19–12
greater than or equal to the contents of RAMLBR, and less than or equal to the
contents of RAMUBR, that is, for addresses A in the range
(RAMLBR)*4096 < A < (RAMUBR+1)*4096
9CKVꢁ5VCVGꢁ)GPGTCVQTU
The Z80S183 includes two registers that control automatic insertion of wait states
into memory and I/O accesses. The outputs of these two generators are logically
OR (Low-active OR, positive-logic AND) with the external WAITpin, such that
for a given address, the number of wait states taken is the largest number among
these two facilities and any external wait-state generator.
The DMA/Wait Control register (DCNTL) is shown on page 109, and is present
on all 8018x family members. DCNTL is one of the DMA registers, but the wait
states that it controls apply to processor cycles as well as to those generated by the
DMA channels.
Bits 7–6 select the number of waits states for all memory accesses.
Bits 5–4 select the number of wait states for I/O accesses other than those to 180
registers. The Z80S183 interprets both fields as a binary number of wait states:
ꢃꢃ 0QꢀYCKVꢀUVCVGU
ꢃꢂ ꢂꢀYCKVꢀUVCVG
ꢂꢃ ꢍꢀYCKVꢀUVCVGU
ꢂꢂ ꢊꢀYCKVꢀUVCVGU
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢍꢊ
1
ꢁ&
+
ꢋ1
The Wait State Generator Control register (WSGCR) is described on page 83, and
is unique to the Z80S183.
Bits 7–6 control the number of wait states for memory accesses in the ROMRD/
ROMWRaddress range.
Bits 5–4 control the number of wait states for memory accesses in the RAMRD/
RAMWRaddress range.
Bits 3–2 control the number of wait states for other memory accesses, but these
cycles do not appear on the external bus.
The Z80S183 interprets these fields as follows:
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
0QꢀYCKVꢀUVCVGU
ꢂꢀYCKVꢀUVCVG
ꢍꢀYCKVꢀUVCVGU
ꢉꢀYCKVꢀUVCVGU
0Qꢁ&4#/ꢁ4GHTGUJ
ZiLOG’s Z80 and Z8018x families have traditionally included dynamic RAM
refresh logic. This logic is identical on all Z8018x devices including the Z80S183,
but the Z80S183 does not have a RFSHpin with which to signal refresh cycles,
nor a Refresh Control Register.
+0276ꢇ176276
+ꢇ1ꢁ+PUVTWEVKQPU
The Z80S183 includes an I/O space that is distinct from memory space. I/O space
is accessed by means of INand OUTinstructions rather than LD, PUSH, POP, and
other instructions that access memory space. The MMU passes addresses in I/O
space through without change; such addresses always have A19–16 all 0.
The original Z80 featured a 256-byte I/O space. The following instructions are
specific to the Z80’s 256-byte I/O space, and should not be used on the Z80S183
except to access external I/O devices that do not decode A15–8:
OUT (port), A
IND
INDR
INI
INIR
OTDR
OTIR
OUTD
OUTI
The following instructions ensure that A15–8 are all 0, and can be used to access
the Z80S183’s on-chip I/O registers, as well as external devices that decode A15–
8 as all 0:
ꢍꢉ
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IN0
r, (port)
OUT0 (port), r
OTDM
OTDMR
OTIM
OTIMR
The following instructions drive A15–0 from the BC register pair, and can be used
to access the full 64 K-byte I/O space:
IN
r, (C)
OUT (C), r
The following instruction can access the entire 64 K-byte I/O space, by pre-
loading the MS 8 bits of the address into A. (This step is unnecessary for external
devices that do not decode A15-8.)
IN
A, (port)
4GNQECVKPIꢁVJGꢁꢂꢃꢄꢂꢃꢁ4GIKUVGTU
The section, “Registers Summary” on page 70, describes how the Z80S183’s I/O
registers are divided into 80180-registers and Z80S183-specific registers. The
latter registers are always located in the range 0040–007FH. After a reset, the
80180 Registers are located in the range 0000–003FH, but bits 7–6 of the I/O
Control Register (page 77) allow software to relocate the 80180 Registers to
higher addresses:
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Relocating the 180 registers is included to ease porting of Z80 applications to the
Z8018x family.
%CWVKQPꢐ Use this facility with caution because certain tools may assume that the 80180
Registers are located in the 0000– 003FHrange. Those tools need to be reconfigured (re-
assembled, recompiled) to allow for relocated 180 Registers.
9TKVGꢁ'PCDNGꢇ.QEMꢁHQTꢁ%TKVKECNꢁ4GIKUVGTU
Some registers are protected from inadvertent modification by software. Writing a
0BHto the Watch-Dog Timer Command Register (WDTCR, page 112) sets bit 0
of the Watch-Dog Timer Master register to 1 (WDTMR, page 111) and enables
writing to these registers. Writing any other value to WDTCR clears bit 0 of the
WDTMR to 0and prevents writing to these registers.
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The Write Enable state has no effect on reading the registers protected by this
mechanism, which include.
•
•
•
•
System Configuration register (SCR, page 79)
Power Control register (PCR, page 78)
Port A-D Data Direction registers (DDRA–D, pages 88–95)
All Real Time Clock registers (pages 119–123)
+ꢇ1ꢁ%JKRꢁ5GNGEVU
If bit 2 in the System Control Register (SCR) is 1, the Z80S183 drives the IOCS1
pin for accesses to I/O addresses 0080–87H, and drives the IOCS2pin Low for
accesses to 0088–8FH. If SCR bit 2 is 0, IOCS1and IOCS2remain High at all
times.
+ꢇ1ꢁ9CKVU
Bits 5–4 of the DMA/Wait Control Register can be used to insert wait states into
I/O cycles with the Z80S183-specific registers at addresses 0040–007FH, and
into I/O cycles with external devices. This field is interpreted as a binary number
of wait states:
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Bit 5 in the Operating Mode Control Register (OMCR, shown on page 76)
controls the timing of the IORDsignal when software reads from an external I/O
device. If this bit is 1, as it is after a reset, the Z80S183 drives IORDLow from the
falling edge of PHIin the T1 clock cycle. If this bit is 0, it drives IORDLow one-
half clock cycle later, from the rising edge of PHIat the start of T2. Both cases are
illustrated in Figure 3.
0QVGꢐ On other Z8018x family members, bits 7 and 6 in the OMCR control how the M1
signal affects Z80 peripheral devices. Since the Z80S183 does not have an IORQ pin, it
cannot be used with Z80 peripherals, and OMCR bits 7–6 do not matter.
6ꢂ
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The Z80S183 can be clocked in any of three ways:
•
•
•
By an external TTL- or CMOS-level clock on the EXTALpin,
By a crystal connected to its XTALand EXTALpins, or
By a low-frequency crystal (typically 32.768 KHz) connected to its LFXTAL
and LFEXTALpins.
An external clock signal must be free of overshoot or ringing, must make contin-
uous, monotonic, and rapid transitions in both directions, and must meet the
minimum High and Low times specified in “AC Characteristics” on page 167.
%NQEMꢁ5GNGEVKQP
Bits 1–0 of the System Configuration Register, which is shown on page 79, select
the source of the main device clock (PHI) between the XTAL/EXTALpins and
the LFXTAL/LFEXTALpins, and in the latter case, a multiplier for the clock:
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Because these bits reset to 00, an application that requires LFXTALand
LFEXTALmust start up using XTALand EXTAL. The circuit in Figure 6 includes
a connection that satisfies this need.
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Regardless of the source of PHI, bit 7 of the CPU Control Register (CCR,
described on page 73) controls whether the Z80S183 uses the signal selected by
bits 1–0 of the SCR directly as PHI, or whether it divides the signal by 2 to obtain
PHI.
If CCR bit 7 is 0, as it is after a reset, the part divides the selected signal by 2. This
mode insulates the part against an asymmetric waveform on the selected signal. If
CCR bit 7 is 1, the Z80S183 uses the selected signal directly. In this case, if an
external clock is connected to EXTAL, the clock must meet the minimum High
and Low times specified in “AC Characteristics” on page 167.
%KTEWKVU
When using a crystal connected to XTALand EXTAL, locate the crystal as close as
possible to the pins. This placement minimizes the trace lengths between the
crystal, the pins, and the two capacitors shown in Figure 4, which illustrates the
connection of a fundamental mode crystal up to and including 20 MHz. C1 and
C2 are 20–30 pF, with 22 pF a typical value.
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For frequencies above 20 MHz, use a third-overtone crystal and include an LC
tank circuit to filter the fundamental frequency, as shown in Figure 5. Again, it is
essential to minimize trace lengths by locating all of the components as close as
possible to the XTALand EXTALpins.
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A low-frequency crystal can be connected between the LFXTALand LFEXTAL
pins without any other components (see Figure 6). If the LF crystal is used as the
clock source for the Real Time Clock, it must be exactly 32.768 KHz.
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The following specifications apply to fundamental mode crystals up to 20 MHz:
•
•
•
•
Fundamental, parallel type (AT cut recommended)
Load capacitance: C = C1 = C2 = 20–30 pF (22 pF typical)
L
Equivalent Resistance R < 60 ohms
S
C
= C
= 15–22 pF
OUT
IN
4GFWEGFꢁ1UEKNNCVQTꢁ&TKXGꢁ1RVKQP
Bit 6 in the Clock Control Register, described on page 73, controls the gain of the
XTAL/EXTALoscillator. When bit 6 is 0, as it is after a reset, a crystal connected
to XTALand EXTALis driven strongly, to guarantee that oscillation always starts.
This drive is suitable for traditional crystals packaged in HC–49-type packages,
but may be too powerful for crystals packaged for miniaturized applications like
PCMCIA.
To reduce the gain of the oscillator, write a 1 to bit 6 of the Clock Control
Register. This action reduces the drive to about 25% of normal mode, and reduces
the maximum oscillator frequency from 33 to 20 MHz.
4'5'6ꢁ%10&+6+105
The effects of Reset on each of the registers in I/O space is described in Tables
16–131 in the section describing “I/O Registers” on page 70. Among processor
registers, the following registers and state bits are cleared to 0: PC, SP, I, IEF1,
IEF2, R, and F. The following are not changed by Reset: A, B, C, D, E, H, L, IX,
and IY.
The Z80S183 resets itself upon power-up. When power is applied, the device
detects power rising. When the oscillator starts, the Power On Reset circuitry
16
holds the Z80S183 in reset for 2 clock cycles, driving RESETLow to provide a
reset to external peripherals. This Power On Reset sequence also occurs in
response to a rising edge on OPMOD1pin. If bit 6 of the Power Control Register
(PCR) is 1, in response to a rising edge on PB2/CTS0/PWRUP.
Another possible source of Reset is the Watch-Dog Timer (WDT). See the section
“Watch-Dog Timer” on page 43, for more information on the WDT.
219'4ꢁ/#0#)'/'06
The Z80S183’s low-power modes are controlled by the Standby and Idle/Quick
bits in the CPU Control Register (page 73), the IOSTOP bit in the I/O Control
Register (page 77), and execution of SLPand HALTinstructions.
The section titled “LOW-POWER Modes” on page 30 describes the LOW-
POWER modes.
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The Power Control Register (PCR, page 78) is unique to the Z80S183, and offers
additional power control options to the board designer and programmer.
%'A176ꢆꢁThis pin can be connected to the CEor CSpin(s) of external RAM, and
to an external pullup resistor. The Z80S183 drives this pin Low when bit 7 of the
Power Control Register is 1. Software sets this bit before trying to access external
RAM. When PCR bit 7 is 0, the Z80S183 does not drive CE_OUT, and the
external resistor pulls it High, which helps safeguard the RAM against modifica-
tion. Software clears PCR bit 7 to 0 before entering a LOW-POWER mode.
The RAM and the external pullup can be powered from a supply that is active
when the Z80S183 is not powered, for example, from standby power or from a
battery.
2$ꢌꢇ%65ꢃꢇ29472ꢆꢁThis pin can be connected to a rising-edge-active wake up
signal from external logic. To use this feature, software sets bit 6 of the Power
Control Register to 1 before entering a LOW-POWER mode. When PCR bit 6 is
1, a rising edge on PB2/CTS0/PWRUP causes a Reset that is identical to a Power
On Reset. This reset brings the Z80S183 out of the LOW-POWER mode and into
normal operation. When bit 6 of the PCR is 0, PB2/CTS0/PWRUPcannot cause
a reset, and can be used for other purposes.
0QVGꢐ A rising edge on the OPMOD1pin also causes a Power On Reset. Assuming that
OPMOD1 remains High, the device executes code from on-chip ROM after the Reset.
After a Power On Reset caused by the PWRUP pin, execution starts in on-chip ROM or
external memory, depending on the state of OPMOD1.
294596%*ꢆꢁThis pin can be connected to a Low-active power switch that
controls power to external devices (for example, a P-channel FET). It is a direct
positive-logic output controlled by bit 5 of the Power Control Register, which
resets to 0 making PWRSWTCHLow, which in turn applies power to the external
devices. Before entering a LOW-POWER mode, software can write a 1 to bit 5 of
the PCR, making PWRSWTCHHigh and removing power from the external
devices.
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2ꢓꢁ6:5ꢆꢁIf bit 4 of the Power Control Register is 1, these pins are 3-stated when
the Z80S183 is in a LOW-POWER mode. This action completes the
PWRSWTCH power control mechanism, in that it keeps external memories and
peripherals from drawing power from these signals. PCR bit 4 resets to 0. To use
this facility, software sets PCR bits 5 and 4 to 1 before entering a LOW-POWER
mode.
.19ꢀ219'4ꢁ/QFGU
The IOSTOP bit in the I/O Control Register (page 77) controls operation of the
ASCIs, PRTs and CSI/O. When this bit is 0, these peripherals operate normally.
When this bit is 1, they are disabled, reducing power use.
ꢊꢃ
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The Standby and Idle/Quick bits in the CPU Control Register (page 73) control
the mode the Z80S183 enters when it executes an SLPinstruction. If the applica-
tion uses the XTAL/EXTAL oscillator and Standby is 1, an SLPinstruction stops
the oscillator. This mode uses less power than any other mode, but requires time to
restart the oscillator in response to a reset, an interrupt request, or optionally a bus
request.
When Standby is 1, the Idle/Quick bit controls the number of PHIclocks the
device waits after reenabling the oscillator and before restarting operation (0
17
selects 2 (128K) clocks, and 1 selects 64 clocks).
When Standby is 0, the oscillator runs for the duration of the SLPinstruction, but
clocking is blocked to most of the Z80S183. The Idle/Quick bit controls whether
the oscillator output is driven onto the PHIpin. A 1 in Idle/Quick disables
clocking on PHI.
When Standby is 1, the BREXT bit, bit 5 in the CPU Control Register (page 73),
controls whether the Z80S183 restarts the oscillator in response to a Low on
BUSREQ, with a 1 enabling this response.
Table 6 below details the interaction of these various bits and states, including the
conditions that make the Z80S183 leave each LOW-POWER mode and resume
normal operation.
6
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In SLEEP, SYSTEM STOP, IDLE, or either STANDBY mode, if the Z80S183
exits the mode because of NMIor an enabled interrupt with the IEF1 flag 1, the
device resumes operation by performing the interrupt, with the return address as
the instruction after the SLPinstruction. If the device exits the LOW-POWER
mode because of an individually-enabled interrupt request, but IEF1 is 0, the
Z80S183 resumes by executing the instruction after the SLP.
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Reduced drive is available on many of the outputs of the Z80S183. These options
reduce power consumption for applications that do not need the full drive and
slew rate capability provided in normal mode. Even more importantly for some
applications, invoking these features results in less noise induced onto power and
ground.
The following register bits govern the drive strength on various output pins. Each
of these bits resets to 0, which selects normal/full drive strength for the outputs.
To save power and reduce noise for outputs that do not need the maximum drive
and slew rate, software sets the associated bit to 1 during device initialization.
This action reduces the drive to about 25% of full strength.
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The Z80S183 includes four 8-bit I/O ports called A through D. All four ports
feature the same basic capabilities. The ports are controlled by three registers for
each port: a Data Register, a Data Direction Register, and an Output Control
Register.
The ports differ primarily in interrupt capability and in pin-multiplexing with
other functions, controlled by an Alternate Function Select (AFS) Register for
each port.
The next two sections describe the common characteristics shared by all the ports,
then the unique capabilities controlled by the AFS register for each port
The section titled, “I/O Port Registers” on page 87, describes the registers associ-
ated with the I/O ports.
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Writing to a Data Register affects the data that is driven onto pins that are desig-
nated as outputs in the Data Direction and Output Control Registers. Reading
from the Data Register returns the states of the pins, for both inputs and outputs.
The output latches cannot be read separately.
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These registers determine which pins in each port are inputs and which are
outputs, and for outputs, select one of three output modes. The following table
shows the four possible states for each pin:
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The totem pole outputs actively drive both High and Low. The classic open-drain
output only drives Low, and relies on an external pull-up resistor to ensure a High
voltage when no open-drain driver is driving Low. (This external pull-up also
avoids excessive current draw by the Z80S183’s receiver and any other CMOS
receivers that may be connected to the signal. The 11Bstate is similar but
connects an internal pull-up resistor of about 15K Ohms, eliminating the need for
an external pullup.
All four DDRs reset to all 1s and all four OCRs reset to all 0s, so Reset configures
all port pins as inputs.
The Data Direction Registers can only be written if the Register Write Enable bit
is 1in the WDT registers.
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This register controls interrupts from port A. AFSA resets to all zeroes, disabling
all interrupts from port A. Setting any of these bits to 1 enables the corresponding
pin to interrupt. When an interrupt is requested by the port and interrupts are
enabled, the Z80S183 fetches the address of the Interrupt Service Routine (ISR)
from memory at address (I : IL : 20). The ISR must read the Data Register to
determine which pin(s) caused the interrupt. Pins selected for interrupts are level-
sensitive and active Low. Regardless of how this register is programmed, software
must set DDRA for each port pin. Setting a pin as an output, and enabling inter-
rupt for it, allows software to force an interrupt.
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This register controls alternate functions for the port B pins. AFSB resets to all 0s,
so that all of the pins are assigned to port B. Setting a bit to 1selects the following
alternate function for the pin:
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Selecting the alternate function for a pin disables any control of the pin by the
DDRB register, but the corresponding bit in OCRB must be 0.
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Most of the inputs on the Z80S183 have weak latch circuits to reduce power
consumption if an input is not driven by an external device. A weak latch can
come up in either state at Power On, and thereafter is easily over-driven by an
external driver, or for bidirectional pins like the Port pins, by an internal driver.
Typically, the only effect of weak latches is to prevent an input voltage from
floating in the threshold region, which makes the receiver circuit draw High
current.
For the PB7–0pins only, the weak latches can be disabled by setting bit 4 of the
Output Control Register to 1, (described on page 77). When this bit 4 is 0, as it is
after a Reset, weak latches are enabled on Port B.
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AFSC resets to all 0s, so that all of the pins are assigned to port C. Setting a bit to
1 assigns that pin to the Programmable I/O Sequencer (PIOS). In this
ALTERNATE FUNCTION mode, the DDRC and OCRC registers determine the
output drive on the pin. This feature allows the PIOS to be used with any of the
output modes of the normal port function. To use PC0 as a 50 or 60 Hz time base
for the Real Time Clock, leave AFSC bit 0 at 0, DDRC bit 0 at 1, and OCRC bit 0
at 0.
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This register controls interrupts from Port D. AFSD resets to all 0s, disabling all
interrupts from port D. Setting any of these bits to 1enables the corresponding pin
to interrupt. When an interrupt is generated by the port and interrupts are enabled,
the Z180 fetches the address of the Interrupt Service Routine (ISR) from memory
at (I: IL: 22). The ISR must read the Data Register to determine which pin(s)
caused the interrupt. Pins selected for interrupts are level-sensitive and active
Low. Regardless of how this register is programmed, software must set DDRD for
each port pin. Setting a pin as an output, and enabling interrupt for it, allows soft-
ware to force an interrupt.
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tion describes how to take DMA Requests from these pins, which programmed
inputs in this case.
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To use the A/D capability of Port D, leave the Alternate Function Select Register
in PORT mode and set the DDRD and OCRD for input.
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The Z80S183 includes two DMA channels called DMA0 and DMA1. Both chan-
nels can transfer data between memory and a peripheral in I/O space. addition,
DMA0 can perform memory-to-memory block transfers, and transfers between
memory and memory-mapped I/O devices.
Both DMA channels are of the flowthrough type, in which each byte transferred
requires two bus cycles—the first to read the source and the second to write the
destination. As a result, neither memory nor peripherals are subject to any special
considerations for bus cycles controlled by the DMA channels, because such
cycles are identical to processor bus cycles.
DMA transfer can occur as fast as 6 clocks/byte. At 33 MHz, this speed
corresponds to 5.5 MBPS. Destination/output devices require Edge-Sensitive
request mode, in which the maximum rate is 9 clocks/byte, or 3.67 MBPS at
33 MHz.
The section, “DMA Registers” on page 98, describes the registers associated with
the DMA channels.
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Each channel has two 20-bit address registers and a 16-bit byte count. For DMA0
the address registers are called the Source and Destination Address Registers
(SAR and DAR). DMA1’s address registers are called the Memory and I/O
Address Registers (MAR and IAR).
Each address register is divided into three Z80S183 I/O registers, called L (Low),
H (High), and B.
When a DMA channel is operating, it drives A7–0 from the L register and A15–8
from the H register. For memory addresses (always for MAR) the channel drives
A19–16 from the least significant four bits of the B register. For I/O addresses
(always for IAR) the channel uses the least significant three bits of the B register
to select the source of the DMA Request signal that controls data transfer.
Each byte count register is divided into two Z80S183 I/O registers, called L (Low)
and H (High).
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After programming a DMA channel’s address and byte count registers, software
starts the channel by setting the Enable bit in the DSTAT register (DE0 or DE1).
As/after the channel transfers each byte, it decrements the byte count register.
When a channel has decremented the byte count to 0, it goes inactive by clearing
its Enable bit to 0.
Software can select whether a channel increments or decrements a memory
address as/after it transfers each byte. DMA0 also features an option to keep a
memory address fixed. This fixed address option is intended for use with a
memory-mapped I/O device that provides a DMA Request signal on the
PD0/AC0/DREQ0pin.
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An external peripheral, that needs a DMA channel to transfer data for it, must
provide a DMA request signal to the PD0/AC0/DREQ0pin for DMA0, and/or to
the PD1/AC1/DREQ1pin for DMA1. A DMA request can be connected directly
to one of these pins if only one external peripheral is serviced by that DMA
channel. If more than one external device is to use a DMA channel, external selec-
tion logic must be included in the application, to route the current device’s request
to the channel’s DREQpin.
The otherwise-unused bits 19–-16 of the I/O address of a peripheral, select either
the external DREQpin or an internal peripheral as the source of each DMA
channel’s request. For a memory-mapped peripheral (a source or destination of a
DMA0 memory-to-memory operation that is programmed to use a fixed address),
the PD0/AC0/DREQ0pin is always used as the Request signal.
The DMA request signal indicates when an input or source peripheral has a byte
to be transferred to memory, or when an output or destination peripheral needs a
byte from memory.
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DMA requests can be programmed to be low-level sensitive or falling-edge sensi-
tive. For an output/destination peripheral, the timing requirements on the DMA
Request signal dictate falling-edge mode. An input/source peripheral can use
either an edge- or level-sensitive DMA Request.
Figure 7 illustrates the timing of a level-sensitive DMA Request. DMA operation
is triggered when the channel samples the DMA request line Low. The channel
samples the Request line again, at the rising PHIedge that begins the second-last
clock cycle of the write cycle to the destination. If the Request line is Low at that
time, as it is at the rightmost down-arrow below, the channel continues on to
transfer another byte. If the Request is High, as at the leftmost down-arrow below,
the DMA channel relinquishes use of the bus (to the processor, the other DMA
channel, or an external master) after completing the write cycle.
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Figure 8 illustrates the timing of an edge-sensitive request. At the first down-
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edge has not occurred by the second-to-last rising PHI edge of the cycle. The
channel relinquishes the bus to the processor.
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has occurred on the Request line, so the DMA channel assumes control of the bus,
and reads and then writes a byte.
At the same point in the DMA write cycle, a new falling edge has not yet
occurred, so the channel returns bus control to the processor. The channel does not
operate again until the Request line goes High and then Low again, some time
after the right edge of Figure 8.
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In a DMA0 memory-to-memory operation, in which both the source and destina-
tion are programmed for address incrementing or decrementing, there is no
peripheral to supply a request signal to control the transfer. In this case, software
can select between two modes of operation by programming MMOD, bit 1 of the
DMA mode register.
If MMOD is 0, the processor and DMA channel alternate bus cycles until the
DMA completes the block transfer and decrements the byte count to 0. This
sequence is called CYCLE STEAL mode.
If MMOD is 1, the DMA channel performs continuous cycles until the block
transfer is complete. The processor can perform no other actions during this time.
This sequence is called BURST mode.
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Software can enable interrupts from each DMA channel, which then requests an
interrupt after decrementing its byte count to 0. When the processor acknowl-
edges this interrupt, it fetches the address of the interrupt service routine from
memory at (I : IL : 8) for DMA0, or (I : IL : 10) for DMA1.
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If the interrupt service routine does not have another block of data for the DMA
channel to transfer, it prevents further interrupts by clearing the interrupt enable
bit (DSTAT bit 2 for DMA0, bit 3 for DMA1), before it reenables interrupts with
an EI instruction. If the ISR programs the DMA channel for another transfer,
interrupts can be reenabled with an EIinstruction, after restarting the DMA by
writing to DCNTL.
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in I/O space, write SAR0B with a code to select the source of the DMA Request
for DMA0, as described in Table 8:
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If the DMA destination is in I/O space, write DAR0B with a code to select the
source of the DMA Request for DMA0, as described in Table 9:
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#5%+ꢂꢀ6&4'
4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
For DMA1, software must write registers MAR1L, MAR1H, MAR1B, IAR1L,
IAR1H, and IAR0B. Write IAR1B with a code to select (with the DIM1 bit in the
DCNTL) the source of the DMA Request for DMA1, as described in Table 10:
ꢉꢃ
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ꢃꢃꢃ
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#5%+ꢃꢀ4&4(
#5%+ꢂꢀ6&4'
#5%+ꢂꢀ4&4(
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
ꢃꢀꢐOGO→+ꢋ1ꢑ
ꢂꢀꢐ+ꢋ1→OGOꢑ
:
ꢃꢂꢃ
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4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
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:
9TKVGꢁVJGꢁ$[VGꢁ%QWPVꢁ4GIKUVGTUꢆꢁWrite the less-significant byte to BCR0L or
BCR1L, and the more-significant byte to BCR0H or BCR1H. An all-0 value
causes the DMA to transfer 65,536 bytes.
(QTꢁ&/#ꢃꢓꢁ9TKVGꢁVJGꢁ&/#ꢁ/QFGꢁ4GIKUVGTꢆꢁBits 3–2 select the operating mode
for the source, as described in Table 11. Bits 5–4 select the operating mode for the
destination, as described in Table 12. For memory-to-memory block transfers, bit
1 (MMOD) selects between Cycle Steal and Burst modes, as described in
“Memory-to-Memory Modes” on page 39.
6
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ꢃꢃ
ꢃꢂ
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+PETGOGPVꢀ/GOQT[ꢀ#FFTGUU
&GETGOGPVꢀ/GOQT[ꢀ#FFTGUU
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6
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ꢃꢃ
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+PETGOGPVꢀ/GOQT[ꢀ#FFTGUU
&GETGOGPVꢀ/GOQT[ꢀ#FFTGUU
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(KZGFꢀ+ꢋ1ꢀ#FFTGUU
9TKVGꢁVJGꢁ&%06.ꢁ4GIKUVGTꢆꢁIf both DMA channels can be used simultaneously,
software reads DCNTL, modifies the bits noted below for the current DMA
channel, and writes back the result. Otherwise, software can simply write
DCNTL.
Bits 7–4 select the number of waits to insert for Memory and I/O accesses, as
described in the section “Wait State Generators” on page 23. For DMA0, bit 2
selects between edge- and level-sensitivity on the DMA Request. For DMA1, bit
3 selects between edge- and level-sensitivity, and bits 1–0 select the operating
mode as described in Table 13:
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ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
+PETGOGPVꢀ/GOQT[ꢀ#FFTGUUꢀ→ꢀ(KZGFꢀ+ꢋ1ꢀ#FFTGUU
&GETGOGPVꢀ/GOQT[ꢀ#FFTGUUꢀ→ꢀ(KZGFꢀ+ꢋ1ꢀ#FFTGUU
(KZGFꢀ+ꢋ1ꢀ#FFTGUUꢀ→ꢀ+PETGOGPVꢀ/GOQT[ꢀ#FFTGUU
(KZGFꢀ+ꢋ1ꢀ#FFTGUUꢀ→ꢀ&GETGOGPVꢀ/GOQT[ꢀ#FFTGUU
9TKVGꢁVJGꢁ&56#6ꢁ4GIKUVGTꢁVQꢁ'PCDNGꢁVJGꢁ&/#ꢁ%JCPPGNꢆꢁIf both DMA channels
can be used simultaneously, software reads DSTAT, modifies the bits noted below
for the current DMA channel, and writes back the result. Otherwise, software can
simply write DSTAT.
For DMA0, write 110 to bits 6–4, and write a 1 to bit 2 if DMA0 interrupts when
it has decremented its byte count to 0, or a 0 if not.
For DMA1, write a 1 to bit 7, 01 to bits 5–4, and a 1 to bit 3 if DMA1 interrupts
when the when it has decremented its byte count to 0, or a 0 if not
0/+ꢁCPFꢁ&/'
When software writes to DSTAT to enable either DMA channel, this action also
sets the DMA Master Enable (DME) bit (bit 0 in DSTAT). A 1 in this bit enables
operation by either or both DMA channels.
To guarantee that a Non Maskable Interrupt (NMI) is handled promptly, when it
detects NMILow the Z80S183 sets DME to 1 to suspend DMA operation.
The NMI service routine reads DSTAT immediately after saving the registers. For
each DMA channel, if the DE bit (DSTAT7 or 6) is 1, and the associated device (if
any) has not overrun or underrun, the service routine clears that channel’s DWE
bit (DSTAT5 or 4) to 0. Then, if either DWE bit is 0, the routine writes the result
back to DSTAT. This sequence sets DME again and reenables DMA operation.
&/#ꢁ%JCPPGNꢁ%QORNGVKQP
While a DMA channel is operating, software can stop it by reading DSTAT,
clearing bits 6 and 4 for DMA0, or 7 and 5 for DMA1, and writing the result back
to DSTAT.
Otherwise, if software enabled the channel to interrupt, when the channel has
decremented its byte count to 0, an interrupt is requested.
If software did not enable the DMA channel to interrupt, it can read the Enable bit
in DSTAT (bit 6 for DMA0, bit 7 for DMA1) to determine whether/when the
DMA channel finishes transferring the current block of data. In some applications,
software can use status or an interrupt from the associated peripheral device to
determine completion of the block transfer.
ꢉꢍ
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When the conditions noted in “On-Chip Interrupt Handling” on page 19 are met
with respect to a DMA interrupt request, the processor fetches the interrupt
service routine (ISR) address from memory at (I : IL : 8) for DMA0 or (I : IL : 10)
for DMA1. The ISR performs the following functions, as a minimum:
•
Reads the DSTAT to verify that the DE bit is 0 for the DMA channel corre-
sponding to the service routine entry point. If a common ISR is used for both
DMAs, the DSTAT value indicates which DMA channel(s) has (have) com-
pleted operation.
•
•
•
Reprograms the channel’s registers and restarts it if the channel is to continue
operation.
Clears the DIE bit for the channel, in the DSTAT register, to prevent another
interrupt for the same DMA completion.
Concludes with EIand RETinstructions, to return to the interrupted process.
9#6%*ꢀ&1)ꢁ6+/'4
The Watch-Dog Timer (WDT) helps protect against unreliable software, power
line faults that put the processor into unusual states, and other system-level prob-
lems.
When the WDT is enabled, software must periodically reload it, to prevent it from
resetting the processor or the entire application. The time period, within which
18 22 25
27
software must reload the WDT, is programmable among 2 , 2 , 2 , or 2
system clocks.
The registers in the WDT are detailed in “Watch-Dog Timer Registers” on
page 110.
Several provisions of the WDT enhance its integrity against runaway execution.
The WDT can only be reloaded by writing the specific value 4EHto the WDT
Command register. The WDT can only be disabled by:
•
•
•
Setting bit 1 of the WDT Master register to 1
Writing the value 40Hto the WDT Command register
Clearing bit 1 to 0 in the Master register.
Core code at logical address 0000Btypically identifies a Reset if the SP contains
0000B. At reset, two bits in the WDT Master register (WDTMR) help identify
the cause of the reset. Bit 3 is 1for a Power On Reset, while bit 2 is 1 for a WDT
Reset. Reading The WDTMR clears these bits for subsequent reads.
241)4#//#$.'ꢁ4'.1#&ꢁ6+/'45ꢁꢎ2465ꢏ
The Z80S183 includes two Programmable Reload Timers called PRT0 and PRT1.
Each includes a 16-bit down-counter that can be read at any time, and a reload
value that can be dynamically programmed. Each PRT can interrupt the processor
when it counts down to 0 and reloads.
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0QVGꢐ On other 8018x family devices, PRT1 has waveform-generation capability on a
pin called TOUT, but on the Z80S183 this function is superseded by the more capable
Programmable I/O Sequencer (PIOS).
“Programmable Reload Timer (PRT) Registers” on page 113, details the PRT
registers. Reset clears both Timer Downcount Enable bits (TDE1, TDE0) in the
Timer Control register to 0, which prevents PRT operation.
5VCTVKPIꢁCꢁ246
To start a PRT:
1. Write the initial down-count value to the Timer Data Registers (TMDR0L and
TMDR0H, or TMDR1L and TMDR1H),
2. Write the second (and possibly constant) down-count value to the Timer
Reload Registers (RLDR0L and RLDR0H, or RLDR1L and RLDR1H).
3. Read the Timer Control Register (TCR),
4. Set the appropriate Timer Downcount Enable bit (TDE0 or TDE1) to 1.
5. Set or clear the corresponding Timer Interrupt Enable bit (TIE0 or TIE1)
depending on whether an interrupt is desired when the count is decremented to
0, and
6. Write the result value back to the TCR.
The read-modify-write procedure of steps 3-6 ensures that starting one PRT does
not affect the operation of the other. Applications that only use one PRT can
simply write the desired value to the TCR instead.
5VQRRKPIꢁCꢁ246
To stop a running PRT:
1. Read the TCR.
2. Clear the PRT’s TDE bit, and
3. Write the result value back to the TCR.
A PRT may be stopped because its timing function is no longer needed, or before
rewriting the RLDR value as described in the next section.
246ꢁ1RGTCVKQP
While a PRT is running, it decrements the down-counter every 20 PHIclocks.
When it counts down to 0, a PRT automatically performs the following actions:
1. Reloads the TMDR from the RLDR
2. Sets the TIE bit in the TCR to 1
3. Requests an interrupt if the TIE bit in the TCR is 1.
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After reading a TIF bit as 1in the TCR, software can clear it by reading either half
of that PRT’s TMDR. However, reading a TMDR, without first reading a TIF bit
as 1in the TCR, does not clear the TIF bit.
Software can read a down-counter, from TMDR0L and TMDR0H or TMDR1L
and TMDR1H at any time. The PRTs ensure that the two 8-bit values read by IN0
instructions are consistent, provided that software reads TMDR0L or TMDR1L
first. Reading one of these registers captures the more significant byte of the
down-counter in a separate 8-bit latch, from which the value is provided when
software subsequently reads TMDR0H or TMDR1H.
9TKVKPIꢁCPꢁ4.&4ꢆꢁSoftware can write a new reload value to RLDR0L and
RLDR0H or RLDR1L and RLDR1H, while a PRT is running, but there is no hard-
ware safeguard against the down-counter decrementing to 0between the two 8-bit
OUT0instructions needed to write the new reload value. If this occurs, the value
loaded into the down-counter may be incorrect.
If a new reload value is written in response to a PRT interrupt or to detecting a TIF
bit 1 in the TCR, and the count values are large enough to prevent this problem,
software can write the RLDR. Otherwise software must perform the following
steps to load an RLDR:
1. Reads the Timer Control Register (TCR).
2. Clears the PRT’s TDE bit.
3. Writes the result back to the TCR.
4. Writes the PRT’s RLDR (L and H, in either order).
5. Writes the value from step 1 (with the TDE bit 1) back to the TCR.
*CPFNKPIꢁ246ꢁ+PVGTTWRVU
When the conditions noted in “On-Chip Interrupt Handling” on page 19 are met
with respect to an interrupt request from a PRT, the processor reads the address of
the interrupt service routine from memory at address (I : IL : 4) for PRT0, or
(I : IL : 6) for PRT1. The PRT ISR performs the following actions:
1. Save as many registers of the interrupted process as it may use (worst case), by
means of PUSH, EXAF,AF’, and/or EXXinstructions.
2. Read the TCR, verifying that the TIF bit is set to 1.
3. Read the PRT’s TMDRL register to clear the TIF bit, preventing another
interrupt for the same zero-count.
4. If the RLDR value must be changed for the next down count sequence, the ISR
proceeds as described in “Writing an RLDR”, described previously.
5. Next, the ISR performs any necessary time-periodic functions in service to the
overall application.
6. When these timer functions are completed, the ISR restores the saved registers,
and returns to the interrupt process using EIand RETinstructions.
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
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If both PRTs are active and both are started and stopped, either at interrupt or
mainline level, the mainline code that reads, modifies, and writes the TCR must
protect against conflicts with an ISR for the other PRT. It surrounds the read-
modify-write sequence (steps 1–5 in “Writing an RLDR” on page 45) with DIand
EIinstructions.
246UꢁCPFꢁ4GUGVꢆꢁBoth TMDRs and both RLDRs reset to FFFFH, and the TCR
resets to all 0s, which inhibits PRT operation until a TDE bit is set.
4'#.ꢁ6+/'ꢁ%.1%-ꢁꢎ46%ꢏ
The Real Time Clock module operates like a watch chip, maintaining readable
registers ranging from seconds to centuries. An application that uses the RTC
must provide it with one of several specific time bases. A 32.768 crystal can be
connected to the LFXTALand LFEXTALpins, or a 50- or 60-Hz clock derived
from AC power can be connected to the PC0pin.
The RTC also includes an alarm function. Programmable registers containing
alarm seconds, minutes, and hours are continually compared to the corresponding
clock values. When all three registers match, the RTC can interrupt the processor.
If a Snooze function is required, it must be implemented by software.
The section titled, “Real Time Clock (RTC) Registers” on page 118, describes the
registers in the RTC. All of them are read/write. After software sets these regis-
ters, the RTC maintains the time provided there is Power On the VDD pins. Reset
has no effect on the RTC.
0QVGꢐ The Register Write Enable bit must be set as described on page 25, before any of
the RTC registers can be written.
%QPHKIWTKPIꢁVJGꢁ46%
First, software must select the time base for the RTC: a 32.768 KHz crystal on the
EXTALand LFEXTALpins, or a 50- or 60-Hz clock on the PC0pin, in bits 4–3 of
the RTC Command/Status register. The RTC divides the selected base clock by
32768, 50, or 60 to produce a 1 Hz clock that increments the Seconds register.
5GVVKPIꢁVJGꢁ6KOGꢁCPFꢁ&CVGꢆꢁ
The first step in setting the time and date is to determine them, from a user inter-
face or a network or serial link. Next software must convert the time and date to
the BCD format used in the RTC registers. The RTC does not include any hard-
ware support for deriving the day of the week from the other values. Finally, soft-
ware writes these values to the RTC Seconds, Minutes, Hours, Day of the Week,
Date, Month, Year, and Century registers.
0QVGꢐ the RTC registers increment in Binary Coded Decimal (BCD) format, and values
written to these registers must be encoded in this format. In most of the RTC registers, bits
7-4 contains a tens digit and bits 3-0 contain a units digit. Neither field may contain any of
the values 1010Bthrough 1111B. Most of the RTC registers have further restrictions
on the range of values that can be written to them, which are noted in “RTC Increment-
ing”, later.
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9TKVKPIꢁVJGꢁ46%ꢁTGIKUVGTUꢆꢁWhile writing a new time and date into the RTC
registers, there is a slight chance that a 1 Hz clock edge that causes a rollover will
occur between writes, so that the registers contain the wrong value. To protect
against this possibility:
1. Write all of the registers starting with the Seconds register.
2. Read the Seconds register.
If the value from step 2 is less than the value written to the Seconds register in step
1, a rollover occurred and the RTC registers may be wrong: Return to step 1.
4GCFKPIꢁVJGꢁ46%ꢁTGIKUVGTUꢆꢁWhen reading the RTC registers, there is a slight
chance that a 1Hz clock edge that causes a rollover will fall between reads, so that
the set of values read is wrong. To protect against this possibility:
3. Read all the registers, starting with the Seconds register,
4. Read the Seconds register again,
If the Seconds value from step 2 is less than the Seconds value from step 1, a roll-
over occurred: return to step 1.
46%ꢁ1RGTCVKQP
46%ꢁ+PETGOGPVKPIꢆꢁThis section describes the functions of clocks and calendars.
1. The Seconds register rolls over from 59 to 0, at which time the Minutes
registers is incremented.
2. The Minutes register rolls over from 59 to 0, at which time the Hours register
is incremented.
3. The Hours register rolls over from 23 to 0, at which time the Day of the Week
and Date registers are incremented. The RTC is a 24-hour clock.
4. The Day of the Week register rolls over from 7 to 1.
5. The contents of the Month, Year, and Century registers determine how the
Date register rolls over. When the Date register rolls over, the Month register
is incremented.
–
If the Month is 1, 3, 5, 7, 8, 10, or 12, the Date register rolls over from 31
to 1.
–
–
If the Month is 4, 6, 9, or 11, the Date register rolls over from 30 to 1.
If the Month is 2 and the Year and Century registers indicate a leap year,
the Date register rolls over from 29 to 1. Otherwise it rolls over from 28
to 1.
6. The Month Register rolls over from 12 to 1, at which time the Year register is
incremented.
7. The Year register rolls over from 99 to 0, at which time the Century register is
incremented.
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
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5GVVKPIꢁCPFꢁ2QNNKPIꢁVJGꢁ#NCTOꢆꢁTo set an alarm, write the Alarm Seconds, Alarm
Minutes, and Alarm Hours registers. The RTC continually compares these values
with those in the Seconds, Minutes, and Hours registers, and sets the Alarm bit
(bit 7) in the RTC Control/Status register (RTCCS) whenever all of these registers
are equal. If the RTC Alarm interrupt is disabled, software can poll bit 7 in the
RTCCS periodically to detect an Alarm.
*CPFNKPIꢁCPꢁ#NCTOꢁ+PVGTTWRVꢆꢁIf an interrupt is desired when the RTC sets the
Alarm bit, sets bit 6 (IE) in the RTC Control/Status register after writing the three
Alarm registers. Thereafter, when the Alarm bit (RTCCS7) is 1 and the conditions
in “On-Chip Interrupt Handling” on page 19 have been met with respect to the
RTC request, the Z80S183 responds by fetching the RTC interrupt service routine
(ISR) address from memory at address (I : IL : 26). Most of this ISR is applica-
tion-dependent, but as a minimum the ISR performs the following actions:
1. Save as many registers of the interrupted process as it may use, using PUSH,
EXAF, AF’, and/or EXXinstructions.
2. Check that the Alarm bit (bit 7) of the RTC Control/Status (RTCCS) register
is 1. If bit 7 is 0, the ISR may log this unknown interrupt, before restoring the
saved register values and returning to the interrupted process using EI and
RETinstructions.
If a future alarm at a different time is desired, the ISR must reprogram the Alarm
registers with that time. If no future Alarm is required, clear the IEbit in the value
read in step 2. If an Alarm is required at the same time tomorrow, increment the
Alarm time by 1 second, and write that value to the Alarm registers. This action
prevents a continuing match from setting the Alarm bit immediately.
3. Clear bit 7 in the value read in step 2, and write it back to RTCCS.
4. Restore the saved registers after application-dependent processing is complete,
and return to the interrupted process by means of EIand RETinstructions.
If an Alarm at the same time tomorrow was needed in step 2, when the next RTC
Alarm interrupt occurs (1 second later) repeat steps 1–4, decrementing the Alarm
registers back to their original value.
&+)+6#.ꢇ#0#.1)ꢁ%108'46'4ꢁꢎ&#%ꢏ
The Digital-to-Analog Converter converts 10-bit digital values to analog voltages
using a 10-stage resistor ladder. The DAC output is protected against latch-up and
can drive output loads.
The AVDDand AGNDpins provide the analog power for both the ADC and DAC
modules. To achieve the specified accuracy, the voltages must be within the spec-
ified tolerances of V and VSS respectively. For maximum accuracy, isolate and
DD
filter AVDDand AGNDfrom power supply noise.
“Digital to Analog Converter (DAC) Registers” on page 124, describes the I/O
registers associated with the D/A Converter. These registers include a Data
register containing the eight most significant bits of the digital value, and a
ꢉꢇ
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Control register (DACCR) which holds the two least significant bits plus configu-
ration and enable bits.
4GHGTGPEGꢁ8QNVCIGꢁ5GNGEVKQP
Bits 5–4 of the Control register select the reference voltage that is multiplied by
the binary fraction represented by the digital value to be converted to obtain the
voltage produced on the AOUTpin.
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Notes:
1. The DAC and A/D Converter share the PA0/VREFpin as an external ana-
log reference voltage.
2. The reference voltage selected by bits 5–4 must be less than AV and
DD
VDD.
'ZCORNGꢐꢁIf the 10-bit binary value in the Data and Control registers is 1000000000B,
and bits 5–4 are 00B, the voltage on the AOUTpin is 2.1 volts.
2TQITCOOKPIꢁVJGꢁ&#%ꢆꢁTo convert a 10-bit value to an analog voltage:
1. Write the eight most significant bits of the value to the DAC data register.
2. Write the two least significant bits of the value to bits 7–6 of the DAC Control
register, along with the reference voltage selection in bits 5–4, and a 1in bit 2
to enable analog voltage drive on the AOUTpin.
The voltage on AOUTsettles to the programmed value within 1 microsecond after
step 2.
%QPXGTUKQPꢁ6KOGꢁ9CHHNGꢆꢁAt the time this document was written, there is concern
about the DAC conversion time in one case. If the selected reference voltage,
times the fraction represented by the digital value, is within 0.5 volts of AV and
DD
V
, settling may take longer than 1 microsecond. This issue will be character-
DD
ized and clarified when silicon is available.
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The Analog-to-Digital Converter is a 10-bit successive–approximation converter
with 8 input pins. Conversion time is 64 PHI clocks, or about 1.92 microseconds
at 33 MHz. Software determines the completion of a conversion using an interrupt
or by polling.
The AV and A
pins provide the analog power for both the ADC and DAC
GND
DD
modules. To achieve the specified accuracy, the voltages on these pins must be
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within the specified tolerances from V and GNDrespectively. For maximum
DD
accuracy, isolate and filter AV and A
from power supply noise.
GND
DD
Though the ADC can operate with small analog reference voltages, noise and
offset are independent of the reference. Accuracy is maximized for reference volt-
ages close to AV and V
.
DD
DD
“Analog to Digital Converter (ADC) Registers” on page 126, describes the I/O
registers associated with the A/D Converter. They include two Control registers,
ADCC0 and ADCC1, and a Data register from which the software can read the
most significant eight bits of the digital value when a conversion is complete.
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The ADC can divide the voltage on any of the pins in Port D by the reference
voltage, to produce a 10-bit binary fraction. This fraction can be read from the
Data register and ADCC1, when the conversion is complete. Bits 2–0 of ADCC1
select the port pin for each conversion:
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Bits 1–0 of ADCC0 select the reference voltage by which the voltage on the
selected channel is divided, to produce the 10-bit binary fraction.
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Notes:
1. The D/A Converter and ADC share the PA0/VREFpin as an external ana-
log reference voltage.
2. The reference voltage selected by bits 1–0 must be less than AV and
DD
V
.
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To convert the voltage on one of the Port D pins to a 10-bit binary fraction:
1. Write ADCC0 bits 1–0 to select the desired reference voltage, with a 1in bit
2 to enable the A/D converter.
2. Write ADCC1 bits 2–0 to select the desired Port D pin, with a 1in bit 3 to start
the conversion. Include a 1in bit 5 if an interrupt at the end of the conversion
is desired. If so, refer to the next section, “Handling an ADC Interrupt”.
3. Read ADCC1 until bit 4 is 1, indicating polled operation. This operation
indicates that the conversion is complete. Because the conversion always takes
64 clocks, 21 NOP instructions can be substituted for reading ADCC1, but
NOPsrequire more memory.
4. Read the ADC Data register to obtain the eight most significant bits of the
result. If all 10 bits of the result are needed, read ADCC1 (bits 7–6 are the two
least significant bits).
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An interrupt takes at least 18 PHIclocks, plus the overhead of saving and
restoring registers, reenabling interrupts, and returning to the interrupted process.
Because a complete ADC conversion takes 64 clocks, many Z8S183 applications
use polling rather than ADC interrupts, for A/D conversions initiated by the
processor.
A/D interrupts are more useful for A/D conversions initiated by the PIOS module,
described in “Programmable I/O Sequencer (PIOS)” on page 52.
Regardless of the initiator, when the conditions noted in “On-Chip Interrupt
Handling” on page 19 are met with respect to an ADC interrupt request, the
Z80S183 fetches the address of the ADC interrupt service routine (ISR) from
memory at (I : IL : 24). This ISR is application-dependent, but at a minimum it
must:
1. Save as many registers of the interrupted process as it may use, using of PUSH,
EXAF,AF’, and/or EXXinstructions.
2. Read the Data register into H and ADCC1 into L if all 10 bits are required. If
only the most significant eight bits of the result are required, the ISR reads
ADCC1 into A to clear the conversion complete flag and prevent further
interrupts for the same conversion, and then read the Data register into A.
3. Process the resulting value. This step is application-dependent.
4. Start another conversion, if desired, as in steps 1–2 of “Programming the
ADC”.
5. Restore the registers using POP, EXAF, AF’and/or EXXinstructions.
6. Return to the interrupted process using EIand RETinstructions.
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During the first 3 PHI clocks of the 64 required for a complete conversion, the
ADC samples the voltage on the selected pin. To ensure the accuracy of the
conversion, the voltage must remain constant during this time. During the last 61
clocks of the conversion, the pin voltage can change without affecting the result.
4GUVCTVKPIꢁ%QPXGTUKQP
An A/D conversion can be started at any time. If a conversion is in progress and a
new start command is written to ADCC1, the conversion in progress is aborted
and a new conversion is initiated. Software must not change bits 2–0 of ADCC1
while a conversion is in progress, unless the write that changes these bits also
includes a 1in bit 3 to start a new conversion.
5CXKPIꢁ2QYGT
When the ADC is not needed, a small amount of power can be saved by clearing
bit 2 of ASCC0, shutting down the ADC.
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The Programmable Input/Output Sequencer can be used to create multiple
complex digital waveforms and trigger A/D and D/A conversions without
processor intervention. In addition the PIOS can generate processor interrupts at
selected points during its operation.
The last 256 bytes of on-chip RAM can be read by the PIOS and can be read and
written by the processor. Depending on the value of bit 5 in the System Control
Register, the processor may locate these bytes at addresses FFF00–FFFFFHor
xFF00–xFFFFH, that is, with or without decoding A19–16.
To the PIOS, this memory area is organized as 64 4-byte entries, each containing:
•
•
•
•
A 14- or 16-bit delay value
A 2-bit entry type
An 8- or 10-bit data value
A 6-bit address of the next entry
When the PIOS fetches an entry from RAM, it stops processing if the next-
address field in the entry is zero. Otherwise it loads the entry into internal registers
and begins counting down the delay value. When the PIOS has counted the delay
down to zero, it performs the action specified by the rest of the entry. The PIOS
then fetches a new entry using the Next Address value as A7–2 of the memory
address.
The section, “Programmable Input/Output Sequencer (PIOS) Registers” on
page 129, details the I/O registers in the PIOS, which include:
•
A Control register that software can use to configure the PIOS
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•
•
An Address/Type register into which the PIOS fetches control information
from each entry
Timer Low and High registers, into which the PIOS fetches a 16-bit delay val-
ue from each entry, and then counts it down to zero.
%QPHKIWTKPIꢁVJGꢁ2+15
Bits 1–0 of the Control register select the clock used to count down the delay
value in each PIOS entry, among PHI, PHI/256, PHI/1024, or PHI/4096.
Software must not change these bits while the PIOS is running. To ensure an accu-
rate delay in the first entry, software set bits 1–0 to the desired value before setting
bit 7 to enable PIOS operation.
Bit 6 of the Control register enables or disables interrupts from the PIOS, if and
when it encounters interrupt entries.
Other registers that affect the PIOS include:
•
•
•
The AFSC (“Port C Alternate Function Select (AFSC)” on page 35) controls
which Port C pins are controlled by the PIOS
The DDRC and OCRC (“Data Direction Registers and Output Control Regis-
ters” on page 34) control Port C pin functions
The System Configuration Register (SCR, page 79) controls whether the proces-
sor as well as the PIOS can access on-chip RAM, and if so, at what addresses.
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Bit 6 of the System Control Register must be 1 to allow the processor to set up
PIOS entries in on-chip RAM. Each entry includes 4 bytes and starts at an address
that is a multiple of 4.
When the processor first enables the PIOS, the PIOS always processes the entry at
xFF00–3Hor FFF00–3Hfirst.
If a new PIOS sequence is needed in the future, software can build the next
sequence in on-chip RAM while the PIOS is still running its current sequence,
provided that the total length of both sequences is 64 entries or less.
To accomplish this task, software builds the next sequence in those parts of the
PIOS RAM that are not used by the current sequence. Next, software can store the
first entry of the next sequence at location xFF00–3Hor FFF00–3H. When the
PIOS has completed its current sequence, software can start the next sequence as
described in “Starting and Polling the PIOS” on page 55.
&KIKVCNꢁ&CVCꢁ1WVRWVꢁ'PVTKGUꢆꢁFigure 9 illustrates the format of a PIOS Digital
Data Output entry. The first two bytes contain a delay value, in the units selected
by bits 1–0 of the PIOS Control register. As with all Z80/180 multi-byte binary
values, the least significant byte is stored first, at the lower address. An all-0 delay
value indicates 65,536 clocks. The third byte holds a value that the PIOS is to
output to Port C after the specified delay. Bits 7–2 of the 4th and last byte hold a
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non-zero address of the next entry, with 00in bits 1–0 to identify this entry as a
Digital Data entry.
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Data Output entry. The first byte, and bits 5–0 of its second byte, contain a delay
value in the units selected by bits 1–0 of the PIOS Control register. As with all
Z80/180 multibyte binary values, the least significant byte is stored first, at the
lower address. An all- zero delay value indicates 65,536 clocks. The third byte
holds bits 9-2, and bits 7-6 of the 2nd byte contain bits 1-0, of a 10-bit value that
the PIOS is to output to the D/A Converter after the specified delay. Bits 7-2 of the
4th and last byte hold a non-zero address of the next entry, with 10in bits 1-0
identifying this entry as an Analog Data Output entry.
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#PCNQIꢁ&CVCꢁ+PRWVꢁ'PVTKGUꢆꢁFigure 11 describes the format of a PIOS Analog
Data Input entry. The first two bytes contain a delay value, in the units selected by
bits 1-0 of the PIOS Control register. As with all Z80/180 multibyte binary values,
the least significant byte is stored first, at the lower address. An all-0 delay value
indicates 65,536 clocks. After the specified delay, bits 2-0 of the third byte hold a
channel (port D pin) number, the voltage on which is to be converted to a digital
value. Bits 7-2 of the fourth byte contain the non-zero address of the next entry,
and 01 in bits 1-0 identify this entry as an Analog Data Input entry.
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first two bytes contain a delay value, in the units selected by bits 1-0 of the PIOS
Control register. As with all Z80/180 multibyte binary values, the least significant
byte is stored first, at the lower address. An all-0 delay value indicates 65,536
clocks. The third byte of an Interrupt entry is not used. Bits 7-2 of the fourth byte
hold the non-zero address of the next entry, with 11in bits 1-0 identifying this
entry as an Interrupt entry.
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the end of a PIOS sequence. This type of entry is 0in bits 7-2 of its fourth byte.
The other bits in the entry can be any value. When the PIOS fetches such an entry,
it stops processing immediately, clearing bit 7 of its Control register.
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After software has built a complete PIOS sequence in PIOS RAM, including the
first entry in addresses xFF00-3Hor FFF00-3H, and the PIOS has completed
any previous sequence, software proceeds as follows:
1. If a change is required to the clock selection, write the new value to the Control
register as a separate step. This action ensures accuracy of the delay associated
with the first entry.
2. Write a 1to bit 7 of the Control register, maintaining the prior clock selection
in bits 1-0. If the sequence contains one or more Interrupt entries, enable PIOS
interrupts by writing a 1in bit 6 of this value.
3. The PIOS fetches all bits of each entry simultaneously. While the PIOS runs,
the software can track its progress through the sequence by reading the PIOS
Address/Type register.
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4. If the Next Address field of an entry is non-zero, the PIOS counts down the
delay value specified in the first two bytes, using the clock selected by bits 1-
0 of the Control register.
0QVGꢐ For a D/A entry, the PIOS automatically loads zeroes into the two most significant
bits of the delay counter. D/A entries are limited to a 16,383 clock delay, or 65,536 for an
all-zero value.
5. After the PIOS has counted the delay value down to zero, it performs the action
specified by bits 1-0 of the last byte of the entry:
–
–
–
–
Writes an 8-bit value to Port C,
Writes a 10-bit value to the D/A converter,
Starts an A/D conversion on a particular channel, or
Requests an interrupt.
6. Software can stop PIOS operation at any time, by clearing bit 7 of the Control
register. Otherwise, when the PIOS reaches an entry with 0in its Next Address
field, it clears bit 7 of the Control register and stops. Software polls the Control
register to detect when this occurs, or the last active entry in the sequence can
be an interrupt entry.
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If bit 6 of the PIOS Control register is 1and the PIOS fetches an Interrupt entry, it
requests an interrupt. When the conditions noted in “On-Chip Interrupts” on
page 18 have been met for this request, the processor fetches the address of the
PIOS interrupt service routine from memory at address (I : IL : 18) The ISR
performs the following operations:
1. Save as many registers of the interrupted process as it may use (worst case),
using PUSH, EXAF, AF’, and/or EXXinstructions.
2. Read the PIOS Status register and verify that bit 5 (Interrupt Pending), is 1. If
not, the ISR can store logging information in memory if desired, before
restoring the registers and using EI and RET instructions to return to the
interrupted process.
3. Clear bit 5 if IP is 1, in the value read in step 2, and write the result back to the
Control register. This action clears the IP bit and prevents further interrupts for
the same PIOS event.
4. Read the Address/Type register, if there is more than one Interrupt entry in the
PIOS sequence, read the Address/Type register to determine which entry
caused this interrupt.
5. Reads ADC Control Register 1 and checks the conversion complete bit if this
interrupt follows the start of an A/D conversion by the PIOS. Assuming that
the delay in the interrupt entry has guaranteed that the conversion is complete,
read the result value from the ADC Result register and, if desired, the two least
significant bits from Control Register 1.
0QVGꢐ Software can use either an A/D interrupt or a PIOS interrupt to signal the comple-
tion of an A/D conversion initiated by the PIOS.
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6. Other processing is application-dependent. If the interrupt marks the end of a
sequence, and another sequence must be run immediately, the ISR can start
that sequence as described above.
7. Restore the saved registers, then use EI and RET instructions to reenable
interrupts and return to the interrupted process.
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The ASCIs are asynchronous full-duplex UARTs with the following features:
7- or 8-bit data
Odd, even, or no parity
•
•
•
•
•
•
•
•
•
•
One or two Tx Stop bits
Checking for Parity, Framing, and Overrun errors
Break Generation and Detection
Choice of two Baud Rate Generators (BRGs)
Rx and Tx interrupts
DCDand CTSpins on ASCI0
Operation with the on-chip DMA channels
A MULTIPROCESSOR mode with an extra bit designating address vs. data
characters
The registers associated with the ASCIs are described in section “Async Serial
Communications Interface (ASCI) Registers” on page 131. Control registers A
and B (CNTLA0, CNTLA1, CNTLB0, and CNTLB1) and the Extension Control
registers (ASEXT0, ASEXT1) are typically written one time each, to configure an
ASCI. The Status registers (STAT0 and STAT1) indicate the current state of each
ASCI’s Receiver and Transmitter. Under control of this status, software can write
bytes to be transmitted to the Transmit Data Registers (TDR0 and TDR1), and
read received bytes from the Receiver Data Registers (RDR0 and RDR1).
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Each ASCI uses the same clock for both transmitting and receiving. Because the
Z80S183 does not include CKApins for either channel, clocking for each ASCI
must be derived from one of its two baud rate generators (BRG). Furthermore, bits
2-0 of each CNTLB register must not be left 111, as they are after a reset.
To use the older version of the BRG, which is compatible with the original ZiLOG
Z80180:
•
Clear bit 3 (BRG Mode) of the Extension Control register, to select the old
BRG.
•
Write bit 5 (PS) and bits 2-0 (SS) in the CNTLB register to select the value by
which the old BRG divides the PHI clock to obtain the Basic Clock, as de-
scribed in Table 14.
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To use the newer BRG, which is compatible with the ZiLOG SCC family:
•
•
Set bit 3 (BRG mode) of the Extension Control register, to select the new BRG.
Write a 16-bit time constant to the Time Constant Low and High registers. This
value is the factor by which the PHI is divided to produce the basic clock, di-
vided by 2, minus 2. The new BRG calculates the basic clock as:
basic clock = PHI / (2 (TC+2)
%NQEMꢁ/QFGꢆꢁSince neither ASCI has a clock pin on the Z80S183, the 1X ISOCH-
RONOUS mode that can be used on other 8018x family members, cannot be used
on the Z80S183, and bit 4 (X1 clock) in the Extension Control register must be 0.
If the DR bit (bit 3) in the CNTLB register is 0, the ASCI divides its basic clock
by 16 to obtain the serial bit rate. If DR is 1, the ASCI divides the basic clock by
64.
#U[PEꢁ6TCPUOKUUKQP
Figure 14 illustrates a single asynchronous character on the TXAor RXApin.
When a transmitter is disabled, or when it has completed sending all characters
that the software or a DMA channel has provided, the transmitter maintained a
High on the TxDpin. This state is also called 1 or Mark.
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When software or a DMA channel provides a character to an idle ASCI trans-
mitter:
1. It drives TXALow on the next falling edge of the basic clock, to begin a start
bit, and maintains TXALow for 16 or 64 basic clocks depending on the value
of DR.
2. It switches TXAto the state of the least significant bit (bit 0) of the character,
and holds that for 16 or 64 clocks.
3. It repeats step 2 for each next-more-significant bit of the character, through the
most significant bit (bit 6 or 7) of the character, and for a parity or MP bit if
one of these is enabled.
4. It drives TXAHigh (1, Mark) again for a stop bit, and maintains it High for at
least 16 or 64 clocks.
5. It continues this High of another 16 or 64 clocks if bit 0 of its CNTLA register
is 1to select two Tx stop bits.
The Tx character is now complete. If software or a DMA channel has provided
another character to send, the transmitter begins another Start bit as described
above. Otherwise, it maintains a High on TXAHigh until a character is provided.
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The Receiver has a more complex task. When it is first enabled, or after a char-
acter has been received the receiver samples the RXApin on the rising edge of
each basic clock.
1. If RXAis High it remains in this state of waiting for a Start bit.
2. If the receiver samples RXALow, it counts off half a bit time (8 basic clocks if
DR is 0, or 32 basic clocks if DR is 1) then samples RXAagain. If RXAis High,
the receiver rejects the transient Low state on RXAas not representing a Start
bit, and returns to step 1. The RXApin is sampled again.
3. If RXAis still Low after half a bit time, it validates the Start bit. The receiver
then counts off the number of basic clocks in a bit—16 if DR is 0, 64 if it is 1,
— and samples RXAfor the Least Significant data bit (bit 0). It continues this
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routine for each progressively significant data bit (through bit 6 or 7), and for
a Parity or MP bit if either is enabled.
Finally, the receiver counts off 16 or 64 more basic clocks and samples the first
Stop bit. If the receiver’s basic clock is close to the clock that the transmitter used
to send the character, this occurs near the middle of the first Stop bit. If there is no
noise or other error on the line, the receiver samples the Stop bit as High/1/Mark.
However, if the receiver’s and transmitter’s clocks were sufficiently different, or if
there is noise or an error on the line, the receiver samples the stop bit as Low/0/
Space. This latter situation is called a framing error. When a framing error
occurs, the receiver sets an error bit that accompanies the character through the
receiver FIFO. The receiver then sets the FE bit in the STAT register when the
character becomes the oldest one in the FIFO.
The received character is now complete, and the receiver returns to step 1 and
samples the line for a new Start bit.
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Combining the operation of the BRGs and the division by 16 or 64 performed by
the transmitter and receiver, where:
•
•
•
•
•
•
•
Serial rate is in bits/second
PHI is the system clock frequency
PS is the value written to bit 5 of CNTLB (0 or 1)
^ indicates exponentiation (2 to the power)
SS is the binary value of bits 2-0 of CNTLB (0 thru 6)
DR is bit 3 of CNTLB (0 or 1)
TC is the 16-bit value in the ASTCL and ASTCH registers:
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ꢈꢁQTꢁꢂꢁ&CVCꢁ$KVUꢆꢁIf bit 2 of CNTLA is 0, the transmitter sends, and the receiver
accumulates, 7 data bits per character. If CNTLA2 is 1, the transmitter sends, and
the receiver accumulates, 8 data bits per character.
2CTKV[ꢆꢁIf bit 1 of CNTLA is 1, the transmitter accumulates and sends a Parity bit
after the data bits, and the receiver samples and checks these bits. If CNTLA1 is
1, a 1in bit 4 of CNTLB selects odd parity and 0in bit 4 selects even parity. Odd
Parity means that a correct character includes an odd number of 1 bits, including
the Parity bit. Even Parity means that a correct character includes an even number
of 1bits.
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If the receiver samples the Parity bit in the incorrect state for a character, it sets an
error bit that accompanies the character through the receiver FIFO. The receiver
then sets the PE bit in the STAT register when the character becomes the oldest
one in the FIFO.
6TCPUOKVꢁ5VQRꢁ$KVUꢆꢁIf bit 0 of CNTLA is 0, the transmitter sends a minimum of
one Stop bit between characters. If CNTLA0 is 1, it sends at least two Stop bits
between characters. Selecting two Stop bits has been known to work around
timing mismatches between a transmitter and a receiver.
0QVGꢐ The ASCI receivers on the Z80S183 check only one Stop bit, regardless of bit 0 of
CNTLA. This is also true of ASCI receivers on other current 8018x family members, as
well as other UARTs, but on the original Z80180, the ASCIs actually checked two Stop
bits if CNTLA0 was 1.
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$TGCMꢁ%QPFKVKQPUꢆꢁBreak conditions date back to the early days of async commu-
nications using Teletypewriters, which were functionally half-duplex in that text
could only flow in one direction at a time.
If the operator of a receiving Teletype had a condition, or something to say, and
wanted to interrupt the data from the other machine, the operator could press a
Break key. Pressing this key drove the line to the 0/Space state for several char-
acter-times, which switched on a light at the other machine, and stopped its paper
tape reader if it had been in use.
A Break is still defined as at least two character times of consecutive zeroes on the
line. A receiver sees this as one or more all-0 characters with Framing errors.
Software can send a break by setting bit 0 of the Extension Control register.
Before doing this, software can ensure that any characters previously written to
the Transmit Data Register have been sent, by monitoring bit 0 of the Extension
Control register. The duration of a transmitted Break is under software control—
the Break is terminated by clearing the ASEXT bit to 0.
While receiving an all-zero character with a Framing error indicates a Break, bit 1
of the Extension Control register provides more specific break detection. When
the receiver detects an all-zero character with a framing error, it sets a Break status
bit that accompanies the character through the receiver FIFO. The receiver sets bit
1 in the ASEXT register to 1when such a character becomes the oldest one in the
FIFO.
After detecting a break, the receiver does not assemble any further characters until
the RXApin returns to High/1/Mark, signalling the end of the Break condition.
4Zꢁ1XGTTWPꢆꢁThe ASCIs in the Z80S183 contain 4-character Rx FIFOs between
the Rx Shift registers and Receive data registers. If a receiver receives a character
and there are already 4 characters in the FIFO, an overrun status bit is set that
accompanies the preceding character through the FIFO. The receiver then sets the
OVRN bit (bit 6 in the STAT register) to 1when that character becomes the oldest
in the FIFO.
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The receiver discards the character that triggers the overrun condition, and subse-
quent characters, until the last good character has come to the top of the FIFO so
that OVRNis 1, and software writes a 0to the EFR bit to clear OVRN.
4GEGKXGꢁ5VCVWUꢆꢁThere are four receive status bits in the STAT register and one in
the Extension Control register. RDRF, bit 7 of STAT, is 1 whenever there is at
least one received character in the Rx FIFO. RDRF is cleared:
•
When the software or a DMA channel has read all characters out of the Rx
FIFO
•
•
•
By a reset
In I/O STOP mode
On ASCI0, when the DCD0pin is autoenabled and is High.
FE, PE, and OVRNin the STAT register are 1when a character with a framing
error or parity error, or the last character before an Rx Overrun, comes to the top
of the receive FIFO. Similarly, bit 1 in the Extension Control register is 1when a
break character comes to the top of the FIFO.
Any of these bits remain 1even if the character associated with the condition is
read out of the receive FIFO. That is, these bits latch an error or exception condi-
tion. All four of these bits are cleared to 0 by reading CNTLA, clearing bit 3
(Error Flag Reset, or EFR) to 0, and writing the result back to CNTLA.
This action also allows the receiver to put subsequent characters into the receive
FIFO after an Overrun, and if the receiver is handled by a DMA channel, allows
the channel to service the receiver again.
/QFGOꢁ%QPVTQNꢇ5VCVWUꢆꢁThe only ASCI modem control or status signals on the
Z80S183 are DCD0 and CTS0. The state of the DCD0 pin can be read as bit 2 of
the STAT0 register, and that of CTS0 as bit 5 of CNTLB0. Both bits read as 1if
the pin is High/inactive.
Bit 6 in the Extension Control register controls whether DCD0 automatically
enables and disables the receiver. Bit 5 controls whether CTS0 automatically
enables and disables the transmitter.
In each case, if one of these ASEXT bits is 0, as it is after a reset, then a Low on
the pin allows the module to operate. However, while a High disables the module.
If one of these ASEXT bits is 1, software can read the state of the pin, but this
state does not affect the hardware.
When ASEXT0 bit 6 is 0, a High on DCD0 forces the status bits RDRF, PE, FE,
OVRN, and RxBreakto 0. If DCD0 goes Low thereafter, the next read of the
STAT register still contains a 1in bit 2 (DCD0). Subsequent reads of STAT indi-
cate current status.
When ASEXT0 bit 5 is 0, a High on CTS0 clears the TDRE bit in STAT. This
action prevents software or a DMA channel from putting further Tx data into
TDR. As many as three characters (one from the Tx shift register, two from the
2-stage Tx FIFO) can appear on TDA0 after CTS0goes High.
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On the Z80S183, data can be transferred to or from either ASCI by either DMA
channel. Setup for these operations is covered in the following ASCI and DMA
topics:
“Starting a Transmitter”, later on this page,
“Starting a Receiver” on page 63,
“Handling ASCI Interrupts” on page 64, and
“Setting Up a DMA Transfer” on page 40.
A DMA channel used with an ASCI transmitter must be programmed to use the
appropriate TDRE flag as its DMA request, and must be set up for edge-sensitive
DMA request.
A DMA channel used with an ASCI receiver must be programmed to use the
appropriate RDRF flag as its DMA request, and can be used in either edge- or
level-sensitive mode. In this application, software sets both the RIE bit in the
STAT register, and bit 7 of the Extension Control register, enabling ASCI receive
interrupts in the event of errors, but not for every received character.
0QVGꢐ The signal that an ASCI receiver provides as a Request to a DMA channel, is not
simply RDRF but rather (RDRF and not PE and not FE and not OVRN and not RxBreak).
DMA operation will be suspended if any of these errors or exceptional conditions occurs.
This operation is performed so that software can determine the point in the receive data
stream at which the error or condition occurred.
2TQITCOOKPIꢁ6GEJPKSWGU
5VCTVKPIꢁCꢁ6TCPUOKVVGTꢆꢁA Software can enable a transmitter at the same time as
its associated receiver, or separately, as follows:
1. Write the CNTLB register to set the clocking and basic options.
2. Write the Extension Control register to select the BRG mode and, on ASCI0,
the mode of the CTS0pin.
3. Set bit 0 (TIE) in the STAT register to enable transmit interrupts, otherwise,
clear it.
4. Set bit 5 to 1of CNTLA to enable the transmitter.
The TDRE flag is set immediately. If transmit interrupts were enabled in step 3, an
interrupt occurs immediately.
0QVGꢐ If a DMA channel is to provide data to the transmitter, software can set it up when-
ever transmit data is available, including selecting TDRE as the DMA Request. Edge-sen-
sitivity is required on the DMA request for transmit/output devices. If TDRE is set before
the DMA channel is started, device software sets up the DMA to not include the first Tx
character, and then write first character to the TDR, to initialize the ASCI-DMA hand-
shake.
5VCTVKPIꢁCꢁ4GEGKXGTꢆꢁA Software can enable a receiver at the same time as its
associated transmitter, or separately, as follows:
1. Write the CNTLB register to set the clocking and basic options.
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2. Write the Extension Control register to select the BRG mode and, on ASCI0,
the mode of the DCD0pin. If the receiver is to be handled by a DMA channel,
set bit 7 of the Extension Control register to 1 to block the RDRF flag from
requesting a receive interrupt.
3. Set bit 3 (RIE) in STAT to 1if receive interrupts are desired, otherwise clear it.
4. Set up the DMA channel if the receiver is to be handled by a DMA channel).
Select the channel, including selecting RDRF as the DMA Request signal.
5. Set the bit 6 in CNTLA to enable the receiver.
RDRF is 1when there is data in the Rx FIFO. If RDRF interrupts are enabled, an
interrupt occurs at that time.
2QNNGFꢁ6TCPUOKUUKQPꢆꢁAfter starting a transmitter without interrupts enabled,
while there is data to send:
1. Read the STAT register (preferably more often than once per character-time)
until bit 1 (TDRE) is 1.
2. Write the next character to be transmitted to the TDR. If there is more data to
transmit, return to step 1.
2QNNGFꢁ4GEGRVKQPꢆꢁAfter starting a receiver without interrupt enabled:
1. Read the STAT register, at least once per character time, until it detects bit 7
(RDRF).
2. Read a received character from the RDR.
3. Process process the received character, then return to step 1.
*CPFNKPIꢁ#5%+ꢁ+PVGTTWRVUꢆꢁA 1 in bit 0 (TIE) of an ASCI’s STAT register enables
transmit interrupts, and a 1 in bit 3 (RIE) enables receive interrupts. If any of
following are true:
•
•
•
•
TIE and TDRE are both 1
RIE is 1and any of OVRN, PE, FE, or RxBreak(ASEXT bit 1) are 1
RIE is 1, bit 7 of the Extension Control register is 0, and RDRF is 1
RIE is 1, bit 6 in the Extension Control register is 0, and the DCD0pin is High
for ASCI0
then an ASCI requests an interrupt from the processor. When the conditions listed
in “On-Chip Interrupt Handling” on page 19 are met with respect to this request,
the processor fetches the address of the interrupt service routine (ISR) from
(I : IL : 14) for ASCI0, or from (I : IL : 16) for ASCI1.
An ASCI ISR that handles both kinds of interrupts must:
1. Save as many registers as it may use, by means of PUSH, EXEXAF,AF’, and/
or EXXinstructions.
2. Read the STAT register for this ASCI.
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3. If TIE and TDRE in STAT are both 1:
a. If another Transmit character is available, write it to the TDR.
b. If not, clear the TIE bit until another Tx character is available.
4. If RIE in STAT is 1and any of OVRN, PE, FE, or RxBreak(ASEXT bit 1)
are 1:
a. If bit 7 of the Extension Control register is 1, indicating that a DMA
channel is handling receive data, read the DSTAT register, clear the DE
and DWE bits for that DMA channel, and write the result back to DSTAT.
b. Read the CNTLA register, clear bit 3 (EFR) to 0and write the result back
to CNTLA
c. Read the associated character from the RDR
d. For PEor FEconditions, applications can discard the character, replace it
with a standard error character, or treat it like other characters.
e. For an OVRN condition (without any other error), most applications
process this last good character normally, as in step 5. An application may
then post an overrun occurred here notification in the received-data
stream.
f. For Break, most applications discard the all-0 character. An application
may post a break occurred here notification in the received-data stream.
The receiver does not assemble more all-0 characters, but waits for RDA
to go High before searching for a new Start bit.
5. If no errors were found in step 4, but RIE is 1, bit 7 of the Extension Control
register is 0, and RDRF is 1, read the next received character from the RDR.
Process it, of which the simplest case is storing it at the next memory location
in a buffer.
6. If for ASCI0, RIE is 1, bit 6 in the Extension Control register is 0, and bit 2 of
STAT is 1, carrier has been lost, and the ASCI receiver does nothing until the
carrier returns. In this case, either clear RIE or set bit 6 in the Extension
Control register, to prevent further interrupts because DCD0is High.
7. Optionally, at this point software can read STAT again, and return to step 3 if
RIE and RDRF are both 1, or TIE and TDRE are both 1. This option saves on
interrupt overhead.)
8. If the ISR disabled the receive DMA channel in step 4a, it restarts the channel.
9. Finally, the ISR must restore the saved registers, and return to the interrupted
process by means of EIand RETinstructions.
/WNVKRTQEGUUQTꢁ/QFG
In this mode, the transmitter sends, and the receiver expects, an extra bit between
the data and stop bits, that differentiates address from data characters. Other
manufacturers’ devices have a similar mode called NINE-BIT mode. To enable
this mode for both the transmitter and receiver, set bit 6 of the CNTLB register as
part of initializing the ASCI.
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0QVGꢐ MULTIPROCESSOR mode cannot be used with parity generation and checking.
In MULTIPROCESSOR mode, data is grouped into frames or messages, each
preceded by an address character, which differs from data characters in that its
extra bit is 1.
To send a frame:
1. Wait, if necessary, for the TDRE bit (bit 1 of the STAT register) to be 1,
indicating that a new Tx character can be written to the TDR. The next two
steps can be performed in an ASCI Interrupt Service Routine.
2. Read the CNTLB register, set bits 7-6 to 11, and write the result back to
CNTLB. This action sets up the transmitter to send the first character of the
frame with the extra bit 1.
3. Write the address value for the intended destination device to the TDR.
4. For each data character in the frame, again wait, if necessary, for the TDRE bit
(bit 1 of the STAT register) to be 1. The following two steps can be performed
in an ASCI ISR.
5. Read CNTLB, clear bit 7, and write the result back. These actions cause the
transmitter to send the next character with the extra bit 0.
6. Write the next data character to the TDR. If there are more characters in the
frame, return to Step 4.
If bit 6 of CNTLB is 1, to receive a frame in MULTIPROCESSOR mode:
1. Read CNTLA, set bit 7, and write the result back to CNTLA. This process
conditions the receiver to ignore data characters, that contain a 0in the extra
bit.
2. Wait for the RDRF bit in the STAT register to be 1. The following steps can
be done in an ASCI ISR.
3. Read CNTLA and verify that bit 3 is 1, namely that the next available character
is an address character. If not, read the RDR, discard the data character, and
return to step 2.
4. Read the RDR and check whether the value obtained indicates a frame destined
for this processor (there may be one or more unique addresses for this node,
plus a broadcast and/or group address) If not, discard the character and return
to step 2. The hardware ignores the data characters in the frame.
5. Optionally, store the address character in memory. (The following steps may
vary depending on the address.)
6. Read CNTLA, clear bit 7, and write the result back to CNTLA. This process
conditions the receiver to assemble the following data characters.
7. For each data character in the frame, wait for the RDRF bit in the STAT
register to be 1. The following steps can be processed in an ASCI interrupt
service routine.
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8. Read the data character from the RDR and store it in memory. (If frames are
not a fixed length, software determines the frame length from its content.) If
the frame is not complete, return to step 7.
9. Check the frame for checking or validation information, check it. Most
protocols specify that a receiving node ignores a frame that fails checking/
validation.
10. Process the frame based on its content. This routine is application-dependent.
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The CSI/O allows synchronous communication with serial memories, peripherals,
and other processors that include compatible interfaces. The CSI/O is a half-
duplex interface that can send or receive 8-bit bytes, but not both simultaneously.
The CSI/O includes separate receive and transmit data pins, RXSand TXS, plus a
clock pin, CKS, that can be either an input or an output. In either direction, CKS
switches only during active data characters on the RXSand TXSpins.
The bit rate for the CSI/O can be up to PHI/20 for an internally-generated clock,
and even faster with an externally-generated clock.
The CSI/O Control (CNTR) and Data (TRDR) registers are described in section
“Clocked Serial Input/Output Module (CSI/O)” on page 67.
%NQEMꢁ5GNGEVKQP
After Reset, bits 2-0 of the CNTR are 111B, which conditions the CKSpin to be
an input. If this Z80S183 is to provide the clock to the other station(s), write bits
2-0 with one of the values 000–110Bdepicted in Table 15. This value determines
the factor by which the CSI/O divides PHI to produce the clock it drives onto
CKS.
6
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0QVGꢐ Wait at least one bit time after the transmitter clears the TE bit, or the receiver
clears the RE bit, before changing the baud rate.
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The clock signal on CKSand the data signals on TXSand RXSfeature the same
basic relationship whether this Z80S183 is driving or receiving the clock on CKS,
and whether it is sending on TXSor receiving on RXS.
Figure 15 illustrates this relationship, along with the state of the flags in the
CNTR.
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CKS is High between bytes. The CSI/O operates as follows in the four possible
cases of clock and data sourcing:
1WVRWVꢁ%NQEMꢓꢁ1WVRWVꢁ&CVCꢆꢁAfter software writes a byte to be transmitted to the
TRDR and sets the TE bit in the CNTR, the CSI/O drives CKSLow, and shortly
thereafter drives bit 0 of the byte onto TXS.
Thereafter, it toggles CKSat the selected clock rate, driving each next-more-
significant bit from each falling edge on TXS, until it has driven bit 7 onto TXS.
Then the CSI/O clears the TE bit and sets the EF bit in the CNTR. The CSI/O
drives CKSHigh to complete the operation.
+PRWVꢁ%NQEMꢓꢁ1WVRWVꢁ&CVCꢆꢁSoftware must write the byte to be transmitted to the
TRDR, and then set the TE bit in the CNTR, before the external clock source
drives the CKSpin Low for the first bit of the byte.
At each falling edge of CKS, CSI/O drives a bit onto TXS, beginning with bit 0.
After driving bit 7 onto TXS, the CSI/O clears the TE bit and sets the EF bit in the
CNTR.
1WVRWVꢁ%NQEMꢓꢁ+PRWVꢁ&CVCꢆꢁAfter software sets the RE bit in the TRDR, the CSI/O
drives CKS Low, and thereafter toggles CKSat the selected clock rate, for a total
of eight falling and eight rising edges. At each rising edge on CKS, the CSI/O
samples one bit of the byte into the TRDR, starting with bit 0. After sampling bit
7, the CSI/O clears the RE bit and sets the EF bit in the CNTR.
+PRWVꢁ%NQEMꢓꢁ+PRWVꢁ&CVCꢆꢁSoftware must set the RE bit in the CNTR, before the
external clock source drives CKSLow for the first bit of the byte. At each rising
edge on CKS, the CSI/O samples one bit of the byte into the TRDR, starting with
bit 0. After sampling bit 7, the CSI/O clears the RE bit and sets the EF bit in the
CNTR.
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another byte can be sent. At that point, software must:
1. Write the byte to be transmitted into the TRDR.
2. Write a 1 to the TE bit (bit 4) in the CNTR, with the selected clock control
value in bits 2-0. If no interrupt is necessary when the byte has been sent, write
a 0in bit 6 (EIE) of this register. Otherwise, write a 1for the interrupt service
routine.
4GEGKXKPIꢁCꢁ$[VGꢆꢁBoth the TE and RE bits in the CNTR must be 0before soft-
ware can condition the CSI/O to receive another byte. At that point software must:
1. Write a 1to the RE bit (bit 5) in the CNTR, with the selected clock control
value in bits 2–0. For polled operation, write a 0in bit 6 (EIE) of this value.
Otherwise, write a 1 and clear the transmit flag for the Interrupt Service
Routine.
2. Read the CNTR (for polled operation) periodically or in a tight loop, until RE
is 0 and EF is 1. For interrupt-driven operation, the following step is
performed in the interrupt service routine, as described in the next topic.
3. Read the TRDR to acquire the byte and clear the EF flag. If the sending station
is to send more data, return to step 1.
%CPEGNNKPIꢁ6TCPUOKUUKQPꢁQTꢁ4GEGRVKQPꢆꢁSoftware can cancel a byte transmission
or reception in progress, by writing 0s to the TE and RE bits. Avoid cancellation
when the Z80S183 is sourcing CKS, because this action may hang the remote
station’s hardware in mid-byte. When operating with an external clock, software
may cancel byte transmission or reception after a time-out period expires, indi-
cating that the remote station has nothing more to send, or cannot accept further
data.
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If software sets bit 6 (EIE) in the CNTR when it starts a transmit or receive opera-
tion, the CSI/O requests an interrupt when it completes the operation and sets the
EF bit. When the conditions listed in “On-Chip Interrupt Handling” on page 19
are met with respect to this request, the processor responds by fetching the address
of the CSI/O interrupt service routine (ISR) from memory at address (I : IL : 12).
The ISR then:
1. Saves as many registers as it may use, using PUSH, EX AF, AF’, or EXX
instructions.
2. Reads the CNTR. If the EF bit is 0, the ISR may log this unknown interrupt,
before restoring the registers and returning to the interrupted process using EI
and RETinstructions.
0QVGꢐ If the Transmit flag is cleared, read the TRDR.
3. Process the byte.
a. If if further reception is necessary, write a 1 to RE as in step 1 of
“Receiving a Byte”, previously.
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b. If data is to be sent, write the first byte to the TRDR (this action clears the
EF flag). Then set TE in the CNTR, as in steps 1–2 of “Transmitting a
Byte”, previously. Set the Transmit flag for the next interrupt.
4. If the Transmit flag is set:
a. Write the next byte to the TRDR (this clears EF).
b. Then set TE in the CNTR, as in steps 1-2 of “Transmitting a Byte”,
previously.
5. If there is data to be received, perform a dummy read of the TRDR to clear the
EF flag, then write a 1to RE as in step 1 of “Receiving a Byte”, previously.
Clear the Transmit flag.
a. If no further data is to be sent or received, perform a dummy read of the
TRDR to clear the EF flag.
6. Restore the saved registers and return to the interrupted process using EIand
RETinstructions.
+ꢇ1ꢁ4')+56'45
“Processor Description” describes the processor registers and the Z80S183’s
programming model. This section describes the registers in I/O space, that control
the operation of the overall device and its on-chip peripherals.
4')+56'45ꢁ57//#4;
I/O registers on the Z80S183 are divided into two classes, the 80180 registers and
other on-chip registers.
The 80180 registers:
•
Are located at addresses between 0000and 003FH
Can be relocated to 0080–00BFHor 00C0–00FFH
Require three cycles per I/O instruction
•
•
Other on-chip registers:
•
•
Are located at addresses between 0040and 007FH, and
Require four cycles per I/O instruction.
All the on-chip registers on the Z80S183 decode 16-bit I/O addresses and require
A15-8 to be all 0. These registers must be accessed using IN0and OUT0instruc-
tions.
The following table includes all on-chip registers in both classes. I/O addresses
not described are not used.
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#FFTGUUGUꢀꢃꢃꢃꢃꢃ ꢃꢃꢊ((*ꢀCTGꢀKPꢀQPꢌEJKRꢀ
41/ꢄ
ꢏ
1PꢌEJKRꢀ 4ꢋ9
4#/ꢀ
'PCDNG
ꢃ
ꢂ
1PꢌEJKRꢀ4#/ꢀKUꢀPQVꢀCEEGUUKDNGꢀVQꢀVJGꢀ
RTQEGUUQT
1PꢌEJKRꢀ4#/ꢀKUꢀCEEGUUKDNGꢀVQꢀVJGꢀ
RTQEGUUQT
ꢆ
4#/ꢀ
*KIJꢀ
'PCDNG
4ꢋ9
ꢃ
1PꢌEJKRꢀ4#/ꢀKUꢀCVꢀZ(ꢇꢃꢃ Z((((*ꢗꢀ
CFFTGUUGUꢀ#ꢂꢁꢌꢂꢏꢀCTGꢀPQVꢀFGEQFGFꢀHQTꢀQPꢌ
EJKRꢀ4#/
ꢂ
ꢂ
1PꢌEJKRꢀ4#/ꢀKUꢀCVꢀ((ꢇꢃꢃ (((((*
ꢉ
41/%5ꢀ 4ꢋ9
'PCDNG
41/%5ꢀRKPꢀKUꢀGPCDNGFꢋCEVKXG
ꢊ
4#/%5ꢀ 4ꢋ9
'PCDNG
ꢂ
ꢂ
4#/%5ꢀRKPꢀKUꢀGPCDNGFꢋCEVKXG
ꢍ
+1%5ꢀ
4ꢋ9
6JGꢀ+1%5ꢂꢀCPFꢀ+1%5ꢍꢀRKPUꢀCTGꢀGPCDNGFꢋ
CEVKXG
'PCDNG
ꢂꢌꢃ
%NQEMꢀ
5GNGEV
4ꢋ9
ꢃꢃ 2*+ꢀVCMGPꢀHTQOꢀ':6#.
ꢃꢂ 2*+ꢀVCMGPꢀHTQOꢀ.(':6#.
ꢂꢃ 2*+ꢀꢔꢀ.(':6#.ꢀVKOGUꢀꢂꢃꢃꢉ
ꢂꢂ 2*+ꢀꢔꢀ.(':6#.ꢀVKOGUꢀꢆꢃꢍ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢎꢁ
+ꢇ1ꢁ4
+
ꢀ4
+06'44726ꢁ4')+56'45
See the Interrupts section, which starts on page 13, for more about these registers.
ꢁꢌꢒꢆ + ꢁ8 ꢁ. ꢁ4 ꢁꢎꢃꢃꢅꢅ*ꢏꢁ+.
6
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
4GUXF
!
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
+.ꢎꢌꢆ
4ꢋ9
ꢃ
4GUGV
ꢃ
ꢃ
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
$KV
2QUKVKQP
$KVꢇ
(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢆ
+.ꢎꢌꢆ
4ꢋ9
6JGꢀRTQEGUUQTꢀWUGUꢀVJGUGꢀDKVUꢀCUꢀ#ꢎꢌ
ꢆꢀꢐCNQPIꢀYKVJꢀVJGꢀEQPVGPVUꢀQHꢀVJGꢀ+ꢀ
TGIKUVGTꢀCUꢀ#ꢂꢆꢌꢇꢑꢀYJGPꢀHGVEJKPIꢀCPꢀ
KPVGTTWRVꢀUGTXKEGꢀTQWVKPGꢀCFFTGUUꢀHQTꢀ
+06ꢂꢌꢍꢅꢀ#5%+ꢃꢌꢂꢅꢀ246ꢃꢌꢂꢅꢀ&/#ꢃꢌꢂꢅꢀ
QTꢀVJGꢀ%5+ꢋ1ꢄ
6
ꢁꢅꢃꢆ +
ꢇ6
ꢁ%
ꢁ4
ꢁꢎꢃꢃꢅꢉ*ꢏꢁ+6%
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
6TCR 7(1
+'(ꢂ
4GUXF
+06ꢍꢀ +06ꢂꢀ +06ꢃꢀ
GP
4ꢋ9
ꢃ
GP
4ꢋ9
ꢃ
GP
4ꢋ9
ꢂ
4ꢋ9
49ꢃ%
ꢃ
4
4
ꢃ
!
4GUGV
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
6TCR
49ꢃ%
ꢂ
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VJKUꢀDKVꢀENGCTUꢀKVꢗꢀYTKVKPIꢀCꢀꢂꢀJCUꢀPQꢀ
GHHGEVꢄ
ꢏ
7(1
4
ꢃ
ꢂ
+PUVꢀUVCTVGFꢀCVꢀUVCEMGFꢀ2%ꢌꢂ
+PUVꢀUVCTVGFꢀCVꢀUVCEMGFꢀ2%ꢌꢍ
ꢆ
ꢍ
ꢂ
ꢃ
+'(ꢂ
4
%WTTGPVꢀUVCVGꢀQHꢀKPVGTTWRVꢀGPCDNG
+06ꢍꢀKPVGTTWRVꢀGPCDNG
+06ꢍꢀGP
+06ꢂꢀGP
+06ꢃꢀGP
4ꢋ9
4ꢋ9
4ꢋ9
+06ꢂꢀKPVGTTWRVꢀGPCDNG
+06ꢃꢀKPVGTTWRVꢀGPCDNG
ꢇꢃ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
+
ꢀ4
+ꢇ1ꢁ4
6
ꢁꢅꢄꢆ + ꢌꢀꢄꢁ+
ꢁ'
ꢁ4
ꢁꢎꢃꢃꢅꢋ*ꢏꢁ+'%4
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
+06ꢍ
+06ꢂ
+06ꢍ
'FIGꢀ 'FIG
+06ꢂ +06ꢍꢀ/QFGꢀ5GN +06ꢂꢀ/QFGꢀ5GN
4ꢋ9
4
4
49ꢂ% 49ꢂ%
49
49
4GUGV
:
:
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
ꢏ
ꢆ
+06ꢍ
4
4
+06ꢍꢀRKPꢀUVCVGꢅꢀꢃꢀKUꢀ.QY
+06ꢂꢀRKPꢀUVCVGꢅꢀꢃꢀKUꢀ.QY
+06ꢂ
+06ꢍꢀ'FIG
49ꢂ%
ꢃ
ꢂ
4ꢈꢀGFIGꢀPQVꢀFGVGEVGFꢅꢀ9ꢈꢀPQꢀGHHGEV
4ꢈꢀGFIGꢀFGVGEVGFꢅꢀ9ꢈꢀENGCTꢀVJKUꢀDKV
ꢉ
+06ꢂꢀ'FIG
+06ꢍꢀ/QFG
49ꢂ%
49
ꢃ
ꢂ
4ꢈꢀGFIGꢀPQVꢀFGVGEVGFꢅꢀ9ꢈꢀPQꢀGHHGEV
4ꢈꢀGFIGꢀFGVGEVGFꢅꢀ9ꢈꢀENGCTꢀVJKUꢀDKV
ꢊꢌꢍ
ꢃꢃ .QYꢌ.GXGNꢀ+PVGTTWRV
ꢃꢂ 4KUKPIꢀ'FIGꢀ+PVGTTWRV
ꢂꢃ (CNNKPIꢀ'FIGꢀ+PVGTTWRV
ꢂꢂ $QVJꢀ'FIGUꢀ+PVGTTWRV
ꢂꢌꢃ
+06ꢂꢀ/QFG
49
ꢃꢃ .QYꢌ.GXGNꢀ+PVGTTWRV
ꢃꢂ 4KUKPIꢀ'FIGꢀ+PVGTTWRV
ꢂꢃ (CNNKPIꢀ'FIGꢀ+PVGTTWRV
ꢂꢂ $QVJꢀ'FIGUꢀ+PVGTTWRV
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢇꢂ
+ꢇ1ꢁ4
//7ꢀ4
//7ꢁ4')+56'45
See “Memory Management Unit (MMU)” on page 10, for more about these regis-
ters.
6
ꢁꢅꢌꢆ %
ꢁ$
ꢁ4
ꢁꢎꢃꢃꢅꢂ*ꢏꢁ%$4
$KV
ꢎ
ꢏ
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ꢉ
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ꢍ
ꢂ
ꢃ
ꢃ
ꢃ
$KVꢋ(KGNF
4ꢋ9
$CUGꢀQHꢀ%QOOQPꢀ#TGCꢀꢂ
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
ꢎꢌꢃ %QOOQPꢀꢂꢀ 4ꢋ9
#TGCꢀ$CUG
4ꢇ9 8CNWG &GUETKRVKQP
+HꢀVJGꢀEQORCTKUQPꢀQHꢀDKVUꢀꢂꢆꢌꢂꢍꢀQHꢀCꢀ
NQIKECNꢀCFFTGUUꢀKPFKECVGUꢀVJCVꢀVJGꢀ
CFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ#TGCꢀꢂꢅꢀVJKUꢀ
XCNWGꢀꢐUJKHVGFꢀNGHVꢀꢂꢍꢀDKVUꢅꢀVKOGUꢀ
ꢉꢃꢁꢏꢑꢀKUꢀCFFGFꢀVQꢀVJGꢀNQIKECNꢀCFFTGUUꢀ
VQꢀHQTOꢀVJGꢀRJ[UKECNꢀCFFTGUUꢄ
6
ꢁꢅꢅꢆ $
ꢁ$
ꢁ4
ꢁꢎꢃꢃꢅꢒ*ꢏꢁ$$4
$KV
ꢎ
ꢃ
ꢏ
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ꢃ
ꢂ
ꢃ
ꢃ
ꢃ
$KVꢋ(KGNF
4ꢋ9
$CUGꢀQHꢀ$CPMꢀ#TGC
4ꢋ9
4GUGV
ꢃ
ꢃ
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
ꢎꢌꢃ $CPMꢀ#TGCꢀ
$CUG
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9
+HꢀVJGꢀEQORCTKUQPꢀQHꢀDKVUꢀꢂꢆ ꢂꢍꢀQHꢀCꢀ
NQIKECNꢀCFFTGUUꢀKPFKECVGUꢀVJCVꢀVJGꢀ
CFFTGUUꢀKUꢀKPꢀVJGꢀ$CPMꢀ#TGCꢅꢀVJKUꢀXCNWGꢀ
ꢐUJKHVGFꢀNGHVꢀꢂꢍꢀDKVUꢅꢀVKOGUꢀꢉꢃꢁꢏꢑꢀKUꢀ
CFFGFꢀVQꢀVJGꢀNQIKECNꢀCFFTGUUꢀVQꢀHQTOꢀ
VJGꢀRJ[UKECNꢀCFFTGUUꢄ
ꢇꢍ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
41/ꢋ4#/ꢀ% ꢀ5
ꢀ
ꢀ9 ꢀ4
+ꢇ1ꢁ4
6
ꢁꢅꢉꢆ %
ꢇ$
ꢁ#
ꢁ4
ꢁ ꢎꢃꢃꢅ#*ꢏꢁ%$#4
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
$CPMꢋ%QOOQPꢀꢂꢀ$QWPFCT[
4ꢋ9
%QOOQPꢀꢃꢋ$CPMꢀ$QWPFCT[
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢃ
ꢃ
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢉ
$CPMꢋ
%QOOQPꢀꢂꢀ
$QWPFCT[
4ꢋ9
+HꢀDKVUꢀꢂꢆ ꢂꢍꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀCTGꢀ
ITGCVGTꢀVJCPꢀQTꢀGSWCNꢀVQꢀVJKUꢀXCNWGꢅꢀ
VJGꢀCFFTGUUꢀKUꢀKPꢀ%QOOQPꢀ#TGCꢀꢂꢄ
ꢊꢌꢃ
%QOOQPꢀꢃꢋ 4ꢋ9
$CPMꢀ
$QWPFCT[
+HꢀDKVUꢀꢂꢆ ꢂꢍꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀCTGꢀ
NGUUꢀVJCPꢀVJKUꢀXCNWGꢅꢀVJGꢀCFFTGUUꢀKUꢀKPꢀ
%QOOQPꢀ#TGCꢀꢃꢄ
0QVGꢐꢁ+HꢀDKVUꢀꢊꢌꢃꢀQHꢀVJKUꢀTGIꢀꢒꢀDKVUꢀꢂꢆꢌꢂꢍꢀQHꢀCꢀNQIKECNꢀCFFTGUUꢀꢒꢀDKVUꢀꢎꢌꢉꢀQHꢀVJKUꢀTGIꢅꢀ
VJGꢀCFFTGUUꢀKUꢀKPꢀVJGꢀ$CPMꢀ#TGCꢄꢀ&QꢀPQVꢀRTQITCOꢀVJKUꢀTGIKUVGTꢀUQꢀVJCVꢀDKVUꢀꢊꢌꢃꢀ ꢀDKVUꢀꢎꢌ
ꢉꢄꢀ#NNꢀEQORCTKUQPUꢀCTGꢀWPUKIPGFꢄ
41/ꢇ4#/ꢁ%*+2ꢁ5'.'%6ꢁ#0&ꢁ9#+6ꢁ4')+56'45
See “Memory”, which starts on page 19, for more detail about these registers.
6
ꢁꢅꢋꢆ 9 ꢁ5
ꢁ)
ꢁ%
ꢁ4
ꢁꢎꢃꢃꢊ$*ꢏꢁ95)%4
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
41/ꢀ9CKVU
4ꢋ9
4#/ꢀ9CKVU
4ꢋ9
1VJGTꢀ9CKVU
4ꢋ9
4GUGTXGF
!
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢏ
41/ꢀ9CKVU
4ꢋ9
6JKUꢀHKGNFꢀFGVGTOKPGUꢀJQYꢀOCP[ꢀYCKVꢀ
UVCVGUꢀCTGꢀKPUGTVGFꢀHQTꢀOGOQT[ꢀ
CFFTGUUGUꢀVJCVꢀCEVKXCVGꢀ41/%5ꢈ
ꢃꢃ 0Qꢀ9CKVꢀUVCVGU
ꢃꢂ ꢂꢀ9CKVꢀUVCVG
ꢂꢃ ꢍꢀ9CKVꢀUVCVGU
ꢂꢂ ꢉꢀ9CKVꢀUVCVGU
ꢆꢌꢉ
4#/ꢀ9CKVU
4ꢋ9
6JKUꢀHKGNFꢀFGVGTOKPGUꢀJQYꢀOCP[ꢀYCKVꢀ
UVCVGUꢀCTGꢀKPUGTVGFꢀHQTꢀOGOQT[ꢀ
CFFTGUUGUꢀVJCVꢀCEVKXCVGꢀ4#/%5ꢈ
ꢃꢃ 0Qꢀ9CKVꢀUVCVGU
ꢃꢂ ꢂꢀ9CKVꢀUVCVG
ꢂꢃ ꢍꢀ9CKVꢀUVCVGU
ꢂꢂ ꢉꢀ9CKVꢀUVCVGU
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢇꢊ
+ꢇ1ꢁ4
41/ꢋ4#/ꢀ% ꢀ5
ꢀ
ꢀ9 ꢀ4
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢊꢌꢍ
1VJGTꢀ9CKVU 4ꢋ9
6JKUꢀHKGNFꢀFGVGTOKPGUꢀJQYꢀOCP[ꢀYCKVꢀ
UVCVGUꢀCTGꢀKPUGTVGFꢀHQTꢀOGOQT[ꢀ
CFFTGUUGUꢀVJCVꢀFQꢀPQVꢀCEVKXCVGꢀGKVJGTꢀ
41/%5ꢀPQTꢀ4#/%5ꢄꢀꢐ6JGUGꢀE[ENGUꢀ
FQꢀPQVꢀCEVKXCVGꢀCP[ꢀEQPVTQNꢀUKIPCNUꢀ
CPFꢀVJWUꢀCTGꢀPQVꢀXKUKDNGꢄꢑ
ꢃꢃ 0Qꢀ9CKVꢀUVCVGU
ꢃꢂ ꢂꢀ9CKVꢀUVCVG
ꢂꢃ ꢍꢀ9CKVꢀUVCVGU
ꢂꢂ ꢉꢀ9CKVꢀUVCVGU
6
ꢁꢅꢊꢆ 41/ꢁ$
ꢁ4
ꢁꢎꢃꢃꢊ%*ꢏꢁ41/$4
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
41/ꢀ7RRGTꢀ$QWPF
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV $KVꢇ
2QUKVKQP (KGNF
4ꢇ9
8CNWG &GUETKRVKQP
ꢎꢌꢃ
41/ꢀ
7RRGTꢀ
$QWPF
4ꢋ9
+HꢀDKVꢀꢉꢀQHꢀVJGꢀ5[UVGOꢀ%QPHKIWTCVKQPꢀ
4GIKUVGTꢀKUꢀꢂꢅꢀCUꢀKVꢀKUꢀCHVGTꢀCꢀTGUGVꢅꢀ
OGOQT[ꢀCEEGUUGUꢀCVꢀCFFTGUUGUꢀYKVJꢀ
#ꢂꢁꢌꢂꢍꢀNGUUꢀVJCPꢀQTꢀGSWCNꢀVQꢀVJKUꢀXCNWGꢅꢀ
CEVKXCVGꢀ41/4&ꢀQTꢀ41/94
ꢇꢉ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
41/ꢋ4#/ꢀ% ꢀ5
ꢀ
ꢀ9 ꢀ4
+ꢇ1ꢁ4
6
ꢁꢅꢈꢆ 4#/ꢁ.
ꢁ$
ꢁ4
ꢁꢎꢃꢃꢊ&*ꢏꢁ4#/.$4
$KV
ꢎ
ꢏ
ꢆ
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0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ 2&ꢎꢌꢃꢀKPV
4ꢋ9
#ꢀꢂꢀKPꢀQPGꢀQHꢀVJGUGꢀDKVUꢀOCMGUꢀVJGꢀ
EQTTGURQPFKPIꢀRKPꢀCꢀ.QYꢌCEVKXGꢀ
KPVGTTWRVꢀTGSWGUVꢀNKPGꢄ
ꢁꢏ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
+ꢋ1ꢀ2
ꢀ4
+ꢇ1ꢁ4
6
ꢁꢋꢋꢆ 2
ꢁ&ꢁ1
ꢁ%
ꢁ4
ꢁꢎꢃꢃꢉ(*ꢏꢁ1%4&
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
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ꢂ
ꢃ
$KVꢋ(KGNF 2&ꢎꢀQE 2&ꢏꢀQE 2&ꢆꢀQE 2&ꢉꢀQE 2&ꢊꢀQE 2&ꢍꢀQE 2&ꢂꢀQE 2&ꢃꢀQE
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9
ꢎꢌꢃ 2&ꢎꢌꢃꢀQE
6QIGVJGTꢀYKVJꢀ&CVCꢀ&KTGEVKQPꢀ4GIKUVGTꢀ
&ꢅꢀVJGUGꢀDKVUꢀFGVGTOKPGꢀYJKEJꢀRKPUꢀ
COQPIꢀ2&ꢎꢌꢃꢀCTGꢀKPRWVUꢀCPFꢀYJKEJꢀ
CTGꢀQWVRWVUꢅꢀCPFꢀHQTꢀQWVRWVUꢅꢀQPGꢀQHꢀ
VJTGGꢀQWVRWVꢀOQFGUꢄꢀ6JGꢀHQWTꢀ
EQPHKIWTCVKQPUꢀHQTꢀGCEJꢀRKPꢀCTGꢀ
FGUETKDGFꢀKPꢀ6CDNGꢀꢆꢍꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢁꢎ
+ꢇ1ꢁ4
&/#ꢀ4
&/#ꢁ4')+56'45
See section “DMA Channels” on page 36, for more about these registers.
6
ꢁꢋꢊꢆ &/#ꢃꢁ5
ꢁ#
ꢁ4
ꢁ. ꢁꢎꢃꢃꢌꢃ*ꢏꢁ5#4ꢃ.
$KV
ꢎ
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4ꢋ9
.5ꢀD[VGꢀQHꢀ&/#ꢃꢀ5QWTEGꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
&/#ꢃꢀ
5QWTEGꢀ
#FFTGUUꢀ.5ꢀ
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4ꢋ9
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EJCPPGNꢀꢃꢄ
6
ꢁꢋꢈꢆ &/#ꢃꢁ5
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ꢁ4
ꢁ. ꢁꢎꢃꢃꢌꢃ*ꢏꢁ5#4ꢃ.
$KV
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4ꢋ9
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4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
&/#ꢃꢀ
5QWTEGꢀ
#FFTGUUꢀ.5ꢀ
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4ꢋ9
.5$ꢀQHꢀVJGꢀ5QWTEGꢀ#FFTGUUꢀHQTꢀ&/#ꢀ
EJCPPGNꢀꢃꢄ
ꢁꢇ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
&/#ꢀ4
+ꢇ1ꢁ4
6
ꢁꢋꢂꢆ &/#ꢃꢁ5
ꢁ#
ꢁ4
ꢁ* ꢁꢎꢃꢃꢌꢄ*ꢏꢁ5#4ꢃ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
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ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/KFFNGꢀD[VGꢀQHꢀ&/#ꢃꢀ5QWTEGꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
&/#ꢃꢀ
5QWTEGꢀ
4ꢋ9
$KVUꢀꢂꢆꢌꢇꢀQHꢀVJGꢀ5QWTEGꢀ#FFTGUUꢀHQTꢀ
&/#ꢀEJCPPGNꢀꢃꢄ
#FFTGUUꢀ
OKFFNGꢀD[VG
6
ꢁꢋꢒꢆ &/#ꢃꢁ5
ꢁ#
ꢁ4
ꢁ$ꢁꢎꢃꢃꢌꢌ*ꢏꢁ5#4ꢃ$
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
4GUGTXGF
/5ꢀRCTVꢀQHꢀ&/#ꢃꢀ5QWTEGꢀ#FFT
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9 +HꢀVJGꢀ5QWTEGꢀ/QFGꢀHKGNFꢀKPꢀVJGꢀ
ꢊꢌꢃ /5ꢀRCTVꢀQHꢀ
&/#ꢃꢀ
5QWTEGꢀ
#FFTGUU
&/1&'ꢀTGIKUVGTꢀKUꢀꢂꢂꢅꢀKPFKECVKPIꢀCPꢀ
+ꢋ1ꢀUQWTEGꢅꢀVJGUGꢀDKVUꢀUGNGEVꢀYJKEJꢀ
UQWTEGꢀFGXKEGꢀJCPFUJCMGꢀNKPGꢀEQPVTQNUꢀ
FCVCꢀVTCPUHGTꢅꢀCUꢀHQNNQYUꢈ
:ꢃꢃꢃ &4'3ꢃꢀRKP
:ꢃꢃꢂ #5%+ꢃꢀ4&4(
:ꢃꢂꢃ #5%+ꢂꢀ4&4(
QVJGT 4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
1VJGTYKUGꢅꢀVJGUGꢀDKVUꢀEQPVCKPꢀ#ꢂꢁꢌꢂꢏꢀ
QHꢀVJGꢀ&/#ꢃꢀ5QWTEGꢀCFFTGUUꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢁꢁ
+ꢇ1ꢁ4
&/#ꢀ4
6
ꢁꢊꢃꢆ &/#ꢃꢁ&
ꢁ#
ꢁ4
ꢁ. ꢁꢎꢃꢃꢌꢅ*ꢏꢁꢃ.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀD[VGꢀQHꢀ&/#ꢃꢀ&GUVKPCVKQPꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
&/#ꢃꢀ
4ꢋ9
.5$ꢀQHꢀVJGꢀ&GUVKPCVKQPꢀ#FFTGUUꢀHQTꢀ
&/#ꢀEJCPPGNꢀꢃꢄ
&GUVKPCVKQPꢀ
#FFTGUUꢀ.5ꢀ
D[VG
6
ꢁꢊꢄꢆ &/#ꢃꢁ&
ꢁ#
ꢁ4
ꢁ* ꢁꢎꢃꢃꢌꢉ*ꢏꢁꢃ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/KFFNGꢀD[VGꢀQHꢀ&/#ꢃꢀ&GUVKPCVKQPꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
&/#ꢃꢀ
&GUVKPCVKQPꢀ
#FFTGUUꢀ
4ꢋ9
$KVUꢀꢂꢆꢌꢇꢀQHꢀVJGꢀ&GUVKPCVKQPꢀ#FFTGUUꢀ
HQTꢀ&/#ꢀEJCPPGNꢀꢃꢄ
OKFFNGꢀD[VG
ꢂꢃꢃ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
&/#ꢀ4
+ꢇ1ꢁ4
6
ꢁꢊꢌꢆ &/#ꢃꢁ&
ꢁ#
ꢁ4
ꢁ$ꢁꢎꢃꢃꢌꢋ*ꢏꢁꢃ$
$KV
ꢎ
ꢏ
ꢆ
ꢉ
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ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4GUGTXGF
/5ꢀRCTVꢀQHꢀ&/#ꢃꢀ&GUVKPCVKQPꢀ
#FFTGUU
4ꢋ9
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢊꢌꢃ /5ꢀRCTVꢀQHꢀ
4ꢋ9
+HꢀVJGꢀ&GUVꢀ/QFGꢀHKGNFꢀKPꢀVJGꢀ&/1&'ꢀ
TGIKUVGTꢀKUꢀꢂꢂꢅꢀKPFKECVKPIꢀCPꢀ+ꢋ1ꢀ
FGUVKPCVKQPꢅꢀVJGUGꢀDKVUꢀUGNGEVꢀYJKEJꢀ
FGUVKPCVKQPꢀFGXKEGꢀJCPFUJCMGꢀNKPGꢀ
EQPVTQNUꢀFCVCꢀVTCPUHGTꢅꢀCUꢀHQNNQYUꢈ
&/#ꢃꢀ
&GUVKPCVKQPꢀ
#FFTGUU
&4'3ꢃꢀRKP
:ꢃꢃꢃ #5%+ꢃꢀ6&4'
:ꢃꢃꢂ #5%+ꢂꢀ6&4'
:ꢃꢂꢃ 4GUGTXGFꢅꢀFQꢀPQVꢀRTQITCO
QVJGT
1VJGTYKUGꢀVJGUGꢀDKVUꢀEQPVCKPꢀ#ꢂꢁꢌꢂꢏꢀ
QHꢀVJGꢀ&/#ꢀꢃꢀ&GUVKPCVKQPꢀCFFTGUUꢄ
6
ꢁꢊꢅꢆ &/#ꢃꢁ$
ꢁ%
ꢁ4
ꢁ. ꢁꢎꢃꢃꢌꢊ*ꢏꢁ$%4ꢃ.
$KV
ꢎ
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ꢆ
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4ꢋ9
.5ꢀD[VGꢀQHꢀ&/#ꢃꢀ$[VGꢀ%QWPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ &/#ꢃꢀ$[VGꢀ 4ꢋ9
.5ꢀD[VGꢀQHꢀVJGꢀ$[VGꢀ%QWPVꢀHQTꢀ&/#ꢀ
EJCPPGNꢀꢃꢄ
%QWPVꢀ.5ꢀ
D[VG
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢃꢂ
+ꢇ1ꢁ4
&/#ꢀ4
6
ꢁꢊꢉꢆ &/#ꢃꢁ$
ꢁ%
ꢁ4
ꢁ* ꢁꢎꢃꢃꢌꢈ*ꢏꢁ$%4ꢃ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
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ꢃ
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4ꢋ9
/5ꢀD[VGꢀQHꢀ&/#ꢃꢀ$[VGꢀ%QWPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ &/#ꢃꢀ$[VGꢀ 4ꢋ9
/5ꢀD[VGꢀQHꢀVJGꢀ$[VGꢀ%QWPVꢀHQTꢀ&/#ꢀ
EJCPPGNꢀꢃꢄ
%QWPVꢀ/5ꢀ
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6
ꢁꢊꢋꢆ &/#ꢄꢁ/
ꢁ#
ꢁ4
ꢁ. ꢁꢎꢃꢃꢌꢂ*ꢏꢁ/#4ꢄ.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
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$KVꢋ(KGNF
4ꢋ9
.5ꢀD[VGꢀQHꢀ&/#ꢂꢀ/GOQT[ꢀ#FFTGUU
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
&/#ꢂꢀ
4ꢋ9
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&/#ꢀEJCPPGNꢀꢂꢄ
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6
ꢁꢊꢊꢆ &/#ꢄꢁ/
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$KV
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4ꢋ9
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4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
&/#ꢂꢀ
4ꢋ9
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&/#ꢀEJCPPGNꢀꢂꢄ
/GOQT[ꢀ
#FFTGUUꢀ
OKFFNGꢀD[VG
ꢂꢃꢍ
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25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
&/#ꢀ4
+ꢇ1ꢁ4
6
ꢁꢊꢈꢆ &/#ꢄꢁ/
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&/#ꢂꢀ/GOQT[ꢀ#FFTGUUꢀꢂꢁꢌꢂꢏ
4ꢋ9
4GUGV
:
:
:
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:
:
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:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
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&/#ꢂꢀ
/GOQT[ꢀ
#FFTGUUꢀꢂꢁꢌ
ꢂꢏ
4ꢋ9
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CFFTGUUꢄ
6
ꢁꢊꢂꢆ &/#ꢄꢁ+ꢇ1ꢁ#
ꢁ4
ꢁ. ꢁꢎꢃꢃꢌ$*ꢏꢁ+#4ꢄ.
$KV
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4ꢋ9
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4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
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ꢎꢌꢃ &/#ꢂꢀ+ꢋ1ꢀ
4ꢋ9
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#FFTGUUꢀ.5ꢀ
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6
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ꢁꢎꢃꢃꢅꢌ*ꢏꢁ&%06.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF /GOQT[ꢀ9CKVU
+ꢋ1ꢀ9CKVU
4GSWGUVꢀ5GPUGꢀ &/#ꢂꢀ/QFG
ꢂꢌꢃ
4ꢋ9
4ꢋ9
4ꢋ9
4ꢋ9
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢃ
ꢃ
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢏ
ꢆꢌꢉ
ꢊꢌꢍ
/GOQT[ꢀ
9CKVU
4ꢋ9
4ꢋ9
4ꢋ9
6JKUꢀHKGNFꢀEQPVTQNUꢀJQYꢀOCP[ꢀYCKVꢀ
UVCVGUꢀCTGꢀKPLGEVGFꢀKPVQꢀ&/#ꢀCPFꢀ
RTQEGUUQTꢀOGOQT[ꢀE[ENGUꢈ
ꢃꢃ 0QPG
ꢃꢂ
ꢂꢃ
ꢂꢂ
ꢂ
ꢍ
ꢊ
+ꢋ1ꢀ9CKVU
6JKUꢀHKGNFꢀEQPVTQNUꢀJQYꢀOCP[ꢀYCKVꢀ
UVCVGUꢀCTGꢀKPLGEVGFꢀKPVQꢀ&/#ꢀCPFꢀ
RTQEGUUQTꢀ+ꢋ1ꢀE[ENGUꢈ
ꢃꢃ 0QPG
ꢃꢂ
ꢂꢃ
ꢂꢂ
ꢂ
ꢍ
ꢊ
4GSWGUVꢀ
5GPUGꢀꢂꢌꢃ
'CEJꢀQHꢀVJGUGꢀDKVUꢀEQPVTQNUꢀJQYꢀVJGꢀ
EQTTGURQPFKPIꢀ&/#ꢀEJCPPGNꢀUCORNGUꢀ
KVUꢀ4GSWGUVꢀUKIPCNꢀꢐGZEGRVꢀYJGPꢀ&/#ꢀ
ꢃ Uꢀ5QWTEGꢀCPFꢀ&GUVꢀ/QFGꢀHKGNFUꢀCTGꢀ
DQVJꢀꢃZꢑ
ꢃ
ꢂ
.GXGNꢀUGPUGꢈꢀVJGꢀ&/#ꢀUCORNGUꢀKVUꢀ
4GSWGUVꢀCICKPꢀFWTKPIꢀVJGꢀꢍPFꢀE[ENGꢀ
HQTꢀGCEJꢀD[VG
'FIGꢀUGPUGꢈꢀCPQVJGTꢀHCNNKPIꢀGFIGꢀKUꢀ
PGGFGFꢀQPꢀVJGꢀ4GSWGUVꢀNKPGꢀDGHQTGꢀVJGꢀ
&/#ꢀEJCPPGNꢀVTCPUHGTUꢀCPQVJGTꢀD[VG
5GGꢀUGEVKQPꢀꢅꢀYJKEJꢀUVCTVUꢀQPꢀRCIGꢀ
ꢊꢎꢅꢀHQTꢀVKOKPIꢀQHꢀDQVJꢀECUGUꢄ
ꢂꢌꢃ
&/#ꢂꢀ
/QFG
4ꢋ9
6JKUꢀHKGNFꢀEQPVTQNUꢀVJGꢀFKTGEVKQPꢀQHꢀ
DQVJꢀVTCPUHGTꢀCPFꢀCFFTGUUꢀUVGRRKPIꢀQPꢀ
&/#ꢀEJCPPGNꢀꢂꢈ
ꢃꢃ +PETGOGPVKPIꢀ/GOQT[ꢀCFFTUꢀVQꢀ+ꢋ1
ꢃꢂ &GETGOGPVKPIꢀ/GOQT[ꢀCFFTUꢀVQꢀ+ꢋ1
ꢂꢃ +ꢋ1ꢀVQꢀKPETGOGPVKPIꢀ/GOQT[ꢀCFFTU
ꢂꢂ +ꢋ1ꢀVQꢀFGETGOGPVKPIꢀ/GOQT[ꢀCFFTU
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢃꢁ
+ꢇ1ꢁ4
9
ꢌ& ꢀ6
ꢀ4
9#6%*ꢀ&1)ꢁ6+/'4ꢁ4')+56'45
See “Watch-Dog Timer” on page 43, for more about these registers.
6
ꢁꢈꢈꢆ 9
ꢀ& ꢁ6
ꢁ/
ꢁ4
ꢁꢎꢃꢃꢊꢉ*ꢏꢁ9&6/4
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF 'PCDNG 2GTKQFꢀ5GNGEV
&TKXGꢀ 2QYGTꢀ 9&6ꢀ 5VCVGꢀ 4GIꢀ
4GUGV
1Pꢀ
4GUGV
4GUGV %JCPIGꢀ 9TKVGꢀ
'PCDNG 'PCDNG
4ꢋ9
4
ꢂ
4ꢋ9
4ꢋ9
4%
4%
4ꢋ9
ꢂ
4
ꢂ
4GUGV
ꢂ
ꢂ
214ꢔ 214ꢔ 9&6
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
9&6ꢀ
'PCDNGF
4
+HꢀVJKUꢀTGCFꢌQPN[ꢀDKVꢀKUꢀ1ꢀVJGꢀ9CVEJꢌꢀ
&QIꢀ6KOGTꢀKUꢀGPCDNGFꢄꢀ
ꢏꢌꢆ
2GTKQFꢀ
5GNGEV
4ꢋ9
6JGꢀHKGNFꢀUGNGEVUꢀJQYꢀNQPIꢀUQHVYCTGꢀ
ECPꢀNGCXGꢀVJGꢀ9CVEJꢌ&QIꢀ6KOGTꢀ
WPCVVGPFGFꢅꢀDGHQTGꢀKVꢀTGUGVUꢀVJGꢀRCTVꢈ
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
ꢍ
ꢍ
ꢍ
ꢍ
ꢀꢐꢍꢏꢍꢅꢂꢉꢉꢑꢀ2*+ꢀENQEMU
ꢀꢐꢉꢅꢂꢁꢉꢅꢊꢃꢉꢑꢀ2*+ꢀENQEMU
ꢀꢐꢊꢊꢅꢆꢆꢉꢅꢉꢊꢍꢑꢀ2*+ꢀENQEMU
ꢀꢐꢂꢊꢉꢅꢍꢂꢎꢅꢎꢍꢇꢑꢀ2*+ꢀENQEMU
ꢉ
ꢊ
&TKXGꢀ4GUGV
4ꢋ9
4%
+HꢀVJKUꢀDKVꢀKUꢀ1ꢅꢀCUꢀKVꢀKUꢀCHVGTꢀCꢀ2QYGTꢀ
1Pꢀ4GUGVꢅꢀGZRKTCVKQPꢀQHꢀVJGꢀ9&6ꢀ
FTKXGUꢀVJGꢀ4GUGVꢀRKPꢀ.QYꢅꢀVQꢀTGUGVꢀ
GZVGTPCNꢀFGXKEGUꢄꢀ9&6ꢀGZRKTCVKQPꢀ
TGUGVUꢀVJGꢀ<ꢇꢃ5ꢂꢇꢊꢀTGICTFNGUUꢀQHꢀVJKUꢀ
DKVꢄ
2QYGTꢀ1Pꢀ
4GUGV
#ꢀ2QYGTꢀ1Pꢀ4GUGVꢀUGVUꢀVJKUꢀDKVꢄꢀꢐ6JKUꢀ
KPENWFGUꢀCꢀ214ꢀUGSWGPEGꢀECWUGFꢀD[ꢀCꢀ
TKUKPIꢀGFIGꢀQPꢀVJGꢀ12/1&ꢂꢀQTꢀ
29472ꢀRKPꢄꢑꢀ4GCFKPIꢀVJKUꢀTGIKUVGTꢀ
ENGCTUꢀVJKUꢀDKVꢄ
ꢍ
ꢂ
9&6ꢀ4GUGV
4%
9&6ꢀGZRKTCVKQPꢀUGVUꢀVJKUꢀDKVꢄꢀ4GCFKPIꢀ
VJKUꢀTGIKUVGTꢀENGCTUꢀKVꢄ
5VCVGꢀ
%JCPIGꢀ
'PCDNGF
4ꢋ9
9JGPꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀYTKVKPIꢀꢉꢃ*ꢀVQꢀVJGꢀ
9&6ꢀ%QOOCPFꢀTGIKUVGTꢀFKUCDNGUꢀVJGꢀ
9&6ꢅꢀCPFꢀYTKVKPIꢀ$ꢃ*ꢀVQꢀKVꢀGPCDNGUꢀ
VJGꢀ9&6ꢄꢀ5WEJꢀEJCPIGUꢀQPN[ꢀDGEQOGꢀ
GHHGEVKXGꢀCHVGTꢀVJKUꢀDKVꢀKUꢀENGCTGFꢄ
ꢂꢂꢃ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
9
ꢌ& ꢀ6
ꢀ4
+ꢇ1ꢁ4
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢃ
4GIKUVGTꢀ
9TKVGꢀ'PCDNG
4
9JGPꢀVJKUꢀTGCFꢌQPN[ꢀDKVꢀKUꢀ1ꢅꢀCUꢀKVꢀKUꢀ
CHVGTꢀCꢀTGUGVꢅꢀVJGꢀ5[UVGOꢀ
%QPHKIWTCVKQPꢀ4GIKUVGTꢅꢀRQTVꢀ&CVCꢀ
&KTGEVKQPꢀ4GIKUVGTUꢅꢀVJGꢀ2QYGTꢀ
%QPVTQNꢀ4GIKUVGTꢅꢀCPFꢀCNNꢀQHꢀVJGꢀ4GCNꢀ
6KOGꢀ%NQEMꢀTGIKUVGTUꢀECPꢀDGꢀYTKVVGPꢄꢀ
9JGPꢀVJKUꢀDKVꢀKUꢀ0ꢅꢀVJGUGꢀTGIKUVGTUꢀCTGꢀ
TGCFꢌQPN[ꢄ
6
ꢁꢈꢂꢆ 9
ꢀ& ꢁ6
ꢁ/
ꢁ4
ꢁꢎꢃꢃꢊꢉ*ꢏꢁ9&6/4
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF 'PCDNG 2GTKQFꢀ5GNGEV
&TKXGꢀ 2QYGTꢀ 9&6ꢀ 5VCVGꢀ 4GIꢀ
4GUGV
4ꢋ9
1Pꢀ
4GUGV
4GUGV %JCPIGꢀ 9TKVGꢀ
'PCDNG 'PCDNG
4ꢋ9
4
ꢂ
4ꢋ9
4%
4%
4ꢋ9
ꢂ
4
ꢂ
4GUGV
ꢂ
ꢂ
214ꢔ 214ꢔ 9&6
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
9&6ꢀ
'PCDNGF
4
+HꢀVJKUꢀTGCFꢌQPN[ꢀDKVꢀKUꢀꢂꢀVJGꢀ9CVEJꢌꢀ
&QIꢀ6KOGTꢀKUꢀGPCDNGFꢄꢀ
ꢏꢌꢆ
2GTKQFꢀ
5GNGEV
4ꢋ9
6JKUꢀHKGNFꢀUGNGEVUꢀJQYꢀNQPIꢀUQHVYCTGꢀ
ECPꢀNGCXGꢀVJGꢀ9CVEJꢌ&QIꢀ6KOGTꢀ
WPCVVGPFGFꢅꢀDGHQTGꢀKVꢀTGUGVUꢀVJGꢀRCTVꢈ
ꢃꢃ
ꢃꢂ
ꢂꢃ
ꢂꢂ
ꢍ
ꢍ
ꢍ
ꢍ
ꢀꢐꢍꢏꢍꢅꢂꢉꢉꢑꢀ2*+ꢀENQEMU
ꢀꢐꢉꢅꢂꢁꢉꢅꢊꢃꢉꢑꢀ2*+ꢀENQEMU
ꢀꢐꢊꢊꢅꢆꢆꢉꢅꢉꢊꢍꢑꢀ2*+ꢀENQEMU
ꢀꢐꢂꢊꢉꢅꢍꢂꢎꢅꢎꢍꢇꢑꢀ2*+ꢀENQEMU
ꢉ
&TKXGꢀ4GUGV
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀCUꢀKVꢀKUꢀCHVGTꢀCꢀ2QYGTꢀ
1Pꢀ4GUGVꢅꢀGZRKTCVKQPꢀQHꢀVJGꢀ9&6ꢀ
FTKXGUꢀVJGꢀ4'5'6ꢀRKPꢀ.QYꢅꢀVQꢀTGUGVꢀ
GZVGTPCNꢀFGXKEGUꢄꢀ9&6ꢀGZRKTCVKQPꢀ
TGUGVUꢀVJGꢀ<ꢇꢃ5ꢂꢇꢊꢀTGICTFNGUUꢀQHꢀVJKUꢀ
DKVꢄ
ꢊ
ꢍ
2QYGTꢀ1Pꢀ
4GUGV
4%
4%
#ꢀ2QYGTꢀ1Pꢀ4GUGVꢀUGVUꢀVJKUꢀDKVꢄꢀꢐ6JKUꢀ
KPENWFGUꢀCꢀ214ꢀUGSWGPEGꢀECWUGFꢀD[ꢀCꢀ
TKUKPIꢀGFIGꢀQPꢀVJGꢀ12/1&ꢂꢀQTꢀ
29472ꢀRKPꢄꢑꢀ4GCFKPIꢀVJKUꢀTGIKUVGTꢀ
ENGCTUꢀVJKUꢀDKVꢄ
9&6ꢀ4GUGV
9&6ꢀGZRKTCVKQPꢀUGVUꢀVJKUꢀDKVꢄꢀ4GCFKPIꢀ
VJKUꢀTGIKUVGTꢀENGCTUꢀKVꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢂꢂ
+ꢇ1ꢁ4
9
ꢌ& ꢀ6
ꢀ4
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢂ
5VCVGꢀ
%JCPIGꢀ
'PCDNGF
4ꢋ9
9JGPꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀYTKVKPIꢀꢉꢃ*ꢀVQꢀVJGꢀ
9&6ꢀ%QOOCPFꢀTGIKUVGTꢀFKUCDNGUꢀVJGꢀ
9&6ꢅꢀCPFꢀYTKVKPIꢀꢃ$ꢃ*ꢀVQꢀKVꢀGPCDNGUꢀ
VJGꢀ9&6ꢄ
ꢃ
4GIKUVGTꢀ
9TKVGꢀ'PCDNG
4
9JGPꢀVJKUꢀTGCFꢌQPN[ꢀDKVꢀKUꢀꢂꢅꢀCUꢀKVꢀKUꢀ
CHVGTꢀCꢀTGUGVꢅꢀVJGꢀ5[UVGOꢀ
%QPHKIWTCVKQPꢀ4GIKUVGTꢅꢀRQTVꢀ&CVCꢀ
&KTGEVKQPꢀ4GIKUVGTUꢅꢀVJGꢀ2QYGTꢀ
%QPVTQNꢀ4GIKUVGTꢅꢀCPFꢀCNNꢀQHꢀVJGꢀ4GCNꢀ
6KOGꢀ%NQEMꢀTGIKUVGTUꢀECPꢀDGꢀYTKVVGPꢄꢀ
9JGPꢀVJKUꢀDKVꢀKUꢀꢃꢅꢀVJGUGꢀTGIKUVGTUꢀCTGꢀ
TGCFꢌQPN[ꢄ
6
ꢁꢈꢒꢆ 9
ꢀ& ꢁ6
ꢁ%
ꢁ4
ꢁꢎꢃꢃꢊꢋ*ꢏꢁ9&6%4
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
9&6ꢀ%QOOCPF
9
4GUGV
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
PꢋC
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ
9&6ꢀ
%QOOCPF
9
5QHVYCTGꢀECPꢀYTKVGꢀVJGꢀHQNNQYKPIꢀ
XCNWGUꢀVQꢀVJKUꢀTGIKUVGTꢅꢀVQꢀCHHGEVꢀVJGꢀ
UVCVWUꢀQHꢀVJGꢀ9&6ꢀCPFꢀ<ꢇꢃ5ꢂꢇꢊꢈ
ꢃ$* 5GVꢀ4GIKUVGTꢀ9TKVGꢀ'PCDNGꢀꢐ9&6/4ꢀ
DKVꢀꢃꢑ
ꢉꢃ* &KUCDNGUꢀ9&6ꢀKHꢀ9&6/4ꢀDKVꢀꢂꢀKUꢀꢂ
ꢉ'* 4GNQCFUꢋ4GUVCTVUꢀ9&6
$ꢃ* 'PCDNGUꢀ9&6ꢀKHꢀ9&6/4ꢀDKVꢀꢂꢀKUꢀꢂ
9TKVKPIꢀCP[ꢀXCNWGꢀQVJGTꢀVJCPꢀꢃ$*ꢀVQꢀ
VJKUꢀTGIKUVGTꢀENGCTUꢀVJGꢀ4GIKUVGTꢀ9TKVGꢀ
'PCDNGꢀDKVꢄ
ꢂꢂꢍ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2
ꢀ4
ꢀ6
ꢀꢐ246ꢑꢀ4
+ꢇ1ꢁ4
241)4#//#$.'ꢁ4'.1#&ꢁ6+/'4ꢁꢎ246ꢏꢁ4')+56'45
See section “Programmable Reload Timers (PRTs)” on page 43, for more about
these registers.
6
ꢁꢂꢃꢆ 246ꢃꢁ6
ꢁ&
ꢁ4
ꢁ. ꢁꢎꢃꢃꢃ%*ꢏꢁ6/&4ꢃ.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ246ꢃꢀ%QWPVGT
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ246ꢃꢀFQYPꢌ
EQWPVGTꢄ
246ꢃꢀ
%QWPVGT
6
ꢁꢂꢄꢆ 246ꢃꢁ6
ꢁ&
ꢁ4
ꢁ* ꢁꢎꢃꢃꢃ&*ꢏꢁ6/&4ꢃ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
/5ꢀ$[VGꢀQHꢀ246ꢃꢀ%QWPVGT
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ /5ꢀD[VGꢀQHꢀ 4ꢋ9
6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ246ꢃꢀFQYPꢌ
EQWPVGTꢄ
246ꢃꢀ
%QWPVGT
6
ꢁꢂꢌꢆ 246ꢃꢁ4
ꢁ4
ꢁ. ꢁꢎꢃꢃꢃ'*ꢏꢁ4.&4ꢃ.
$KV
ꢎ
ꢏ
ꢂ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ246ꢃꢀ4GNQCFꢀ8CNWG
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀVJGꢀXCNWGꢀVJCVꢀKUꢀ
NQCFGFꢀKPVQꢀVJGꢀ246ꢃꢀFQYPꢌEQWPVGTꢅꢀ
YJGPꢀKVꢀKUꢀFGETGOGPVGFꢀVQꢀꢃꢄ
246ꢃꢀ
4GNQCFꢀ
8CNWG
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢂꢊ
+ꢇ1ꢁ4
2
ꢀ4
ꢀ6
ꢀꢐ246ꢑꢀ4
6
ꢁꢂꢅꢆ 246ꢃꢁ6
ꢁ&
ꢁ4
ꢁ. ꢁꢎꢃꢃꢃ%*ꢏꢁ6/&4ꢃ.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ246ꢃꢀ%QWPVGT
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ246ꢃꢀFQYPꢌ
EQWPVGTꢄ
246ꢃꢀ
%QWPVGT
6
ꢁꢂꢉꢆ 246ꢃꢁ6
ꢁ&
ꢁ4
ꢁ* ꢁꢎꢃꢃꢃ&*ꢏꢁ6/&4ꢃ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
/5ꢀ$[VGꢀQHꢀ246ꢃꢀ%QWPVGT
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ /5ꢀD[VGꢀQHꢀ 4ꢋ9
6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀVJGꢀ246ꢃꢀFQYPꢌ
EQWPVGTꢄ
246ꢃꢀ
%QWPVGT
6
ꢁꢂꢋꢆ 246ꢃꢁ4
ꢁ4
ꢁ. ꢁꢎꢃꢃꢃ'*ꢏꢁ4.&4ꢃ.
$KV
ꢎ
ꢏ
ꢂ
ꢆ
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ꢍ
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ꢂ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ246ꢃꢀ4GNQCFꢀ8CNWG
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀVJGꢀXCNWGꢀVJCVꢀKUꢀ
NQCFGFꢀKPVQꢀVJGꢀ246ꢃꢀFQYPꢌEQWPVGTꢅꢀ
YJGPꢀKVꢀKUꢀFGETGOGPVGFꢀVQꢀꢃꢄ
246ꢃꢀ
4GNQCFꢀ
8CNWG
ꢂꢂꢉ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2
ꢀ4
ꢀ6
ꢀꢐ246ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢂꢊꢆ 246ꢃꢁ4
ꢁ4
ꢁ* ꢁꢎꢃꢃꢃ(*ꢏꢁ4.&4ꢃ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
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ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
/5ꢀ$[VGꢀQHꢀ246ꢃꢀ4GNQCFꢀ8CNWG
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ /5ꢀD[VGꢀQHꢀ 4ꢋ9
6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀVJGꢀXCNWGꢀVJCVꢀKUꢀ
NQCFGFꢀKPVQꢀ246ꢃ UꢀFQYPꢌEQWPVGTꢅꢀ
YJGPꢀKVꢀKUꢀFGETGOGPVGFꢀVQꢀꢃꢄ
246ꢃꢀ
4GNQCFꢀ
8CNWG
6
ꢁꢂꢈꢆ 6
ꢁ%
ꢁ4
ꢁꢎꢃꢃꢄꢃ*ꢏꢁ6%4
$KV
ꢎ
ꢏ
6+(ꢃ
4
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
6+(ꢂ
4
6+'ꢂ
4ꢋ9
ꢃ
6+'ꢃ
4ꢋ9
ꢃ
4GUXF
!
6&'ꢂ 6&'ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
ꢃ
ꢃ
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢏ
ꢆꢌꢉ
ꢂꢌꢃ
6+(ꢂꢅꢃ
6+'ꢂꢅꢃ
6&'ꢂꢅꢃ
4
1PGꢀQHꢀVJGUGꢀUVCVWUꢀDKVUꢀKUꢀUGVꢀYJGPꢀCꢀ
246ꢀFGETGOGPVUꢀKVUꢀFQYPꢌEQWPVGTꢀVQꢀ
ꢃꢄꢀ+VꢀKUꢀENGCTGFꢀYJGPꢀUQHVYCTGꢀJCUꢀ
TGCFꢀVJKUꢀTGIKUVGTꢀCPFꢀGKVJGTꢀD[VGꢀQHꢀ
VJGꢀ6/&4ꢄ
4ꢋ9
4ꢋ9
+HꢀQPGꢀQHꢀVJGUGꢀDKVUꢀKUꢀꢂꢅꢀVJGꢀ
EQTTGURQPFKPIꢀ246ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀKVUꢀFQYPꢌEQWPVGTꢀJCUꢀ
EQWPVGFꢀFQYPꢀVQꢀꢃꢀCPFꢀKVꢀJCUꢀUGVꢀVJGꢀ
6+(ꢀDKVꢄ
ꢃ
ꢂ
6JGꢀEQTTGURQPFKPIꢀ246ꢀKUꢀUVQRRGFꢄ
6JGꢀEQTTGURQPFKPIꢀ246ꢀKUꢀTWPPKPIꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢂꢆ
+ꢇ1ꢁ4
2
ꢀ4
ꢀ6
ꢀꢐ246ꢑꢀ4
6
ꢁꢂꢂꢆ 246ꢄꢁ6
ꢁ&
ꢁ4
ꢁ. ꢁꢎꢃꢃꢄꢉ*ꢏꢁ6/&4ꢄ.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ246ꢂꢀ%QWPVGT
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀ246ꢂ UꢀFQYPꢌ
EQWPVGTꢄ
246ꢂꢀ
%QWPVGT
6
ꢁꢂꢒꢆ 246ꢄꢁ6
ꢁ&
ꢁ4
ꢁ* ꢁꢎꢃꢃꢄꢋ*ꢏꢁ6/&4ꢄ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
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ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
/5ꢀ$[VGꢀQHꢀ246ꢂꢀ%QWPVGT
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ /5ꢀD[VGꢀQHꢀ 4ꢋ9
6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀ246ꢂ UꢀFQYPꢌ
EQWPVGTꢄ
246ꢂꢀ
%QWPVGT
6
ꢁꢒꢃꢆ 246ꢄꢁ4
ꢁ4
ꢁ. ꢁꢎꢃꢃꢄꢊ*ꢏꢁ4.&4ꢄ.
$KV
ꢎ
ꢏ
ꢂ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ246ꢂꢀ4GNQCFꢀ8CNWG
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.5ꢀꢇꢀDKVUꢀQHꢀVJGꢀXCNWGꢀVJCVꢀKUꢀ
NQCFGFꢀKPVQꢀ246ꢂ UꢀFQYPꢌEQWPVGTꢅꢀ
YJGPꢀKVꢀKUꢀFGETGOGPVGFꢀVQꢀꢃꢄ
246ꢂꢀ
4GNQCFꢀ
8CNWG
ꢂꢂꢏ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2
ꢀ4
ꢀ6
ꢀꢐ246ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢒꢄꢆ 246ꢄꢁ4
ꢁ4
ꢁ* ꢁꢎꢃꢃꢄꢈ*ꢏꢁ4.&4ꢄ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
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ꢂ
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ꢂ
$KVꢋ(KGNF
4ꢋ9
/5ꢀ$[VGꢀQHꢀ246ꢂꢀ4GNQCFꢀ8CNWG
4ꢋ9
4GUGV
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ /5ꢀD[VGꢀQHꢀ 4ꢋ9
6JGꢀ/5ꢀꢇꢀDKVUꢀQHꢀVJGꢀXCNWGꢀVJCVꢀKUꢀ
NQCFGFꢀKPVQꢀ246ꢂ UꢀFQYPꢌEQWPVGTꢅꢀ
YJGPꢀKVꢀKUꢀFGETGOGPVGFꢀVQꢀꢃꢄ
246ꢂꢀ
4GNQCFꢀ
8CNWG
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢂꢎ
+ꢇ1ꢁ4
4
ꢀ6 ꢀ%
ꢀꢐ46%ꢑꢀ4
4'#.ꢁ6+/'ꢁ%.1%-ꢁꢎ46%ꢏꢁ4')+56'45
See the section titled “Real Time Clock (RTC)” on page 46, for more about these
registers.
6
ꢁꢒꢌꢆ 46%ꢁ%
ꢇ5
ꢁ4
ꢁꢎꢃꢃꢊ(*ꢏꢁ46%%5
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
4GUXF
!
ꢃ
$KVꢋ(KGNF
4ꢋ9
#NCTO
4ꢋ9
ꢃ
+'
4GUXF
%NQEMꢀ5GNGEV
4ꢋ9
4ꢋ9
ꢃ
!
4GUGV
:
ꢃ
ꢃ
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
#NCTO
4ꢋ9
6JGꢀ46%ꢀUGVUꢀVJKUꢀDKVꢀYJGPꢀVJGꢀJQWTUꢅꢀ
OKPWVGUꢅꢀCPFꢀUGEQPFUꢀTGIKUVGTUꢀGSWCNꢀ
VJGꢀRTQITCOOGFꢀCNCTOꢀXCNWGꢄꢀ
5QHVYCTGꢀECPꢀUGVꢀVJKUꢀDKVꢀVQꢀꢃꢅꢀDWVꢀ
GKVJGTꢈ
ꢀYCKVꢀCꢀUGEQPFꢀDGHQTGꢀFQKPIꢀUQꢀQT
ꢀEJCPIGꢀVJGꢀ#NCTOꢀXCNWGꢀDGHQTGꢀ
FQKPIꢀUQꢅꢀVQꢀRTGXGPVꢀVJGꢀEQPVKPWKPIꢀ
OCVEJꢀHTQOꢀTGUGVVKPIꢀ#NCTOꢄ
ꢏ
+'
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ46%ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀVJGꢀ#NCTOꢀDKVꢀKUꢀꢂꢄꢀ+Hꢀ
VJGꢀUGTXKEGꢀTQWVKPGꢀHQTꢀVJKUꢀKPVGTTWRVꢀ
ENGCTUꢀ#NCTOꢀD[ꢀOGVJQFꢀCꢑꢀCDQXGꢅꢀKVꢀ
ENGCTUꢀVJKUꢀDKVꢀFWTKPIꢀVJGꢀOCVEJꢀ
UGEQPFꢀVQꢀCXQKFꢀHWTVJGTꢀKPVGTTWRVUꢄ
ꢉꢌꢊ
%NQEMꢀ5GNGEV 4ꢋ9
ꢃZ 6JGꢀ46%ꢀVCMGUꢀKVUꢀENQEMꢀHTQOꢀVJGꢀ
.(:6#.ꢀCPFꢀ.(':6#.ꢀRKPUꢅꢀYJKEJꢀ
OWUVꢀDGꢀEQPPGEVGFꢀVQꢀCꢀꢊꢍꢄꢎꢏꢇꢀ-*\ꢀ
ET[UVCNꢄ
ꢂꢃ 6JGꢀ46%ꢀVCMGUꢀKVUꢀENQEMꢀHTQOꢀVJGꢀ2%ꢃꢀ
RKPꢅꢀYJKEJꢀOWUVꢀDGꢀRTQITCOOGFꢀCUꢀ
CPꢀKPRWVꢀCPFꢀEQPPGEVGFꢀVQꢀCꢀꢏꢃꢀ*\ꢀ
NKPGꢀHTGSWGPE[ꢄ
ꢂꢂ 6JGꢀ46%ꢀVCMGUꢀKVUꢀENQEMꢀHTQOꢀVJGꢀ2%ꢃꢀ
RKPꢅꢀYJKEJꢀOWUVꢀDGꢀRTQITCOOGFꢀCUꢀ
CPꢀKPRWVꢀCPFꢀEQPPGEVGFꢀVQꢀCꢀꢆꢃꢀ*\ꢀ
NKPGꢀHTGSWGPE[ꢄ
ꢂꢂꢇ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
4
ꢀ6 ꢀ%
ꢀꢐ46%ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢒꢅꢆ 46%ꢁ%
ꢇ5
ꢁ4
ꢁꢎꢃꢃꢊ(*ꢏꢁ46%%5
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF #NCTO
+'
4GUXF
%NQEMꢀ5GNGEV
4ꢋ9
4GUXF
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
!
!
4GUGV
:
ꢃ
ꢃ
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
#NCTO
4ꢋ9
6JGꢀ46%ꢀUGVUꢀVJKUꢀDKVꢀYJGPꢀVJGꢀJQWTUꢅꢀ
OKPWVGUꢅꢀCPFꢀUGEQPFUꢀTGIKUVGTUꢀGSWCNꢀ
VJGꢀRTQITCOOGFꢀCNCTOꢀXCNWGꢄꢀ
5QHVYCTGꢀECPꢀYTKVGꢀCꢀꢃꢀVQꢀVJKUꢀDKVꢀVQꢀ
ꢃꢅꢀDWVꢀUJQWNFꢀEJCPIGꢀVJGꢀ#NCTOꢀXCNWGꢀ
DGHQTGꢀFQKPIꢀUQꢅꢀVQꢀRTGXGPVꢀVJGꢀ
EQPVKPWKPIꢀOCVEJꢀHTQOꢀUGVVKPIꢀ#NCTOꢀ
CICKPꢄ
ꢏ
+'
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ46%ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀVJGꢀ#NCTOꢀDKVꢀKUꢀꢂꢄꢀ
ꢉꢌꢊ
%NQEMꢀ5GNGEV 4ꢋ9
ꢃZ 6JGꢀ46%ꢀVCMGUꢀKVUꢀENQEMꢀHTQOꢀVJGꢀ
.(:6#.ꢀCPFꢀ.(':6#.ꢀRKPUꢅꢀYJKEJꢀ
OWUVꢀDGꢀEQPPGEVGFꢀVQꢀCꢀꢊꢍꢄꢎꢏꢇꢀ-*\ꢀ
ET[UVCNꢄ
ꢂꢃ 6JGꢀ46%ꢀVCMGUꢀKVUꢀENQEMꢀHTQOꢀVJGꢀ2%ꢃꢀ
RKPꢅꢀYJKEJꢀOWUVꢀDGꢀRTQITCOOGFꢀCUꢀ
CPꢀKPRWVꢀCPFꢀEQPPGEVGFꢀVQꢀCꢀꢏꢃꢀ*\ꢀ
NKPGꢀHTGSWGPE[ꢄ
ꢂꢂ 6JGꢀ46%ꢀVCMGUꢀKVUꢀENQEMꢀHTQOꢀVJGꢀ2%ꢃꢀ
RKPꢅꢀYJKEJꢀOWUVꢀDGꢀRTQITCOOGFꢀCUꢀ
CPꢀKPRWVꢀCPFꢀEQPPGEVGFꢀVQꢀCꢀꢆꢃꢀ*\ꢀ
NKPGꢀHTGSWGPE[ꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢂꢁ
+ꢇ1ꢁ4
4
ꢀ6 ꢀ%
ꢀꢐ46%ꢑꢀ4
6
ꢁꢒꢉꢆ 46%ꢁ5
ꢁ4
ꢁꢎꢃꢃꢈꢃ*ꢏꢁ46%5'%
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
ꢃ
4
ꢃ
5GEQPFU
4ꢋ9
4GUGV
0%
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9 +PETGOGPVGFꢀD[ꢀVJGꢀ46%ꢀQPEGꢀRGTꢀ
UGEQPFꢄꢀ$%&ꢀꢆꢁ*ꢀKUꢀHQNNQYGFꢀD[ꢀꢃꢄ
ꢏꢌꢃ
5GEQPFU
6
ꢁꢒꢋꢆ 46%ꢁ/
ꢁ4
ꢁꢎꢃꢃꢈꢄ*ꢏꢁ46%/+0
$KV
ꢎ
ꢏ
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/KPWVGU
4ꢋ9
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
ꢃ
4
ꢃ
4GUGV
0%
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9 +PETGOGPVGFꢀD[ꢀVJGꢀ46%ꢀYJGPꢀVJGꢀ
ꢏꢌꢃ
/KPWVGU
5GEQPFUꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀ
ꢆꢁ*ꢀVQꢀꢃꢄꢀ6JKUꢀ$%&ꢀTGIKUVGTꢀCNUQꢀ
KPETGOGPVUꢀHTQOꢀꢆꢁ*ꢀVQꢀꢃꢄ
6
ꢁꢒꢊꢆ 46%ꢁ*
ꢁ4
ꢁꢃꢃꢈꢌ*ꢏꢁ46%*4
$KV
ꢎ
ꢏ
ꢃ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
ꢃ
4
*QWTU
4ꢋ9
4
4GUGV
0%
0%
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
ꢆꢌꢃ *QWTU
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9
+PETGOGPVGFꢀD[ꢀVJGꢀ46%ꢀYJGPꢀVJGꢀ
/KPWVGUꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢆꢁ*ꢀ
VQꢀꢃꢄꢀ6JKUꢀ$%&ꢀTGIKUVGTꢀKPETGOGPVUꢀ
HTQOꢀꢍꢊ*ꢀVQꢀꢃꢄ
ꢂꢍꢃ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
4
ꢀ6 ꢀ%
ꢀꢐ46%ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢒꢈꢆ 46%ꢁ&
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ꢁꢎꢃꢃꢈꢅ*ꢏꢁ46%&#;
$KV
ꢎ
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4
ꢃ
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4
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4
ꢃ
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4
ꢃ
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ꢂ
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4ꢋ9
4GUGV
ꢃ
4
ꢃ
&C[
4ꢋ9
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9 +PETGOGPVGFꢀD[ꢀVJGꢀ46%ꢀYJGPꢀVJGꢀ
ꢍꢌꢃ
&C[
*QWTUꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢍꢊ*ꢀ
VQꢀꢃꢄꢀ6JKUꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢎꢀ
VQꢀꢂꢄ
6
ꢁꢒꢂꢆ 46%ꢁ&
ꢁ4
ꢁꢎꢃꢃꢈꢉ*ꢏꢁ46%
$KV
ꢎ
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ꢉ
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$KVꢋ(KGNF
4ꢋ9
ꢃ
4
ꢃ
ꢃ
4
ꢃ
&CVG
4ꢋ9
4GUGV
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
ꢆꢌꢃ &CVG
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9
+PETGOGPVGFꢀD[ꢀVJGꢀ46%ꢀYJGPꢀVJGꢀ
*QWTUꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢍꢊ*ꢀ
VQꢀꢃꢄꢀ6JKUꢀ$%&ꢀTGIKUVGTꢀKPETGOGPVUꢀ
HTQOꢀꢍꢇ*ꢅꢀꢊꢃ*ꢅꢀQTꢀꢊꢂ*ꢀVQꢀꢂꢅꢀ
FGRGPFKPIꢀQPꢀVJGꢀOQPVJꢀCPFꢀꢐHQTꢀ
(GDTWCT[ꢑꢀVJGꢀ[GCTꢀCPFꢀEGPVWT[ꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢍꢂ
+ꢇ1ꢁ4
4
ꢀ6 ꢀ%
ꢀꢐ46%ꢑꢀ4
6
ꢁꢒꢒꢆ 46%ꢁ/
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ꢁꢎꢃꢃꢈꢋ*ꢏꢁ46%/1
$KV
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4ꢋ9
ꢃ
4
ꢃ
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4ꢋ9
0%
4GUGV
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢉꢌꢃ
/QPVJ
4ꢋ9
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TGIKUVGTꢀKPETGOGPVUꢀVQꢀꢂꢄꢀ6JKUꢀ$%&ꢀ
TGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢂꢍ*ꢀVQꢀꢂꢄ
6
ꢁꢄꢃꢃꢆ 46%ꢁ;
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4ꢋ9
;GCT
4ꢋ9
4GUGV
0%
0%
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
ꢎꢌꢃ ;GCT
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9
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/QPVJꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢂꢍ*ꢀ
VQꢀꢂꢄꢀ6JKUꢀ$%&ꢀTGIKUVGTꢀKPETGOGPVUꢀ
HTQOꢀꢁꢁ*ꢀVQꢀꢃꢄ
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25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
4
ꢀ6 ꢀ%
ꢀꢐ46%ꢑꢀ4
+ꢇ1ꢁ4
6
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4ꢋ9
4GUGV
ꢃ
4
ꢃ
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4ꢋ9
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9 +PETGOGPVGFꢀD[ꢀVJGꢀ46%ꢀKPꢀCꢀ$%&ꢀ
ꢆꢌꢃ
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HCUJKQPꢅꢀYJGPꢀVJGꢀ;GCTUꢀTGIKUVGTꢀ
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6
ꢁꢄꢃꢌꢆ 46%ꢁ#
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ꢁꢎꢃꢃꢈꢂ*ꢏꢁ#.#4/5
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4ꢋ9
ꢃ
4
ꢃ
#NCTOꢀ5GEQPFU
4ꢋ9
4GUGV
0%
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9 6JGꢀUGEQPFUꢀEQORQPGPVꢀQHꢀVJGꢀ#NCTOꢀ
ꢏꢌꢃ
#NCTOꢀ
5GEQPFU
VKOGꢀꢐ$%&ꢑꢄ
6
ꢁꢄꢃꢅꢆ 46%ꢁ#
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ꢁꢎꢃꢃꢈꢒ*ꢏꢁ#.#4//
$KV
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4ꢋ9
ꢍ
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ꢃ
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4ꢋ9
ꢃ
4
ꢃ
4GUGV
0%
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9 +PETGOGPVGFꢀD[ꢀVJGꢀ46%ꢀYJGPꢀVJGꢀ
ꢏꢌꢃ
;GCT
/QPVJꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢂꢍꢀVQꢀ
ꢂꢄꢀ6JKUꢀTGIKUVGTꢀKPETGOGPVUꢀHTQOꢀꢁꢁꢀVQꢀ
ꢃꢄ
6
ꢁꢄꢃꢉꢆ 46%ꢁ#
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25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢍꢊ
+ꢇ1ꢁ4
&
ꢀ
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6
ꢁꢄꢃꢉꢆ 46%ꢁ#
ꢁ*
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ꢁꢎꢃꢃꢈ#*ꢏꢁ#.#4/*
$KVꢋ(KGNF
4ꢋ9
4GUGV
ꢃ
4
ꢃ
ꢃ
#NCTOꢀ*QWTU
4ꢋ9
4
ꢃ
0%
0%
0%
0%
0%
0%
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
6JKUꢁTGIKUVGTꢁECPꢁQPN[ꢁDGꢁYTKVVGPꢁKHꢁVJGꢁ4GIKUVGTꢁ9TKVGꢁ'PCDNGꢁDKVꢁꢎ9&6/4ꢁꢃꢏꢁKUꢁꢄꢆ
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢉꢌꢃ #NCTOꢀ*QWTU 4ꢋ9
6JGꢀJQWTUꢀEQORQPGPVꢀQHꢀVJGꢀ#NCTOꢀ
VKOGꢀꢐ$%&ꢑꢄ
&+)+6#.ꢁ61ꢁ#0#.1)ꢁ%108'46'4ꢁꢎ&#%ꢏꢁ4')+56'45
See “Digital/Analog Converter (DAC)” on page 48, for more about these regis-
ters.
6
ꢁꢄꢃꢋꢆ &#%ꢁ%
ꢁ4
ꢁꢎꢃꢃꢊꢒ*ꢏꢁ&#%%4
$KV
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ꢉ
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$KVꢋ(KGNF
&CVCꢀꢂꢌꢃ
4GHꢀ5GNGEV
4GUXF 1WVRWVꢀ
'PCDNG
4GUXF
!
4ꢋ9
4ꢋ9
4ꢋ9
!
4ꢋ9
ꢃ
4GUGV
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢏ
ꢆꢌꢉ
ꢍ
&CVCꢀꢂꢌꢃ
4ꢋ9
4ꢋ9
4ꢋ9
6JKUꢀHKGNFꢀEQPVCKPUꢀVJGꢀꢍꢀ.5ꢀD[VGUꢀQHꢀ
VJGꢀꢂꢃꢌDKVꢀFKIKVCNꢀXCNWGꢀVJCVꢀVJGꢀ&#%ꢀ
EQPXGTVUꢀVQꢀCPCNQIꢄ
4GHGTGPEGꢀ
8QNVCIGꢀ
5GNGEV
ꢃꢃ +PVGTPCNꢀTGHGTGPEGꢀꢍꢄꢏ8
ꢃꢂ +PVGTPCNꢀTGHGTGPEGꢀꢉꢄꢍ8
ꢂZ &#%ꢀTGHGTGPEGꢀKUꢀ2#ꢃꢀRKP
1WVRWVꢀ
'PCDNG
#ꢀꢂꢀKPꢀVJKUꢀDKVꢀGPCDNGUꢀVJGꢀ&#%ꢀVQꢀ
FTKXGꢀKVUꢀCPCNQIꢀTGUWNVꢀXQNVCIGꢀQPVQꢀ
VJGꢀ#176ꢀRKPꢄ
ꢂꢍꢉ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
&
ꢀ
ꢀ#
ꢀ%
ꢀꢐ&#%ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢄꢃꢊꢆ &#%ꢁ&
ꢁ4
ꢁꢎꢃꢃꢊ#*ꢏꢁ&#%
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
&CVCꢀꢁꢌꢍ
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ &CVCꢀꢁꢌꢍ
4
9TKVKPIꢀVQꢀVJKUꢀTGIKUVGTꢀUGVUꢀDKVUꢀꢁꢌꢍꢀQHꢀ
VJGꢀFKIKVCNꢀXCNWGꢀVJGꢀ&#%ꢀKUꢀVQꢀ
EQPXGTVꢄꢀ9KVJꢀDKVUꢀꢎꢌꢏꢀQHꢀVJGꢀ&#%%4ꢅꢀ
VJKUꢀXCNWGꢀKUꢀCꢀꢂꢃꢌDKVꢀDKPCT[ꢀHTCEVKQPꢀQHꢀ
VJGꢀUGNGEVGFꢀTGHGTGPEGꢀXQNVCIGꢄꢀ(QTꢀ
GZCORNGꢅꢀꢂꢃꢃꢃꢃꢃꢃꢃꢃꢃ$ꢀOGCPUꢀVJCVꢀ
VJGꢀ&#%ꢀQWVRWVUꢀJCNHꢀQHꢀVJGꢀTGHGTGPEGꢀ
XQNVCIGꢄꢀ6JGꢀ&#%ꢀEQPVKPWQWUN[ꢀ
EQPXGTVUꢀVJKUꢀXCNWGꢅꢀUQꢀTGYTKVKPIꢀVJKUꢀ
TGIKUVGTꢀRTQFWEGUꢀVJGꢀEQTTGURQPFKPIꢀ
XQNVCIGꢀQPꢀ#176ꢀYKVJKPꢀVJGꢀURGEKHKGFꢀ
EQPXGTUKQPꢀVKOGꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢍꢆ
+ꢇ1ꢁ4
#
ꢀ
ꢀ&
ꢀ%
ꢀꢐ#&%ꢑꢀ4
#0#.1)ꢁ61ꢁ&+)+6#.ꢁ%108'46'4ꢁꢎ#&%ꢏꢁ4')+56'45
See section “Analog/Digital Converter (ADC)” on page 49, for more about these
registers.
6
ꢁꢄꢃꢈꢆ #&%ꢁ%
ꢁ4
ꢁꢃꢁꢎꢃꢃꢊꢊ*ꢏꢁ#&%%ꢃ
$KV
ꢎ
ꢏ
ꢆ
4GUXF
!
ꢉ
ꢊ
ꢍ
'PCDNG
4ꢋ9
ꢃ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
4GHꢀ5GNGEV
4ꢋ9
4GUGV
:
:
:
:
:
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢍ
'PCDNG
4ꢋ9
6JKUꢀDKVꢀGPCDNGUꢀVJGꢀ#&%ꢀCPFꢀOWUVꢀDGꢀ
UGVꢀRTKQTꢀVQꢀUVCTVKPIꢀCPꢀ#&%ꢀ
EQPXGTUKQPꢄꢀ9JGPꢀVJKUꢀDKVꢀKUꢀꢃꢅꢀVJGꢀ
#&%ꢀRQYGTUꢀFQYPꢄ
ꢂꢌꢃ
4GHGTGPEGꢀ
8QNVCIGꢀ
5GNGEV
4ꢋ9
ꢃZ #&%ꢀ4GHGTGPEGꢀXQNVCIGꢀKUꢀ2#ꢃꢀRKP
ꢂꢃ +PVGTPCNꢀ4GHGTGPEGꢀꢉꢄꢍꢀ8
ꢂꢂ +PVGTPCNꢀ4GHGTGPEGꢀꢍꢄꢏꢀ8
ꢂꢍꢏ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
#
ꢀ
ꢀ&
ꢀ%
ꢀꢐ#&%ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢄꢃꢂꢆ ꢁ#&%ꢁ%
ꢁ4
ꢁꢄꢁꢎꢃꢃꢊꢈ*ꢏꢁ#&%%ꢄ
$KV
ꢎ
ꢏ
4GUWNVꢀꢂꢌꢃ
4
ꢆ
+'
ꢉ
%%
4
ꢊ
5VCTV
9
ꢍ
ꢃ
ꢂ
ꢃ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%JCPPGNꢀ5GNGEV
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
:
:
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢏ
4GUWNVꢀꢂꢌꢃ
4
4ꢋ9
4
9JGPꢀCꢀEQPXGTUKQPꢀKUꢀEQORNGVGFꢅꢀ
VJGUGꢀDKVUꢀJQNFꢀVJGꢀ.5ꢀDKVUꢀQHꢀVJGꢀ
FKIKVCNꢀXCNWG
ꢆ
+'
+HꢀVJKUꢀDKVꢀKUꢀꢂꢀYJGPꢀVJGꢀ#&%ꢀ
EQORNGVGUꢀCꢀEQPXGTUKQPꢅꢀCPꢀKPVGTTWRVꢀ
KUꢀTGSWGUVGFꢄ
ꢉ
%QPXGTUKQPꢀ
%QORNGVGꢀ
ꢐ%%ꢑ
6JGꢀ#&%ꢀUGVUꢀVJKUꢀDKVꢀYJGPꢀKVꢀ
EQORNGVGUꢀCꢀEQPXGTUKQPꢄꢀ6JKUꢀDKVꢀKUꢀ
ENGCTGFꢀYJGPꢀUQHVYCTGꢀYTKVGUꢀCꢀꢂꢀVQꢀ
VJGꢀ5VCTVꢀDKVꢅꢀVQꢀDGIKPꢀCꢀPGYꢀ
EQPXGTUKQPꢄ
ꢊ
5VCTV
9
9TKVKPIꢀCꢀꢂꢀVQꢀVJKUꢀDKVꢀECWUGUꢀVJGꢀ#&%ꢀ
VQꢀUVCTVꢀCꢀPGYꢀEQPXGTUKQPꢄꢀ+HꢀVJGꢀ#&%ꢀ
JCFꢀCꢀEQPXGTUKQPꢀKPꢀRTQITGUUꢅꢀKVꢀKUꢀ
CDQTVGFꢄ
ꢍꢌꢃ
%JCPPGNꢀ
5GNGEV
4ꢋ9
6JGUGꢀDKVUꢀUGNGEVꢀYJKEJꢀRKPꢀKUꢀ
UCORNGFꢀHQTꢀCꢀEQPXGTUKQPꢄ
ꢃꢃꢃ 2KPꢀ2&ꢃ
ꢃꢃꢂ 2KPꢀ2&ꢂ
ꢃꢂꢃ 2KPꢀ2&ꢍ
ꢃꢂꢂ 2KPꢀ2&ꢊ
ꢂꢃꢃ 2KPꢀ2&ꢉ
ꢂꢃꢂ 2KPꢀ2&ꢆ
ꢂꢂꢃ 2KPꢀ2&ꢏ
ꢂꢂꢂ 2KPꢀ2&ꢎ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢍꢎ
+ꢇ1ꢁ4
#
ꢀ
ꢀ&
ꢀ%
ꢀꢐ#&%ꢑꢀ4
6
ꢁꢄꢃꢒꢆ #&%ꢁ4
ꢁ4
ꢁꢎꢃꢃꢊꢂ*ꢏꢁ#&%
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
4GUWNVꢀꢁꢌꢍ
4
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
#HVGTꢀVJGꢀ#&%ꢀJCUꢀEQORNGVGFꢀCꢀ
ꢎꢌꢃ 4GUWNVꢀꢁꢌꢍ
4
EQPXGTUKQPꢅꢀVJKUꢀTGIKUVGTꢀEQPVCKPUꢀDKVUꢀ
ꢁꢌꢍꢀQHꢀVJGꢀTGUWNVꢀFKIKVCNꢀXCNWGꢄꢀ9KVJꢀ
DKVUꢀꢎꢌꢏꢀQHꢀVJGꢀ#&%%ꢂꢅꢀVJKUꢀXCNWGꢀKUꢀCꢀ
ꢂꢃꢌDKVꢀDKPCT[ꢀHTCEVKQPꢀQHꢀVJGꢀUGNGEVGFꢀ
TGHGTGPEGꢀXQNVCIGꢄꢀ(QTꢀGZCORNGꢅꢀ
ꢂꢃꢃꢃꢃꢃꢃꢃꢃꢃ$ꢀOGCPUꢀVJCVꢀVJGꢀ
XQNVCIGꢀQPꢀVJGꢀUGNGEVGFꢀRKPꢀYCUꢀJCNHꢀ
QHꢀVJGꢀTGHGTGPEGꢀXQNVCIGꢄ
ꢂꢍꢇ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2
ꢀ+
ꢋ1
ꢀ5
ꢀꢐ2+15ꢑꢀ4
+ꢇ1ꢁ4
241)4#//#$.'ꢁ+0276ꢇ176276ꢁ5'37'0%'4ꢁꢎ2+15ꢏꢁ4')+56'45
See section “Programmable I/O Sequencer (PIOS)” on page 52, for more about
these registers.
6
ꢁꢄꢄꢃꢆ 2+15ꢁ%
ꢁ4
ꢁꢎꢃꢃꢊꢃ*ꢏꢁ2+15%4
$KV
ꢎ
ꢏ
+'
ꢆ
+2
ꢉ
ꢊ
4GUXF
!
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF 'PCDNG
%NQEMꢀ5GNGEV
4ꢋ9
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
:
:
:
ꢃ
ꢃ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
ꢏ
'PCDNG
+'
4ꢋ9
4ꢋ9
#ꢀꢂꢀKPꢀVJKUꢀDKVꢀGPCDNGUꢀVJGꢀ2+15ꢄ
#ꢀꢂꢀKPꢀVJKUꢀDKVꢀCNNQYUꢀVJGꢀ2+15ꢀVQꢀ
TGSWGUVꢀCPꢀKPVGTTWRVꢀYJGPꢀKVꢀ
GPEQWPVGTUꢀCPꢀGPVT[ꢀKPꢀKVUꢀ4#/ꢅꢀ
FKTGEVKPIꢀKVꢀVQꢀFQꢀUQꢄ
ꢆ
+2
4ꢋ9
6JGꢀ2+15ꢀUGVUꢀVJKUꢀDKVꢀYJGPꢀKVꢀ
GPEQWPVGTUꢀCPꢀ KPVGTTWRV ꢀGPVT[ꢀKPꢀKVUꢀ
4#/ꢄꢀ+PVGTTWRVꢀUGTXKEGꢀTQWVKPGUꢀYTKVGꢀ
CꢀꢃꢀVQꢀVJKUꢀDKVꢀVQꢀENGCTꢀVJGꢀ2+15ꢀ
KPVGTTWRVꢀTGSWGUVꢄ
ꢂꢌꢃ
%NQEMꢀ5GNGEV 4ꢋ9
6JKUꢀHKGNFꢀFGVGTOKPGUꢀVJGꢀ2+15ꢀENQEMꢀ
HTGSWGPE[
ꢃꢃ 2*+
ꢃꢂ 2*+ꢋꢍꢆꢏ
ꢂꢃ 2*+ꢋꢂꢃꢍꢉ
ꢂꢂ 2*+ꢋꢉꢃꢁꢏ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢍꢁ
+ꢇ1ꢁ4
2
ꢀ+
ꢋ1
ꢀ5
ꢀꢐ2+15ꢑꢀ4
6
ꢁꢄꢄꢄꢆ 2+15ꢁ#
ꢇ6 ꢁ4
ꢁꢎꢃꢃꢊꢄ*ꢏꢁ2+15#6
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
0GZVꢀ#FFTGUU
4
'PVT[ꢀ6[RG
4
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢍ
0GZVꢀ
#FFTGUU
4
5QHVYCTGꢀECPꢀTGCFꢀVJGꢀ0GZVꢀ#FFTGUUꢀ
XCNWGꢀHTQOꢀVJGꢀ4#/ꢀGPVT[ꢀOQUVꢀ
TGEGPVN[ꢀHGVEJGFꢀD[ꢀVJGꢀ2+15ꢅꢀKPꢀVJKUꢀ
HKGNFꢄ
ꢂꢌꢃ
'PVT[ꢀ6[RG
4
5QHVYCTGꢀECPꢀTGCFꢀVJGꢀ'PVT[ꢀ6[RGꢀ
XCNWGꢀHTQOꢀVJGꢀ4#/ꢀGPVT[ꢀOQUVꢀ
TGEGPVN[ꢀHGVEJGFꢀD[ꢀVJGꢀ2+15ꢅꢀKPꢀVJKUꢀ
HKGNFꢄ
6
ꢁꢄꢄꢌꢆ 2+15ꢁ%
ꢁ. ꢁꢎꢃꢃꢊꢌ*ꢏꢁ2+15%.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀD[VGꢀQHꢀ2+15ꢀ%QWPVGT
4
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎꢌꢃ %QWPVGTꢀ.5ꢀ
4
5QHVYCTGꢀECPꢀTGCFꢀVJGꢀ.5ꢀꢇꢀD[VGUꢀQHꢀ
VJGꢀEWTTGPVꢀ2+15ꢀ%QWPVGTꢀXCNWGꢀHTQOꢀ
VJKUꢀTGIKUVGTꢄ
D[VG
6
ꢁꢄꢄꢅꢆ 2+15ꢁ%
ꢁ* ꢁꢎꢃꢃꢊꢅ*ꢏꢁ2+15%*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
/5ꢀD[VGꢀQHꢀ2+15ꢀ%QWPVGT
4
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
ꢎꢌꢃ %QWPVGTꢀ/5ꢀ
D[VG
4ꢇ9 8CNWG &GUETKRVKQP
4
5QHVYCTGꢀECPꢀTGCFꢀVJGꢀ/5ꢀꢇꢀD[VGUꢀQHꢀ
VJGꢀ2+15ꢀ%QWPVGTꢀXCNWGꢅꢀCVꢀVJGꢀVKOGꢀ
VJCVꢀ2+15%.ꢀYCUꢀNCUVꢀTGCFꢅꢀHTQOꢀVJKUꢀ
TGIKUVGTꢄ
ꢂꢊꢃ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢇ1ꢁ4
#5;0%ꢁ5'4+#.ꢁ%1//70+%#6+105ꢁ+06'4(#%'ꢁꢎ#5%+ꢏꢁ4')+56'45
See section “Clocked Serial Input/Output Module (CSI/O)” on page 67, for more
detail about these registers.
6
ꢁꢄꢄꢉꢆ #5%+ꢃꢁ%
ꢁ4
ꢁ#ꢁꢎꢃꢃꢃꢃ*ꢏꢁ%06.#ꢃ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
/2'
4'
6'
4GUGTX /2$4ꢋ /1&ꢍ /1&ꢂ /1&ꢃ
GF
4ꢋ9
ꢂ
'(4
4ꢋ9
:
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
/WNVKꢌ
RTQEGUUQTꢀ
/QFGꢀ
4ꢋ9
+HꢀVJKUꢀDKVꢀCPFꢀVJGꢀ/2ꢀDKVꢀKPꢀ%06.$ꢀCTGꢀ
DQVJꢀꢂꢅꢀQPN[ꢀTGEGKXGFꢀEJCTCEVGTUꢀ
JCXKPIꢀCꢀꢂꢀKPꢀCPꢀCFFKVKQPCNꢀDKVꢀ
'PCDNG
DGVYGGPꢀVJGꢀNCUVꢀFCVCꢀDKVꢀCPFꢀVJGꢀUVQRꢀ
DKVꢀCTGꢀRNCEGFꢀKPꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+HꢀGKVJGTꢀ
VJGꢀ/2ꢀDKVꢀQTꢀVJKUꢀDKVꢀKUꢀꢃꢅꢀCNNꢀTGEGKXGFꢀ
EJCTCEVGTUꢀCTGꢀRNCEGFꢀKPꢀVJGꢀ4Zꢀ(+(1ꢄ
ꢏ
ꢆ
ꢉ
ꢊ
4GEGKXGꢀ
'PCDNG
4ꢋ9
4ꢋ9
4ꢋ9
#ꢀꢂꢀKPꢀVJKUꢀDKVꢀGPCDNGUꢀVJGꢀTGEGKXGTꢄꢀ
9TKVKPIꢀCꢀꢃꢀUVQRUꢀTGEGRVKQPꢄ
6TCPUOKVꢀ
'PCDNG
#ꢀꢂꢀKPꢀVJKUꢀDKVꢀGPCDNGUꢀVJGꢀVTCPUOKVVGTꢄꢀ
9TKVKPIꢀCꢀꢃꢀUVQRUꢀVTCPUOKUUKQPꢄ
4GUGTXGF
1PꢀQVJGTꢀꢂꢇꢃꢀFGXKEGUꢀVJKUꢀDKVꢀ
EQPVTQNNGFꢀVJGꢀ465ꢃꢀQWVRWVꢄ
/2ꢀ$KVꢀ4EXꢋ 4ꢋ9
'TTQTꢀ(NCIꢀ
4GUGV
4GCFKPIꢀVJKUꢀDKVꢀTGVWTPUꢀVJGꢀXCNWGꢀQHꢀ
VJGꢀOWNVKRTQEGUUQTꢀꢐ/2ꢑꢀDKVꢄꢀ4GCFꢀVJKUꢀ
TGIKUVGTꢀDGHQTGꢀTGCFKPIꢀVJGꢀ4&4ꢄꢀ
9TKVKPIꢀCꢀꢃꢀVQꢀVJKUꢀDKVꢀENGCTUꢀVJGꢀ
1840ꢅꢀ('ꢅꢀ2'ꢅꢀCPFꢀ$TGCMꢀ&GVGEVꢀDKVUꢄꢀ
9TKVKPIꢀCꢀꢂꢀJCUꢀPQꢀGHHGEVꢄ
ꢍ
ꢂ
ꢃ
/1&ꢍ
/1&ꢂ
/1&ꢃ
4ꢋ9
4ꢋ9
4ꢋ9
ꢃ
ꢂ
ꢎꢀDKVꢀFCVCꢀꢐ6ZꢀCPFꢀ4Zꢑ
ꢇꢀDKVꢀFCVC
ꢃ
ꢂ
0QꢀRCTKV[ꢀꢐ6ZꢀCPFꢀ4Zꢑ
2CTKV[ꢀIGPGTCVGFꢀꢐ6ZꢑꢅꢀEJGEMGFꢀꢐ4Zꢑ
ꢃ
ꢂ
ꢂꢀ5VQRꢀDKVꢀVTCPUOKVVGF
ꢍꢀ5VQRꢀDKVUꢀVTCPUOKVVGF
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢊꢂ
+ꢇ1ꢁ4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
6
ꢁꢄꢄꢋꢆ #5%+ꢄꢁ%
ꢁ4
ꢁ#ꢁꢎꢃꢃꢃꢄ*ꢏꢁ%06.#ꢄ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
/2'
4'
6'
4GUXF /2$4ꢋ /1&ꢍ /1&ꢂ /1&ꢃ
'(4
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
!
4ꢋ9
ꢂ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4GUGV
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
All bits in this register are as described in Table 114.
6
ꢁꢄꢄꢊꢆ #5%+ꢃꢁ%
ꢁ4
ꢁ$ꢁꢎꢃꢃꢃꢌ*ꢏꢁ%06.$ꢃ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF /2$6
/2
%65ꢋ
25
2'1
&4
5RGGFꢀ5GNGEV
4ꢋ9
4ꢋ9
:
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢂ
4GUGV
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
/WNVKꢌꢀ
2TQEGUUQTꢀ
$KVꢀ6Z
4ꢋ9
+HꢀVJGꢀ/2ꢀDKVꢀꢐDKVꢀꢏꢑꢀKUꢀꢂꢅꢀVJKUꢀDKVꢀ
FGHKPGUꢀVJGꢀXCNWGꢀVQꢀUGPFꢀKPꢀVJGꢀ/2ꢀ
DKVꢀYKVJꢀVJGꢀPGZVꢀEJCTCEVGTꢀYTKVVGPꢀVQꢀ
VJGꢀ6TCPUOKVꢀ&CVCꢀ4GIKUVGTꢄ
ꢏ
/WNVKRTQꢌ
EGUUQTꢀ
/QFG
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ#5%+ꢀUGPFUꢅꢀCPFꢀ
GZRGEVUꢀVQꢀTGEGKXGꢅꢀCPꢀGZVTCꢀDKVꢀCHVGTꢀ
VJGꢀNCUVꢀFCVCꢀDKVꢄꢀ6JGꢀGZVTCꢀDKVꢀKUꢀꢂꢀKPꢀ
CFFTGUUꢀEJCTCEVGTUꢀVJCVꢀDGIKPꢀHTCOGUꢀ
CPFꢀꢃꢀKPꢀHQNNQYKPIꢀFCVCꢀEJCTCEVGTUꢄ
ꢆ
%65ꢋ25
4ꢋ9
4GCFKPIꢀVJKUꢀRKPꢀTGVWTPUꢀVJGꢀUVCVGꢀQHꢀ
VJGꢀ%65ꢀRKPꢀꢐꢃꢀKUꢀ.QYꢅꢀꢂꢀKUꢀ*KIJꢑꢄꢀ(QTꢀ
YTKVKPIꢅꢀVJKUꢀDKVꢀKUꢀ25ꢄꢀ+HꢀDKVUꢀꢍ ꢃꢀKPꢀ
VJKUꢀTGIKUVGTꢀCTGꢀPQVꢀꢂꢂꢂꢀCPFꢀVJGꢀ$4)ꢀ
/QFGꢀDKVꢀKPꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀ
TGIKUVGTꢀKUꢀꢃꢅꢀ25ꢀFGVGTOKPGUꢀYJGVJGTꢀ
VJGꢀ2*+ꢀENQEMꢀKUꢀRTGUECNGFꢀD[ꢀꢂꢃꢀꢐHQTꢀ
ꢃꢑꢀQTꢀꢊꢃꢀꢐHQTꢀꢂꢑꢀCUꢀVJGꢀHKTUVꢀUVCIGꢀKPꢀ
#5%+ꢀENQEMKPIꢄ
ꢉ
ꢊ
2CTKV[ꢀ'XGPꢋ 4ꢋ9
1FF
+Hꢀ/1&ꢂꢀꢐ%06.#ꢀDKVꢀꢂꢑꢀKUꢀꢂꢅꢀVJKUꢀDKVꢀ
UGNGEVUꢀYJGVJGTꢀRCTKV[ꢀKUꢀIGPGTCVGFꢀ
CPFꢀEJGEMGFꢀCUꢀGXGPꢀꢐHQTꢀꢃꢑꢀQTꢀQFFꢀ
ꢐHQTꢀꢂꢑꢄ
&4
4ꢋ9
ꢃ
ꢂ
6JGꢀ#5%+ꢀFKXKFGUꢀKVUꢀDCUKEꢀENQEMꢀD[ꢀ
ꢂꢏꢀVQꢀQDVCKPꢀKVUꢀDKVꢀTCVGꢄꢀ
6JGꢀ#5%+ꢀFKXKFGUꢀKVUꢀDCUKEꢀENQEMꢀD[ꢀ
ꢏꢉꢀVQꢀQDVCKPꢀKVUꢀDKVꢀTCVGꢄ
ꢂꢊꢍ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢇ1ꢁ4
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢍ ꢃ
5RGGFꢀ
5GNGEV
4ꢋ9
ꢂꢂꢂ &QꢀPQVꢀRTQITCOꢀVJKUꢀXCNWGꢄ
ꢐQVJGTꢑ +HꢀVJGꢀ$4)ꢃꢀ/QFGꢀDKVꢀKUꢀꢂꢅꢀVJGꢀQWVRWVꢀ
QHꢀVJGꢀPGYꢀ$4)ꢀKUꢀVJGꢀDCUKEꢀENQEMꢀQHꢀ
VJGꢀ#5%+ꢄꢀ+Hꢀ$4)ꢃꢀ/QFGꢀKUꢀꢃꢅꢀVJGUGꢀ
DKVUꢀFGVGTOKPGꢀYJCVꢀVJGꢀQWVRWVꢀQHꢀVJGꢀ
2TGUECNGTꢀKUꢀFKXKFGFꢀD[ꢅꢀVQꢀQDVCKPꢀ
DCUKEꢀENQEMꢀHQTꢀVJGꢀ#5%+ꢈ
WUGFꢀCUꢀKU
ꢃꢃꢃ &KXKFGꢀD[ꢀꢍ
ꢃꢃꢂ &KXKFGꢀD[ꢀ4
ꢃꢂꢃ &KXKFGꢀD[ꢀꢇ
ꢃꢂꢂ &KXKFGꢀD[ꢀꢂꢏ
ꢂꢃꢃ &KXKFGꢀD[ꢀꢊꢍ
ꢂꢃꢂ &KXKFGꢀD[ꢀꢏꢉ
ꢂꢂꢃ 6JGꢀ#5%+ꢀFKXKFGUꢀVJGꢀDCUKEꢀENQEMꢀD[ꢀ
ꢂꢏꢀQTꢀꢏꢉꢀVQꢀQDVCKPꢀVJGꢀDKVꢀTCVGꢄ
6
ꢁꢄꢄꢈꢆ #5%+ꢄꢁ%
ꢁ4
ꢁ$ꢁꢎꢃꢃꢃꢅ*ꢏꢁ%06.$ꢄ
$KV
ꢎ
ꢏ
/2
4ꢋ9
ꢃ
ꢆ
ꢉ
ꢊ
&4
4ꢋ9
ꢃ
ꢍ
ꢂ
ꢃ
ꢂ
$KVꢋ(KGNF /2$6
25
2'1
4ꢋ9
ꢃ
5RGGFꢀ5GNGEV
4ꢋ9
4ꢋ9
:
4ꢋ9
ꢃ
4ꢋ9
ꢂ
4GUGV
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
All bits in this register are as described in Table 116, except that bit 5 has no func-
tion in write operations on the Z80S183 ASCI1.
6
ꢁꢄꢄꢂꢆ #5%+ꢃꢁ5
ꢁ4
ꢁꢎꢃꢃꢃꢉ*ꢏꢁ56#6ꢃ
$KV
ꢎ
ꢏ
ꢆ
2'
4
ꢉ
('
4
ꢊ
4+'
4ꢋ9
ꢃ
ꢍ
ꢂ
ꢃ
6+'
4ꢋ9
ꢃ
$KVꢋ(KGNF
4ꢋ9
4&4( 1840
&%&ꢃ 6&4'
4
ꢃ
4
ꢃ
4
4
ꢃ
4GUGV
ꢃ
ꢃ
RKP
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
4&4(
4
6JGꢀ<ꢇꢃ5ꢂꢇꢊꢀUGVUꢀVJKUꢀDKVꢀYJGPꢀCꢀ
EJCTCEVGTꢀKUꢀTGEGKXGFꢄꢀ4GCFKPIꢀVJGꢀNCUVꢀ
TGEGKXGFꢀD[VGꢀHTQOꢀVJGꢀ4Zꢀ(+(1ꢀENGCTUꢀ
VJKUꢀDKVꢄꢀ5GGꢀ0QVGꢀDGNQYꢄ
ꢏ
1840
4
6JKUꢀDKVꢀKUꢀUGVꢀYJGPꢀVJGꢀNCUVꢀEJCTCEVGTꢀ
TGEGKXGFꢀDGHQTGꢀCPꢀ1XGTTWPꢀEQPFKVKQPꢀ
EQOGUꢀVQꢀVJGꢀVQRꢀQHꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+VꢀKUꢀ
ENGCTGFꢀYJGPꢀCꢀꢃꢀKUꢀYTKVVGPꢀVQꢀVJGꢀ
'(4ꢀDKVꢀKPꢀ%06.ꢃꢄꢀ5GGꢀ0QVGꢀDGNQYꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢊꢊ
+ꢇ1ꢁ4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢆ
2'
4
6JKUꢀDKVꢀKUꢀUGVꢀKHꢀRCTKV[ꢀKUꢀGPCDNGFꢅꢀCPFꢀ
CꢀEJCTCEVGTꢀYKVJꢀCꢀ2CTKV[ꢀ'TTQTꢀEQOGUꢀ
VQꢀVJGꢀVQRꢀQHꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+VꢀKUꢀENGCTGFꢀ
YJGPꢀCꢀꢃꢀKUꢀYTKVVGPꢀVQꢀVJGꢀ'(4ꢀDKVꢀKPꢀ
%06.ꢃꢄꢀ5GGꢀ0QVGꢀDGNQYꢄ
ꢉ
('
4
6JKUꢀDKVꢀKUꢀUGVꢀKHꢀCꢀEJCTCEVGTꢀYKVJꢀCꢀ
(TCOKPIꢀ'TTQTꢀꢐQPGꢀKPꢀYJKEJꢀVJGꢀ5VQRꢀ
DKVꢀYCUꢀUCORNGFꢀCUꢀꢃꢑꢀEQOGUꢀVQꢀVJGꢀ
VQRꢀQHꢀVJGꢀ4Zꢀ(+(1ꢄꢀ+VꢀKUꢀENGCTGFꢀYJGPꢀ
CꢀꢃꢀKUꢀYTKVVGPꢀVQꢀVJGꢀ'(4ꢀDKVꢀKPꢀ
%06.ꢃꢄꢀ5GGꢀ0QVGꢀDGNQYꢄ
ꢊ
4+'
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ#5%+ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀCP[ꢀQHꢀVJGꢀHNCIUꢀ
1840ꢅꢀ2'ꢅꢀ('ꢅꢀQTꢀ$TGCMꢀ&GVGEVꢀKUꢀUGVꢅꢀ
QTꢀKHꢀDKVꢀꢎꢀQHꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀ
TGIKUVGTꢀKUꢀꢃꢀCPFꢀRDRFꢀKUꢀꢂꢅꢀQTꢀKHꢀDKVꢀꢏꢀ
QHꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀTGIKUVGTꢀKUꢀꢃꢀ
CPFꢀ&%&ꢃꢀKUꢀ.QYꢄ
ꢍ
ꢂ
&%&ꢃ
6&4'
4
4
6JKUꢀDKVꢀKUꢀꢂꢀYJGPGXGTꢀVJGꢀDCD0ꢀRKPꢀ
KUꢀ*KIJꢄꢀ9JGPꢀ&%&ꢃꢀIQGUꢀ.QYꢅꢀVJGꢀ
PGZVꢀTGCFꢀQHꢀVJKUꢀTGIKUVGTꢀTGVWTPUꢀCꢀꢂꢄꢀ
6JGꢀPGZVꢀTGCFꢀTGVWTPUꢀCꢀꢃꢀKHꢀ&%&ꢃꢀKUꢀ
UVKNNꢀ.QYꢄꢀ
6JKUꢀDKVꢀKUꢀENGCTGFꢀYJGPꢀUQHVYCTGꢀ
YTKVGUꢀCꢀEJCTCEVGTꢀVQꢀVJGꢀ6&4ꢄꢀ+VꢀKUꢀ
UGVꢀYJGPꢀVJGꢀEJCTCEVGTꢀNGCXGUꢀVJGꢀ
6&4ꢀHQTꢀVTCPUOKUUKQPꢅꢀD[ꢀ4GUGVꢅꢀCPFꢀ
KPꢀ+ꢋ1ꢀ5VQRꢀOQFGꢄꢀ+VꢀKUꢀENGCTGFꢀKHꢀDKVꢀꢆꢀ
QHꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀTGIKUVGTꢀKUꢀꢃꢀ
CPFꢀ%65ꢃꢀKUꢀ*KIJꢄ
ꢃ
6+'
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ#5%+ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀ6&4'ꢀKUꢀꢂꢄ
0QVGꢐꢁ6JGꢀ4&4(ꢅꢀ1840ꢅꢀ2'ꢅꢀCPFꢀ('ꢀDKVUꢀCTGꢀENGCTGFꢀD[ꢀ4GUGVꢅꢀFWTKPIꢀ+ꢋ1ꢀ5VQRꢀOQFGꢅꢀ
CPFꢀHQTꢀ#5%+ꢃꢅꢀKHꢀVJGꢀ&%&ꢀ&KUCDNGꢀDKVꢀKPꢀVJGꢀ'ZVGPUKQPꢀ%QPVTQNꢀTGIKUVGTꢀKUꢀꢃꢀCPFꢀ&%&ꢃꢀ
KUꢀ*KIJꢄ
6
ꢁꢄꢄꢒꢆ #5%+ꢄꢁ5
ꢁ4
ꢁꢎꢃꢃꢃꢋ*ꢏꢁ56#6ꢄ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4&4( 1840
2'
('
4+'
4GUGTX 6&4'
GF
6+'
4ꢋ9
4
ꢃ
4
ꢃ
4
ꢃ
4
ꢃ
4ꢋ9
ꢃ
4
4
ꢃ
4ꢋ9
ꢃ
4GUGV
RKP
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
This register is as described in Table 118, except that bit 2 has no function for
Z80S183 ASCI1.
ꢂꢊꢉ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢄꢌꢃꢆ #5%+ꢃꢁ6 ꢁ&
ꢁ4
ꢁꢎꢃꢃꢃꢊ*ꢏꢁ6&4ꢃ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%JCTCEVGTꢀVQꢀ6Z
9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ 6ZꢀEJCTCEVGT 4ꢋ9
5QHVYCTGꢀECPꢀYTKVGꢀCꢀEJCTCEVGTꢀVQꢀDGꢀ
VTCPUOKVVGFꢀVQꢀVJKUꢀTGIKUVGTꢅꢀYJGPꢀVJGꢀ
6&4'ꢀHNCIꢀKPꢀ56#6ꢃꢀKUꢀꢂꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢊꢆ
+ꢇ1ꢁ4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
6
ꢁꢄꢌꢄꢆ #5%+ꢄꢁ6 ꢁ&
ꢁ4
ꢁꢎꢃꢃꢃꢈ*ꢏꢁ6&4ꢄ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
%JCTCEVGTꢀVQꢀ6Z
9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ 6ZꢀEJCTCEVGT 4ꢋ9
5QHVYCTGꢀECPꢀYTKVGꢀCꢀEJCTCEVGTꢀVQꢀDGꢀ
VTCPUOKVVGFꢀVQꢀVJKUꢀTGIKUVGTꢅꢀYJGPꢀVJGꢀ
6&4'ꢀHNCIꢀKPꢀ56#6ꢂꢀKUꢀꢂꢄ
6
ꢁꢄꢌꢌꢆ #5%+ꢃꢁ4 ꢁ&
ꢁ4
ꢁꢎꢃꢃꢃꢂ*ꢏꢁ4&4ꢃ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
4GEGKXGFꢀ%JCTCEVGT
4
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ 4ZꢀEJCTCEVGT 4ꢋ9
9JGPꢀVJGꢀ4&4(ꢀHNCIꢀKPꢀ56#6ꢃꢀKUꢀꢂꢅꢀ
UQHVYCTGꢀECPꢀTGCFꢀCꢀTGEGKXGFꢀ
EJCTCEVGTꢀHTQOꢀVJKUꢀTGIKUVGTꢄ
6
ꢁꢄꢌꢅꢆ #5%+ꢄꢁ4 ꢁ&
ꢁ4
ꢁꢎꢃꢃꢃꢒ*ꢏꢁ4&4ꢄ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
4GEGKXGFꢀ%JCTCEVGT
4
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ 4ZꢀEJCTCEVGT 4ꢋ9
9JGPꢀVJGꢀ4&4(ꢀHNCIꢀKPꢀ56#6ꢂꢀKUꢀꢂꢅꢀ
UQHVYCTGꢀECPꢀTGCFꢀCꢀTGEGKXGFꢀ
EJCTCEVGTꢀHTQOꢀVJKUꢀTGIKUVGTꢄ
ꢂꢊꢏ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢄꢌꢉꢆ #5%+ꢃꢁ'
ꢁ%
ꢁ4
ꢁꢎꢃꢃꢄꢌ*ꢏꢁ#5':6ꢃ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4&+& &%&ꢃꢀ %65ꢃꢀ
:ꢂꢀ
$4)ꢀ 5VCTVꢀ+'
4Z
6Z
&KUCDNG &KUCDNG %NQEM /QFG
$TGCM $TGCMꢋ
6Z'PF
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4
ꢃ
4ꢋ9
ꢃ
4GUGV
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
4Zꢀ&CVCꢀ
+PVGTTWRVꢀ
&KUCDNG
4ꢋ9
+Hꢀ4+'ꢀꢐ56#6ꢀDKVꢀꢊꢑꢀCPFꢀVJKUꢀDKVꢀCTGꢀ
DQVJꢀꢂꢅꢀVJGꢀ#5%+ꢀTGSWGUVUꢀTGEGKXGꢀ
KPVGTTWRVUꢀQPN[ꢀYJGPꢀ1840ꢅꢀ2'ꢅꢀQTꢀ('ꢀ
KUꢀUGVꢄꢀ+Hꢀ4+'ꢀKUꢀꢂꢀCPFꢀVJKUꢀDKVꢀKUꢀꢃꢅꢀVJGꢀ
#5%+ꢀCNUQꢀTGSWGUVUꢀKPVGTTWRVUꢀYJGPꢀ
4&4(ꢀKUꢀUGVꢀꢐHQTꢀGCEJꢀTGEGKXGFꢀ
EJCTCEVGTꢑꢄꢀ+Hꢀ4+'ꢀKUꢀꢃꢀVJKUꢀDKVꢀJCUꢀPQꢀ
GHHGEVꢄ
ꢏ
ꢆ
&%&ꢃꢀ
&KUCDNG
4ꢋ9
4ꢋ9
ꢃ
ꢂ
&%&ꢃꢀCWVQꢌGPCDNGUꢀVJGꢀTGEGKXGT
&%&ꢃꢀJCUꢀPQꢀGHHGEVꢀQPꢀVJGꢀTGEGKXGT
%65ꢃꢀ
&KUCDNG
ꢃ
ꢂ
%65ꢃꢀCWVQꢌGPCDNGUꢀVJGꢀVTCPUOKVVGT
%65ꢃꢀJCUꢀPQꢀGHHGEVꢀQPꢀVJGꢀVTCPUOKVVGT
ꢉ
ꢊ
:ꢂꢀ%NQEM
4ꢋ9
4ꢋ9
ꢃ
ꢃ
#NYC[UꢀꢃꢀQPꢀVJGꢀ<ꢇꢃ5ꢂꢇꢊꢄ
$4)ꢀ/QFG
6JGꢀ55ꢀDKVUꢀKPꢀ%QPVTQNꢀ4GIKUVGTꢀ$ꢀ
FGVGTOKPGꢀVJGꢀHCEVQTꢀD[ꢀYJKEJꢀVJGꢀ
2TGUECNGTꢀQWVRWVꢀKUꢀFKXKFGFꢅꢀVQꢀQDVCKPꢀ
VJGꢀ#5%+ UꢀDCUKEꢀENQEMꢄ
ꢂ
6JGꢀ#5%+ UꢀDCUKEꢀENQEMꢀEQOGUꢀHTQOꢀ
VJGꢀPGYꢀ$4)ꢄ
ꢍ
ꢂ
5VCTVꢀ+'
4Z$TGCM
4ꢋ9
4
+HꢀVJKUꢀDKVꢀCPFꢀ4+'ꢀCTGꢀDQVJꢀꢂꢅꢀVJGꢀ
#5%+ꢀTGSWGUVUꢀCPꢀKPVGTTWRVꢀYJGPꢀVJGꢀ
UVCTVꢀQHꢀCꢀUVCTVꢀDKVꢀKUꢀFGVGEVGFꢅꢀHQTꢀ
CWVQꢌDCWFKPIꢄꢀ9TKVKPIꢀCꢀꢃꢀVQꢀVJKUꢀDKVꢀ
ENGCTUꢀVJGꢀKPVGTTWRVꢀTGSWGUVꢄꢀ
6JKUꢀDKVꢀKUꢀꢂꢀKHꢀVJGꢀTGEGKXGTꢀJCUꢀ
FGVGEVGFꢀCꢀ$TGCMꢀEQPFKVKQPꢅꢀVJCVꢀKUꢅꢀKHꢀ
CNNꢀDKVUꢀKPꢀCꢀEJCTCEVGTꢅꢀKPENWFKPIꢀVJGꢀ
5VQRꢀDKVꢅꢀCTGꢀꢃꢄꢀ6JGꢀCNNꢌꢃꢀEJCTCEVGTꢀKUꢀ
RNCEGFꢀKPꢀVJGꢀ4Zꢀ(+(1ꢀKHꢀVJGTGꢀKUꢀTQQOꢅꢀ
DWVꢀVJGꢀTGEGKXGTꢀFQGUꢀPQVꢀCUUGODNGꢀ
CP[ꢀOQTGꢀEJCTCEVGTUꢀWPVKNꢀVJGꢀ4:#ꢀRKPꢀ
JCUꢀTGVWTPGFꢀ*KIJꢄ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢊꢎ
+ꢇ1ꢁ4
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
4ꢋ9
ꢃ
6Z$TGCMꢋ
6Z'PF
9TKVKPIꢀCꢀꢂꢀVQꢀVJKUꢀDKVꢀOCMGUꢀVJGꢀ
VTCPUOKVVGTꢀFTKXGꢀ6:#ꢀ.QYꢀVQꢀUGPFꢀCꢀ
$TGCMꢀEQPFKVKQPꢅꢀWPVKNꢀUQHVYCTGꢀYTKVGUꢀ
CꢀꢃꢀVQꢀVJKUꢀDKVꢄꢀ6JKUꢀDKVꢀTGCFUꢀCUꢀꢃꢀ
YJKNGꢀCꢀEJCTCEVGTꢀKUꢀVTCPUOKVVGFꢅꢀDWVꢀ
DGEQOGUꢀꢂꢀYJGPꢀVJGꢀPWODGTꢀQHꢀ5VQRꢀ
DKVUꢀUGNGEVGFꢀD[ꢀ/1&ꢃꢀKPꢀ%06.#ꢀ
JCXGꢀDGGPꢀUGPVꢄ
6
ꢁꢄꢌꢋꢆ #5%+ꢄꢁ'
ꢁ%
ꢁ4
ꢁꢎꢃꢃꢄꢅ*ꢏꢁ#5':6ꢄ
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4&+&
4GUXF
!
:ꢂꢀ
%NQEM /QFG
$4)ꢀ 5VCTVꢀ+'
4Z
6Z
$TGCM $TGCMꢋ
6Z'PF
4ꢋ9
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4ꢋ9
ꢃ
4
ꢃ
4ꢋ9
ꢃ
4GUGV
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVGꢀ!ꢀꢔꢀ0QVꢀ#RRNKECDNG
This register is as described in the previous table, except that bits 6–5 have no
function for Z80S183 ASCI1.
6
ꢁꢄꢌꢊꢆ #5%+ꢃꢁ6 ꢁ%
ꢁ. ꢁꢎꢃꢃꢄ#*ꢏꢁ#56%ꢃ.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.GCUVꢀ5KIPKHKECPVꢀꢇꢀDKVUꢀQHꢀVJGꢀ
#5%+ꢃꢀ$CWFꢀ4CVGꢀ)GPGTCVQT Uꢀ6KOGꢀ
%QPUVCPVꢄ
6KOGꢀ
%QPUVCPV
ꢂꢊꢇ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
#
ꢀ5
ꢀ%
ꢀ+
ꢀꢐ#5%+ꢑꢀ4
+ꢇ1ꢁ4
6
ꢁꢄꢌꢈꢆ #5%+ꢃꢁ6 ꢁ%
ꢁ* ꢁꢎꢃꢃꢄ$*ꢏꢁ#56%ꢃ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ /5ꢀD[VGꢀQHꢀ 4ꢋ9
6JGꢀ/QUVꢀ5KIPKHKECPVꢀꢇꢀDKVUꢀQHꢀVJGꢀ
#5%+ꢃꢀ$CWFꢀ4CVGꢀ)GPGTCVQT Uꢀ6KOGꢀ
%QPUVCPVꢄ
6KOGꢀ
%QPUVCPV
6
ꢁꢄꢌꢂꢆ #5%+ꢄꢁ6 ꢁ%
ꢁ. ꢁꢎꢃꢃꢄ%*ꢏꢁ#56%ꢄ.
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ .5ꢀD[VGꢀQHꢀ
4ꢋ9
6JGꢀ.GCUVꢀ5KIPKHKECPVꢀꢇꢀDKVUꢀQHꢀVJGꢀ
#5%+ꢂꢀ$CWFꢀ4CVGꢀ)GPGTCVQT Uꢀ6KOGꢀ
%QPUVCPVꢄ
6KOGꢀ
%QPUVCPV
6
ꢁꢄꢌꢒꢆ #5%+ꢃꢁ6 ꢁ%
ꢁ* ꢁꢎꢃꢃꢄ&*ꢏꢁ#56%ꢄ*
$KV
ꢎ
ꢏ
ꢆ
ꢉ
ꢊ
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
.5ꢀ$[VGꢀQHꢀ6KOGꢀ%QPUVCPV
4ꢋ9
4GUGV
:
:
:
:
:
:
:
:
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ ꢃ /5ꢀD[VGꢀQHꢀ 4ꢋ9
6JGꢀ/QUVꢀ5KIPKHKECPVꢀꢇꢀDKVUꢀQHꢀVJGꢀ
#5%+ꢂꢀ$CWFꢀ4CVGꢀ)GPGTCVQT Uꢀ6KOGꢀ
%QPUVCPVꢄ
6KOGꢀ
%QPUVCPV
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢊꢁ
+ꢇ1ꢁ4
%
ꢀ5
ꢀ+ꢋ1ꢀꢐ%5+ꢋ1ꢑꢀ4
%.1%-'&ꢁ5'4+#.ꢁ+ꢇ1ꢁꢎ%5+ꢇ1ꢏꢁ4')+56'45
See section , which starts on page 67, for more about these registers.
6
ꢁꢄꢅꢃꢆ ꢁ%5+ꢇ1ꢁ%
ꢁ4
ꢁꢎꢃꢃꢃ#*ꢏꢁ%064
$KV
ꢎ
ꢏ
'+'
4ꢋ9
ꢃ
ꢆ
ꢉ
6'
4ꢋ9
ꢃ
ꢊ
4GUXF
!
ꢍ
ꢂ
ꢃ
$KVꢋ(KGNF
4ꢋ9
'(
4
4'
5RGGFꢀ5GNGEVꢀꢐ55ꢑ
4ꢋ9
4ꢋ9
ꢃ
4GUGV
ꢃ
:
ꢂ
ꢂ
ꢂ
0QVGꢐꢁ4ꢀꢔꢀ4GCFꢀ9ꢀꢔꢀ9TKVGꢀ:ꢀꢔꢀ+PFGVGTOKPCVG!ꢀꢔꢀ0QVꢀ#RRNKECDNG
$KV
2QUKVKQP $KVꢇ(KGNF
4ꢇ9 8CNWG &GUETKRVKQP
ꢎ
'PFꢀ(NCIꢀ
ꢐ'(ꢑ
4
6JGꢀ%5+ꢋ1ꢀUGVUꢀVJKUꢀDKVꢀVQꢀꢂꢀYJGPꢀKVꢀ
HKPKUJGUꢀUGPFKPIꢀQTꢀTGEGKXKPIꢀCꢀD[VGꢄꢀ+Vꢀ
ENGCTUꢀVJKUꢀDKVꢀYJGPꢀUQHVYCTGꢀTGCFUꢀQTꢀ
YTKVGUꢀVJGꢀ64&4ꢅꢀQPꢀ4GUGVꢅꢀCPFꢀ
FWTKPIꢀ+ꢋ1ꢀ5VQRꢀOQFGꢄ
ꢏ
ꢆ
'PFꢀ
+PVGTTWRVꢀ
'PCDNGꢀꢐ'+'ꢑ
4ꢋ9
4ꢋ9
+HꢀVJKUꢀDKVꢀKUꢀꢂꢅꢀVJGꢀ%5+ꢋ1ꢀTGSWGUVUꢀCPꢀ
KPVGTTWRVꢀYJGPꢀKVꢀEQORNGVGUꢀUGPFKPIꢀ
QTꢀTGEGKXKPIꢀCꢀD[VGꢀCPFꢀUGVUꢀ'(ꢄ
4GEGKXGꢀ
'PCDNGꢀꢐ4'ꢑ
9TKVGꢀCꢀꢂꢀVQꢀVJKUꢀDKVꢀVQꢀUVCTVꢀCꢀ%5+ꢋ1ꢀ
TGEGKXGꢀQRGTCVKQPꢄꢀ+HꢀVJGꢀ55ꢀDKVUꢀCTGꢀ
ꢂꢂꢂꢅꢀVJGꢀ%5+ꢋ1ꢀYCKVUꢀHQTꢀꢇꢀENQEMꢀ
RWNUGUꢀQPꢀ%-5ꢄꢀ1VJGTYKUGꢅꢀKVꢀQWVRWVUꢀ
ꢇꢀENQEMꢀRWNUGUꢀQPꢀ%-5ꢄꢀ+PꢀGKVJGTꢀECUGꢅꢀ
KVꢀENQEMUꢀFCVCꢀQPꢀ4:5ꢀKPVQꢀVJGꢀ64&4ꢀ
CVꢀGCEJꢀTKUKPIꢀGFIGꢀQPꢀ%-5ꢄꢀ#HVGTꢀ
ECRVWTKPIꢀVJGꢀꢇVJꢀDKVꢅꢀKVꢀENGCTUꢀVJKUꢀDKVꢀ
CPFꢀUGVUꢀ'(ꢄ
ꢉ
6TCPUOKVꢀ
'PCDNGꢀꢐ6'ꢑ
4ꢋ9
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UGPFKPIꢀꢇꢀDKVUꢅꢀVJGꢀ%5+ꢋ1ꢀENGCTUꢀVJKUꢀ
DKVꢀCPFꢀUGVUꢀ'(ꢄ
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CNNQYKPIꢀVJGꢀ%5+ꢋ1ꢀVQꢀUGPFꢀKVꢄꢀ
5QHVYCTGꢀTGCFUꢀCꢀTGEGKXGFꢀD[VGꢀHTQOꢀ
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'(ꢀDKVꢀKPꢀTGURQPUGꢀVQꢀUQHVYCTGꢀUGVVKPIꢀ
VJGꢀ4'ꢀDKVꢄ
+05647%6+10ꢁ5'6
The Z80S183 includes the 8S180 processor, which is descended from the ZiLOG
Z80. The 8-bit data bus and 20-bit address space fit well into a wide variety of
mid-range embedded processing applications. This processor provides signifi-
cantly more computing power than a microcontroller, at a fraction of the system
cost of a larger microprocessor.
For details of these instructions see the Z80S183 User Manual, or the Z8S180 or
Z80185 User Manuals until the Z80S183 UM is available.
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
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Table 142 describes the Flag register. Bits in this register are set and cleared by
certain instructions as described in the Z80S183 User Manual. Some of the Flags
are tested by conditional JR, JP, CALL, and RETinstructions, and some are used
ꢂꢉꢉ
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%
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+
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by subsequent instructions such as ADC, SBC, and DAA. Accumulator A can also
perform PUSHand POPinstructions on the Flags.
6
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Table 143 describes the codes used in the Flags Affected columns of the Instruc-
tion Summary Table, Table 146, to indicate how each flag is affected by each type
of instruction.
6
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Table 144 describes the condition codes that can be used in conditional JP, CALL,
and RETinstructions in assembly language. A subset of these codes can also be
used in JRinstructions, which are shorter and faster than JPs.
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;
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0
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Table 145 describes other notation used in the subsequent Instruction Summary
table.
6
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Stresses greater than those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This rating is a stress rating only. Operation of
the device at any condition outside those indicated in the operational sections of
these specifications is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
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Unless otherwise noted, the DC and AC characteristics in this document are
measured under standard test conditions that include the load circuit illustrated in
Figure 16. This circuit closely mimics the loading presented by active devices
such as memories and peripheral devices.
All voltages are referenced to the V pins (ground, 0V). Positive current flows
SS
into the referenced pin.
All AC parameters assume a load capacitance of 100 pF. See “Characteristic
Curves” on page 178 for the effect of lesser or greater total capacitance on the
timing. AC timing measurements are referenced to the High and low voltage
thresholds given in the DC specifications, as indicated in Figures 17 through 25.
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input, output, or both. The total capacitance associated with outputs affects their
AC characteristics (switching time) as described in “Characteristic Curves” on
page 178.
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ZiLOG expects Revision BA of the Z80S183 to fix the following problems. The
errata apply to revision AB of the Z80S183, which is identified by a 0in the
Device Revision register, I/O address 003DH.
5EJOKVVꢁ6TKIIGTU
The RESET, NMI, ZCLand ZDApins are specified to include Schmitt triggers, but
these were not included on Rev AB. The 50 mS max rise and fall time specified
for RESETthus becomes much shorter, 50 nS or less. Since RESETis an open-
drain output, perhaps the best workaround is to simply connect a pullup resistor,
and not drive RESETexternally.
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The Alarm function of the Real Time Clock is not operative.
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The PWRSWTCHpin is specified as positive logic, but in Rev AB is implemented
as negative logic (1 is Low, 0 is High).
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The OCR is specified to reset to 0xx00000, but instead resets to 0xx11000.
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A rising edge on OPMOD1does not trigger a Power On Reset sequence.
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The Programmable I/O Sequencer enables Port C outputs when it is enabled. Soft-
ware needs to define the state of Port C outputs before enabling the PIOS, by
writing to the Port C Data Register.
If software writes to the PRT Reload registers while the PRT is operating, and a
write coincides with a window near the end of the PRT’s countdown cycle, the
down counter may end up reloaded with the wrong value.
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The RTC specs read that if bit 4 of the RTC Control/Status Register is 1, the RTC
takes a 50 or 60 Hz clock from the PC0pin. Rev AB makes the frequency adjust-
ment when this bit is 1, but takes the clock from LFEXTAL, as when the bit is 0.
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The Register Write Enable state that is readable as bit 0 of the Watch-Dog Timer
Master register is specified to reset to 1. However, its value is indeterminate after
power up and unchanged by other Resets. Reset-initialization software writes a
0BHto the Watch-Dog Timer Command Register to set this bit, before writing any
of the System Configuration, Power Control, Port Data Direction, or Real Time
Clock registers.
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The Z80S183 includes this serial interface to allow ZiLOG and 3rd-party develop-
ment systems and emulators to control and monitor the processor and other on-
chip resources, during application development and debugging. This 2-wire inter-
face is intended to be a standard feature of ZiLOG processors, obviating the need
for expensive and cumbersome pods and clip-on emulation equipment.
To use the ZiLOG Developer Studio (ZDS) or equivalent equipment with an
application or target board, include a standard right angle, 0.1 in spaced, 0.025 in
square post, six pin header on the board (Berg P/N 75867-131 or equivalent).
Connect the ZCL and ZDA pins of the Z80S183 to pins 4 and 6 of this header as
illustrated in Figure 27, which is a top view.
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For fast results, contact your nearest ZiLOG sale office or the ZiLOG Customer
Support Center at 877-945-6427 (web site: www.zilog.com) for assistance in
ordering parts.
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ZiLOG part numbers consist of a number of components.
'ZCORNGꢐꢁ
Part number Z80S183 33 A S C, a Z80S183, 33 MHz, Thin Quad Flat Pack, 0 to
70 C, Plastic Standard Flow, is made up of the codes described in the following
table.
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Outlook Public Folders: All Public Folders: ZiLOG Corporate:
ROM Submission Forms: Z8S183-4.2.
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To submit a ROM Code:
1. Complete ROM code submission form.
2. Send this form and the hex file (in Intel Hex format) as separate attachments in
an E-mail to: codes@zilog.com.
%QORCP[ꢀ0COGꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAA &KUV[ꢋ5WDEQPꢈꢀAAAAAAAAAAAAAAAAAAAAAA &CVGꢈꢀAAAAAA
<K.1)ꢀ2ꢋ0ꢈꢀ
%JGEMUWOꢀ
2CEMCIGꢀ%QFGꢀ.GIGPFꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAA
4GXꢄꢀꢐKPRWVꢀD[ꢀ<K.1)ꢑꢀAAAAAAAAAAAAAAAAAAAAAAAAAAA
%QORCP[ꢀ2ꢋ0ꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAA (KNGꢀ2ꢀ+PRWVꢈꢀꢐKPRWVꢀD[ꢀ<K.1)ꢑꢀAAAAAAAAAAAAAAAAAAAA
'ZRGEVGFꢀ#PPWCNꢀXQNWOGꢀKPꢀ7PKVUꢈꢀAAAAAAAAAA
#RRNKECVKQPꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
52'%+#.ꢁ+05647%6+105ꢐꢁꢎ1RVKQPCNꢏ
<K.1)ꢀ5CNGUꢀ1HHKEGꢀꢐQTꢀ[QWTꢀ%KV[ꢀCPFꢀ%QWPVT[ꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
5GPFꢀ41/ꢀ8GTKHKECVKQPꢀVQꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
2JQPGꢈꢀAAAAAAAAAAAAAAAAAAAAAAA 'ꢌOCKNꢈꢀAAAAAAAAAAAAAAAAAAAAAAA (CZꢈꢀAAAAAAAAAAAAAAAAAAAAAAAAA
612/#4-ꢁ1(ꢁ2#465
To submit a topmark:
1. Check box for default or custom for the preferred package.
2. On default, 9999 indicates ROM number assigned to part by ZiLOG.
3. If custom topmark is selected, enter characters in the space provided. ZiLOG
adds the date code (XXYY BB) as bottom line and align as shown on default
topmark.
4. If you do not use all the lines on a custom topmark you must leave the top line
blank.
5. For ™ (Trademark) symbol, place lowercase tm.
6. For © (Copyright) symbol, place lowercase c followed by a space.
7. For custom logo, attach BMP, JPEG or GIF file to this form.
8. To use ZiLOG in a custom topmark, type: pZiLOG. The pis a placemark
for the ZiLOG name.
The Z logo is used when applicable. (See Default)
83(2ꢀꢂꢃꢃꢀ2+0
%WUVQOꢀAAAAA
ꢂꢂꢀ%JCTꢀ/CZꢄꢀAAAAAAAAAAAAAAAAAAAAAAAAAA &GHCWNVꢀAAAAAA
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
ꢂꢇꢊ
&
2
ꢀ2
&+5%.#+/'4
©1999 by ZiLOG, Inc. All rights reserved. Information in this publication
concerning the devices, applications, or technology described is intended to
suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCU-
RACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME
LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECH-
NOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express
written approval of ZiLOG, use of information, devices, or technology as critical
components of life support systems is not authorized. No licenses are conveyed,
implicitly or otherwise, by this document under any intellectual property rights.
24'%*#4#%6'4+<#6+10ꢁ241&7%6
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or noncon-
formance with some aspects of the document may be found, either by ZiLOG or
its customers, in the course of further application and characterization work. In
addition, ZiLOG cautions that delivery may be uncertain at times, because of
start-up yield issues.
ZiLOG, Inc.
910 East Hamilton Avenue
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: HTTP://WWW.ZILOG.COM
&1%7/'06ꢁ+0(14/#6+10
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ꢃꢁꢋꢂꢊꢋꢁꢁ 1TKIKPCNꢀKUUWG
IICODNG
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2TGNKOKPCT[ꢀ<ꢇꢃ5ꢂꢇꢊ
25ꢃꢃꢃꢆꢃꢃꢌ:/2ꢃꢆꢁꢁ
Time constant low register . . . . . . . . . . 138
Tx data register . . . . . . . . . . . . . . . . . . . 135
ASCI1
#
Absolute maximum ratings . . . . . . . . . . . . 165
AC characteristics
Control register A . . . . . . . . . . . . . . . . . 132
Control register B . . . . . . . . . . . . . . . . . 133
Extension control register . . . . . . . . . . 138
Rx data register . . . . . . . . . . . . . . . . . . 136
Status register . . . . . . . . . . . . . . . . . . . . 135
Time constant low register . . . . . . . . . . 139
Tx data register . . . . . . . . . . . . . . . . . . . 136
Assembly language syntax . . . . . . . . . . . . 147
Extended temperature range . . . . . . . . . 171
Normal temperature range . . . . . . . . . . 168
ADC
Control register 0 . . . . . . . . . . . . . . . . . 126
Control register 1 . . . . . . . . . . . . . . . . . 127
Result register . . . . . . . . . . . . . . . . . . . . 128
ADC instruction . . . . . . . . . . . . . . . . . . . . 148
ADD intsruction . . . . . . . . . . . . . . . . . . . . 148
Addressing modes
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register indirect . . . . . . . . . . . . . . . . . . . 21
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Alarm hours registers . . . . . . . . . . . . . . . . 124
Alarm minutes register . . . . . . . . . . . . . . . 123
Alarm seconds register . . . . . . . . . . . . 123
Alarm, RTC . . . . . . . . . . . . . . . . . . . . . . . . 180
Analog/digital converter (ADC)
Channel selection . . . . . . . . . . . . . . . . . . 50
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 51
Power save . . . . . . . . . . . . . . . . . . . . . . . 52
Programming . . . . . . . . . . . . . . . . . . . . . 51
Restarting . . . . . . . . . . . . . . . . . . . . . . . . 52
Sampling . . . . . . . . . . . . . . . . . . . . . . . . . 52
AND instruction . . . . . . . . . . . . . . . . . . . . 148
Architectural overview . . . . . . . . . . . . . . . . . 1
Arithmatic instructions . . . . . . . . . . . . . . . 142
ASCI
ASYNC reception . . . . . . . . . . . . . . . . . . 59
ASYNC transmission . . . . . . . . . . . . . . . 58
BRG and clock mode . . . . . . . . . . . . . . . 60
Clock mode . . . . . . . . . . . . . . . . . . . . . . . 58
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . 57
Features . . . . . . . . . . . . . . . . . . . . . . . . . . 57
ASCI options
7 or 8 bit . . . . . . . . . . . . . . . . . . . . . . . . . 60
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Transmit Stop bits . . . . . . . . . . . . . . . . . . 61
ASCI0
$
Bank base register . . . . . . . . . . . . . . . . . . . . 82
Basic timing diagram . . . . . . . . . . . . . . . . 175
Baud rate generator (BRG) . . . . . . . . . . . . . 57
Bit instruction . . . . . . . . . . . . . . . . . . . . . . 148
Bit manipulation instructions . . . . . . . . . . 143
Block diagram . . . . . . . . . . . . . . . . . . . . . . . 2
Illustrated . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block transfer instructions . . . . . . . . . . . . 143
Break conditions status . . . . . . . . . . . . . . . . 61
Bus exchange timing diagram . . . . . . . . . 178
%
Call instruction . . . . . . . . . . . . . . . . . . . . . 148
Cancellation of transmit or
receive capability . . . . . . . . . . . . . . . . . . . 69
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . 175
Capacitive load . . . . . . . . . . . . . . . . . . . . . 179
CCF instruction . . . . . . . . . . . . . . . . . . . . 148
Century register . . . . . . . . . . . . . . . . . . . . 123
Change log . . . . . . . . . . . . . . . . . . . . . . . . 185
Channel completion . . . . . . . . . . . . . . . . . . 42
Channels
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DMA basics . . . . . . . . . . . . . . . . . . . . . . 36
Characteristics, electrical
Absolute maximum ratings . . . . . . . . . 165
AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Capacitive load . . . . . . . . . . . . . . . . . . . 179
Curves . . . . . . . . . . . . . . . . . . . . . . . . . 179
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Standard test conditions . . . . . . . . . . . . 165
Chip select, I/O . . . . . . . . . . . . . . . . . . . . . . 26
Classes of instructions . . . . . . . . . . . . . . . 142
Control register A . . . . . . . . . . . . . . . . . 131
Control register B . . . . . . . . . . . . . . . . . 132
Extension control register . . . . . . . . . . . 137
Rx data register . . . . . . . . . . . . . . . . . . . 136
Status register . . . . . . . . . . . . . . . . . . . . 134
Time constant high register . . . . . . . . . . 139
PS000500-ZMP0599
Preliminary Z80S183
Index-1
Clock
ASCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DC characteristics . . . . . . . . . . . . . . . . . . . 166
Extended temperature range . . . . . . . . . 167
Normal temperature range . . . . . . . . . . 166
Debug interface . . . . . . . . . . . . . . . . . . . . . 181
DEC instruction . . . . . . . . . . . . . . . . . . . . 149
Decoding
External RAM . . . . . . . . . . . . . . . . . . . . 23
External ROM/Flash . . . . . . . . . . . . . . . 23
Description
Circuit description . . . . . . . . . . . . . . . . . 27
Crystal specifications . . . . . . . . . . . . . . . 29
CSI/O selection . . . . . . . . . . . . . . . . . . . . 67
Direct vs. divide-by-2 option . . . . . . . . . 27
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reduced oscillator drive option . . . . . . . 29
Selection . . . . . . . . . . . . . . . . . . . . . . . . . 27
Clock control register . . . . . . . . . . . . . . . . . 73
Command register . . . . . . . . . . . . . . . . . . . 112
Common bank area register . . . . . . . . . . . . 83
Common base register . . . . . . . . . . . . . . . . . 82
Condition codes . . . . . . . . . . . . . . . . . . . . . 145
Control register . . . . . . . . . . . . . . . . . . . . . 140
Converters
Analog/digital (ADC) . . . . . . . . . . . . . . . 49
Digita/Analog (DAC) . . . . . . . . . . . . . . . 48
CP instruction . . . . . . . . . . . . . . . . . . . . . . 149
CPD instruction . . . . . . . . . . . . . . . . . . . . . 149
CPDR instruction . . . . . . . . . . . . . . . . . . . 149
CPI instruction . . . . . . . . . . . . . . . . . . . . . 149
CPIR instruction . . . . . . . . . . . . . . . . . . . . 149
CPL instruction . . . . . . . . . . . . . . . . . . . . . 149
CPU control register . . . . . . . . . . . . . . . . . . 73
CSI/O
Operational . . . . . . . . . . . . . . . . . . . . . . . 10
Processor . . . . . . . . . . . . . . . . . . . . . . . . 10
Design considerations . . . . . . . . . . . . . . . . 180
Device and version ID registers . . . . . . . . . 13
DI instruction . . . . . . . . . . . . . . . . . . . . . . 149
Digital/Analog converter (DAC) . . . . . . . . 48
Direct addressing mode . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . 185
Divide-by-2 . . . . . . . . . . . . . . . . . . . . . . . . . 27
DJNZ instruction . . . . . . . . . . . . . . . . . . . 149
DMA
Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Channel completion . . . . . . . . . . . . . . . . 42
Channels . . . . . . . . . . . . . . . . . . . . . . . . . 36
Edge-sensitive requests . . . . . . . . . . . . . 37
Handling interrupts . . . . . . . . . . . . . . . . . 43
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . 39
Level-sensitive requests . . . . . . . . . . . . . 37
Memory-to-memory modes . . . . . . . . . . 39
Mode register . . . . . . . . . . . . . . . . . . . . 107
Processor/DMA operation . . . . . . . . . . . 38
Requests . . . . . . . . . . . . . . . . . . . . . . . . . 37
Setting up transfers . . . . . . . . . . . . . . . . . 40
Source and destination modes . . . . . . . . 41
Status register . . . . . . . . . . . . . . . . . . . . 106
Timing diagram . . . . . . . . . . . . . . . . . . 179
Wait control register . . . . . . . . . . . . . . . 109
DMA0
Byte reception . . . . . . . . . . . . . . . . . . . . . 69
Byte transmission . . . . . . . . . . . . . . . . . . 69
Cancellation of transmit or receive capability
69
Clock selection . . . . . . . . . . . . . . . . . . . . 67
Data register . . . . . . . . . . . . . . . . . . . . . 141
Input clock . . . . . . . . . . . . . . . . . . . . . . . 68
Operation . . . . . . . . . . . . . . . . . . . . . . . . 68
Output clock . . . . . . . . . . . . . . . . . . . . . . 68
Curves, characteristic . . . . . . . . . . . . . . . . 179
&
DAA instruction . . . . . . . . . . . . . . . . . . . . 149
DAC
Byte count high register . . . . . . . . . . . . 102
Byte count low register . . . . . . . . . . . . 101
Destination address B register . . . . . . . 101
Destination address high register . . . . . 100
Destination address low register . . . . . 100
Source address B register . . . . . . . . . . . . 99
Source address high register . . . . . . . . . . 99
Source address low register . . . . . . . . . . 98
Control register . . . . . . . . . . . . . . . . . . . 124
Data register . . . . . . . . . . . . . . . . . . . . . 125
Data bits, 7 or 8 option . . . . . . . . . . . . . . . . 60
Data direction registers . . . . . . . . . . . . . . . . 34
Data registers . . . . . . . . . . . . . . . . . . . . . . . . 34
Date register . . . . . . . . . . . . . . . . . . . . . . . 121
Day of week register . . . . . . . . . . . . . . . . . 121
Index-2
Preliminary Z80S183
PS000500-ZMP0599
DMA1
Byte count high register . . . . . . . . . . . . 106
Data direction registers 34
Data registers . . . . . . . . . . . . . . . . . . . . . 34
Iinstructions . . . . . . . . . . . . . . . . . . . . . . 24
Instructions . . . . . . . . . . . . . . . . . . . . . . 144
IORD timing . . . . . . . . . . . . . . . . . . . . . . 26
Port A alternate function select (AFSA) 34
Port A alternate function select register . 88
Port A data direction register . . . . . . . . . 88
Port A data register . . . . . . . . . . . . . . . . . 87
Port A output control register . . . . . . . . . 89
Port B alternate function select (AFSB) . 35
Port B data direction register . . . . . . . . . 90
Port B data register . . . . . . . . . . . . . . . . . 89
Port B output control register . . . . . . . . . 92
Port B weak latch disable feature . . . . . . 35
Port C alternate function register . . . . . . 94
Port C alternate function select (AFSC) . 35
Port C data direction register . . . . . . . . . 93
Port C data register . . . . . . . . . . . . . . . . . 92
Port C output control register . . . . . . . . . 94
Port D alternate function select (AFSD) 35
Port D alternate function select register . 96
Port D data direction register . . . . . . . . . 95
Port D data register . . . . . . . . . . . . . . . . . 95
Port D output control register . . . . . . . . . 97
Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Read timing diagram . . . . . . . . . . . . . . 177
Relocating the 180 registers . . . . . . . . . . 25
Space . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Waits . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Write enable/lock . . . . . . . . . . . . . . . . . . 25
Write timing diagram . . . . . . . . . . . . . . 177
IEF1, IEF2 bits . . . . . . . . . . . . . . . . . . . . . . 14
Illegal instruction traps . . . . . . . . . . . . . . . . 12
Error message vs. restart . . . . . . . . . . . . 13
Extending the instruction set . . . . . . . . . 13
Trap handling . . . . . . . . . . . . . . . . . . . . . 12
IM instruction . . . . . . . . . . . . . . . . . . . . . . 150
IN instruction . . . . . . . . . . . . . . . . . . . . . . 150
IND instruction . . . . . . . . . . . . . . . . . . . . . 150
Indexed addressing mode . . . . . . . . . . . . . . 21
INDR instruction . . . . . . . . . . . . . . . . . . . 150
INI instruction . . . . . . . . . . . . . . . . . . . . . 150
INIR instruction . . . . . . . . . . . . . . . . . . . . 151
IN0 instruction . . . . . . . . . . . . . . . . . . . . . 150
Byte count low register . . . . . . . . . . . . . 105
I/O address high register . . . . . . . . . . . . 103
I/O address low register . . . . . . . . . . . . 103
I/O address register B . . . . . . . . . . . . . . 104
Memory address B register . . . . . . . . . . 103
Memory address high register . . . . . . . . 102
Memory address low register . . . . . 102
'
Edge-senstive requests . . . . . . . . . . . . . . . . 37
EI instruction . . . . . . . . . . . . . . . . . . . . . . . 150
Electrical characteristics
AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Capacitance . . . . . . . . . . . . . . . . . . . . . . 175
Capacitive load vs. switching time . . . . 179
Curves . . . . . . . . . . . . . . . . . . . . . . . . . . 179
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Timing diagrams . . . . . . . . . . . . . . . . . . 175
Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Error message vs. restart . . . . . . . . . . . . . . . 13
EX AF AF’ instruction . . . . . . . . . . . . . . . 150
EX instruction . . . . . . . . . . . . . . . . . . . . . . 150
Exchange instructions . . . . . . . . . . . . . . . . 142
Extending the instruction set . . . . . . . . . . . . 13
EXX instruction . . . . . . . . . . . . . . . . . . . . 150
(
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ASCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Reduced drive/low noise . . . . . . . . . . . . . 33
Flag
Condition codes . . . . . . . . . . . . . . . . . . 146
Description . . . . . . . . . . . . . . . . . . . . . . . 11
R register . . . . . . . . . . . . . . . . . . . . . . . . 145
Settings definitions . . . . . . . . . . . . . . . . 145
Free-running register . . . . . . . . . . . . . . . . . . 72
*
+
HALT instruction . . . . . . . . . . . . . . . . . . . 150
Hours register . . . . . . . . . . . . . . . . . . . . . . 120
I/O 91
Chip select 26
Control register 77
PS000500-ZMP0599
Preliminary Z80S183
Index-3
Instruction
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
OTR . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
OUT0 154
ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
AND . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Assembly language syntax . . . . . . . . . . 147
Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CPDR . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CPIR . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
DAA . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
DJNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
EX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
EX AF,AF’ . . . . . . . . . . . . . . . . . . . . . . 150
Extending . . . . . . . . . . . . . . . . . . . . . . . . 13
EXX . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
HALT . . . . . . . . . . . . . . . . . . . . . . . . . . 150
IM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
IN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
IND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
INDR . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
INI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
INIR . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
JP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
JR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
LDD . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
LDDR . . . . . . . . . . . . . . . . . . . . . . . . . . 152
LDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
LDIR . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
MLT . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
OTDM . . . . . . . . . . . . . . . . . . . . . . . . . . 153
OTDMR . . . . . . . . . . . . . . . . . . . . . . . . 153
OTDR . . . . . . . . . . . . . . . . . . . . . . . . . . 153
OTIM . . . . . . . . . . . . . . . . . . . . . . . . . . 153
OTIMR . . . . . . . . . . . . . . . . . . . . . . . . . 154
OUTD 154
OUTI . . . . . . . . . . . . . . . . . . . . . . . . . . 154
POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . 154
RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
RET . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RETN . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RLA . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RLCA . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RLD . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RLRL . . . . . . . . . . . . . . . . . . . . . . . . . . 148
RR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RRA . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
RRCA . . . . . . . . . . . . . . . . . . . . . . . . . . 156
RRD . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SLA . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SRA . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
TST . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
TSTIO . . . . . . . . . . . . . . . . . . . . . . . . . . 157
XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Instruction Set
Summary . . . . . . . . . . . . . . . . . . . . . . . 148
Symbols . . . . . . . . . . . . . . . . . . . . . . . . 146
Interrupts
A/D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Edge register . . . . . . . . . . . . . . . . . . . 14, 81
high address register . . . . . . . . . . . . . . . . 11
I register . . . . . . . . . . . . . . . . . . . . . . . . . 14
IEF1, IEF2 . . . . . . . . . . . . . . . . . . . . . . . 14
IL register . . . . . . . . . . . . . . . . . . . . . . . . 14
Registers . . . . . . . . . . . . . . . . . . . . . . . . . 80
Timing diagram . . . . . . . . . . . . . . . . . . 178
Trap control register . . . . . . . . . . . . . 14, 80
Index-4
Preliminary Z80S183
PS000500-ZMP0599
Vector low register . . . . . . . . . . . . . . . . . 80
IORD timing . . . . . . . . . . . . . . . . . . . . . . . . 26
Month register . . . . . . . . . . . . . . . . . . . . . 122
0
1
No DRAM Refresh . . . . . . . . . . . . . . . . . . . 24
NOP instruction . . . . . . . . . . . . . . . . . . . . 153
,
.
JP instruction . . . . . . . . . . . . . . . . . . . . . . . 151
JR instruction . . . . . . . . . . . . . . . . . . . . . . 151
On-chip
Observing read data . . . . . . . . . . . . . . . . 12
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Op code map
1st op code . . . . . . . . . . . . . . . . . . . . . . 158
2nd op code after 0CBH . . . . . . . . . . . . 159
2nd op code after 0DDH . . . . . . . . . . . 160
2nd op code after 0EDH . . . . . . . . . . . . 161
2nd op code after 0FDH . . . . . . . . . . . . 162
4th byte, after 0DDH, 0CBH, and d . . . 163
4th byte, after 0FDH, 0CBH, and d . . . 164
Operating mode control register . . . . . . . . . 76
Operation
LD instruction . . . . . . . . . . . . . . . . . . . . . . 151
LDD instruction . . . . . . . . . . . . . . . . . . . . 152
LDDR instruction . . . . . . . . . . . . . . . . . . . 152
LDI instruction . . . . . . . . . . . . . . . . . . . . . 152
LDIR instruction . . . . . . . . . . . . . . . . . . . . 153
Level-sensitive requests . . . . . . . . . . . . . . . 37
Load instructions . . . . . . . . . . . . . . . . . . . . 142
logic, negative . . . . . . . . . . . . . . . . . . . . . . 180
Logical instructions . . . . . . . . . . . . . . . . . . 142
/
Memory Management Unit (MMU) . . . . . . 10
Memory
CSI/O . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Status . . . . . . . . . . . . . . . . . . . . . . . . 61, 63
Operational overview . . . . . . . . . . . . . . . . . . 2
OR instruction . . . . . . . . . . . . . . . . . . . . . 153
Order information . . . . . . . . . . . . . . . . . . . 183
Part number description . . . . . . . . . . . . 183
ROM code submission . . . . . . . . . . . . . 183
Topmark submission . . . . . . . . . . . . . . 184
OTDM instruction . . . . . . . . . . . . . . . . . . 153
OTDMR instruction . . . . . . . . . . . . . . . . . 153
OTDR instruction . . . . . . . . . . . . . . . . . . . 153
OTIM instruction . . . . . . . . . . . . . . . . . . . 153
OTIMR instruction . . . . . . . . . . . . . . . . . . 154
OTR instruction . . . . . . . . . . . . . . . . . . . . 154
OUT instruction . . . . . . . . . . . . . . . . . . . . 154
OUT0 instruction . . . . . . . . . . . . . . . . . . . 154
OUTD instruction . . . . . . . . . . . . . . . . . . . 154
OUTI instruction . . . . . . . . . . . . . . . . . . . 154
Output control register . . . . . . . . . . . . . . . . 77
Output control register reset . . . . . . . . . . . 180
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Read timing diagram . . . . . . . . . . . . . . . 176
Write timing diagram . . . . . . . . . . . . . . 176
Memory-to-memory modes . . . . . . . . . . . . 39
MLT instruction . . . . . . . . . . . . . . . . . . . . 153
Modes
Addressing . . . . . . . . . . . . . . . . . . . . . . . 21
ASCI clock . . . . . . . . . . . . . . . . . . . . . . . 58
BRG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cycle steal . . . . . . . . . . . . . . . . . . . . . . . . 39
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DMA0 source and destination . . . . . . . . 41
DMA1 operating . . . . . . . . . . . . . . . . . . . 42
Edge-sensitive request . . . . . . . . . . . . . . 36
Falling-edge . . . . . . . . . . . . . . . . . . . . . . 37
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
INT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Isochronous . . . . . . . . . . . . . . . . . . . . . . . 58
Low-power . . . . . . . . . . . . . . . . . . . . . . . 30
Memory-to-memory . . . . . . . . . . . . . . . . 39
Multiprocessor . . . . . . . . . . . . . . . . . . . . 65
Nine-bit . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Standby with Quick recovery . . . . . . . . . 32
System stop . . . . . . . . . . . . . . . . . . . . . . . 32
2
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . 182
Parity option . . . . . . . . . . . . . . . . . . . . . . . . 60
Part number description . . . . . . . . . . . . . . 183
PS000500-ZMP0599
Preliminary Z80S183
Index-5
PIOS
address/type register . . . . . . . . . . . . . . . 130
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reception
Control register . . . . . . . . . . . . . . . . . . . 129
Counter high . . . . . . . . . . . . . . . . . . . . . 130
Counter low . . . . . . . . . . . . . . . . . . . . . 130
Port 1 initialization . . . . . . . . . . . . . . . . 180
POP instruction . . . . . . . . . . . . . . . . . . . . . 154
Port B alternate function select register . . . 91
Power control register . . . . . . . . . . . . . . . . . 78
Power save . . . . . . . . . . . . . . . . . . . . . . . . . 52
Precharacterization . . . . . . . . . . . . . . . . . . 185
Processor control instructions . . . . . . . . . . 144
Processor control registers
Flags (F) . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interrupt high address (I) . . . . . . . . . . . . 11
Program counter (PC) . . . . . . . . . . . . . . . 11
R counter (R) . . . . . . . . . . . . . . . . . . . . . 11
Stack pointer (SP) . . . . . . . . . . . . . . . . . . 11
Processor description
Input/output space . . . . . . . . . . . . . . . . . . 10
Memory ManagementUnit (MMU) . . . . 10
Processor control registers . . . . . . . . . . . 11
Processor/DMA operation . . . . . . . . . . . . . . 38
Program control instructions . . . . . . . . . . . 143
Program counter (PC) . . . . . . . . . . . . . . . . . 11
PRT
Race condition . . . . . . . . . . . . . . . . . . . 180
PRT0
Data high register . . . . . . . . . . . . . . . . . 113
Reload high register . . . . . . . . . . . . . . . 115
Reload low register . . . . . . . . . . . . . . . . 113
PRT1
Reload register high . . . . . . . . . . . . . . . 117
Reload register low . . . . . . . . . . . . . . . . 116
Timer data high register . . . . . . . . . . . . 116
Timer data low register . . . . . . . . . . . . . 116
PRTO
Data low register . . . . . . . . . . . . . . . . . . 113
PUSH instruction . . . . . . . . . . . . . . . . . . . 154
PWRSWTCH negative logic . . . . . . . . . . . 180
ASCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Reduced drive/low noise feature . . . . . . . . 33
Refresh control register . . . . . . . . . . . . . . . 74
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 145
180 relocation . . . . . . . . . . . . . . . . . . . . . 25
ADC control 0 . . . . . . . . . . . . . . . . . . . 126
ADC control 1 . . . . . . . . . . . . . . . . . . . 127
ADC result . . . . . . . . . . . . . . . . . . . . . . 128
Alarm hours . . . . . . . . . . . . . . . . . . . . . 124
Alarm minutes . . . . . . . . . . . . . . . . . . . 123
Alarm seconds. . . . . . . . . . . . . . . . . . . . 123
ASCI0 control A . . . . . . . . . . . . . . . . . . 131
ASCI0 extension control . . . . . . . . . . . 137
ASCI0 Rx data . . . . . . . . . . . . . . . . . . . 136
ASCI0 status . . . . . . . . . . . . . . . . . . . . . 134
ASCI0 time constant high . . . . . . . . . . 139
ASCI0 time constant low . . . . . . . . . . . 138
ASCI0 Tx data . . . . . . . . . . . . . . . . . . . 135
ASCI1 control B . . . . . . . . . . . . . . . . . . 133
ASCI1 extension control . . . . . . . . . . . 138
ASCI1 Rx data . . . . . . . . . . . . . . . . . . . 136
ASCI1 status . . . . . . . . . . . . . . . . . . . . . 135
ASCI1 time constant low . . . . . . . . . . . 139
ASCI1 Tx data . . . . . . . . . . . . . . . . . . . 136
ASCI1control A . . . . . . . . . . . . . . . . . . 132
Bank base . . . . . . . . . . . . . . . . . . . . . . . . 82
Century . . . . . . . . . . . . . . . . . . . . . . . . . 123
Clock control . . . . . . . . . . . . . . . . . . . . . 73
Common bank area . . . . . . . . . . . . . . . . . 83
Common base . . . . . . . . . . . . . . . . . . . . . 82
CPU control . . . . . . . . . . . . . . . . . . . . . . 73
CSI/O control register . . . . . . . . . . . . . 140
CSI/O data . . . . . . . . . . . . . . . . . . . . . . 141
DAC control . . . . . . . . . . . . . . . . . . . . . 124
DAC data . . . . . . . . . . . . . . . . . . . . . . . 125
Date . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Day of week . . . . . . . . . . . . . . . . . . . . . 121
Device and version ID . . . . . . . . . . . . . . 13
DMA mode . . . . . . . . . . . . . . . . . . . . . . 107
DMA Status . . . . . . . . . . . . . . . . . . . . . 106
DMA wait control . . . . . . . . . . . . . . . . 109
DMA0 byte count high . . . . . . . . . . . . . 102
DMA0 byte count low . . . . . . . . . . . . . 101
DMA0 destination address B . . . . . . . . 101
DMA0 destination address high . . . . . . 100
DMA0 destination address low . . . . . . 100
4
R counter register . . . . . . . . . . . . . . . . . . . . 11
RAM
Lower boundary register . . . . . . . . . . . . . 85
Upper boundary register . . . . . . . . . . . . . 85
Receive
CSI/O byte . . . . . . . . . . . . . . . . . . . . . . . 69
Index-6
Preliminary Z80S183
PS000500-ZMP0599
Registers, continued
PIOS counter low . . . . . . . . . . . . . . . . . 130
Power control . . . . . . . . . . . . . . . . . . . . . 78
Processor control . . . . . . . . . . . . . . . . . . 11
Processor program . . . . . . . . . . . . . . . . . 10
PRT0 data high . . . . . . . . . . . . . . . . . . . 113
PRT0 data low . . . . . . . . . . . . . . . . . . . 113
PRT0 reload high . . . . . . . . . . . . . . . . . 115
PRT0 reload low . . . . . . . . . . . . . . . . . 113
PRT1 reload high . . . . . . . . . . . . . . . . . 117
PRT1 reload low . . . . . . . . . . . . . . . . . 116
PRT1 timer data high . . . . . . . . . . . . . . 116
PRT1 timer data low . . . . . . . . . . . . . . 116
R counter (R) . . . . . . . . . . . . . . . . . . . . . 11
RAM lower boundary . . . . . . . . . . . . . . 85
RAM upper boundary . . . . . . . . . . . . . . 85
Refresh control . . . . . . . . . . . . . . . . . . . . 74
Revision ID . . . . . . . . . . . . . . . . . . . . . . 76
ROM boundary . . . . . . . . . . . . . . . . . . . . 84
RTC control/status . . . . . . . . . . . . . . . . 118
System configuration . . . . . . . . . . . . . . . 79
Timer control . . . . . . . . . . . . . . . . . . . . 115
Wait state generator control . . . . . . . . . . 83
Watch-Dog timer command . . . . . . . . . 112
Watch-Dog timer master . . . . . . . . . . . 110
Write enable state . . . . . . . . . . . . . . . . . 181
Write enable/lock . . . . . . . . . . . . . . . . . . 25
Year . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Relative addressing mode . . . . . . . . . . . . . . 21
Requests, DMA . . . . . . . . . . . . . . . . . . . . . 37
RES instruction . . . . . . . . . . . . . . . . . . . . . 154
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
RET instruction . . . . . . . . . . . . . . . . . . . . 154
RETI instruction . . . . . . . . . . . . . . . . . . . . 155
RETN instruction . . . . . . . . . . . . . . . . . . . 155
Revision ID register . . . . . . . . . . . . . . . . . . 76
RL instruction . . . . . . . . . . . . . . . . . . . . . . 155
RLA instruction . . . . . . . . . . . . . . . . . . . . 155
RLC instruction . . . . . . . . . . . . . . . . . . . . 155
RLCA instruction . . . . . . . . . . . . . . . . . . . 155
RLD instruction . . . . . . . . . . . . . . . . . . . . 155
ROM boundary register . . . . . . . . . . . . . . . 84
ROM codde submission . . . . . . . . . . . . . . 183
Rotate and shift instructions . . . . . . . . . . . 143
RR instruction . . . . . . . . . . . . . . . . . . . . . . 155
RRA instruction . . . . . . . . . . . . . . . . . . . . 155
RRC instruction . . . . . . . . . . . . . . . . . . . . 155
RRCA instruction . . . . . . . . . . . . . . . . . . . 156
RRD instruction . . . . . . . . . . . . . . . . . . . . 156
DMA0 source address B . . . . . . . . . . . . . 99
DMA0 source address high . . . . . . . . . . . 99
DMA0 source address low . . . . . . . . . . . 98
DMA1 byte count high . . . . . . . . . . . . . 106
DMA1 byte count low . . . . . . . . . . . . . 105
DMA1 I/O address high . . . . . . . . . . . . 103
DMA1 I/O address low . . . . . . . . . . . . . 103
DMA1 I/O address register B . . . . . . . . 104
DMA1 memory address B . . . . . . . . . . 103
DMA1 memory address high . . . . . . . . 102
DMA1 memory address low . . . . . . . . . 102
Flags (F) . . . . . . . . . . . . . . . . . . . . . . . . . 11
Free-running . . . . . . . . . . . . . . . . . . . . . . 72
Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
I register . . . . . . . . . . . . . . . . . . . . . . . . . 14
Indirect addressing mode . . . . . . . . . . . . 21
Interrupt edge . . . . . . . . . . . . . . . . . . . . . 14
I/O control . . . . . . . . . . . . . . . . . . . . . . . . 77
I/O Port A alternate function select . . . . 88
I/O Port A data . . . . . . . . . . . . . . . . . . . . 87
I/O Port A data direction . . . . . . . . . . . . . 88
I/O Port A output control . . . . . . . . . . . . 89
I/O Port B alternate function select . . . . . 91
I/O Port B data . . . . . . . . . . . . . . . . . . . . 89
I/O Port B data direction . . . . . . . . . . . . . 90
I/O Port B output control . . . . . . . . . . . . 92
I/O Port C alternate function select . . . . . 94
I/O Port C data . . . . . . . . . . . . . . . . . . . . 92
I/O Port C data direction . . . . . . . . . . . . . 93
I/O Port C output control . . . . . . . . . . . . 94
I/O Port D alternate function select . . . . 96
I/O Port D data . . . . . . . . . . . . . . . . . . . . 95
I/O Port D data direction . . . . . . . . . . . . . 95
I/O Port D output control . . . . . . . . . . . . 97
IL register . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 80
Interrupt edge . . . . . . . . . . . . . . . . . . . . . 81
Interrupt high address (I) . . . . . . . . . . . . 11
Interrupt trap control . . . . . . . . . . . . . . . . 80
Interrupt vector low . . . . . . . . . . . . . . . . 80
Interrupt/trap control . . . . . . . . . . . . . . . . 14
Month . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Operating mode control . . . . . . . . . . . . . 76
Output control . . . . . . . . . . . . . . . . . . . . . 77
PIOS address/type . . . . . . . . . . . . . . . . . 130
PIOS control . . . . . . . . . . . . . . . . . . . . . 129
PIOS counter high . . . . . . . . . . . . . . . . . 130
PS000500-ZMP0599
Preliminary Z80S183
Index-7
RST instruction . . . . . . . . . . . . . . . . . . . . . 156
RTC
Transfers, DMA . . . . . . . . . . . . . . . . . . . . . 40
Transmission
Clock taken from wrong pin . . . . . . . . . 180
Control/status register . . . . . . . . . . . . . . 118
RTC alarm . . . . . . . . . . . . . . . . . . . . . . . . . 180
Rx overrun status . . . . . . . . . . . . . . . . . . . . . 61
ASCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Transmit
CSI/O byte . . . . . . . . . . . . . . . . . . . . . . . 69
Stop bits . . . . . . . . . . . . . . . . . . . . . . . . . 61
Trap handling . . . . . . . . . . . . . . . . . . . . . . . 12
Triggers, Schmitt . . . . . . . . . . . . . . . . . . . 180
TST instruction . . . . . . . . . . . . . . . . . . . . . 157
TSTIO instruction . . . . . . . . . . . . . . . . . . . 157
5
Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SBC instruction . . . . . . . . . . . . . . . . . . . . . 156
SCF instruction . . . . . . . . . . . . . . . . . . . . . 156
Schmitt triggers . . . . . . . . . . . . . . . . . . . . . 180
SET instruction . . . . . . . . . . . . . . . . . . . . . 156
SLA instruction . . . . . . . . . . . . . . . . . . . . . 156
SLP instruction . . . . . . . . . . . . . . . . . . . . . 156
SRA instruction . . . . . . . . . . . . . . . . . . . . . 156
SRL instruction . . . . . . . . . . . . . . . . . . . . . 156
Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . 11
Status
Break conditions . . . . . . . . . . . . . . . . . . . 61
Operation . . . . . . . . . . . . . . . . . . . . . . . . 61
Receive . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Rx overrun . . . . . . . . . . . . . . . . . . . . . . . 61
SUB instruction . . . . . . . . . . . . . . . . . . . . . 157
Symbols, instruction summary . . . . . . . . . 146
system configuration register . . . . . . . . . . . 79
9
Wait state generator control register . . . . . . 83
Waits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Watch-Dog timer . . . . . . . . . . . . . . . . . . . 112
Master register . . . . . . . . . . . . . . . . . . . 110
:
;
<
XOR instruction . . . . . . . . . . . . . . . . . . . . 157
Year register . . . . . . . . . . . . . . . . . . . . . . . 122
ZiLOG Debug Interface (ZDI) . . . . . . . . . 181
6
Temperature, operating
AC extended range . . . . . . . . . . . . . . . . 171
AC normal range . . . . . . . . . . . . . . . . . . 168
Temperature, operation
DC extended range . . . . . . . . . . . . . . . . 167
DC normal range . . . . . . . . . . . . . . . . . . 166
Test conditions . . . . . . . . . . . . . . . . . . . . . 165
Timer control register . . . . . . . . . . . . . . . . 115
Timing
IORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timing diagrams . . . . . . . . . . . . . . . . . . . . 175
Basic timing . . . . . . . . . . . . . . . . . . . . . 175
Bus exchange timing . . . . . . . . . . . . . . . 178
DMA timing . . . . . . . . . . . . . . . . . . . . . 179
I/O read timing . . . . . . . . . . . . . . . . . . . 177
I/O write timing . . . . . . . . . . . . . . . . . . 177
Interrupt timing . . . . . . . . . . . . . . . . . . . 178
Memory read timing (one wait state) . . 176
Memory write timing . . . . . . . . . . . . . . 176
Topmark submission . . . . . . . . . . . . . . . . . 184
Index-8
Preliminary Z80S183
PS000500-ZMP0599
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