Z86E0816PSG [ZILOG]
Z86E3016PSG;
| 型号： | Z86E0816PSG |
| 厂家： | 
ZILOG, INC. |
| 描述： | Z86E3016PSG |
| 文件： | 总348页 (文件大小：1590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z8 Family of Microcontrollers
Z8 CPU
User Manual
UM001602-0904
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
Z8 Family of Microcontrollers
User Manual
ii
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products
and/or service names mentioned herein may be trademarks of the companies with which they are associated.
©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and
limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc.
makes no warranty of merchantability or fitness for any purpose Except with the express written approval of
ZiLOG, use of information, devices, or technology as critical components of life support systems is not
authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual
property rights.
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Revision History
Each instance in Table 1 reflects a change to this document from its previ-
ous revision. To see more detail, click the appropriate link in the table.
Table 1. Revision History of this Document
Revision
Date
Level
Section
Description
Page #
Sept.
2004
02
Formatted to current publication standards
All
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Revision History
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Table of Contents
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
Z8 CPU Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Z8 CPU Standard Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RAM Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Working Register Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Z8 Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Z8 Control and Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Standard Z8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Expanded Z8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Z8 External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Z8 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SCLK ÷ TCLK Divide-By-16 Select . . . . . . . . . . . . . . . . . . . . . . . . . 34
External Clock Divide-By-Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Indications of an Unreliable Design . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Crystals and Resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
LC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reset Pin, Internal POR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Watch–Dog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Power-On-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Input and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
General I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
General I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Handshake Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
General Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
General Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Port Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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I/O Port Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Full Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Comparator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Comparator Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Comparator Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Open-Drain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Low EMI Emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Z8 CMOS Autolatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Autolatch Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Counters and Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Prescalers and Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Counter/Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Load and Enable Count Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Prescaler Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
T
T
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
OUT
IN
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Gated Internal Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Triggered Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Retriggerable Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Cascading Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
External Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Internal Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Interrupt Request Register Logic and Timing . . . . . . . . . . . . . . . . . . . . . 141
Interrupt Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Interrupt Priority Register Initialization . . . . . . . . . . . . . . . . . . . . . . 143
Interrupt Mask Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . 145
Interrupt Request Register Initialization . . . . . . . . . . . . . . . . . . . . . . 147
IRQ Software Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Vectored Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Vectored Interrupt Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Nesting of Vectored Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Polled Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Halt Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Serial Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
UART Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
UART Bit-Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
UART Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Receiver Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
UART Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
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Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SPI Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
SPI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Receive Character Available and Overrun . . . . . . . . . . . . . . . . . . . . . . . 182
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
External Addressing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
External Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Extended Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Z8 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Processor Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Sign Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Decimal Adjust Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Half Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Notation and Binary Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Z8 Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
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Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Customer Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
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List of Figures
Figure 1. Z8 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. 16-Bit Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Accessing Individual Bits (Example) . . . . . . . . . . . . . . . . . 9
Figure 4. Working Register Addressing Examples . . . . . . . . . . . . . 12
Figure 5. Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Expanded Register File Architecture . . . . . . . . . . . . . . . . 15
Figure 7. Register Pointer Example . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Z8 Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 10. Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11. Stack Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
®
Figure 12. Z8 CPU Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. External Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16. Pierce Oscillator with Internal Feedback Circuit . . . . . . . 37
Figure 17. Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 18. Crystal/Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . 41
Figure 19. LC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20. External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. RC Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22. Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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List of Figures
Z8 Family of Microcontrollers
User Manual
xii
Figure 23. Example of External Power-On Reset Circuit . . . . . . . . . . 50
Figure 24. Example of Z8 Reset with RESET Pin, WDT, SMR,
and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 25. Example of Z8 Reset with WDT, SMR, and POR . . . . . . 54
Figure 26. Example of Z8 Watch–Dog Timer Mode Register . . . . . . 56
Figure 27. Example of Z8 with Simple SMR and POR . . . . . . . . . . . 59
Figure 28. I/O Ports and Mode Registers . . . . . . . . . . . . . . . . . . . . . . 62
Figure 29. Ports 0, 1, 2 Generic Block Diagram . . . . . . . . . . . . . . . . 64
Figure 30. Port 0 Configuration with Open-Drain Capability,
Autolatch, and Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . . 66
Figure 31. Port 0 Configuration with TTL Level Shifter . . . . . . . . . . 67
Figure 32. Port 0 I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 33. Port 0 Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 34. Port 1 Configuration with Open-Drain Capability,
Autolatch, and Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . . 70
Figure 35. Port 1 Configuration with TTL Level Shifter . . . . . . . . . . 71
Figure 36. Port 1 I/O Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 37. Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 38. Port 2 I/O Mode Configuration . . . . . . . . . . . . . . . . . . . . . 74
Figure 39. Port 2 Configuration with Open-Drain Capability,
Autolatch, and Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . . 75
Figure 40. Port 2 Configuration with TTL Level Shifter . . . . . . . . . . 76
Figure 41. Port 2 Configuration with Open-Drain Capability,
Autolatch, Schmitt-Trigger and SPI . . . . . . . . . . . . . . . . . 77
Figure 42. Port 2 Handshake Configuration . . . . . . . . . . . . . . . . . . . . 79
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List of Figures
Z8 CPU
User Manual
xiii
Figure 43. Port 2 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 44. Port 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 45. Port 3 Configuration with Comparator, Autolatch, and
Schmitt-Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 46. Port 3 Configuration with Comparator . . . . . . . . . . . . . . . 84
Figure 47. Port 3 Configuration with SPI and Comparator Outputs . 86
Figure 48. Port 3 Configuration with TTL Level Shifter and
Autolatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 49. Port 3 Mode Register Configuration . . . . . . . . . . . . . . . . . 88
Figure 50. Z8 Input Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 51. Z8 Output Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 52. Output Strobed Handshake on Port 2 . . . . . . . . . . . . . . . . 94
Figure 53. Input Strobed Handshake on Port 2 . . . . . . . . . . . . . . . . . 94
Figure 54. Port 0/1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 55. Port 2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 56. Port 3 Mode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 57. Port 3 Input Analog Selection . . . . . . . . . . . . . . . . . . . . . . 99
Figure 58. Port 3 Comparator Output Selection . . . . . . . . . . . . . . . . 100
Figure 59. Port Configuration of Comparator Inputs on P31, P32,
and P33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 60. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 61. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 62. Port Configuration Register . . . . . . . . . . . . . . . . . . . . . . 106
Figure 63. Diode Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 64. OTP Diode Input Protection . . . . . . . . . . . . . . . . . . . . . . 110
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List of Figures
Z8 Family of Microcontrollers
User Manual
xiv
Figure 65. Simplified CMOS Z8 I/O Circuit . . . . . . . . . . . . . . . . . . 111
Figure 66. Autolatch Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . 113
Figure 67. Effect of Pulldown Resistors on Autolatches . . . . . . . . . 114
Figure 68. Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . 116
Figure 69. Counter/Timer Register Map . . . . . . . . . . . . . . . . . . . . . . 118
Figure 70. Prescaler 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 71. Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 72. Counter/Timer 0 and 1 Registers . . . . . . . . . . . . . . . . . . . 119
Figure 73. Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 74. Starting The Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 75. Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 76. Timer Mode Register (T
Figure 77. Port 3 Mode Register (T
Operation) . . . . . . . . . . . . . 124
Operation) . . . . . . . . . . . . . 125
OUT
OUT
Figure 78. T0 and T1 Output Through T
. . . . . . . . . . . . . . . . . . 126
OUT
Figure 79. Internal Clock Output Through T
. . . . . . . . . . . . . . . 127
OUT
Figure 80. Timer Mode Register (T Operation) . . . . . . . . . . . . . . 128
IN
Figure 81. Prescaler 1 Register (T Operation) . . . . . . . . . . . . . . . . 128
IN
Figure 82. External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 83. Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 84. Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 85. Cascaded Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 86. Counter/Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 87. Prescaler 1 Register Reset . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 88. Prescaler 0 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
List of Figures
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User Manual
xv
Figure 89. Timer Mode Register Reset . . . . . . . . . . . . . . . . . . . . . . 135
Figure 90. Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 91. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 92. Interrupt Sources IRQ0-IRQ2 Block Diagram . . . . . . . . 140
Figure 93. Interrupt Source IRQ3 Block Diagram . . . . . . . . . . . . . . 141
Figure 94. IRQ Register Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 95. Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 96. Interrupt Priority Register . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 97. Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 98. Interrupt Request Register . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 99. IRQ Reset Functional Logic Diagram . . . . . . . . . . . . . . . 149
Figure 100. Effects of an Interrupt on the Stack . . . . . . . . . . . . . . . . . 151
Figure 101. Interrupt Vectoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 102. Z8 Interrupt Acknowledge Timing . . . . . . . . . . . . . . . . . 153
Figure 103. Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . 160
Figure 104. Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . 163
Figure 105. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 106. Port 3 Mode Register and Bit-Rate Generation . . . . . . . 167
Figure 107. Bit Rate Divide Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 108. Prescaler 0 Register Bit-Rate Generation . . . . . . . . . . . . 169
Figure 109. Timer Mode Register Bit Rate Generation . . . . . . . . . . . 169
Figure 110. Receiver Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 111. Receiver Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 112. Port 3 Mode Register Parity . . . . . . . . . . . . . . . . . . . . . . 173
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Figure 113. Transmitter Data Formats . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 114. SIO Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 115. P3M Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 116. SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 117. SPI System Configuration . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 118. SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 119. SPI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 120. SPI Data In/Out Configuration . . . . . . . . . . . . . . . . . . . . 184
Figure 121. SPI Clock/SPI Slave Select Output Configuration . . . . . 185
Figure 122. Z8 CPU External Interface Pins . . . . . . . . . . . . . . . . . . . 187
Figure 123. External Address Configuration . . . . . . . . . . . . . . . . . . . 190
Figure 124. Z8 Stack Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 125. Port 3 Data Memory Operation . . . . . . . . . . . . . . . . . . . . 192
Figure 126. External Instruction Fetch or Memory Read Cycle . . . . . 193
Figure 127. External Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . 194
Figure 128. Extended External Instruction Fetch or Memory Read
Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 129. Extended External Memory Write Cycle . . . . . . . . . . . . 197
Figure 130. Extended Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 131. Instruction Cycle Timing (1-Byte Instructions) . . . . . . . 199
Figure 132. Instruction Cycle Timing (2- and 3-Byte Instructions) . . 200
Figure 133. Z8 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 134. Op Code Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
List of Figures
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xvii
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Revision History of this Document . . . . . . . . . . . . . . . . . . . iii
ZiLOG General-Purpose Microcontroller Product Family . 4
Z8 Standard Register File . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Working Register Groups . . . . . . . . . . . . . . . . . . . . . . . . . 11
ERF Bank Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register Pointer Access Example . . . . . . . . . . . . . . . . . . . 18
ERF Bank C Access Example . . . . . . . . . . . . . . . . . . . . . . 20
Z8 Expanded Register File Bank Layout . . . . . . . . . . . . . 20
Expanded Register File Register Bank C . . . . . . . . . . . . . 23
Table 10. Expanded Register File Bank 0 . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Expanded Register File Bank F . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Crystal/Resonator Characteristics . . . . . . . . . . . . . . . . . . . 41
Table 13. Sample Control and Peripheral Register Reset Values
(ERF Bank 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 14. Expanded Register File Bank 0 Reset Values at RESET . 51
Table 15. Sample Expanded Register File Bank C Reset Values . . . 51
Table 16. Sample Expanded Register File Bank F Reset Values . . . 52
Table 17. Time-Out Period of the WDT . . . . . . . . . . . . . . . . . . . . . . 57
Table 18. Port 3 Line Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 19. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . 139
Table 20. Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 21. Interrupt Group Priority . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 22. IRQ Register Configuration . . . . . . . . . . . . . . . . . . . . . . 149
Table 23. Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . 161
Table 24. UART Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 25. Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
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Z8 Family of Microcontrollers
User Manual
xviii
Table 26. SPI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 27. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 28. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 29. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 30. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . 202
Table 31. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . 203
Table 32. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . 203
Table 33. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . 204
Table 34. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 35. Z8 Flag Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 36. Flag Settings Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 37. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 38. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 39. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 40. Summary of Z8 Instruction Set . . . . . . . . . . . . . . . . . . . . 213
Table 41. Summary of Z8 Address Modes . . . . . . . . . . . . . . . . . . . 221
Table 42. Process Manipulation Functions . . . . . . . . . . . . . . . . . . . 223
List of Tables
UM001602-0904
Z8 CPU
User Manual
1
Z8 CPU Product Overview
The ZiLOG Z8 microcontroller (MCU) product line continues to expand
with new product introductions. ZiLOG MCU products are targeted for
cost-sensitive, high-volume applications including consumer, automotive,
security, and HVAC. It includes ROM-based products geared for high-
volume production (where software is stable) and one-time programma-
ble (OTP) equivalents for prototyping as well as volume production
where time to market or code flexibility is critical (see Table 1 on page 4).
A variety of packaging options are available including plastic DIP, SOIC,
PLCC, and QFP.
®
A generalized Z8 CPU block diagram is shown in Figure 1. The same
on-chip peripherals are used across the MCU product line with the pri-
mary differences being the amount of ROM/RAM, number of I/O lines
present, and packaging/temperature ranges available. This allows code
written for one MCU device to be easily ported to another family mem-
ber.
Key Features
General-Purpose Register File. Every RAM register acts like an accu-
mulator, speeding instruction execution and maximizing coding effi-
ciency. Working register groups allow fast context switching.
Flexible I/O. I/O byte, nibble, and/or bit programmable as inputs or out-
puts. Outputs are software programmable as open-drain or push–pull on a
port basis. Inputs are Schmitt-triggered with autolatches to hold unused
inputs at a known voltage state.
Analog Inputs. Three input pins are software programmable as digital or
analog inputs. When in analog mode, two comparator inputs are provided
with a common reference input. These inputs are ideal for a variety of
common functions, including threshold level detection, analog-to-digital
UM001602-0904
Z8 CPU Product Overview
Z8 Family of Microcontrollers
User Manual
2
conversion, and short circuit detection. Each analog input provides a
unique maskable interrupt input.
Timer/Counter. The Timer/Counter (T/C) consists of a programmable 6-
bit prescaler and 8-bit downcounter, with maskable interrupt upon end-of-
count. Software controls T/C load/start/stop, countdown read (at any time
on the fly), and maskable end-of-count interrupt. Special functions avail-
able include T (external counter input, external gate input, or external
IN
trigger input) and T
(external access to timer output or the internal
OUT
system clock.) These special functions allow accurate hardware input
pulse measurement and output waveform generation.
Interrupts. There are six vectored interrupt sources with software-pro-
grammable enable and priority for each of the six sources.
Watch–Dog Timer. An internal Watch–Dog Timer (WDT) circuit is
included as a fail-safe mechanism so that if software strays outside the
bounds of normal operation, the WDT will time-out and reset the MCU.
To maximize circuit robustness and reliability, the default WDT clock
source is an internal RC circuit (isolated from the device clock source).
Auto Reset/Low-Voltage Protection. All family devices have internal
Power-On Reset. ROM devices add low-voltage protection. Low-voltage
protection ensures the MCU is in a known state at all times (in active
RUN mode or RESET) without external hardware (or a device reset pin).
Low-EMI Operation. Mode is programmable via software or as a mask
option. This new option provides for reduced radiated emission via clock
and output drive circuit changes.
Low-Power. CMOS with two standby modes; STOP and HALT.
Full Z8 Instruction Set. Forty-eight basic instructions, supported by six
addressing modes with the ability to operate on bits, nibbles, bytes, and
words.
Z8 CPU Product Overview
UM001602-0904
Z8 CPU
User Manual
3
Input
Output
GND
V
XTAL
AS DS
CC
R/W RESET
Machine Timing
& Instruction Control
Port 3
RESET, WDT,
POR
ALU
Counter/
Timers (2)
FLAG
Prg. Memory
512/K x 8-Bit
Interrupt
Control
Register
Pointer
Register File
256 x 8-Bit
Program
Counter
Analog
Comparators
(2)
Port 1
8
Port 2
Port 0
4
4
I/O
Address or I/O
(Nibble Programmable)
Address/Data or I/O
(Byte Programmable)
(Bit Programmable)
Figure 1. Z8 CPU Block Diagram
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Z8 Family of Microcontrollers
User Manual
4
Product Development Support
®
The Z8 MCU product line is fully supported with a range of cross
assemblers, C compilers, ICEBOX emulators, single and gang OTP/
EPROM programmers, and software simulators.
The Z86CCP01ZEM low-cost Z8 CCP™ real-time emulator/programmer
kit was designed specifically to support all of the products outlined in
Table 1.
Table 1. ZiLOG General-Purpose Microcontroller Product Family
ROM/
RAM
Speed
(MHz) Count
Pin
Product
Z86C03
Z86E03
I/0
14
14
T/C AN INT WDT POR
V
RC
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
BO
512/60
512/60
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
6
6
6
6
6
6
6
6
6
6
6
6
6
6
F
F
F
F
P
P
F
F
P
P
P
P
P
P
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
Y
N
Y
N
Y
N
Y
N
Y
N
8
8
18
18
Z86C04 1K/124 14
Z86E04 1K/124 14
Z86C06 1K/124 14
Z86E06 1K/124 14
Z86C08 2K/124 14
Z86E08 2K/124 14
Z86C30 4K/236 24
Z86E30 4K/236 24
Z86C31 2K/124 24
Z86E31 2K/124 24
Z86C40 4K/236 32
Z86E40 4K/236 32
8
18
8
18
12
12
12
12
12
12
8
18
18
18
18
28
28
28
8
28
16
16
40/44
40/44
*Note: Z86Cxx signify ROM devices; 86xx signify EPROM devices; F = fixed; P = programmable
Z8 CPU Product Overview
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The Z86CCP01ZEM kit comes with:
•
•
•
Z8 CCP Evaluation Board
Z8 CCP Power Cable
ZiLOG Developer’s Studio (ZDS) CD-ROM , Including Windows-
Based GUI Host Software
•
•
1999 ZiLOG Technical Library
Z8 CCP User Manual
A Z8 CCP Emulator Accessory Kit (Z8CCP00ZAC) is also available and
provides an RS-232 cable and power cable along with the 28- and 40- pin
ZIF sockets and 28- and 40- pin target connector cables required to emu-
late/program 28/40 pin devices.
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Z8 CPU Product Overview
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Address Space
Introduction
®
Four address spaces are available for the Z8 CPU:
®
•
The Z8 Standard Register File contains addresses for peripheral,
control, all general-purpose, and all I/O port registers. This is the
default register file specification.
®
•
•
•
The Z8 Expanded Register File (ERF) contains addresses for con-
trol and data registers for additional peripherals/features.
Z8 external program memory contains addresses for all memory loca-
tions having executable code and/or data.
Z8 external data memory contains addresses for all memory locations
that hold data only, whether internal or external.
Z8 CPU Standard Register File
®
The Z8 Standard Register File totals up to 256 consecutive bytes (Regis-
ters). The register file consists of 4 I/O ports (00h–03h), 236 General-
Purpose Registers (04h–EFh), and 16 control registers (F0h–FFh).
Table 2 shows the layout of the register file, including register names,
locations, and identifiers.
Table 2. Z8 Standard Register File
Hex Address Register Identifier Register Description
FF
FE
FD
SPL
SPH
RP
Stack Pointer Low Byte
Stack Pointer High Byte
Register Pointer
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Table 2. Z8 Standard Register File (Continued)
Hex Address Register Identifier Register Description
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
EF
FLAGS
IMR
Program Control Flags
Interrupt Mask Register
Interrupt Request Register
Interrupt Priority Register
Port 0–1 Mode Register
Port 3 Mode Register
Port 2 Mode Register
T0 Prescaler
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
Timer/Counter 0
PRE1
T1
T1 Prescaler
Timer/Counter 1
TMR
SIO
Timer Mode
Serial I/O
R239
General-Purpose Registers (GPR)
04
03
02
01
00
R4
P3
P2
P1
P0
Port 3
Port 2
Port 1
Port 0
Registers can be accessed as either 8-bit or 16-bit registers using Direct,
Indirect, or Indexed Addressing. All 236 general-purpose registers can be
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referenced or modified by any instruction that accesses an 8-bit register,
without the requirement for special instructions. Registers accessed as 16
bits are treated as even-odd register pairs (there are 118 valid pairs). In
this case, the data’s Most Significant Byte (MSB) is stored in the even
numbered register, while the Least Significant Byte (LSB) goes into the
next higher odd numbered register. See Figure 2.
MSB
Rn
LSB
Rn+1
n = Even Address
Figure 2. 16-Bit Register Addressing
By using a logical instruction and a mask, individual bits within registers
can be accessed for bit set, bit clear, bit complement, or bit test opera-
tions. For example, the instruction AND R15, MASK performs a bit clear
operation. Figure 3 shows this example.
R15
0
1
1
1
0
0
0
0
MASK
1
1
0
1
1
1
1
1
AND R15, DFh
;Clear Bit 5 of Working Register 15
R15
0
1
0
1
0
0
0
0
Figure 3. Accessing Individual Bits (Example)
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When instructions are executed, registers are read when defined as
sources and written when defined as destinations. All General-Purpose
Registers function as accumulators, address pointers, index registers,
stack areas, or scratch pad memory.
General-Purpose Registers
General-Purpose Registers (GPR) are undefined after the device is pow-
ered up. The registers keep their last value after any reset, as long as the
reset occurs in the V voltage-specified operating range. It will not keep
CC
its last state from a V reset if V drops below 1.8v.
LV
CC
Note: Registers in Bank E0-EF may only be accessed through the working regis-
ter and indirect addressing modes. Direct access cannot be used because
the 4-bit working register address mode already uses the format [E | dst],
where dst represents the working register number from 0h to Fh.
RAM Protect
The upper portion of the register file address space 80hto EFh(excluding
the control registers) may be protected from reading and writing. The
RAM Protect bit option is mask-programmable and is selected by the cus-
tomer when the ROM code is submitted. After the mask option is
selected, the user activates this feature from the internal ROM code to
turn off/on the RAM Protect by loading either a 0 or 1 into the IMR regis-
ter, bit D6. A 1 in D6 enables RAM Protect. Only devices that use regis-
ters 80hto EFhoffer this feature.
Working Register Groups
Z8 instructions can access 8-bit registers and register pairs (16-bit words)
using either 4-bit or 8-bit address fields. 8-bit address fields refer to the
actual address of the register. For example, Register 58his accessed by
calling upon its 8-bit binary equivalent, 01011000(58h).
With 4-bit addressing, the register file is logically divided into 16 Work-
ing Register Groups of 16 registers each, as shown in Table 3. These 16
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registers are known as Working Registers. A Register Pointer (one of the
control registers, FDh) contains the base address of the active Working
Register Group. The high nibble of the Register Pointer determines the
current Working Register Group.
When accessing one of the Working Registers, the 4-bit address of the
Working Register is combined within the upper four bits (high nibble) of
the Register Pointer, thus forming the 8-bit actual address. Figure 4 illus-
trates this operation. Because working registers are typically specified by
short format instructions, there are fewer bytes of code required, which
reduces execution time. In addition, when processing interrupts or chang-
ing tasks, the Register Pointer speeds context switching. A special Set
Register Pointer (SRP) instruction sets the contents of the Register
Pointer.
Table 3. Working Register Groups
Register Pointer
(FDh) High Nibble
Working Register ActualRegisters
Group (Hex)
(Hex)
F0–FF
E0–EF
D0–DF
C0–CF
B0–BF
A0–AF
90–9F
80–8F
70–7F
60–6F
50–5F
40–4F
1111b
1110b
1101b
1100b
1011b
1010b
1001b
1000b
0111b
0110b
0101b
0100b
F
E
D
C
B
A
9
8
7
6
5
4
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Table 3. Working Register Groups (Continued)
Register Pointer
(FDh) High Nibble
Working Register ActualRegisters
Group (Hex)
(Hex)
30–3F
20–2F
10–1F
00–0F
0011b
0010b
0001b
0000b
3
2
1
0
Register Pointer (FDh), Standard Register File
0
1
1
1
0
0
1
1
0
0
1
0
INC R6 (instruction, short format)
1
0
1
1
1
1
Actual register address (76h)
0
1
1
1
0
1
Figure 4. Working Register Addressing Examples
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R253
(Register Pointer)
R7 R6 R5 R4 R3 R2 R1 R0
The upper nibble of the register file address,
provided by the register pointer, specifies
the active working-register group.
FF
Working Register Group F
F0
EF
80
7F
70
6F
60
5F
50
4F
40
3F
30
2F
20
1F
10
0F
The lower nibble
of the register
file address
(provided by the
instruction) points
to the specified
register.
Specified Working Register Group
R15 to R0
R15 to R4
R3 to R0
Working Register Group 1
Working Register Group 0
I/O Ports
00
*Note: The full register file is shown. Please refer to the selected device product specification for actual file size.
Figure 5. Register Pointer
Error Conditions
®
Registers in the Z8 Standard Register File must be correctly used
because certain conditions produce inconsistent results and should be
avoided.
•
Registers F3hand F5h–F9hare write-only registers. If an attempt is
made to read these registers, FFhis returned. Reading any write-only
register will return FFh.
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•
When register FDh(Register Pointer) is read, the least significant four
bits (lower nibble) will indicate the current Expanded Register File
Bank. (Example: 0000indicates the Standard Register File, while
1010indicates Expanded Register File Bank A.)
•
•
•
•
When Ports 0 and 1 are defined as address outputs, registers 00hand
01hwill return 1s in each address bit location when read.
Writing to bits that are defined as timer output, serial output, or hand-
shake output will have no effect.
®
The Z8 CPU instruction DJNZ uses any general-purpose working
register as a counter.
Logical instructions such as OR and AND require that the current
contents of the operand be read. They therefore will not function
properly on write-only registers.
•
The WDTMR register must be written within the first 60 internal sys-
tem clocks (SCLK) of operation after a reset.
Z8 Expanded Register File
®
The standard register file of the Z8 CPU has been expanded to form 16
Expanded Register File (ERF) Banks, as shown in Figure 6. Each ERF
Bank consists of up to 256 registers (the same amount as in the Standard
Register File) that can then be divided into 16 Working Register Groups.
This expansion allows for access to additional feature/peripheral control
and data registers.
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Expanded Register File
Bank (F)
(F) 0F WDTMR
(F) 0E Reserved
(F) 0D Reserved
(F) 0C Reserved
Register Pointer
D7 D6 D5 D4 D3 D2 D1 D0
(F) 0B SMR
Working Register
Group Pointer
Expanded Register
Group Pointer
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
Z8 Register File
FF
F0
Expanded Register File
Bank (C)
(C) 0F Reserved
(C) 0E Reserved
(C) 0D Reserved
(C) 0C Reserved
(C) 0B Reserved
(C) 0A Reserved
(C) 09 Reserved
(C) 08 Reserved
(C) 07 Reserved
7F
Expanded Register File
Bank (0)
(0) 0F
(0) 0E
(0) 0D
(0) 0C
(0) 0B
(0) 0A
(0) 09
(0) 08
(0) 07
GPR
0F
00
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
P3
(C) 06 Reserved
(C) 05 Reserved
(C) 04 Reserved
(C) 03 Reserved
(C) 02 SCON
(C) 01 RXBUF
(C) 00 SCOMP
(0) 06
(0) 05
(0) 04
(0) 03
(0) 02 P2
(0) 01 P1
(0) 00 P0
*Note: The fully implemented register file is shown. Please refer to the specific product specification for actual register file archi-
tecture implemented.
Figure 6. Expanded Register File Architecture
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Currently, three out of the possible sixteen Z8 ERF Banks have been
®
implemented. ERF Bank 0, also known as the Z8 Standard Register File,
has all 256 bytes defined, as shown in Figure 7. Only Working Register
Group 0 (register addresses 00hto 0Fh) have been defined for ERF Bank
C and ERF Bank F (see Table 4). All other working register groups in
ERF Banks C and F, as well as the remaining thirteen ERF Banks, are not
implemented. All are reserved for future use.
When an ERF Bank is selected, register addresses 00hto 0Fhaccess
those sixteen ERF Bank registers—in effect replacing the first sixteen
®
locations of the Z8 Standard Register File.
®
For example, if ERF Bank C is selected, the Z8 Standard Registers 00h
through 0Fhare no longer accessible. Registers 00hthrough 0Fhare now
the 16 registers from ERF Bank C, Working Register Group 0. No other
Z8 Standard Registers are affected because only Working Register Group
0 is implemented in ERF Bank C.
Access to the ERF is accomplished through the Register Pointer (FDh).
The lower nibble of the Register Pointer determines the ERF Bank while
the upper nibble determines the Working Register Group within the regis-
ter file, as Figure 7 shows.
0 1 1 1
1 1 0 0
Expanded
Register
Bank
Working
Register
Group
Select ERF Bank Ch
Working Register Group 7h
Figure 7. Register Pointer Example
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The value of the lower nibble in the Register Pointer (FDh) corresponds to
the ERF Bank identification. Table 4 shows the lower nibble value and the
register file assigned to it.
Table 4. ERF Bank Address
Register
Pointer (FDh)
Hex
Low Nibble
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Register File
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Z8 Standard Register File.*
Expanded Register File Bank 1.
Expanded Register File Bank 2.
Expanded Register File Bank 3..
Expanded Register File Bank 4
Expanded Register File Bank 5..
Expanded Register File Bank 6
Expanded Register File Bank 7..
Expanded Register File Bank 8
Expanded Register File Bank 9..
Expanded Register File Bank A
Expanded Register File Bank B.
Expanded Register File Bank C.
Expanded Register File Bank D..
Expanded Register File Bank E
Expanded Register File Bank F.
*Note: the Z8® Standard Register File is equivalent to Expanded Register File Bank 0.
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The upper nibble of the register pointer selects which group of 16 bytes in
the Register File, out of the 256 total bytes, will be accessed as working
registers. Table 5 shows an example.
Table 5. Register Pointer Access Example
R253 RP = 00h ;ERF Bank 0, Working Reg. Group 0.
R0 = Port 0 = 00h
R1 = Port 1 = 01h
R2 = Port 2 = 02h
R3 = Port 3 = 03h
R11 = GPR 0Bh
R15 = GPR 0Fh
If R253 RP = 0Fh ;ERF Bank F, Working Reg. Group 0.
R0 = PCON = 00h
R1 = Reserved = 01h
R2 = Reserved = 02h
R11 = SMR = 0Bh
R15 = WDTMR = 0Fh
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Table 5. Register Pointer Access Example (Continued)
If R253 RP = FFh
;ERF Bank F, Working Reg. Group F.
00h = PCON
R0 = SI0
01h = Reserved
02h = Reserved
...
R1 = TMR
R2 = T1
0Bh = SMR
...
R15 = SPL
0Fh = WDTMR
Because enabling an ERF Bank (C or F) only changes register addresses
00hto 0Fh, the working register pointer can be used to access either the
®
selected ERF Bank (Bank C or F, Working Register Group 0) or the Z8
Standard Register File (ERF Bank 0, Working Register Groups 1 through
F).
When an ERF Bank other than Bank 0 is enabled, the first 16 bytes of the
®
Z8 Standard Register File (I/O ports 0 to 3, Groups 4 to F) are no longer
accessible (the selected ERF Bank, Registers 00hto 0Fhare accessed
instead). It is important to re-initialize the Register Pointer to enable ERF
Bank 0 when these registers are required for use.
The SPI register is mapped into ERF Bank C. Access is easily done using
the example in Table 6.
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Table 6. ERF Bank C Access Example
LD
RP, #0Ch
;Select ERF Bank C working
;register group 0 for access.
;access SCON
LD
LD
LD
R2,#xx
R1, #xx
RP, #00h
;access RXBUF
;Select ERF Bank 0 so I/O ports
;are again accessible.
Table 7. Z8 Expanded Register File Bank Layout
Expanded Register
File Bank
ERF
Fh
PCON, SMR, WDT, (00h, 0Bh, 0Fh),
Working Register Group 0 only
implemented.
Eh
Dh
Ch
Not implemented (reserved)
Not implemented (reserved)
SPI Registers: SCOMP, RXBUF, SCON
(00h, 01h, 02h), Working Register Group 0
only implemented.
Bh
Ah
9h
8h
7h
6h
5h
Not implemented (reserved)
Not implemented (reserved)
Not implemented (reserved)
Not implemented (reserved)
Not implemented (reserved)
Not implemented (reserved)
Not implemented (reserved)
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Table 7. Z8 Expanded Register File Bank Layout
Expanded Register
File Bank
ERF
4h
3h
2h
1h
0h
Not implemented (reserved)
Not implemented (reserved)
Not implemented (reserved)
Not implemented (reserved)
Z8 Ports 0, 1, 2, 3, and General-Purpose
Registers 04h to EFh, and control
registers F0h to FFh.
Please refer to the specific product specification to determine the above
registers are implemented.
Z8 Control and Peripheral Registers
Standard Z8 Registers
The standard Z8 control registers govern the operation of the CPU. Any
instruction which references the register file can access these control reg-
isters. Available control registers are:
•
•
•
•
•
•
•
Interrupt Priority Register (IPR)
Interrupt Mask Register (IMR)
Interrupt Request Register (IRQ)
Program Control Flags (FLAGS)
Register Pointer (RP)
Stack Pointer High-Byte (SPH)
Stack Pointer Low-Byte (SPL)
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®
The Z8 CPU uses a 16-bit Program Counter (PC) to determine the
sequence of current program instructions. The PC is not an addressable
register.
Peripheral registers are used to transfer data, configure the operating
mode, and control the operation of the on-chip peripherals. Any instruc-
tion that references the register file can access the peripheral registers.
The peripheral registers are:
•
•
•
•
•
•
•
•
•
Serial I/O (SIO)
Timer Mode (TMR)
Timer/Counter 0 (T0)
T0 Prescaler (PRE0)
Timer/Counter 1 (T1)
T1 Prescaler (PRE1)
Port 0–1 Mode (P01M)
Port 2 Mode (P2M)
Port 3 Mode (P3M)
In addition, the four port registers (P0–P3) are considered to be peripheral
registers.
Expanded Z8 Registers
The expanded Z8 control registers govern the operation of additional fea-
tures or peripherals. Any instruction which references the register file can
access these registers.
The ERF contains the control registers for WDT, Port Control, Serial
Peripheral Interface (SPI), and the SMR functions. Figure 6 on page 15
shows the layout of the Register Banks in the ERF. Register Bank C in the
ERF consists of the registers for the SPI. Table 8 shows the registers
within ERF Bank C, Working Register Group 0.
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Table 8. Expanded Register File Register Bank C
WR Group 0
Working
Register
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPI Control (SCON)
Register
R15
R14
R13
R12
R11
R10
R9
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
R8
R7
R6
R5
R4
R3
R2
SPI Tx/Rx Data (Roxburgh) R1
SPI Compare (SCOMP) R0
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Working Register Group 0 in ERF Bank 0 consists of the registers for Z8
General-Purpose Registers and ports. Table 9 shows the registers within
this group.
Table 9. Expanded Register File Bank 0
WR Group 0
Working
Register
Function
Register
R15
R14
R13
R12
R11
R10
R9
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
Port 3
R8
R7
R6
R5
R4
R3
Port 2
R2
Port 1
R1
Port 0
R0
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Working Register Group 0 in ERF Bank F consists of the control registers
for STOP mode, WDT, and port control. Table 10 shows the registers
within this group.
Table 10. Expanded Register File Bank F
WR Group 0
Working
Register
Function
WDTMR
Reserved
Reserved
Reserved
SMR
Register
R15
R14
R13
R12
R11
R10
R9
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCON
R8
R7
R6
R5
R4
R3
R2
R1
R0
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The functions and applications of the control and peripheral registers are
described in subsequent sections of this manual.
Program Memory
The first 12 bytes of program memory are reserved for the interrupt vec-
tors, as shown in Figure 8. These locations contain six 16-bit vectors that
correspond to the six available interrupts. Address 12 up to the maximum
ROM address consists of on-chip mask-programmable ROM. See the
product data sheet for the exact program, data, register memory size, and
®
address range available. At addresses outside the internal ROM, the Z8
CPU executes external program memory fetches through Port 0 and Port
1 in Address/Data mode for devices with Port 0 and Port 1 featured. Oth-
erwise, the program counter will continue to execute NOPs up to address
FFFFh, roll over to 0000h, and continue to fetch executable code (see
Figure 8).
The internal program memory is one-time programmable (OTP) or mask
programmable dependent on the specific device. A ROM protect feature
prevents dumping of the ROM contents by inhibiting execution of the
LDC, LDCI, LDE, and LDEI instructions to program memory in all
modes. ROM look-up tables cannot be used with this feature.
The ROM Protect option is mask-programmable, to be selected by the
customer when the ROM code is submitted. For the OTP ROM, the ROM
Protect option is an OTP programming option.
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65535
External
ROM and RAM
4096
4095
Location of
First Byte of
Instruction
Executed
On–Chip
ROM
After RESET
12
11
10
9
IRQ
IRQ
IRQ
5
5
4
IRQ
8
7
6
4
3
IRQ
IRQ
Interrupt
Vector
(Lower Byte)
3
2
2
IRQ
IRQ
5
4
3
2
1
0
Interrupt
Vector
(Upper Byte)
IRQ
1
IRQ
IRQ
1
0
IRQ
0
Figure 8. Z8 Program Memory Map
Z8 External Memory
®
The Z8 CPU, in some cases, has the capability to access external pro-
gram memory with the 16-bit Program Counter. To access external pro-
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®
gram memory the Z8 CPU offers multiplexed address/data lines (AD7–
AD0) on Port 1 and address lines (A15–A8) on Port 0. This feature only
applies to devices that offer Port 0 and Port 1. The maximum external
address is FFFF. This memory interface is supported by the control lines
AS (Address Strobe), DS (Data Strobe), and R/W (Read/Write). The ori-
gin of the external program memory starts after the last address of the
internal ROM. Figure 9 shows an example of external program memory
®
for the Z8 CPU.
External Data Memory
®
The Z8 CPU, in some cases, can address up to 60KB of external data
memory beginning at location 4096. External data memory (DM) can be
included with, or separated from, the external program memory space.
DM, an optional I/O function that can be programmed to appear on pin
P34, is used to distinguish between data and program memory space. The
state of the DM signal is controlled by the type of instruction being exe-
cuted. An LDC opcode references program memory (DM inactive) , and
an LDE instruction references data memory (DM active Low) . The user
must configure Port 3 Mode Register (P3M) bits D3 and D4 for this
mode.
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65535
External
Memory
4096
4095
Not Addressable
0
*Note: For additional information on using external memory, see Chapter 10 of this manual. For exact
memory addressing options available, see the device product specification.
Figure 9. External Memory Map
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Z8 Stacks
®
Stack operations can occur in either the Z8 Standard Register File or
external data memory. Under software control, Port 0–1 Mode register
(F8h) selects the stack location. Only the General-Purpose Registers can
be used for the stack when the internal stack is selected.
The register pair FEhand FFhform the 16-bit Stack Pointer (SP), that is
used for all stack operations. The stack address is stored with the MSB in
FEhand LSB in FFh; see Figure 10.
FFh
LOWER Byte
Stack Pointer Low
Stack Pointer High
FEh
UPPER Byte
Figure 10. Stack Pointer
The stack address is decremented prior to a PUSH operation and incre-
mented after a POP operation. The stack address always points to the data
®
stored on the top of the stack. The Z8 CPU stack is a return stack for
CALL instructions and interrupts, as well as a data stack.
During a CALL instruction, the contents of the PC are saved on the stack.
The PC is restored during a RETURN instruction. Interrupts cause the
contents of the PC and Flag registers to be saved on the stack. The IRET
instruction restores them Figure 11.
®
®
When the Z8 CPU is configured for an internal stack (using the Z8
Standard Register File), register FFhserves as the Stack Pointer. The
Address Space
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value in FEhis ignored. FEhcan be used as a general-purpose register in
this case only.
An overflow or underflow can occur when the stack address is incre-
mented or decremented during normal stack operations. The programmer
must prevent this occurrence or unpredictable operation will result.
PCL
PCH
PCL
PCH
Top of Stack
Top of Stack
FLAGS
Stack Contents
After a Call
Instruction
Stack Contents
After an
Interrupt Cycle
Figure 11. Stack Operations
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Address Space
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Clock
®
The Z8 CPU derives its timing from on-board clock circuitry connected
to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a
divide-by-two shaping circuit, and a clock buffer. Figure 12 illustrates the
clock circuitry. The oscillator’s input is XTAL1 and its output is XTAL2.
The clock can be driven by a crystal, a ceramic resonator, LC clock, RC,
or an external clock source.
Frequency Control
®
In some cases, the Z8 CPU has an EPROM/OTP option or a Mask ROM
option bit to bypass the divide-by-two flip flop in Figure 12. This feature
is used in conjunction with the low EMI option. When low EMI is
selected, the device output drive and oscillator drive is reduced to approx-
imately 25 percent of the standard drive and the divide-by-two flip flop is
bypassed such that the XTAL clock frequency is equal to the internal sys-
tem clock frequency. In this mode, the maximum frequency of the XTAL
clock is 4MHz. Please refer to specific product specification for availabil-
ity of options and output drive characteristics.
XTAL1
Internal
Clock
÷2
OSC
XTAL2
Buffer
®
Figure 12. Z8 CPU Clock Circuit
Clock Control
®
In some cases, the Z8 CPU offers software control of the internal system
clock via programming register bits. The bits are located in the Stop-
Mode Recovery Register in Expanded Register File Bank F, Register 0Bh.
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This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (see Figure 13). Please refer to the specific product
specification for availability of this feature/register.
SMR (F) OB
D7 D6 D5 D4 D3 D2 D1 D0
SCLK ÷ TCLK Divide by 16
0 OFF **
1 ON
External Clock Divide Mode by 2
0 = SCLK ÷ TCLK = XTAL ÷ 2*
1 = SCLK ÷ TCLK = XTAL
* Default setting after RESET.
**Default setting after RESET and Stop-Mode Recovery.
Figure 13. Stop-Mode Recovery Register (Write-Only Except D7,
Which is Read-Only)
SCLK ÷ TCLK Divide-By-16 Select
The D0 bit of the SMR controls a divide-by-16 prescaler of
SCLK ÷ TCLK. The purpose of this control is to selectively reduce
device power consumption during normal processor execution (SCLK
control) and/or HALT mode (where TCLK sources counter/timers and
interrupt logic).
External Clock Divide-By-Two
The D1 bit can eliminate the oscillator divide-by-two circuitry. When this
bit is 0, SCLK (System Clock) and TCLK (Timer Clock) are equal to the
external clock frequency divided by two. The SCLK ÷ TCLK is equal to
the external clock frequency when this bit is set (D1 = 1). Using this bit,
together with D7 of PCON, further helps lower EMI (D7 (PCON) = 0, D1
(SMR) = 1). The default setting is 0. Maximum frequency is 4MHz with
D1 = 1 (see Figure 14).
Clock
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OSC
D1 (SMR)
÷2
D0 (SMR)
÷16
External Clock
Figure 14. External Clock Circuit
Oscillator Control
®
In some cases, the Z8 CPU offers software control of the oscillator to
select low EMI drive or standard drive. The selection is done by program-
ming bit D7 of the Port Configuration (PCON) register (see Figure 15).
The PCON register is located in Expanded Register File Bank F, Register
00h.
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A 1 in bit D7 configures the oscillator with standard drive, while a 0 con-
figures the oscillator with Low EMI drive. This only affects the drive
capability of the oscillator and does not affect the relationship of the
XTAL clock frequency to the internal system clock (SCLK).
PCON (Fh) 00h
D7 D6 D5 D4 D3 D2 D1 D0
Low EMI Oscillator
0 Low EMI
1 Standard
Figure 15. Port Configuration Register (Write-Only)
Oscillator Operation
®
The Z8 CPU uses a Pierce oscillator with an internal feedback (see
Figure 16). The advantages of this circuit are low cost, large output signal,
low-power level in the crystal, stability with respect to V and tempera-
CC
ture, and low impedances (not disturbed by stray affects).
One drawback is the requirement for high gain in the amplifier to com-
pensate for feedback path losses. The oscillator amplifies its own noise at
start-up until it settles at the frequency that satisfies the gain/phase
requirements A x B = 1, where A = V /VI is the gain of the amplifier and
0
B = VI/V is the gain of the feedback element. The total phase shift
0
around the loop is forced to zero (360 degrees). Because VIN must be in
phase with itself, the amplifier/inverter provides 180 degree phase shift
and the feedback element is forced to provide the other 180 degrees of
phase shift.
R1 is a resistive component placed from output to input of the amplifier.
The purpose of this feedback is to bias the amplifier in its linear region
and to provide the start-up transition.
Clock
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Capacitor C combined with the amplifier output resistance provides a
2
small phase shift. It will also provide some attenuation of overtones.
Capacitor C combined with the crystal resistance provides additional
1
phase shift.
C and C can affect the start-up time if they increase dramatically in size.
1
2
As C and C increase, the start-up time increases until the oscillator
1
2
reaches a point where it does not start up any more.
For fast and reliable oscillator start-up over the manufacturing process
range, ZiLOG recommends that the load capacitors be sized as low as
possible without resulting in overtone operation.
Z8 CPU
VSS
A
RI
V1
V0
XTAL1
XTAL2
C2
C1
Figure 16. Pierce Oscillator with Internal Feedback Circuit
Layout
®
Traces connecting crystal, caps, and the Z8 CPU oscillator pins should
be as short and wide as possible. This reduces parasitic inductance and
resistance. The components (caps, crystal, resistors) should be placed as
®
close as possible to the oscillator pins of the Z8 CPU .
The traces from the oscillator pins of the IC and the ground side of the
lead caps should be guarded from all other traces (clock, V , address/
CC
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data lines, system ground) to reduce cross talk and noise injection. This is
usually accomplished by keeping other traces and system ground trace
®
planes away from the oscillator circuit and by placing a Z8 CPU device
V
ground ring around the traces/components. The ground side of the
SS
®
oscillator lead caps should be connected to a single trace to the Z8
CPU’s V (GND) pin. It should not be shared with any other system
SS
®
ground trace or components except at the Z8 CPU’s V pin. This is to
SS
prevent differential system ground noise injection into the oscillator (see
Figure 17).
Indications of an Unreliable Design
Start-up time and output level are two major indicators that are used in
working designs to determine their reliability over full lot and tempera-
ture variations. These two indicators are described below.
Start-Up Time. If start-up time is excessive, or varies widely from unit to
unit, there is probably a gain problem. C1/C2 must be reduced; the ampli-
fier gain is not adequate at frequency, or crystal resistance is too large.
Output Level. The signal at the amplifier output should swing from
ground to V . This indicates there is adequate gain in the amplifier. As
CC
the oscillator starts up, the signal amplitude grows until clipping occurs,
at which point the loop gain is effectively reduced to unity and constant
oscillation is achieved. A signal of less than 2.5 volts peak-to-peak is an
indication that low gain may be a problem. Either C or C should be
1
2
made smaller or a low-resistance crystal should be used.
Circuit Board Design Rules
The following circuit board design rules are suggested:
•
To prevent induced noise the crystal and load capacitors should be
®
physically located as close to the Z8 CPU as possible.
Clock
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39
•
Signal lines should not run parallel to the clock oscillator inputs. In
particular, the crystal input circuitry and the internal system clock
output should be separated as much as possible.
•
•
V
power lines should be separated from the clock oscillator input
CC
circuitry.
Resistivity between XTAL1 or XTAL2 and the other pins should be
greater than 10MΩ.
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Signal Line
Layout Should
Avoid High
Lighted Areas
XTAL1
20 mm
max
C1
Z8 CPU
XTAL2
C2
V
SS
1
Clock Generator Circuit
2
3
Signals A B
(Parallel Traces
Must Be Avoided)
Z8 CPU
V
SS
Signal C
2
Board Design Example
(Top View)
Z8 CPU
3
(Connection to System Group
Must Be Avoided)
Figure 17. Circuit Board Design Rules
Crystals and Resonators
Crystals and ceramic resonators, shown in Figure 18 should have the
characteristics listed in Table 11 to ensure proper oscillator operation.
Clock
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Table 11. Crystal/Resonator Characteristics
Crystal Cut:
Mode:
AT (crystal only)
Parallel, Fundamental mode
Crystal Capacitance: <7pF
Load Capacitance:
Resistance:
10pF < CL < 220 pF, 15 typical
100Ω max
Depending on operation frequency, the oscillator may require the addition
of capacitors C1 and C2 (shown in Figure 18). The capacitance values are
dependent on the manufacturer’s crystal specifications.
V
SS
Z8 CPU
XTAL2
XTAL1
R
R
F
D
C2
C1
Figure 18. Crystal/Ceramic Resonator Oscillator
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XTAL1
C1
Z8 CPU
XTAL2
L
V
SS
C2
Figure 19. LC Clock
In most cases, the R is 0Ω and R is infinite. It is determined and speci-
D
F
fied by the crystal/ceramic resonator manufacturer. The R can be
D
increased to decrease the amount of drive from the oscillator output to the
crystal. It can also be used as an adjustment to avoid clipping of the oscil-
lator signal to reduce noise. The R can be used to improve the start-up of
F
®
the crystal/ceramic resonator. The Z8 oscillator already has an internal
shunt resistor in parallel to the crystal/ceramic resonator.
XTAL1
Z8 CPU
V
SS
XTAL2
Figure 20. External Clock
Clock
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In Figures 18 through 20, ZiLOG recommends that the user connect the
®
load capacitor ground trace directly to the V (GND) pin of the Z8
SS
®
CPU to ensure that no system noise is injected into the Z8 clock. This
trace should not be shared with any other components except at the V
SS
®
pin of the Z8 CPU.
®
In some cases, the Z8 CPU’s XTAL1 pin also functions as one of the
EPROM high-voltage mode programming pins or as a special factory test
pin. In this case, applying 2 V above V on the XTAL1 pin will cause
CC
the device to enter one of these modes. Because this pin accepts high volt-
ages to enter these respective modes, the standard input protection diode
to V is not on XTAL1. ZiLOG recommends that in applications where
CC
®
the Z8 CPU is exposed to much system noise, a diode from XTAL1 to
V
be used to prevent accidental enabling of these modes. This diode
CC
will not affect the crystal/ceramic resonator operation.
Please note that a parallel resonant crystal or resonator data sheet will
specify a load capacitor value that is the series combination of C and C ,
1
2
including all parasitics (PCB and holder).
LC Oscillator
®
The Z8 CPU oscillator can use a LC network to generate a XTAL clock
(see Figure 19).
The frequency stays stable over V and temperature. The oscillation fre-
CC
quency is determined by the equation.
1
Frequency =
1/2
2 π (LC )
T
where L is the total inductance including parasitics and C is the total
T
series capacitance including the parasitics.
Simple series capacitance is calculated using the following equation:
UM001602-0904
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1
1
1
=
+
C
C
C
2
T
1
If C
1
= C
= 2
= C
1
2
C
C
T
1
= 2CT
1
Sample calculation of capacitance C and C for 5.83MHz frequency and
1
2
inductance value of 27 µH.
1
6
5.83 (10 ) =
–6
2π [2.7 (10 ) C ] 1/2
T
C = 27.6 pF
T
Thus C = 55.2 pF and C = 55.2 pF.
1
2
RC Oscillator
®
In some cases, the Z8 CPU features an RC oscillator option. Please refer
to the specific product specification for availability. The RC oscillator
requires a resistor across XTAL1 and XTAL2. An additional load capaci-
tor is required from the XTAL1 input to V pin (see Figure 21).
SS
Clock
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XTAL1
R
Z8 CPU
XTAL2
V
SS
C1
Figure 21. RC Clock
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Clock
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Reset
®
This section describes the Z8 CPU reset conditions, reset timing, and
register initialization procedures. Reset is generated by Power-On Reset
(POR), Reset Pin, Watch–Dog Timer (WDT), and Stop-Mode Recovery.
®
A system reset overrides all other operating conditions and puts the Z8
CPU into a known state. To initialize the chip’s internal logic, the RESET
input must be held Low for at least 21 SCP or 5 XTAL clock cycles. The
control register and ports are reset to their default conditions after a POR,
a reset from the RESET pin, or Watch–Dog Timer time-out while in RUN
mode and HALT mode. The control registers and ports are not reset to
their default conditions after Stop- Mode Recovery and WDT time-out
while in STOP mode.
While RESET pin is Low, AS is output at the internal clock rate, DS is
forced Low, and R/W remains High. The program counter is loaded with
000Ch. I/O ports and control registers are configured to their default reset
state.
®
Resetting the Z8 CPU does not affect the contents of the general-pur-
pose registers.
Reset Pin, Internal POR Operation
®
In some cases, the Z8 CPU hardware RESET pin initializes the control
and peripheral registers, as shown in Tables 12 through 15. Specific reset
values are shown by 1 or 0, while bits whose states are unknown are indi-
cated by the letter U. Tables 12 through 15 show the reset conditions for
the Z8 CPU.
Note: The register file reset state is device dependent. Please refer to the selected
device product specifications for register availability and reset state.
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Table 12. Sample Control and Peripheral Register Reset Values (ERF Bank 0)
Bits
Register
(Hex)
Register Name
Serial I/O
7
U
0
6
U
0
5
U
0
4
U
0
3
U
0
2
U
0
1
U
0
0 Comments
F0
U
F1
Timer Mode
Counter/Timer1
T1 Prescaler
0 Counter/Timers stopped.
U
F2
U
U
U
U
U
U
U
U
U
U
U
U
U
0
F3
0 Single-pass count mode,
external clock source.
F4
F5
F6
F7
Counter/Timer0
T0 Prescaler
Port 2 Mode
Port 3 Mode
U
U
1
U
U
1
U
U
1
U
U
1
U
U
1
U
U
1
U
U
1
U
0 Single-pass count mode.
1 All inputs.
0
0
0
0
0
0
0
0 Port 2 open-drain, P33–
P30 Input, P37–P34
Output.
F8
Port 0–1 Mode
0
1
0
0
1
1
0
1 Internal Stack, Normal
Memory Timing.
F9
FA
FB
FC
FD
FE
Interrupt Priority
Interrupt Request
Interrupt Mask
Flags
U
0
U
0
U
0
U
0
U
0
U
0
U
0
U
0 All Interrupts Cleared.
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U Interrupts Disabled.
U
0
U
0
Register Pointer
Stack Pointer
(High)
U
U
U
U
U
U
U
U
FF
Stack Pointer
(Low)
U
U
U
U
U
U
U
U
Reset
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Program execution starts 5 to 10 clock cycles after internal RESET has
returned High. The initial instruction fetch is from location 000Ch.
Figure 22 illustrates reset timing.
First Machine Cycle
T1
Clock
SCLK
Hold Low For 4 SCLK
Periods (Minimum)
RESET
AS
DS
R/W
First Instruction Fetch
Figure 22. Reset Timing
After a reset, the first routine executed should be one that initializes the
control registers to the required system configuration.
The RESET pin is the input of a Schmitt-triggered circuit. Resetting the
®
Z8 CPU will initialize port and control registers to their default states.
To form the internal reset line, the output of the trigger is synchronized
with the internal clock. The clock must therefore be running for RESET
to function. It requires 4 internal system clocks after reset is detected for
®
the Z8 CPU to reset the internal circuitry. An internal pull-up, combined
with an external capacitor of 1 uf, provides enough time to properly reset
®
®
the Z8 CPU (see Figure 23). In some cases, the Z8 CPU has an internal
®
POR timer circuit that holds the Z8 CPU in reset mode for a duration
UM001602-0904
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(T
) before releasing the device out of reset. On these Z8 devices, the
POR
internally generated reset drives the reset pin low for the POR time. Any
devices driving the reset line must be open-drained in order to avoid dam-
age from possible conflict during reset conditions. This reset time allows
the on-board clock oscillator to stabilize.
®
To avoid asynchronous and noisy reset problems, the Z8 CPU is
equipped with a reset filter of four external clocks (4TpC). If the external
reset signal is less than 4TpC in duration, no reset occurs. On the fifth
clock after the reset is detected, an internal RST signal is latched and held
for an internal register count of 18 external clocks, or for the duration of
the external reset, whichever is longer. During the reset cycle, DS is held
active low while AS cycles at a rate of the internal system clock. Program
execution begins at location 000Ch, 5-10 TpC cycles after RESET is
released. For the internal Power-On Reset, the reset output time is speci-
fied as T
ues.
. Please refer to specific product specifications for actual val-
POR
+5V
100 KΩ
to
RESET
200 KΩ
1K
1 µF
10 V
Figure 23. Example of External Power-On Reset Circuit
Reset
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Table 13. Expanded Register File Bank 0 Reset Values at RESET
Bits
Register
(Hex)
Register Name
7
6
5
4
3
2
1
0 Comments
00
01
02
03
Port 0
U
U
U
U
U
U
1
U
U
U
U Input mode, output set to
push–pull.
Port 1
Port 2
Port 3
U
U
1
U
U
1
U
U
1
U
U
U
U
U
U
U
U
U
U Input mode, output set to
push–pull.
U Input mode, output set to
open drain.
U Standard digital input and
output
Z86L7X Family Device
Port P34-P37 = 0
(Except Z86L70/71/75)
All other Z8 = 1.
04–EF
General-Purpose
Registers 04h–
EFh
U
U
U
U
U
U
U
U Undefined.
Table 14. Sample Expanded Register File Bank C Reset Values
Bits
Register
(Hex)
Register Name
7
6
5
4
3
2
1
0 Comments
00
01
02
SPI Compare
(SCOMP)
0
0
0
0
0
0
0
0
Receive Buffer
(RxBUF)
U
U
U
U
U
U
U
U
U
0
U
0
U
0
U
0
SPI Control
(SCON)
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Table 15. Sample Expanded Register File Bank F Reset Values
Bits
Register
(Hex)
Register Name
7
6
5
4
3
2
1
0 Comments
00
PortConfiguration
(PCON)
1
1
1
1
1
1
1
0 Comparator outputs
disabled on Port 3.
Port 0 and 1 output is
push–pull.
Port 0, 1, 2, 3, and
oscillator with standard
output drive.
0B
Stop-Mode
Recovery (SMR)
0
0
1
0
0
0
0
0 Clock divide by 16 off.
XTAL divide by 2.
POR and/OR External
Reset.
Stop delay on.
Stop recovery level is low,
STOP flag is POR.
0F
Watch–Dog Timer
Mode (WDTMR)
U
U
U
0
1
1
0
1 512 TPC for WDT time
out, WDT runs during
STOP.
Reset
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RESET
4 Clock
Filter
Clear
CLK
18 Clock RESET
Generator
RESET
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CLK Source
Select (WDTMR)
XTAL
256 TpC
POR
256
TpC
512
TpC
1024
TpC
4096
TpC
M
U
X
RC
OSC.
WDT/POR Counter Chain
CK CLR
2.6V Operating
Voltage Det.
VDD
+
-
2.6V REF
WDT
.
From Stop Mode
Recovery Source
Stop Delay
Select (SMR)
Figure 24. Example of Z8 Reset with RESET Pin, WDT, SMR, and POR
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CLEAR 18 Clock RESET RESET
CLK Generator
4 Clock
Filter
Internal
RESET
WDT Select
(WDTMR)
WDT TAP SELECT
CLK Source
Select (WDTMR)
XTAL
5ms POR 5ms 15ms 25ms
CLK
100ms
M
U
WDT/POR Counter Chain
Internal
X
CLR
RC OSC.
2V Operating
Voltage Det.
V
DD
+
-
V
LV
WDT
.
From Stop Mode
Recovery Source
Stop Delay
Select (SMR)
Figure 25. Example of Z8 Reset with WDT, SMR, and POR
Reset
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Watch–Dog Timer
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets
®
the Z8 CPU if it reaches its terminal count. When operating in the RUN
or HALT modes, a WDT reset is functionally equivalent to a hardware
POR reset. The WDT is initially enabled by executing the WDT instruc-
tion and refreshed on subsequent executions of the WDT instruction. The
WDT cannot be disabled after it has been initially enabled. Permanently
enabled WDTs are always enabled and the WDT instruction is used to
refresh it. The WDT circuit is driven by an on-board RC oscillator or
external oscillator from the XTAL1 pin. The POR clock source is selected
with bit 4 of the Watch–Dog Timer Mode register (WDTMR). In some
cases, a Z8 that offers the WDT but does not have a WDTMR register, has
a fixed WDT time-out and uses the on board RC oscillator as the only
clock source. Please refer to specific product specifications for selectabil-
ity of time-out, WDT during HALT and STOP modes, source of WDT
clock, and availability of the permanently-on WDT option.
Execution of the WDT instruction affects the Z (zero), S (sign), and V
(overflow) flags.
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WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
INT
RC
OSC
WDT
TAP*
SYS
CLK
00
01**
10
5
10
20
80
128
256
512
2048
11
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC
Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Must be 0 for Z86C03
** Default setting after RESET
Figure 26. Example of Z8 Watch–Dog Timer Mode Register (Write-
Only)
The WDTMR register is accessible only during the first 60 processor
cycles from the execution of the first instruction after Power-On Reset,
Watch–Dog Reset or a Stop-Mode Recovery. After this point, the register
cannot be modified by any means, intentional or otherwise. The WDTMR
is a write-only register.
WDTMR is located in Expanded Register File Bank F, register 0Fh. This
register’s control bits are described on the next two pages.
Watch–Dog Timer
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57
WDT Time Select. Bits D1 and D0 control a tap circuit that determines
the time-out period. Table 16 shows the different values that can be
obtained. The default value of D1 and D0 are 0 and 1, respectively.
Table 16. Time-Out Period of the WDT
Time-Out of
Typical Time-Out of
D1
0
D0 Internal RC OSC
System Clock
256 TpC
0
1
0
1
5 ms min
0
15 ms min
25 ms min
100 ms min
512 TpC
1
1024 TpC
4096 TpC
1
*Notes: The values given are for VCC = 5.0V. See the device product specification
for exact WDTMR time out select options available.
1. TpC = XTAL clock cycle
2. The default on reset is, D0 = 1 and D1 = 0.
WDT During HALT. The D2 bit determines whether or not the WDT is
active during HALT mode. A 1 indicates active during HALT. The default
is 1. A WDT time out during HALT mode will reset control register ports
to their default reset conditions.
WDT During STOP. The D3 bit determines whether or not the WDT is
active during STOP mode. Because XTAL clock is stopped during STOP
mode, unless as specified below, the on-board RC must be selected as the
clock source to the POR counter. A 1 indicates active during STOP. The
default is 1. If bits D3 and D4 are both set to 1, the WDT only, is driven
by the external clock during STOP mode. This feature makes it possible
to wake up from STOP mode from an internal source. Please refer to spe-
cific product specifications for conditions of control and port registers
®
when the Z8 CPU comes out of STOP mode. A WDT time out during
STOP mode will not reset all control registers. The reset conditions of the
ports from STOP mode due to WDT time out is the same as if recovered
using any of the other STOP mode sources.
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Clock Source for WDT. The D4 bit determines which oscillator source
is used to clock the internal POR and WDT counter chain. If the bit is a 1,
the internal RC oscillator is bypassed and the POR and WDT clock source
is driven from the external pin, XTAL1. The default configuration of this
bit is 0, which selects the internal RC oscillator.
Bits 5, 6, and 7. These bits are reserved.
V
Voltage Comparator. An on-board voltage comparator checks that
CC
CC
V
is at the required level to insure correct operation of the device. Reset
is globally driven if V is below the specified voltage. This feature is
CC
available in select ROM Z8 devices. See the device product specification
for feature availability and operating range.
Power-On-Reset
A timer circuit clocked by a dedicated on-board RC oscillator is used for
the Power-On Reset (POR) timer function, T . This POR time allows
POR
V
and the oscillator circuit to stabilize before instruction execution
CC
begins.
The POR timer circuit is a one-shot timer triggered by one of three condi-
tions:
•
•
•
Power fail to Power OK status (cold start)
Stop-Mode Recovery (if bit 5 of SMR = 1)
WDT time-out
The POR time is specified as T
. On Z8 devices that feature a Stop-
POR
Mode Recovery register (SMR), bit 5 selects whether the POR timer is
used after Stop-Mode Recovery or by-passed. If bit D5 = 1 then the POR
timer is used. If bit 5 = 0 then the POR timer is by-passed. In this case, the
Stop-Mode Recovery source must be held in the recovery state for 5 T C
or 5 crystal clocks to pass the reset signal internally. This option is used
P
Watch–Dog Timer
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when the clock is provided with an RC/LC clock. See the device product
specification for timing details.
®
POR (cold start) will always reset the Z8 CPU control and port registers
to their default condition. If a Z8 has a SMR register, the warm start bit
will be reset to a 0 to indicate POR.
XTAL OSC
INT OSC
POR
(Cold Start)
VBO
WDT
Chip
Reset
Delay Line
TPOR ms
18 CLK
Reset Filter
P27
(Stop Mode)
Figure 27. Example of Z8 with Simple SMR and POR
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Watch–Dog Timer
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I/O Ports
®
The Z8 CPU features up to 32 lines dedicated to input and output. These
lines are grouped into four 8-bit ports known as Port 0, Port 1, Port 2, and
Port 3. Port 0 is nibble programmable as input, output, or address. Port 1
is byte configurable as input, output, or address/data. Port 2 is bit pro-
grammable as either inputs or outputs, with or without handshake and
SPI. Port 3 can be programmed to provide timing, serial and parallel
input/output, or comparator input/output.
All ports have push–pull CMOS outputs. In addition, the push–pull out-
puts of Port 2 can be turned off for open-drain operation.
Mode Registers
Each port has an associated Mode Register that determines the port’s
functions and allows dynamic change in port functions during program
execution. Port and Mode Registers are mapped into the Standard Regis-
ter File as shown in Figure 28.
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HEX
F8h
Identifier
P01M
Register
Port 0–1 Mode
Port 3 Mode
Port 2 Mode
F7h
F6h
P3M
P2M
Port 3
Port 2
03h
02h
P3
P2
Port 1
Port 0
01h
00h
P1
P0
Figure 28. I/O Ports and Mode Registers
Because of their close association, Port and Mode registers are treated
like any other general-purpose register. There are no special instructions
for port manipulation. Any instruction which addresses a register can
address the ports. Data can be directly accessed in the Port Register, with
no extra moves.
Input and Output Registers
Each bit of Ports 0, 1, and 2, have an input register, an output register,
associated buffer, and control logic. Because there are separate input and
output registers associated with each port, writing to bits defined as inputs
stores the data in the output register. This data cannot be read as long as
the bits are defined as inputs. However, if the bits are reconfigured as out-
puts, the data stored in the output register is reflected on the output pins
I/O Ports
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and can then be read. This mechanism allows the user to initialize the out-
puts prior to driving their loads (see Figure 29).
®
Because port inputs are asynchronous to the Z8 CPU internal clock, a
READ operation could occur during an input transition. In this case, the
logic level might be uncertain (somewhere between a logic 1 and 0). To
®
eliminate this meta-stable condition, the Z8 CPU latches the input data
two clock periods prior to the execution of the current instruction. The
input register uses these two clock periods to stabilize to a legitimate logic
level before the instruction reads the data.
®
Note: The following sections describe the generic function of the Z8 CPU
ports. Any additional features of the ports such as SPI, C/T, and Stop-
Mode Recovery are covered in their own section.
Port 0
This section deals with only the I/O operation of Port 0. The port's exter-
nal memory interface operation is covered later in this manual. Figure 29
shows a block diagram of Port 0. This diagram also applies to Ports 1 and
2.
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Port I/O
Lines
8
8
8
Input
Buffer
Input
Register
Read
Port
E
Internal
Timing
8
Handshake
Selected
DAV/RDY
RDY/DAV
Handshake
Logic
Write
Port
Output
Buffer
Output
Register
8
8
8
Output
Enable
Internal
Bus
Figure 29. Ports 0, 1, 2 Generic Block Diagram
I/O Ports
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General I/O Mode
Port 0 can be an 8-bit, bidirectional, CMOS or TTL compatible I/O port.
These eight I/O lines can be configured under software control as a nibble
I/O port (P03–P00 input/output and P07–P04 input/output), or as an
address port for interfacing external memory. The input buffers can be
Schmitt-triggered, level shifted, or a single-trip point buffer and can be
nibble programmed. Either nibble output can be globally programmed as
push–pull or open-drain. Low EMI output buffers in some cases can be
globally programmed by the software as an OTP program option or as a
®
ROM mask option. In such cases, the Z8 MCU features autolatches that
are hardwired to the inputs. Please refer to the specific Z8 MCU product
specification for the exact input/output buffer features that are available
(see Figures 30 and 31).
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4
4
Port 1
(I/O or AD15–AD08)
Z8
Handshake Controls
DAV0 and RDY0
(P32 and P35)
OPEN-DRAIN
OEN
PIN
OUT
1.5
2.3V Hysteresis
IN
Autolatch
R ≈ 500 KΩ
Figure 30. Port 0 Configuration with Open-Drain Capability,
Autolatch, and Schmitt-Trigger
I/O Ports
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OEN
PIN
OUT
TTL Level Shifter
IN
Figure 31. Port 0 Configuration with TTL Level Shifter
Read/Write Operations
In the nibble I/0 Mode, Port 0 is accessed as general-purpose register P0
(00h) with ERF Bank set to 0. The port is written by specifying P0 as an
instruction's destination register. Writing to the port causes data to be
stored in the port's output register.
The port is read by specifying P0 as the source register of an instruction.
When an output nibble is read, data on the external pins is returned.
Under normal loading conditions this is equivalent to reading the output
register. However, for Port 0 outputs defined as open–drain, the data
returned is the value forced on the output by the external system. This
may not be the same as the data in the output register. Reading a nibble
defined as input also returns data on the external pins. However, input bits
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under handshake control return data latched into the input register via the
input strobe.
The Port 0–1 Mode resistor bits D1–D0 and D7–D6 are used to configure
Port 0 nibbles. The lower nibble (P00–P03) can be defined as inputs by
setting bits D1 to 0 and D0 to 1, or as outputs by setting both D1 and D0
to 0. Likewise, the upper nibble (P04–P07) can be defined as inputs by
setting bits D7 to 0 and D6 to 1, or as outputs by setting both D6 and D7
to 0 (see Figure 32).
Handshake Operation
When used as an I/0 port, Port 0 can be placed under handshake control
by programming the Port 3 Mode register bit D2 to 1. In this configura-
tion, handshake control lines are DAV0 (P32) and RDY0 (P35) when Port
0 is an input port, or RDY0 (P32) and DAV0 (P35) when Port 0 is an out-
put port (see Figure 33).
Handshake direction is determined by the configuration (input or output)
assigned to the Port 0 upper nibble, P04–P07. The lower nibble must have
the same I/0 configuration as the upper nibble to be under handshake con-
trol. Figure 30 illustrates the Port 0 upper and lower nibbles and the asso-
ciated handshake lines of Port 3.
Port 1
This section deals only with the I/0 operation. The port's external memory
interface operation is discussed later in this manual. Figure 29 shows a
block diagram of Port 1.
General I/O Mode
Port 1 can be an 8-bit, bidirectional, CMOS or TTL compatible port with
multiplexed address (A7–A0) and data (D7–D0) ports. These eight I/O
lines can be byte programmed as inputs or outputs or can be configured
under software control as an Address/Data port for interfacing to external
I/O Ports
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memory. The input buffers can be Schmitt-triggered, level- shifted, or a
single-point buffer. In some cases, the output buffers can be globally pro-
grammed as either push–pull or open-drain. Low-EMI output buffers can
be globally programmed by software, as an OTP program option, or as a
®
ROM Mask Option. In some cases, the Z8 MCU can have autolatches
hardwired to the inputs. Please refer to specific product specifications for
exact input/output buffer-type features available (Figures 32 and 33).
Register F8h (P01M)
Port 0–1 Mode Register (P01M)
(Write-Only)
D7 D6
D1 D0
P04–P07 Mode
00 = Output
01 = Input
P00–P03 Mode
00 = Output
01 = Input
1X = A12–A15
1X = A8–A11
Figure 32. Port 0 I/O Operation
Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D2
0 P32 = Input
P35 = Output
1 P32 = DAV0/RDY0
P35 = RDY0/DAV0
Figure 33. Port 0 Handshake Operation
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Port 1
(I/O or AD7–AD0)
8
Z8
Handshake Controls
DAV1 and RDY1
(P33 and P34)
OPEN-DRAIN
OEN
PIN
OUT
1.5
2.3V Hysteresis
IN
Autolatch
R ≈ 500 KΩ
Figure 34. Port 1 Configuration with Open-Drain Capability,
Autolatch, and Schmitt-Trigger
I/O Ports
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Port 1
(I/O or AD7–AD0)
8
Z8
Handshake Controls
DAV1 and RDY1
(P33 and P34)
OEN
PIN
OUT
IN
TTL Level Shifter
Figure 35. Port 1 Configuration with TTL Level Shifter
Read/Write Operations
In byte input or byte output mode, the port is accessed as General-Purpose
Register P1 (01h). The port is written by specifying P1 as an instruction's
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destination register. Writing to the port causes data to be stored in the
port's output register.
The port is read by specifying P1 as the source register of an instruction.
When an output is read, data on the external pins is returned. Under nor-
mal loading conditions, this is equivalent to reading the output register.
However, if Port 1 outputs are defined as open-drain, the data returned is
the value forced on the output by the external system. This may not be the
same as the data in the output register. When Port 1 is defined as an input,
reading also returns data on the external pins. However, inputs under
handshake control return data latched into the input register via the input
strobe.
Using the Port 0–1 Mode Register, Port 1 is configured as an output port
by setting bits D4 and D3 to 0, or as an input port by setting D4 to 0 and
D3 to 1 (see Figure 36).
R248 P01M
Port 0–1 Mode Register
(F8, Write-Only)
D4 D3
P10–P13 Mode
00 = Byte Output
01 = Byte Output
10 = AD0-AD7
11 = High Impedance AD0–AD7,
AS, DS, R/W,
A8–A11, A12–A15
Figure 36. Port 1 I/O Operation
I/O Ports
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Handshake Operations
When used as an I/O port, Port 1 can be placed under handshake control
by programming the Port 3 Mode register bits D4 and D3 both to 1. In this
configuration, handshake control lines are DAV1 (P33) and RDY1 (P34)
when Port 1 is an input port, or RDY1 (P33) and DAV1 (P34) when Port 1
is an output port. See Figures 37 and 39.
Handshake direction is determined by the configuration (input and output)
assigned to Port 1. For example, if Port 1 is an output port then handshake
is defined as output.
R247 P3M
Port 3 Mode Register
(F7, Write-Only)
D4 D3
00 P33 = Input
01 P33 = Input
10 P33 = Input
P34 = Output
P34 = DM
P34 = DM
11 P33 = DAV1/RDY1 P34 = RDY1/DAV1
Figure 37. Handshake Operation
Port 2
Port 2 is a general-purpose port. Figure 29 shows a block diagram of Port
2. Each of its lines can be independently programmed as input or output
via the Port 2 Mode Register (F6h) as seen in Figure 38. A bit set to a 1 in
P2M configures the corresponding bit in Port 2 as an input, while a bit set
to 0 configures an output line.
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Register F6h
Port 2 Mode Register (P2M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port 2 Mode
0 = Output
1 = Input
Figure 38. Port 2 I/O Mode Configuration
General Port I/O
Port 2 can be an 8-bit, bidirectional, CMOS- or TTL- compatible I/O port.
These eight I/O lines can be configured under software control to be an
input or output, independently. Input buffers can be Schmitt-triggered,
level-shifted, or a single trip point buffer and may contain autolatches.
Bits programmed as outputs may be globally programmed as either push–
pull or open-drain. Low-EMI output buffers can be globally programmed
by the software, an OTP program option, or as a ROM mask option. In
addition, when the SPI is featured and enabled, P20 functions as data-in
(DI), and P27 functions as data-out (DO). Please refer to specific product
specifications for exact input/output buffer type features available. See
Figures 39 through 41.
I/O Ports
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OPEN-DRAIN
P21–P26 OE
P21–P26
PIN
P21–P26 OUT
P21–P26 IN
1.5
2.3V Hysteresis @ V = 5.0V
CC
Autolatch
R ≈ 500 KΩ
Figure 39. Port 2 Configuration with Open-Drain Capability,
Autolatch, and Schmitt-Trigger
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Open-Drain
OEN
PIN
OUT
IN
TTL Level Shifter
Figure 40. Port 2 Configuration with TTL Level Shifter
I/O Ports
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OPEN-DRAIN
P20 OE
SPI EN
P20
PIN
P20 OUT
P20 IN
or
SPI DI
Autolatch
R ≈ 500 KΩ
OPEN-DRAIN
Standard
SPI
P27 OUT
SPI DO
P27
PIN
Standard
SPI
P27 OE
SPI Active
SCON
0 SOI D0 Enable
D2
1 P27 OUT
*SPI must be enabled with D0
P27 IN
Autolatch
R ≈ 500 KΩ
Figure 41. Port 2 Configuration with Open-Drain Capability,
Autolatch, Schmitt-Trigger and SPI
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Read/Write Operations
Port 2 is accessed as General-Purpose Register P2 (02h). Port 2 is written
by specifying P2 as an instruction’s destination register. Writing to Port 2
causes data to be stored in the output register of Port 2, and reflected
externally on any bit configured as an output.
Port 2 is read by specifying P2 as the source register of an instruction.
When an output bit is read, data on the external
pin is returned. Under normal loading conditions, this is equivalent to
reading the output register. However, if a bit of Port 2 is defined as an
open-drain output, the data returned is the value forced on the output pin
by the external system. This may not be the same as the data in the output
register. Reading input bits of Port 2 also returns data on the external pins.
However, inputs under handshake control return data latched into the
input register via the input strobe.
Handshake Operation
Port 2 can be placed under handshake control by programming bit 6 in the
Port 3 Mode Register (see Figure 42). In this configuration, Port 3 lines
P31 and P36 are used as the handshake control lines DAV2 and RDY2 for
input handshake, or RDY2 and DAV2 for output handshake.
Handshake direction is determined by the configuration (input or output)
assigned to bit 7 of Port 2. Only those bits with the same configuration as
P27 will be under handshake control. Figure 43 illustrates the bit lines of
Port 2 and the associated handshake lines of Port 3.
I/O Ports
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Register F7h
Port 3 Mode Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port 2 Handshaking
0 P31 = Input (T )
P36 = Output (T
)
IN
OUT
1 P31 = DAV2/RDY2 P36 = RDY2/DAV2
Figure 42. Port 2 Handshake Configuration
P20
Port 2 (I/O)
P27
Handshake Controls
DAV2 and RDY2
(P31 and P36)
Figure 43. Port 2 Handshaking
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Port 3
General Port I/O
Port 3 differs structurally from Port 0, 1, and 2. Port 3 lines are fixed as
four inputs (P33–P30) and four outputs (P37–P34) Port 3 does not have
an input and output register for each bit. Instead, all of the input lines have
one input register, and all of the output lines have an output register. Port
3 can be a CMOS- or TTL- compatible I/O port. Under software control,
the lines can be configured as special control lines for handshake, com-
parator inputs, SPI control, external memory status, or I/O lines for the
on-board serial and timer facilities. Figure 44 is a generic block diagram
of Port 3.
The inputs can be Schmitt-triggered, level-shifted, or single-trip point
®
buffered. In some cases, the Z8 MCU may have autolatches hardwired
on certain Port 3 inputs and Low-EMI capabilities on the outputs. Please
refer to specific product specifications for exact input/output buffer type
features. Please refer to the section on counter/timers, Stop-Mode Recov-
ery, serial I/O, comparators, and interrupts for more information on the
relationships of Port 3 to that feature.
I/O Ports
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Read
Port
Port
Input
Input
Input
Register
4
4
Buffer
4
Lines
P3 –P3
0
3
To Interrupt Timer,
Handshake Logic,
or Serial I/O
Read
Port
Output
Data
Return
Buffer
4
4
Write
Port
Port
Output
Register
Output
Output
Lines
4
4
4
Buffer
P3 –P3
4
7
From Timer,
Internal
Bus
Handshake Logic,
or Serial I/O
Figure 44. Port 3 Block Diagram
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I/O Ports
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P30
P31
P32
P33
Port 3
(I/O or Control)
Z8
P34
P35
P36
P37
Autolatch
R
≈ 500 KΩ
P30 Data
Latch IRQ3
P30
R247 = P3M
1 = Analog
0 = Digital
D1
DIG.
AN.
P31 (AN1)
IRQ2, T , P31 Data Latch
IN
+
-
P32 (AN2)
P33 (REF)
IRQ0, P32 Data Latch
+
-
From Stop-Mode
Recovery Source
IRQ1, P33 Data Latch
Figure 45. Port 3 Configuration with Comparator, Autolatch,
and Schmitt-Trigger
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P34
PIN
P37 OUT
P32
+
-
REF (P33)
P37
PIN
P37 OUT
P32
+
-
REF (P33)
PCON
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
D0
Figure 46. Port 3 Configuration with Comparator
I/O Ports
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SK IN
SPI EN
SPI MSTR
P34
PIN
SPI EN
SK OUT
P34 OUT
MUX
P31
+
-
SS
REF
SPI EN
SPI MSTR
P35
PIN
P34 OUT
P31
+
-
REF
PCON
0 P34, P35 Standard Output
1 P34, P35 Comparator Output
D0
Figure 47. Port 3 Configuration with SPI and Comparator
Outputs
I/O Ports
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Port 3 Output Configuration
PIN
OUT
TTL Level Shifter
Port 3 Input Configuration
IN
PIN
Autolatch
R ≈ 500 KΩ
Port 3 Configuration with TTL Level Shifter and
Autolatch
Figure 48.
Read/Write Operations
Port 3 is accessed as a General-Purpose Register P3 (03h). Port 3 is writ-
ten by specifying P3 as an instruction’s destination register. However,
Port 3 outputs cannot be written to if they are used for special functions.
When writing to Port 3, data is stored in the output register.
Port 3 is read by specifying P3 as the source register of an instruction.
When reading from Port 3, the data returned is both the data on the input
pins and in the output register.
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Special Functions
Special functions for Port 3 are defined by programming the Port 3 Mode
Register. By writing 0s in bit 6 through bit 1, lines P37–P30 are config-
ured as input/output pairs (see Figure 49). Table 17 shows available func-
tions for Port 3. The special functions indicated in the figure are discussed
in detail in their corresponding sections in this manual.
Port 3 input lines P33–P30 always function as interrupt requests regard-
less of the configuration specified in the Port 3 Mode Register.
Register F7h
Port 3 Mode Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open-Drain
1 Port 2 Push–Pull
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
0 P32 = Input
P35 = Output
00 P33 = Input
01 P33 = Input
10 P33 = Input
P34 = Output
P34 = DM
P34 = DM
0 P31 = Input
P36 = Output
0 P30 = Input
1 P30 = Serial In
P37 = Output
P37 = Serial Out
0 Party ON
1 Party OFF
Figure 49. Port 3 Mode Register Configuration
I/O Ports
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Table 17. Port 3 Line Functions
Function
Line
Signal
Inputs
P30
P31
P32
P33
P34
P35
P36
P37
P32
P33
P31
P35
P34
P36
P31
P32
P33
P34
P35
P37
Input
Input
Input
Input
Outputs
Output
Output
Output
Output
Port 0 Handshake Input
Port 1 Handshake Input
Port 2 Handshake Input
Port 0 Handshake Output
Port 1 Handshake Output
Port 2 Handshake Output
Analog Comparator Input
DAV0/RDY0
DAV1/RDY1
DAV2/RDY2
RDY0/DAV0
RDY1/DAV1
RDY2/DAV2
AN1
AN2
REF
Analog Comparator Output
AN1-OUT
AN2-OUT
AN2-OUT
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Table 17. Port 3 Line Functions (Continued)
Function
Line
P30
P31
P32
P33
P30
P37
P35
P34
P31
P36
P34
Signal
IRQ3
IRQ2
IRQ0
IRQ1
DI
Interrupt Requests
Serial Input (UART)
Serial Output (UART)
SPI Slave Select
SPI Clock
DO
SS
SK
Counter/Timer
T
T
IN
OUT
External Memory Status
DM
Port Handshake
When Ports 0, 1, and 2 are configured for handshake operation, a pair of
lines from Port 3 are used for handshake controls. The handshake controls
are interlocked to properly time asynchronous data transfers between the
®
Z8 and a peripheral. One control line (DAV) functions as a strobe from
the sender to indicate to the receiver that data is available. The second
control line (RDY) acknowledges receipt of the sender’s data, and indi-
cates when the receiver is ready to accept another data transfer.
In input mode, data is latched into the Port’s input register by the first
DAV signal, and is protected from being overwritten if additional pulses
occur on the DAV line. This overwrite protection is maintained until the
port data is read. In output mode, data written to the port is not protected
®
and can be overwritten by the Z8 CPU during the handshake sequence.
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To avoid losing data, the software must not overwrite the port until the
corresponding interrupt request indicates that the external device has
latched the data.
The software can always read Port 3 output and input handshake lines, but
cannot write to the output handshake line.
The following is the recommended setup sequence when configuring a
Port for handshake operation for the first time after a reset:
•
•
•
Load P01M or P2M to configure the port for input/output
Load P3 to set the Output Handshake bit to a logic 1
Load P3M to select HANDSHAKE mode for the port
Once a data transfer begins, the configuration of the handshake lines
should not be changed until the handshake is completed.
Figures 50 and 51 show detailed operation for the handshake sequence.
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4
5
1
2
3
DAV
(Input To Z8)
RDY
(Output From Z8)
Data on Port
(Input To Z8)
Valid Data
State 1.
State 2.
Port 3 output is High, indicating that the I/O device is ready to accept data.
The I/O device puts data on the port and then activates the DAV input. This causes the data to be latched
.into the port input register and generates an interrupt request.
the Z8® CPU forces the Ready (RDY) output Low, signaling to the I/O device that the data has been latched.
State 3.
State 4.
State 5.
The I/O device returns the DAV line High in response to RDY going Low.
the Z8® CPU RR software must respond to the interrupt request and read the contents of the port in order for t
handshake sequence to be completed. The RDY line goes High if and only if the port has been read and
DAV is High. This returns the interface to its initial state.
Figure 50. Z8 Input Handshake
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4
5
1
2
3
RDY
(Input To Z8)
DAV
(Output From Z8)
Data on Port
(Output From Z8)
Valid Data
State 1.
State 2.
RDY input is High indicating that the I/O device is ready to accept data.
the Z8® CPU Writes to the port register to initiate a data transfer. Writing to the port outputs new data and
forces DAV Low if and only if RDY is High.
State 3.
The I/O device forces RDY Low after latching the data. RDY Low causes an interrupt request to be generate
the Z8® CPU can write new data responses to RDY going Low; however, the data is not output until State 5
State 4.
State 5.
The DAV output from the Z8® CPU is driven High in response to RDY going Low.
The DAV goes High, the I/O device is free to raise RDY High thus returning the interface to its initial state.
Figure 51. Z8 Output Handshake
In applications requiring a strobed signal instead of the interlocked hand-
®
shake, the Z8 CPU can satisfy this requirement as follows:
•
In the Strobed Input mode, data can be latched in the Port input regis-
ter using the DAV input. The data transfer rate must allow enough
time for the software to read the Port before strobing in the next char-
acter. The RDY output is ignored.
•
In the Strobed Output Mode, the RDY input should be tied to the
DAV output.
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Figures 52 and 53 illustrate the strobed handshake connections.
P20–P27
I/O
Device
Z8
DAV
RDY
P36
P31
Figure 52. Output Strobed Handshake on Port 2
P20–P27
I/O
Device
Z8
DAV
P31
Figure 53. Input Strobed Handshake on Port 2
I/O Port Reset Conditions
Full Reset
After a hardware reset, Watch–Dog Timer (WDT) reset, or a Power-On
Reset (POR), Port Mode Registers P01M, P2M, and P3M are set as
I/O Ports
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shown in Figures 54 through 56. Port 2 is configured for input operation
on all bits and is set for open-drain (see Figure 55). If push-pull outputs
are required for Port 2 outputs, remember to configure them using P3M.
Please note that a WDT time-out from Stop-Mode Recovery does not do a
full reset. Certain registers that are not reset after Stop-Mode Recovery
will not be reset.
For the condition of the Ports after Stop-Mode Recovery, please refer to
®
specific device product specifications. In some cases, an Z8 MCU fea-
tures the P01M, P2M, and P3M control register set back to the default
condition after reset while others do not.
All special I/O functions of Port 3 are inactive, with P33–P30 set as inputs
and P37–P34 set as outputs (see Figure 56).
®
Because the types and amounts of I/O vary greatly among the Z8 CPU
family devices, the user is advised to review the selected device's product
specifications for the register default state after reset.
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Register F8h
Port 0–1 Mode Register (P01M)
(Write-Only)
0
1
0
0
1
1
0
1
P00–P03 Mode
00 = Output
01 = Input
1X = A8–A11
Stack Selection
0 = External
1 = Internal
P10–P17 Mode
00 = Byte Output
01 = Byte Output
10 = AD0–AD7
11 = High Impedance AD0–AD7,
A8–A15, AS, DS, R/W
External Memory Timing
Normal = 0
Extended = 1
P04–P07 Mode
Output = 00
Input = 01
A12–A15 = 1X
Figure 54. Port 0/1 Reset
I/O Ports
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Register F6h
Port 2 Mode Register (P2M)
(Write-Only)
1
1
1
1
1
1
1
1
Port 2 Mode
0 = Output
1 = Input
Figure 55. Port 2 Reset
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Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
0
0
0
0
0
0
0
0
0 Port 2 Open-Drain
1 Port 2 Push–Pull
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
0 P32 = Input
P35 = Output
1 P32 = DAV0/RDY0 P35 = RDY0/DAV0
00 P33 = Input
01 P33 = Input
10 P33 = Input
P34 = Output
P34 = DM
P34 = DM
11 P33 = DAV1/RDY1 P34 = RDY1/DAV1
0 P31 = Input P36 = Output
1 P32 = DAV2/RDY2 P36 = RDY2/DAV2
0 P30 = Input
1 P30 = Serial In
P37 = Output
P37 = Serial Out
0 Parity OFF
1 Parity ON
Figure 56. Port 3 Mode Reset
Analog Comparators
Select Z8 devices include two independent on-chip analog comparators.
See the device product specification for feature availability and use. Port
3, Pins P31 and P32 each have a comparator front end. The comparator
reference voltage, pin P33, is common to both comparators. In analog
mode, the P31 and P32 are the positive inputs to the comparators and P33
is the reference voltage supplied to both comparators. In digital mode, pin
P33 can be used as a P33 register input or IRQ1 source. P34, P35, or P37
I/O Ports
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may output the comparator outputs by software-programming the PCON
Register bit D0 to 1.
Comparator Description
Two on-board comparators can process analog signals on P31 and P32
with reference to the voltage on P33. The analog function is enabled by
programming the Port 3 Mode Register (P3M bit 1). For interrupt func-
tions during analog mode, P31 and P32 can be programmable as rising,
falling, or both edge triggered interrupts (IRQ register bits 6 and bit 7).
P33 cannot generate an external interrupt while in this mode. P33 can only
generate interrupts in digital mode.
Port 3 inputs must be in digital mode if Port 3 is a Stop-Mode Recovery
source. The analog comparator is disabled in STOP mode.
P31 can be used as T in analog or digital modes, but it must be refer-
IN
enced to P33, when in analog mode.
Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D1
0 = Digital Mode P31, P32, P33
1 = Analog Mode P31, P32, P33
Figure 57. Port 3 Input Analog Selection
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ERF Bank F
Register 00h
Port Configuration Register (PCON)
(Write-Only)
D0
0 = P34, P35, or P37 Standard Outputs
1 = P34, P35, or P37 Comparator Outputs
Figure 58. Port 3 Comparator Output Selection
I/O Ports
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P30
P31
P32
P33
Port 3
(I/O or Control)
Z8
P34
P35
P36
P37
Autolatch
R ≈ 500 KΩ
P30 Data
Latch IRQ3
P30
R247 = P3M
1 = Analog
0 = Digital
D1
DIG.
AN.
P31 (AN1)
IRQ2, T , P31 Data Latch
IN
+
-
P32 (AN2)
P33 (REF)
IRQ0, P32 Data Latch
+
-
From Stop-Mode
Recovery Source
IRQ1, P33 Data Latch
Figure 59. Port Configuration of Comparator Inputs on P31,
P32, and P33
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P34
PIN
P34 OUT
P31
+
-
REF (P33)
P37
PIN
P37 OUT
P32
+
-
REF (P33)
PCON
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
D0
Figure 60. Port 3 Configuration
Comparator Programming
Example of enabling analog comparator mode.
LD P3M, #XXXX XX1Xb
X = any binary number
Example of enabling analog comparator output.
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LD RP, #%0Fh
;Sets register pointer to
;working register group 0
;and Expanded Register
;File Bank F.
LD R0, #XXXX XXX1b
;Enables comparator
;outputs using PCON
;Register programming.
Comparator Operation
After enabling the Analog Comparator mode, P33 becomes a common
reference input for both comparators. The P33 (Ref) is hard wired to the
reference inputs to both comparators and cannot be separated. P31 and
P32 are always connected to the positive inputs to the comparators. P31 is
the positive input to comparator AN1 while P32 is the positive input to
comparator AN2. The outputs to comparators AN1 and AN2 are AN1-out
and AN2-out, respectively.
The comparator output reflects the relationship between the positive input
to the reference input.
Example
If the voltage on AN1 is higher than the voltage on Ref then AN1-out will
be at a high state. If voltage on AN2 is lower than the voltage on Ref then
AN2-out will be at a Low state. In this example, when the Port 3 register
is read, Bits D1 = 1 and D2 = 0. If the comparator outputs are enabled to
come out on P34 and P37, then P34 = 1 and P37 = 0. Please note that the
previous data stored in P34 and P37 is not disturbed. Once the comparator
outputs are de-selected the stored values in the P34 and P37 register bits
will be reflected on these pins again.
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Interrupts
In the example from Section 5.8.3, P32 (AN2) will generate an interrupt
based on the result of the comparison being low and the Interrupt Request
Register (IRQ FAh) having bits D7 = 0 and D6 = 0. If IRQ D7 = 1 and D6
= 0 then both P31 and P32 would generate interrupts.
Comparator Definitions
V
ICR
The usable voltage range for both positive inputs and the reference input
is called the common mode voltage range (V ). The comparator is not
ICR
guaranteed to work if the inputs are outside of the V
range.
ICR
VOFFSET
The absolute value of the voltage between the positive input and the refer-
ence input required to make the comparator output voltage switch is the
input offset voltage (VOFFSET). If AN1 is 3.000V and Ref is 3.001V when
the comparator output switches states then the Voffset = 1mV.
I
IO
For CMOS voltage comparator inputs, the input offset current (I ) is the
IO
leakage current of the CMOS input gate.
Run Mode
P33 is not available as an interrupt input during analog mode. P31 and
P32 are valid interrupt inputs in conjunction with P33 (Ref) when in ana-
log mode.
P31 can still be used as T when analog mode is selected. If comparator
IN
outputs are required to be outputted on the Port 3 outputs, please refer to
specific products specification for priority of mixing when other special
features are sharing those same Port 3 pins.
I/O Ports
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Halt Mode
The analog comparators are functional during HALT mode if analog
mode has been enabled. P31 and P32, in conjunction with P33 (Ref) will
be able to generate interrupts. Only P33 cannot generate an interrupt
Because the P33 input goes directly to the Ref input of the comparators
and is disconnected from the interrupt sensing circuits.
Stop Mode
The analog comparators are disabled during STOP mode so it does not
use any current at that time. If P31, P32, or P33 are used as a source for
Stop-Mode Recovery, the Port 3 digital mode must be selected by setting
bit D1 = 0 in the Port 3 Mode Register. Otherwise in STOP mode, the
P31, P32, and P33 cannot be sensed. If analog mode was selected when
entering STOP mode, it will still be enabled after a valid SMR triggered
reset.
Open-Drain Configuration
®
All Z8 MCUs can configure Port 2 to provide open-drain outputs by pro-
gramming the Port 3 Mode Register (P3M) bit D0 = 0.
Register F7h
Port 3 Mode Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port 2 Configuration
1 = Pull-Ups Open-Drain
0 = Pull-Ups Active
Figure 61. Port 2 Configuration
®
Other Z8 MCUs feature a Port Configuration Register (PCON) for
which Port 0 and Port 1 can be configured to provide open-drain outputs.
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The PCON Register is located in Expanded Register File (ERF) Bank F,
Register 00h. See Figure 62.
PCON (Fh) 00h
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
0 Port 1 Open Drain
1 Port 1 Push–pull Active *
0 Port 0 Open Drain
1 Port 0 Push–pull Active *
0 Port 0 Low EMI
1 Port 0 Standard *
0 Port 1 Low EMI
1 Port 1 Standard *
0 Port 2 Low EMI
1 Port 2 Standard *
0 Port 3 Low EMI
1 Port 3 Standard *
Low EMI Oscillator
0 Low EMI
* Default Setting After RESET
1 Standard *
Figure 62. Port Configuration Register (Write-Only)
Port 1 Open-Drain. Port 1, D1 can be configured as open-drain by reset-
ting this bit (D1 = 0) or configured as push–pull active by setting this bit
(D1 = 1). The default value is 1.
Port 0 Open Drain. Port 0, D2 can be configured as open-drain by reset-
ting this bit (D2 = 0) or configured as push–pull active by setting this bit
(D2 = 1). The default value is 1.
I/O Ports
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Low EMI Emission
®
Some Z8 MCUs can be programmed to operate in a Low EMI Emission
Mode using the Port configuration register (PCON). The PCON register
allows the oscillator and all I/O ports to be programmed in the Low-EMI
®
Mode independently. Other Z8 MCUs may offer a ROM Mask or OTP
®
programming option to configure the Z8 MCU ports and oscillator glo-
bally to a Low-EMI mode (where the XTAL frequency is set equal to the
internal system clock frequency.
Use of the Low EMI feature results in:
•
•
•
•
•
The output pre-drivers slew rate reduced to 10 ns (typical)
Low EMI output drivers have resistance of 200Ω (typical)
Low EMI Oscillator
All output drivers are approximately 25 percent of the standard drive
Internal SCLK ÷ TCLK = XTAL operation limited to a maximum of
4MHz–250 ns cycle time, when Low EMI Oscillator is selected and
system clock (SCLK = XTAL, SMR Reg. Bit D1 = 1)
®
For Z8 MCUs having the PCON register feature, the following bits con-
trol the Low EMI options.
Low EMI Port 0. Port 0, D3 can be configured as a Low EMI Port by
resetting this bit (D3 = 0) or configured as a Standard Port by setting this
bit (D3 = 1). The default value is 1.
Low EMI Port 1. Port 1, D4 can be configured as a Low EMI Port by
resetting this bit (D4 = 0) or configured as a Standard Port by setting this
bit (D4 = 1). The default value is 1.
Low EMI Port 2. Port 2, D5 can be configured as a Low EMI Port by
resetting this bit (D5 = 0) or configured as a Standard Port by setting this
bit (D5 = 1). The default value is 1.
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Low EMI Port 3. Port 3, D6 can be configured as a Low EMI Port by
resetting this bit (D6 = 0) or configured as a Standard Port by setting this
bit (D6 = 1). The default value is 1.
Low EMI OSC. This D7 bit of the PCON Register controls the Low EMI
oscillator. A 1 in this location configures the oscillator with standard
drive, while a 0 configures the oscillator with low noise drive. The Low-
EMI mode will reduce the drive of the oscillator (OSC). The default value
is 1. XTAL ÷ 2 mode is not affected by this bit.
The maximum external clock frequency is 4MHz when running in the
Low EMI oscillator mode.
Please refer to the selected device product specification for availability of
the Low EMI feature and programming options.
Input Protection
®
All CMOS ROM Z8 MCUs have I/O pins with diode input protection.
There is a diode from the I/O pad to V and to V . See Figure 63.
CC
SS
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V
CC
PIN
V
SS
Figure 63. Diode Input Protection
®
On CMOS OTP EPROM Z8 MCUs, the Port 3 inputs P31, P32, P33 and
the XTAL 1 pin have only the input protection diode from pad to V . See
SS
Figure 64.
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PIN
V
SS
Figure 64. OTP Diode Input Protection
The high-side input protection diodes were removed on these pins to
allow the application of +12.5V during the various OTP programming
modes.
For better noise immunity in applications that are exposed to system EMI,
a clamping diode to V from these pins may be required to prevent
CC
entering the OTP programming mode or to prevent high voltage from
damaging these pins.
Z8 CMOS Autolatches
I/O port bits that are configurable as inputs are protected against open cir-
cuit conditions using autolatches. An autolatch is a circuit which, in the
event of an open circuit condition, latches the input at a valid CMOS
level. This inhibits the tendency of the input transistors to self-bias in the
forward active region, thus drawing excessive supply current. A simplified
schematic of the CMOS Z8 I/O circuit is shown in Figure 65.
I/O Ports
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V
DD
Open-Drain
OE
P
Data Out
N
PIN
Data In
V
DD
Autolatch
P
N
G1
Figure 65. Simplified CMOS Z8 I/O Circuit
The operation of the autolatch circuit is straight-forward. Assume the
input pad is latched at +5V (logic 1). The inverter G1 inverts the bit, turn-
ing the P-channel FET ON and the N-channel FET OFF. The output of the
circuit is effectively shorted to V , returning +5V to the input. If the pad
DD
is then disconnected from the +5V source, the autolatch will hold the
input at the previous state. If the device is powered up with the input float-
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ing, the state of the autolatch will be at either supply, but which state is
unpredictable.
There are four operating conditions which will activate the autolatches.
The first, which occurs when the input pin is physically disconnected
from any source, is the most obvious. The second occurs when the input is
connected to the output of a device with tri-state capability.
The autolatch will also activate when the input voltage at the pin is not
within 200 microvolts or so of either supply rail. In this case, the circuit
will draw current, which is not significant compared to the I operating
CC
current of the device, but will increase I
device dramatically.
STOP mode current of the
CC2
The fourth condition occurs when the I/O bit is configured as an output.
Referring to the output section of Figure 65, there are two ways of tri-stat-
ing the port pin. The first is by configuring the port as an input, which dis-
ables the OE signal turning both transistors off. The second can be
achieved in output mode by writing a 1 to the output port, then activating
the open drain mode. Both transistors are again off, and the port bit is in a
high impedance state. The autolatches then pull the input section toward
V
.
DD
Autolatch Model
The autolatch’s equivalent circuit is shown in Figure 66. When the input
is high, the circuit consists of a resistance Rp from V (the P-channel
DD
transistor in its ON state) and a much greater resistance Rh to G . Cur-
ND
rent I flows from V to the output. When the input is low, the circuit
AO
DD
may be modeled as a resistance Rp from G (the N-channel transistor in
ND
the ON state) and a much greater resistance Rh to V . Current I now
DD
AO
flows from the input to ground. The autolatch is characterized with
respect to I , so the equivalent resistance Rp is calculated according to
AO
R = (V –V )/I . The worst case equivalent resistance Rp (min) may
P
DD
IN AO
be calculated at the worst case input voltage, VI = VIH (min).
I/O Ports
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V
V
DD
DD
A0
R
R
R
R
P
H
Data in
Logic 0
Data in
Logic 1
PIN
PIN
A0
H
P
Figure 66. Autolatch Equivalent Circuit
Design Considerations
For circuits in which the autolatch is active, consideration should be given
to the loading constraints of the autolatches. For example, with weak val-
ues of V , close to Vih (min) or Vil (max), pullup or pull-down resis-
IN
tances must be calculated using Ref = R/Rp. For best case STOP mode
operation, the inputs should be within 200 mV of the supply rails.
In output mode, if a port bit is forced into a tri-state condition, the auto-
latches will force the pad to V . If there is an external pulldown resistor
DD
on the pin, the voltage at the pin may not switch to GND due to the auto-
latch. As shown in Figure 67, the equivalent resistance of the autolatch
and the external pulldown form a voltage divider, and if the external resis-
tor is large, the voltage developed across it will exceed V (max). For
IL
worst case.
VIL(max > V [R
÷ (R
+ R )]
DD
EXT
EXT P
R
(max) = [(VIL(max) ÷ V ) R ] ÷ [1—(VIL(max) ÷ V )]
EXT
DD P DD
For V = 5.0V and I = 5µA, VIH(max) = 0.8V:
DD
AO
REXT(max) = (0.16 ÷ 1M) ÷ (1—0.16) = 190KΩ.
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Rp increases rapidly with V , so increased V will relax the require-
DD
DD
ment on Rext.
In summary, the CMOS Z8 autolatch inhibits excessive current drain in
Z8 devices by latching an open input to either V or GND. The effect of
DD
the autolatch on the I/O characteristics of the device may be modeled by a
current I and a resistor Rp, whose value is V /I
.
AO
DD AO
V
LO
R
P
V
(min.)
IH
R
EXT
Figure 67. Effect of Pulldown Resistors on Autolatches
I/O Ports
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Counters and Timers
®
The Z8 CPU provides up to two 8-bit counter/timers, T0 and T1, each
driven by its own 6-bit prescaler, PRE0 and PRE1 (see Figure 68). Both
counter/timers are independent of the processor instruction sequence, that
relieves software from time-critical operations such as interval timing or
event counting. Some MCUs offer clock scaling using the SMR register.
See the device product specification for clock available options. The fol-
lowing description is typical.
Each counter/timer operates in either Single-Pass or Continuous mode. At
the end-of-count, counting either stops or the initial value is reloaded and
counting continues. Under software control, new values are loaded imme-
diately or when the end-of-count is reached. Software also controls the
counting mode, how a counter/timer is started or stopped, and its use of I/
O lines. Both the counter and prescaler registers can be altered while the
counter/timer is running.
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Internal Data Bus
Write
OSC
Read
Write
D1 (SMR)
T0
PRE0
Initial Value
Register
T0
Current Value
Register
Initial Value
Register
÷2
8-Bit
Down
Counter
6-Bit
Down
Counter
D0 (SMR)
÷4
IRQ
4
÷16
T
P36
OUT
÷2
IRQ
5
8-Bit
Down
Counter
6-Bit
Down
Counter
Internal
Clock
External Clock
Clock
Logic
T1
PRE1
Initial Value
Register
T1
÷4
Current Value
Register
Initial Value
Register
Write
Write
Internal Data Bus
Read
Internal Clock
Gated Clock
Triggered Clock
T
P31
IN
Figure 68. Counter/Timer Block Diagram
Counter/timers 0 and 1 are driven by a timer clock generated by dividing
the internal clock by four. The divide-by-four stage, the 6-bit prescaler,
and the 8-bit counter/timer form a synchronous 16-bit divide chain.
Counter/timer 1 can also be driven by a external input (T ) using P31.
IN
Port 3 line P36 can serve as a timer output (T
) through which T0, T1,
OUT
or the internal clock can be output. The timer output will toggle at the
end-of-count.
The counter/timer, prescaler, and associated mode registers are mapped
into the register file as shown in Figure 69. This allows the software to
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treat the counter/timers as general-purpose registers, and eliminates the
requirement for special instructions.
Prescalers and Counter/Timers
The prescalers, PRE0 (F5h) and PRE1 (F3h), each consist of an 8-bit reg-
ister and a 6-bit down-counter as shown in Figure 68. The prescaler regis-
ters are write-only registers. Reading the prescalers returns the value FFh.
Figures 70 and 71 show the prescaler registers.
The six most significant bits (D2–D7) of PRE0 or PRE1 hold the prescal-
ers count modulo, a value from 1 to 64 decimal. The prescaler registers
also contain control bits that specify T0 and T1 counting modes. These
bits also indicate whether the clock source for T is internal or external.
1
These control bits will be discussed in detail throughout this chapter.
The counter/timer registers, T0 (F4h) and T1 (F2h), each consist of an 8-
bit down-counter, a write-only register that holds the initial count value,
and a read-only register that holds the current count value (Figure 68).
The initial value can range from 1 to 256 decimal (01h,02h,..,00h).
Figure 72 illustrates the counter/timer registers.
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DEC
HEX Identifiers
F7
247
Port 3 Mode
T0 Prescaler
Timer/Counter0
T1 Prescaler
Time/Counter1
Timer Mode
F5
F4
F3
F2
F1
245
244
243
242
241
Figure 69. Counter/Timer Register Map
R245 PRE0
Prescaler 0 Register
(%F5; Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 = T Single Pass
0
1 = T Modulo-n
0
Reserved (Must be 0)
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 70. Prescaler 0 Register
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R243 PRE1
Prescaler 1 Register
(%F3; Write-Only)
U
U
U
U
U
U
0
0
Count Mode
0 = T Single Pass
1
1 = T Modulo-n
1
Clock Source
1 = T Internal
1
0 = T External (T )
1
IN
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 71. Prescaler 1 Register
R242 T1
Counter/Timer 1 Register
(%F2; Write/Read Only)
R244 T0
Counter/Timer 0 Register
(%F4; Write/Read Only)
D7 D6 D5 D4 D3 D2 D1 D0
Initial value when written
(Range 1-256 decimal, 01-00 HEX)
current value when read
Figure 72. Counter/Timer 0 and 1 Registers
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Counter/Timer Operation
Under software control, counter/timers are started and stopped via the
Timer Mode Register (TMR,F1h) bits D0–D3 (see Figure 73). Each
counter/timer is associated with a Load bit and an Enable Count bit.
Load and Enable Count Bits
Setting the Load bit (D0 for T0 and D2 for T1) transfers the initial value
in the prescaler and the counter/timer registers into their respective down-
counters. The next internal clock resets bits D0 and D2 to 0, readying the
Load bit for the next load operation. New values may be loaded into the
down-counters at any time. If the counter/timer is running, it continues to
do so and starts the count over with the new value. Therefore, the Load bit
actually functions as a software re-trigger.
R241 TMR
Timer Mode Register
(% F1; Read/Write)
D3 D2 D1 D0
0 = No Function
1 = Load T
0
0 = Disable T Count
0
1 = Enable T Count
0
0 = No Function
1 = Load T
1
0 = Disable T Count
1
1 = Enable T Count
1
Figure 73. Timer Mode Register
The counter timers remain at rest as long as the Enable Count bits are 0.
To enable counting, the Enable Count bit (D for T0 and D for T1) must
1
3
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be set to 1. Counting actually starts when the Enable Count bit is written
by an instruction. The first decrement occurs four internal clock periods
after the Enable Count bit has been set. If T1 is configured to use an exter-
nal clock, the first decrement begins on the next clock period. The Load
and Enable Count bits can be set at the same time. For example, using the
instruction:
OR TMR,#03h
sets both D0 and D1 of the TMR. This loads the initial values of PRE0
and T0 into their respective counters and starts the count after the M2T2
machine state after the operand is fetched (see Figure 74).
R243 PRE1
Prescaler 1 Register
(% F3; Write-Only)
R245 PRE0
Prescaler 0 Register
(% F5; Write-Only)
D0
Count Mode
0 = T Single Pass
1
1 = T Modulo-n
1
Figure 74. Starting The Count
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M3
M1
M2
Mn
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
First Decrement Occurs
Four Clock Periods Later
TMR is Written, Counter/Timer
is Loaded
#03h is Fetched
Figure 75. Counting Modes
Prescaler Operations
During counting, the programmed clock source drives the 6-bit Prescaler
Counter. The counter is counted down from the value specified by bits of
the corresponding Prescaler Register, PRE0 (bit 7 to bit 2) or PRE1 (bit 7
to bit 2; see Figures 70 and 71). When the Prescaler Counter reaches its
end-of-count, the initial value is reloaded and counting continues. The
prescaler never actually reaches 0. For example, if the prescaler is set to
divide-by-three, the count sequence is:
3–2–1–3–2–1–3–2–1–3...
Each time the prescaler reaches its end of count a carry is generated, that
allows the Counter/Timer to decrement by one on the next timer clock
input. When the Counter/Timer and the prescaler both reach the end-of-
count, an interrupt request is generated (IRQ4 for T0, IRQ5 for T1).
Depending on the counting mode selected, the Counter/Timer will either
come to rest with its value at 00h(Single-Pass Mode) or the initial value
will be automatically reloaded and counting will continue (Continuous
Mode). The counting modes are controlled by bit 0 of PRE0 and bit 0 of
PRE1 (see Figure 75). A 0, written to this bit configures the counter for
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Single-pass counting mode, while a 1 written to this bit configures the
counter for Continuous mode.
The Counter/Timer can be stopped at any time by setting the Enable
Count bit to 0, and restarted by setting it back to 1. The Counter/Timer
will continue its count value at the time it was stopped. The current value
in the Counter/Timer can be read at any time without affecting the count-
ing operation.
Note: The prescaler registers are write-only and cannot be read.
New initial values can be written to the prescaler or the Counter/Timer
registers at any time. These values will be transferred to their respective
down counters on the next load operation. If the Counter/Timer mode is
continuous, the next load occurs on the timer clock following an end-of-
count. New initial values should be written before the load operation,
because the prescalers always effectively operate in Continuous count
mode.
The time interval (i) until end-of-count, is given by the equation:
i = t x p x v
in which t = four times the internal clock period.
The internal clock frequency defaults to the external clock source (XTAL,
ceramic resonator, and others) divided by 2. Some Z8 microcontrollers
allow this divisor to be changed via the Stop-Mode Recovery register. See
the product data sheet for available clock divisor options.
t is equal to eight divided-by-XTAL frequency of the external clock
source for T1 (external clock mode only).
p = the prescaler value (1–63) for T and T .
0
1
The minimum prescaler count of 1 is achieved by loading 000001xx. The
maximum prescaler count of 63 is achieved by loading 111111xx.
v = the Counter/Timer value (1–256)
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Minimum duration is achieved by loading 01h(1 prescaler output count),
maximum duration is achieved by loading 00h(256 prescaler outputs
counts).
The prescaler and counter/timer are true divide-by-n counters.
T
Modes
OUT
The Timer Mode Register TMR (F1h; see Figure 76), is used in conjunc-
tion with the Port 3 Mode Register P3M (F7h; see Figure 77) to configure
P36 for T
operation for T0 and T1. In order for T
to function, P36
OUT
OUT
must be defined as an output line by setting P3M bit 5 to 0. Output is con-
trolled by one of the counter/timers (T0 or T1) or the internal clock.
Register F1hR
Timer Mode Register (TMR)
(Read/Write)
D7 D6
D3
D0
0 = No Function
1 = Load T
0
0 = Disable T Count
1
1 = Enable T Count
1
T
Modes:
OUT
T
OFF = 00
OUT
T OUT = 01
0
T OUT = 10
1
Internal Clock OUT = 11
Figure 76. Timer Mode Register (T
Operation)
OUT
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Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
0 P31 = Input (T )
P36 = Output (T
)
IN
OUT
1 P31 = DAV2/RDY2 P36 = RDY2/DAV2
Figure 77. Port 3 Mode Register (T
Operation)
OUT
The counter/timer to be output is selected by TMR bit 7 and bit 6. T0 is
selected to drive the T line by setting bit 7 to 0 and bit 6 to 1. Like-
OUT
wise, T1 is selected by setting bit 7 and bit 6 to 1 and 0, respectively. The
counter/timer T mode is turned off by setting TMR bit and bit 6 both
OUT
to 0, freeing P36 to be a data output line.
T
is initialized to a logic 1 whenever the TMR Load bit (bit 0 for T0
OUT
or bit 1 for T2) is set to 1. The T
configuration timer load, and Timer
OUT
Enable Count bits for the counter/timer driving the T
the same time. For example, using the instruction:
pin can be set at
OUT
OR TMR,#43h
•
•
•
Configures T0 to drive the T
pin (P36)
OUT
Sets the P36 T
pin to a logic 1 level
OUT
Loads the initial PRE0 and T0 levels into their respective counters
and starts the counter after the M2T2 machine state after the operand
is fetched
At end-of-count, the interrupt request line (IRQ4 or IRQ5), clocks a tog-
gle flip-flop. The output of this flip-flop drives the T line, P36. In all
OUT
cases, when the selected counter/timer reaches its end-of-count, T
OUT
toggles to its opposite state (see Figure 78). If, for example, the counter/
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timer is in Continuous Counting Mode, Tout will have a 50 percent duty
cycle output. This duty cycle can easily be controlled by varying the ini-
tial values after each end-of-count.
The internal clock can be selected as output instead of T0 or T1 by setting
TMR bit 7 and bit 6 both to 1. The internal clock (XTAL frequency ÷ 2) is
then directly output on P36 (see Figure 79).
While programmed as T
, P36 cannot be modified by a write to port
OUT
®
register P3. However, the Z8 software can examine the P36 current out-
put by reading the port register.
TMR
D7–D6 = 01
IRQ
4
(T0 End-of-Count)
P36
÷2
T
OUT
IRQ
TMR
D7–D6 = 10
5
(T1 End-of-Count)
Figure 78. T0 and T1 Output Through T
OUT
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Internal
Clock
÷2
OSC
P3
T
6
OUT
TMR D
6
TMR D
7
Figure 79. Internal Clock Output Through T
OUT
T Modes
IN
The Timer Mode Register TMR (F1h; see Figure 80) is used in conjunc-
tion with the Prescaler Register PRE1 (F3h; see Figure 81) to configure
P31 as T . T is used in conjunction with T1 in one of four modes:
IN IN
•
•
•
•
External Clock Input
Gated Internal Clock
Triggered Internal Clock
Retriggerable Internal Clock
The T mode is restricted for use with timer 1 only. To enable the T
IN
IN
mode selected (via TMR bits 4- 5), bit 1 of PRE1 must be set to 0.
The counter/timer clock source must be configured for external by setting
the PRE1 Register bit 2 to 1. The Timer Mode Register bit 5 and bit 4 can
then be used to select the appropriate T operation.
IN
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For T1 to start counting as a result of a T input, the Enable Count bit
IN
(bit 3 in TMR) must be set to 1. When using T as an external clock or a
IN
gate input, the initial values must be loaded into the down counters by set-
ting the Load bit (bit 2 in TMR) to a 1 before counting begins. In the
descriptions of T that follow, it is assumed the programmer has per-
IN
formed these operations. Initial values are automatically loaded in Trigger
and Retrigger modes so software loading is unnecessary.
Register F1h
Timer Mode Register (TMR)
(Read/Write)
D5 D4
T
= Modes:
IN
External Clock Input = 00
Gate Input = 01
Trigger Input = 10 (Non-retriggerable)
(Retriggerable)
Trigger Input = 11
Figure 80. Timer Mode Register (T Operation)
IN
Register F3h
Prescaler 1 Register (PRE1)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Clock Source
0 = T External Enable T Mode
1
1
IN
IN
1 = T Internal Disable T Mode
Figure 81. Prescaler 1 Register (T Operation)
IN
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It is suggested that P31 be configured as an input line by setting P3M
Register bit 5 to 0, although T is still functional if P31 is configured as a
IN
handshake input.
Each High-to-Low transition on T generates an interrupt request IRQ2,
IN
regardless of the selected T mode or the enabled/disabled state of T1.
IN
IRQ2 must therefore be masked or enabled according to the requirements
of the application.
External Clock Input Mode
The T External Clock Input Mode (TMR bit 5 and bit 4 both set to 0)
IN
supports counting of external events, where an event is considered to be a
High-to-Low transition on T (see Figure 82).
IN
See the product data sheet for the minimum allowed T external clock
IN
input period (T T ).
P
IN
TMR
D –D = 00
5
4
IRQ
5
T
IN
T1
PRE1
P3
D
D
1
Clock
IRQ
2
Internal
Clock
Figure 82. External Clock Input Mode
Gated Internal Clock Mode
The T Gated Internal Clock Mode (TMR bit 5 and bit 4 set to 0 and 1
IN
respectively) measures the duration of an external event. In this mode, the
T1 prescaler is driven by the internal timer clock, gated by a High level on
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T
(see Figure 83). T1 counts while T is High and stops counting
IN
IN
while
T
is Low. Interrupt request IRQ2 is generated on the High-to-Low tran-
IN
sition of T signalling the end of the gate input. Interrupt request IRQ5 is
IN
generated if T1 reaches its end-of-count.
Internal
Clock
÷2
OSC
TMR
D5–D4 = 01
÷4
PRE1 T1
IRQ5
IRQ2
P31
TIN
Gate
D
D
Figure 83. Gated Clock Input Mode
Triggered Input Mode
The T Triggered Input Mode (TMR bits 5 and 4 are set to 1 and 0,
IN
respectively) causes T1 to start counting as the result of an external event
(see Figure 84). T1 is then loaded and clocked by the internal timer clock
following the first High-to-Low transition on the T input. Subsequent
IN
T
transitions do not affect T1. In SINGLE-PASS mode, the Enable bit is
IN
reset whenever T1 reaches its end-of-count. Further T transitions will
IN
have no effect on T1 until software sets the Enable Count bit again. In
Continuous mode, once T1 is triggered counting continues until software
resets the Enable Count bit. Interrupt request IRQ5 is generated when T1
reaches its end-of-count.
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Internal
Clock
÷2
OSC
TMR
D5 =
1
÷4
PRE1 T1
IRQ5
Edge
Trigger
P31
TIN
Trigger
D
D
TMR
D5–D4 = 11
IRQ2
Figure 84. Triggered Clock Mode
Retriggerable Input Mode
The T Retriggerable Input Mode (TMR bits 5 and 4 are set to 1) causes
IN
T1 to load and start counting on every occurrence of a High-to-Low tran-
sition on T (see Figure 84). Interrupt request IRQ5 will be generated if
IN
the programmed time interval (determined by T1 prescaler and counter/
timer register initial values) has elapsed because the last High-to-Low
transition on T . In Single-Pass Mode, the end-of-count resets the Enable
IN
Count bit. Subsequent T transitions will not cause T1 to load and start
IN
counting until software sets the Enable Count bit again. In Continuous
Mode, counting continues once T1 is triggered until software resets the
Enable Count bit. When enabled, each High-to-Low T transition causes
IN
T1 to reload and restart counting. Interrupt request IRQ5 is generated on
every end-of-count.
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Cascading Counter/Timers
For some applications, it may be necessary to measure a time interval
greater than a single counter/timer can measure. In this case, T and
IN
T
can be used to cascade T0 and T1 as a single unit (see Figure 85).
OUT
T0 should be configured to operate in Continuous mode and to drive
T
. T should be configured as an external clock input to T1 and
OUT IN
wired back to T
. On every other T0 end-of-count, T
undergoes a
OUT
OUT
High-to-Low transition that causes T1 to count.
T1 can operate in either Single-Pass or Continuous mode. When the T1
end-of-count is reached, interrupt request IRQ5 is generated. Interrupt
requests IRQ2 (T High-to-Low transitions) and IRQ4 (T0 end-of-count)
IN
are also generated but are most likely of no importance in this configura-
tion and should be disabled.
P3
÷2
÷4
÷2
PRE1 T1
OSC
PRE0 T0
P3
IRQ
5
6
1
T
T
IN
OUT
IRQ
IRQ
2
4
Figure 85. Cascaded Counter/Timers
Reset Conditions
After a hardware reset, the counter/timers are disabled and the contents of
the counter/timer and prescaler registers are undefined. However, the
counting modes are configured for Single-Pass and the T1 clock source is
set for external.
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R242 T1
Counter/Timer 1 Register
(%F2; Write/Read Only)
R244 T0
Counter/Timer 0 Register
(%F4; Write/Read Only)
U
U
U
U
U
U
U
U
Initial value when written
(Range 1–256 decimal, 01–00 HEX)
current value when read
Figure 86. Counter/Timer Reset
T
is set for External Clock mode, and the T
mode is off. Figures 87
IN
OUT
through 89 show the binary reset values of the Prescaler, Counter/Timer,
and Timer Mode registers.
R243 PRE1
PRESCALER 1 REGISTER
(%F3; WRITE-ONLY)
U
U
U
U
U
U
0
0
COUNT MODE
0 = T SINGLE PASS
1
1 = T MODULO-N
1
CLOCK SOURCE
1 = T INTERNAL
1
0 = T EXTERNAL (T )
IN
1
PRESCALER MODULO
(RANGE: 1–64 DECIMAL
01–00 HEX)
Figure 87. Prescaler 1 Register Reset
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R245 PRE0
Prescaler 0 Register
(%F5; Write-Only)
U
U
U
U
U
U
U
0
Count Mode
0 = T Single Pass
0
1 = T Modulo-n
0
Reserved (Must be 0)
Prescaler Modulo
(Range: 1–64 Decimal
01–00 HEX)
Figure 88. Prescaler 0 Reset
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R241 TMR
Timer Mode Register
(% F1; Read/Write)
0
0
0
0
0
0
0
0
0 = No Function
1 = Load T
0
0 = Disable T Count
0
1 = Enable T Count
0
0 = No Function
1 = Load T
1
0 = Disable T Count
1
1 = Enable T Count
1
T
= Modes:
IN
External Clock Input = 00
Gate Input = 01
Trigger Input = 10
(Non-retriggerable)
Trigger Input = 11
(Retriggerable)
T
Modes:
OUT
T
OFF = 00
OUT
T OUT = 01
0
T OUT = 10
1
Internal Clock OUT = 11
Figure 89. Timer Mode Register Reset
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Interrupts
®
The Z8 CPU allows 6 different interrupts from a variety of sources; up
to four external inputs, the on-chip Counter/Timer(s), software, and serial
I/O peripherals. These interrupts can be masked and their priorities set by
using the Interrupt Mask and the Interrupt Priority Registers. All six inter-
rupts can be globally disabled by resetting the master Interrupt Enable, bit
7 in the Interrupt Mask Register, with a Disable Interrupt (DI) instruction.
Interrupts are globally enabled by setting bit 7 with an Enable Interrupt
(EI) instruction.
HEX
Identifier
Register
7
FBh
FAh
F9h
IMR
IRQ
IPR
Interrupt Mask
Interrupt Request
Interrupt Priority
Figure 90. Interrupt Control Registers
There are three interrupt control registers: the Interrupt Request Register
(IRQ), the Interrupt Mask register (IMR), and the Interrupt Priority Regis-
ter (IPR). Figure 90 shows addresses and identifiers for the interrupt con-
trol registers. Figure 91 is a block diagram showing the Interrupt Mask
and Interrupt Priority logic.
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®
The Z8 family supports both vectored and polled interrupt handling.
Details on vectored and polled interrupts can be found later in this chap-
ter.
IRQ –IRQ
0
5
6
IRQ
IMR
IPR
Global
Interrupt
Enable
6
Interrupt
Request
Priority Logic
Vector Select
Figure 91. Interrupt Block Diagram
Note: See the selected Z8 CPU's product specification for the exact interrupt
sources supported.
Interrupts
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Interrupt Sources
Table 18 presents the interrupt types, sources, and vectors available in the
®
Z8 family of processors.
Table 18. Interrupt Types, Sources, and Vectors
Name
Sources
Vector Location Comments
IRQ
IRQ
IRQ
DAV0, IRQ0, Comparator
0,1
External (P32), Edge
Triggered; Internal
0
1
2
DAV1, IRQ1
2,3
External (P33), Edge
Triggered; Internal
DAV2, IRQ2, T , Comparator 4,5
External (P31), Edge
Triggered; Internal
IN
IRQ3
6,7
External (P30) or (P32),
Edge Triggered;
Internal
Serial In
T0
6,7
Internal
Internal
Internal
Internal
8,9
Serial Out
T1
8,9
IRQ
10,11
5
External Interrupt Sources
External sources involve interrupt request lines IRQ0–IRQ3. IRQ0,
IRQ1, and IRQ2 can be generated by a transition on the corresponding
Port 3 pin (P32, P33, and P31 correspond to IRQ0, IRQ1, and IRQ2,
respectively).
Figure 92 is a block diagram for interrupt sources IRQ0, IRQ1, and IRQ2.
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The interrupt sources and trigger conditions are device dependent. See the
device product specification to determine available sources (internal and
external), triggering edge options, and exact programming details.
IRQ
m
m = 0,1,2
n = 2, 3, 1
Q
Q
Q
D
S
R
D
Multiple Input
and Signal
Conditioning
Circuitry
P3
n
System Clock
(Internal)
Figure 92. Interrupt Sources IRQ0-IRQ2 Block Diagram
When the Port 3 pin (P31, P32, or P33) transitions, the first flip-flop is set.
The next two flip-flops synchronize the request to the internal clock and
delay it by two internal clock periods. The output of the last flip-flop
(IRQ0, IRQ1, or IRQ2) goes to the corresponding Interrupt Request Reg-
ister.
IRQ3 can be generated from an external source only if Serial In is not
enabled. Otherwise, its source is internal. The external request is gener-
ated by a Low edge signal on P30 as shown in Figure 93. Again, the exter-
nal request is synchronized and delayed before reaching IRQ3. Some Z8
products replace P30 with P32 as the external source for IRQ3. In this
case, IRQ3 interrupt generation follows the logic as illustrated in
Figure 92.
Although interrupts are edge triggered, minimum interrupt request Low
and High times must be observed for proper operation. See the device
product specification for exact timing requirements on external interrupt
requests (T IL, T IH).
W
W
Interrupts
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P3M
6
Q
Q
D
D
PIN
(IRQ
3
Serial In)
IRQ
3
Clock
IRQ External Source
3
IRQ
3
Internal Source
Serial Receiver
Figure 93. Interrupt Source IRQ3 Block Diagram
Internal Interrupt Sources
Internal sources involve interrupt requests IRQ0, IRQ2, IRQ3, IRQ4, and
IRQ5. Internal sources are ORed with the external sources, so either an
internal or external source can trigger the interrupt. Internal interrupt
sources and trigger conditions are device dependent.
See the device product specification to determine available sources, trig-
gering edge options, and exact programming details. For more details on
the internal interrupt sources, refer to the chapters describing the Counter/
Timer, I/O ports, and Serial I/O.
Interrupt Request Register Logic and Timing
Figure 94 shows the logic diagram for the Interrupt Request (IRQ) Regis-
ter. The leading edge of the request will set the first flip-flop, that will
remain set until interrupt requests are sampled.
Requests are sampled internally during the last clock cycle before an
opcode fetch (see Figure 95). External requests are sampled two internal
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clocks earlier, due to the synchronizing flip-flops shown in Figures 92 and
93.
At sample time the request is transferred to the second flip-flop in
Figure 94, that drives the interrupt mask and priority logic. When an inter-
rupt cycle occurs, this flip-flop will be reset only for the highest priority
level that is enabled.
The user has direct access to the second flip-flop by reading and writing
the IRQ Register. IRQ is read by specifying it as the source register of an
instruction and written by specifying it as the destination register.
To Mask
and
Priority
Logic
Q
Q
IRQ0–IRQ5
S
R
Sample
Clock
R
From
Priority
Logic
Figure 94. IRQ Register Logic
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Mn
M1
M2
T1 T2 T3 T1 T2 T3 T1 T2 T3
Interrupt Request
Sampled Internally
External Interrupt
Request Sampled
Figure 95. Interrupt Request Timing
Interrupt Initialization
After reset, all interrupts are disabled and must be initialized before vec-
tored or polled interrupt processing can begin. The Interrupt Priority Reg-
ister (IPR), Interrupt Mask Register (IMR), and Interrupt Request
Register (IRQ) must be initialized, in that order, to start the interrupt pro-
cess.
Interrupt Priority Register Initialization
The Interrupt Priority Register (IPR) shown in Figure 96 is a write-only
register that sets priorities for the vectored interrupts in order to resolve
simultaneous interrupt requests. (There are 48 sequence possibilities for
interrupts.) The six interrupt levels IRQ0-IRQ5 are divided into three
groups of two interrupt requests each. One group contains IRQ3 and
IRQ5. The second group contains IRQ0 and IRQ2, while the third group
contains IRQ1 and IRQ4.
Priorities can be set both within and between groups as shown in
Tables 19 and 20. Bits 1, 2, and 5 define the priority of the individual
members within the three groups. Bits 0, 3, and 4 are encoded to define
six priority orders between the three groups. Bits 6 and 7 are reserved.
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Register F9h
Interrupt Priority Register (IPR)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
Bits
Priority
000
001
010
011
100
101
110
111
Reserved
C > A > B
A > B > C
A > C > B
B > C > A
C > B > A
B > A > C
Reserved
Group C (IRQ1 and IRQ4 Priority)
0 = IRQ1 > IRQ4
1 = IRQ4 > IRQ1
Group B (IRQ0 and IRQ2 Priority)
0 = IRQ2 > IRQ0
1 = IRQ0 > IRQ2
Group A (IRQ3 and IRQ5 Priority)
0 = IRQ5 > IRQ3
1 = IRQ3 > IRQ5
Reserved (Must be 0)
Figure 96. Interrupt Priority Register
Table 19. Interrupt Priority
Priority
Highest
Group
Bit
Value
Lowest
IRQ4
IRQ1
IRQ0
IRQ2
C
Bit 1
0
1
0
1
IRQ1
IRQ4
IRQ2
IRQ0
B
Bit 2
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Table 19. Interrupt Priority (Continued)
Priority
Group
Bit
Value
Highest
Lowest
IRQ3
A
Bit 5
0
1
IRQ5
IRQ3
IRQ5
Table 20. Interrupt Group Priority
Bit Pattern
Bit 4 Bit 3
Group Priority
Medium
Bit 0
High
Low
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Not Used
C
A
B
C
C
B
A
B
C
B
A
A
C
A
A
B
C
B
Not Used
Interrupt Mask Register Initialization
The Interrupt Mask Register individually or globally enables or disables
the six interrupt requests (see Figure 97). When bit 0 to bit 5 are set to 1,
the corresponding interrupt requests are enabled. Bit 7 is the master
enable and must be set before any of the individual interrupt requests can
be recognized. Resetting bit 7 globally disables all of the interrupt
requests. Bit 7 is set and reset by the EI and DI instructions. It is automat-
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ically reset during an interrupt service routine and set following the exe-
cution of an Interrupt Return (IRET) instruction.
Bit 7 must be reset by the DI instruction before the contents of the Inter-
rupt Mask Register or the Interrupt Priority Register are changed except:
•
•
Immediately after a hardware reset
Immediately after executing an interrupt service routine and before
IMR bit 7 has been set by any instruction
Register FBh
Interrupt Request Register (IMR)
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
0 = Disables IRQ0
1 = Enables IRQ0
0 = Disables IRQ1
1 = Enables IRQ1
0 = Disables IRQ2
1 = Enables IRQ2
0 = Disables IRQ3
1 = Enables IRQ3
0 = Disables IRQ4
1 = Enables IRQ4
0 = Disables IRQ5
1 = Enables IRQ5
0 = Disables RAM Protect
1 = Enables RAM Protect
0 = Disables Interrupt
1 = Enables Interrupt
Figure 97. Interrupt Mask Register
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The RAM Protect option is selected at ROM mask submission time or at
EPROM program time. If not selected or not an available option, this bit is
reserved and must be 0.
Interrupt Request Register Initialization
The Interrupt Request Register (IRQ), shown in Figure 98, is a read/write
register that stores the interrupt requests for both vectored and polled
interrupts. When an interrupt is made on any of the six, the corresponding
bit position in the register is set to 1. Bit 0 to bit 5 are assigned to interrupt
requests IRQ0 to IRQ5, respectively.
Whenever Power-On Reset (POR) is executed, the IRQ resister is reset to
00hand disabled. Before the IRQ register will accept requests, it must be
enabled by executing an ENABLE INTERRUPTS (EI) instruction.
Setting the Global Interrupt Enable bit in the Interrupt Mask Register
(IMR, bit 7) will not enable the IRQ. Execution of the EI instruction is
required (see Figure 99).
For polled processing, IRQ must still be initialized by an EI instruction.
To properly initialize the IRQ register, the following code is provided.
CLR
EI
IMR
// Make sure vectored interrupts are disabled.
// Enable IRQ register, otherwise read only.
// Not required if interrupts were previously enabled.
DI
// Disable interrupt heading.
Note: IRQ is always cleared to 00hand is read only until the first EI instruction,
which enables the IRQ to be read/write.
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Register FAh
Interrupt Request Register (IRQ)
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
0 = IRQ0 RESET
1 = IRQ0 SET
0 = IRQ1 RESET
1 = IRQ1 SET
0 = IRQ2 RESET
1 = IRQ2 SET
0 = IRQ3 RESET
1 = IRQ3 SET
0 = IRQ4 RESET
1 = IRQ4 SET
0 = IRQ5 RESET
1 = IRQ5 SET
Reserved /Int Edge Select
Figure 98. Interrupt Request Register
IMR is cleared before the IRQ enabling sequence to insure no unexpected
interrupts occur when EI is executed. This code sequence should be exe-
cuted prior to programming the application required values for IPR and
IMR.
IRQ bits 6 and 7 are device dependent. When reserved, the bits are not
used and will return a 0 when read. When used as the Interrupt Edge select
bits, the configuration options are as show in Table 21.
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Table 21. IRQ Register Configuration*
IRQ Interrupt Edge
D7
0
D6
0
P31
F
P32
F
0
1
F
R
1
0
R
F
1
1
R/F
R/F
*Note: F = Falling Edge; R = Rising Edge.
The proper sequence for programming the interrupt edge select bits is
(assumes IPR and IMR have been previously initialized).
DI
;Inhibit all interrupts until input edges are
configured.
OR
EI
IRQ,#XX 000000b ;Configure interrupt; do not disturb edges
as required—IRQ 0-5.
;Reenable interrupts.
El Instruction
Interrupt Request Register
(IRQ, FAh)
S
RESET
R
POR
Figure 99. IRQ Reset Functional Logic Diagram
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IRQ Software Interrupt Generation
IRQ can be used to generate software interrupts by specifying IRQ as the
®
destination of any instruction referencing the Z8 Standard Register File.
These Software Interrupts (SWI) are controlled in the same manner as
hardware generated requests (in other words, the IPR and the IMR control
the priority and enabling of each SWI level).
To generate a SWI, the appropriate request bit in the IRQ is set as follows:
ORIRQ, #NUMBER
where the immediate data, NUMBER, has a 1 in the bit position corre-
sponding to the appropriate level of the SWI. For example, if an SWI is
required on IRQ5, NUMBER would have a 1 in bit 5:
OR IRQ, #00100000b
With this instruction, if the interrupt system is globally enabled, IRQ5 is
enabled, and there are no higher priority pending requests, control is
transferred to the service routine pointed to by the IRQ5 vector.
Vectored Processing
Each Z8 interrupt level has its own vector. When an interrupt occurs, con-
trol passes to the service routine pointed to by the interrupt’s vector loca-
tion in program memory. The sequence of events for vectored interrupts is
as follows:
•
•
•
•
•
PUSH PC Low byte on stack
PUSH PC High byte on stack
PUSH FLAGS on stack
Fetch High byte of vector
Fetch Low byte of vector
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•
Branch to service routine specified by vector
Figures 100 and 101 show the vectored interrupt operation.
SP and Stack before an interrupt
SP and Stack after an interrupt
SP
SP
Top of Stack
PC LOW Byte
PC HIGH Byte
FLAGS
Figure 100. Effects of an Interrupt on the Stack
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Program Memory
XXFFh
Interrupt
Service
Routine
PC HIGH Byte
FLAGS
000Ch
Vector Selected
By Priority Logic
Interrupt
Vector Table
0000h
Figure 101. Interrupt Vectoring
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Vectored Interrupt Cycle Timing
The interrupt acknowledge cycle time is 24 internal clock cycles and is
shown in Figure 102. In addition, two internal clock cycles are required
for the synchronizing flip-flops. The maximum interrupt recognition time
is equal to the number of clock cycles required for the longest executing
instruction present in the user program (assumes worst case condition of
interrupt sampling, Figure 95, just prior to the interrupt occurrence). To
calculate the worst case interrupt latency (maximum time required from
interrupt generation to fetch of the first instruction of the interrupt service
routine), sum these components:
Worst Case Interrupt Latency ≈ 24 INT CLK (interrupt acknowledge
time) + # T C of longest instruction present in the user's application pro-
P
gram + 2T C (internal synchronization time).
P
Fetch
Vector High
Fetch
Vector Low
M1
M1
M2
M3
Stack Push
M2
Stack Push
Stack Push
Internal Clock
AS
/DS
For Stack External Only
Odd Vector Address
A0-A7 OUT
A0-A7 IN
PC+1
PC
SP-1 PCL
PCH
SP-3 FLAGS
SP-2
VECT
VECT+1
PC
Even Vector Address
Op Code (Discarded)
VECTL
VECTH
First Instruction Of Interrupt Service Routine
R/W
For Stack External Only
Figure 102. Z8 Interrupt Acknowledge Timing
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Nesting of Vectored Interrupts
Nesting of vectored interrupts allows higher priority requests to interrupt
a lower priority request. To initiate vectored interrupt nesting, do the fol-
lowing during the interrupt service routine:
•
•
•
•
•
•
Push the old IMR on the stack
Load IMR with a new mask to disable lower priority interrupts
Execute EI instruction
Proceed with interrupt processing
After processing is complete, execute DI instruction
Restore the IMR to its original value by returning the previous mask
from the stack
•
Execute IRET
Depending on the application, some simplification of the above procedure
may be possible.
Polled Processing
Polled interrupt processing is supported by masking off the IRQ to be
polled. This is accomplished by clearing the corresponding bits in the
IMR.
To enable any interrupt, first the interrupt mechanism must be engaged
with an EI instruction. If only polled interrupts are to be serviced, exe-
cute:
EI ;Enable interrupt mechanism
DI ;Disable vectored interrupts.
To initiate polled processing, check the bits of interest in the IRQ using
the Test Under Mask (TM) instruction. If the bit is set, call or branch to
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the service routine. The service routine services the request, resets its
Request Bit in the IRQ, and branches or returns back to the main pro-
gram. An example of a polling routine is as follows:
TM IRQ, #MASKA
JR Z, NEXT
;Test for request
;If no request go to NEXT
;If request is there, then
;service it
CALL SERVICE
NEXT:
.
.
.
SERVICE:
;Process Request
.
.
.
AND IRQ, #MASKB ;Clear Request Bit
RET ;Return to next
In this example, if IRQ2 is being polled, MASKA will be 00000100b
and MASKB will be 11111011b.
Reset Conditions
Upon reset, all bits in IPR are undefined.
In IMR, bit 7 is 0 and bits 0–6 are undefined. The IRQ register is reset and
held in that state until an enable interrupt (EI) instruction is executed.
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Power-Down Modes
®
In addition to the standard RUN mode, the Z8 CPU supports two Power-
Down modes to minimize device current consumption. The two modes
supported are HALT and STOP.
Halt Mode Operation
HALT mode suspends instruction execution and turns off the internal
CPU clock. The on-chip oscillator circuit remains active so the internal
clock continues to run and is applied to the Counter/Timer(s) and inter-
rupt logic.
To enter HALT mode, it is necessary to first flush the instruction pipeline
to avoid suspending execution in mid-instruction. To do this, the applica-
tion program must execute a NOP instruction (opcode = FFh) immedi-
ately before the HALT instruction (opcode 7Fh), that is:
FF NOP ;clear the instruction pipeline
7F HALT ;enter HALT mode
HALT mode is exited by interrupts, either externally or internally gener-
ated. Upon completion of the interrupt service routine, the user program
continues from the instruction after HALT.
HALT mode may also be exited via a POR/RESET activation or a Watch–
Dog Timer (WDT) time-out. (See the product data sheet for WDT avail-
ability). In this case, program execution will restart at the reset restart
address 000Ch.
To further reduce power consumption in HALT mode, some Z8 family
devices allow dynamic internal clock scaling. Clock scaling may be
accomplished on the fly by reprogramming bit 0 and/or bit1 of the Stop-
Mode Recovery register (SMR). See Figure 103 on page 160.
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Note: Internal clock scaling directly affects Counter/Timer operation—adjust-
ment of the prescaler and downcounter values may be required. To deter-
mine the actual HALT mode current (I ) value for the various optional
CC1
modes available, see the related Z8 device’s product specification.
Stop Mode Operation
STOP mode provides the lowest possible device standby current. This
instruction turns off the on-chip oscillator and internal system clock.
To enter STOP mode, it is necessary to first flush the instruction pipeline
to avoid suspending execution in mid-instruction. To do this, the applica-
tion program must execute a NOP instruction (opcode = FFh) immedi-
ately before the STOP instruction (opcode = 6Fh), that is,
FF NOP ;clear the instruction pipeline
6F STOP ;enter STOP mode
STOP mode is exited by any one of the following resets: Power-On Reset
activation, WDT time out (if available), or a Stop-Mode Recovery source.
Upon reset generation, the processor will always restart the application
program at address 000Ch.
POR/RESET activation is present on all Z8 devices and is implemented as
a reset pin and/or an on-chip power on reset circuit.
Some Z8 devices allow for the on-chip WDT to run in STOP mode. If so
activated, the WDT time-out will generate a reset some fixed time period
after entering STOP mode.
Stop-Mode Recovery by the WDT will increase STOP mode standby cur-
rent (I ). This is due to the WDT clock and divider circuitry that is now
CC2
enabled and running to support this recovery mode. See the product data
sheet for actual I
values.
CC2
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All Z8 devices provide some form of dedicated Stop-Mode Recovery
(SMR) circuitry. Two SMR methods are implemented—a single fixed
input pin or a flexible, programmable set of inputs. The selected Z8
device product specification should be reviewed to determine the SMR
options available for use.
For devices that support SPI, the slave mode compare feature also serves
as a SMR source.
In the simple case, a low level applied to input pin P27 will trigger a
SMR. To use this mode, pin P27 (I/O Port 2, bit 7) must be configured as
an input before STOP mode is entered. The low level on P27 must meet a
minimum pulse width T
. (See the product data sheet) to trigger the
WSM
device reset mode). Some Z8 devices provide multiple SMR input
sources. The appropriate SMR source is selected via the SMR Register.
Use of specialized SMR modes (P2.7 input or SMR register based) or the
WDT time-out (only when in STOP mode) provide a unique reset opera-
tion. Some control registers are initialized differently for a SMR/WDT
triggered POR than a standard reset operation. See the product specifica-
tion (register file map) for exact details.
To determine the actual STOP mode current (I ) value for the optional
CC2
SMR modes available, see the selected Z8 device’s product data sheet.
STOP mode current (I ) will be minimized when:
CC2
•
•
•
•
V
is at the low end of the devices operating range
CC
WDT is off in STOP mode
Output current sourcing is minimized
All inputs (digital and analog) are at the low or high rail voltages
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Stop-Mode Recovery Register
This register selects the clock divide value and determines the mode of
Stop-Mode Recovery (see Figure 103). All bits are Write-Only, except bit
7, that is Read-Only. Bit 7 is a flag bit that is hardware set on the condi-
tion of stop-recovery and reset by a power-on cycle. Bit 6 controls
whether a low level or a high level is required from the recovery source.
Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, of the SMR
register, specify the source of the Stop-Mode Recovery signal. Bits 0 and
1 control internal clock divider circuitry. The SMR is located in Bank F of
the Expanded Register File at address 0Bh.
SMR (Fh) 0B
D7 D6 D5 D4 D3 D2 D1 D0
SCLK ÷ TCLK Divide-by-16
0 OFF **
1 ON
External Clock Divide by 2
0 SCLK ÷ TCLK = XTAL ÷ 2*
1 SCLK ÷ TCLK = XTAL
Stop-Mode Recovery Source
000 POR Only and/or External Reset
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0–3
111 P2 NOR 0–7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read Only)
0 POR*
1 Stop Recovery
* Default setting after RESET.
** Default setting after RESET and Stop-Mode Recovery.
Figure 103. Stop-Mode Recovery Register (Write-Only Except Bit D7,
Which Is Read-Only)
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The SMR register is available in select Z8 CPU products. Refer to the
device product specification to determine SMR options available.
SCLK ÷ TCLK Divide-by-16 Select. This D0 bit of the SMR controls a
divide-by-16 prescaler of SCLK ÷ TCLK. The purpose of this control is
to selectively reduce device power consumption during normal processor
execution (SCLK control) and/or HALT mode (where TCLK sources
counter/timers and interrupt logic).
External Clock Divide-by-Two. This D1 bit can eliminate the oscillator
divide-by-two circuitry. When this bit is 0, the System Clock (SCLK) and
Timer Clock (TCLK) are equal to the external clock frequency divided by
two. The SCLK ÷ TCLK is equal to the external clock frequency when
this bit is set (D1 = 1). Using this bit together with D7 of PCON helps fur-
ther lower EMI (D7 (PCON) = 0, D1 (SMR) = 1). The default setting is
zero.
Stop-Mode Recovery Source. The D2, D3, and D4 bits of the SMR
specify the wake-up source of the stop-recovery and (Table 22 and
Figure 104).
Table 22. Stop-Mode Recovery Source
SMR: 432
D4
0
D3 D2 Description of Operation
0
0
1
1
0
0
1
0
1
0
POR and/or external reset recovery.
P30 transition.
0
0
P31 transition (not in Analog Mode).
P32 transition (not in Analog Mode).
P33 transition (not in Analog Mode).
0
1
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Table 22. Stop-Mode Recovery Source
SMR: 432
D3 D2 Description of Operation
D4
1
0
1
1
1
0
1
P27 transition.
1
Logical NOR of P20 through P23.
Logical NOR of P20 through P27.
1
Stop-Mode Recovery Delay Select. This D5 bit, if High, enables the
T
RESET delay after Stop-Mode Recovery. The default configuration
POR
of this bit is 1. If the fast wake up is selected, the Stop-Mode Recovery
source is kept active for at least 5 TpC.
Stop-Mode Recovery Edge Select. A 1 in this D6 bit position indicates
®
that a high level on any one of the recovery sources wakes the Z8 CPU
from STOP mode. A 0 indicates low-level recovery. The default is 0 on
POR (see Figure 104).
Cold or Warm Start. This D7 bit is set by the device upon entering
STOP mode. A 0 in this bit (cold) indicates that the device reset by POR/
WDT RESET. A 1 in this bit (warm) indicates that the device awakens by
a SMR source.
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SMR D4 D3 D2
0
0
0
SMR D4 D3 D2 SMR D4 D3 D2
SMR D4 D3 D2
SMR D4 D3 D2
SMR D4 D3 D2
V
DD
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
1
0
1
0
1
P20
P20
P30
P31
P32
P27
P33
P27
P23
To POR
RESET
Stop Mode Recovery Edge
Select (SMR)
To P33 Data
Latch and IRQ
1
MUX
P33 From Pads
Digital/Analog Mode
Select (P3M)
Figure 104. Stop-Mode Recovery Source
If P31, P32, or P33 are to be used for a SMR source, the digital mode of
operation must be selected prior to entering STOP mode.
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Power-Down Modes
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Serial Input/Output
UART Introduction
®
Select Z8 CPU microcontrollers contain an on-board full-duplex Uni-
versal Asynchronous Receiver/Transmitter (UART) for data communica-
tions. The UART consists of a Serial I/O Register (SIO) located at address
F0h, and its associated control logic (see Figure 105). The SIO is actually
two registers, the receiver buffer and the transmitter buffer, which are
used in conjunction with Counter/Timer T0 and Port 3 I/O lines P30
(input) and P37 (output). Counter/Timer T0 provides the clock input for
control of the data rates.
Internal Data Bus
Read FOH
IRQ
4
Stop
Bit Detect
Receiver
Buffer
Transfer
Write FOH
Mark
Transmitter
Shift Register
Serial
Out
Receiver
Shift Register
Char
Detect
Serial
In
P3
7
P3
0
Shift
Clock
Shift
Clock
RESET
Parity
Gan
Parity
Check
÷16
Start
Bit Detect
Start
IRQ
3
Clock
Control
÷6
Stop
Serial I/O Clock (From T0)
Figure 105. UART Block Diagram
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Configuration of the UART is controlled by the Port 3 Mode Register
®
(P3M) located at address F7h. the Z8 CPU always transmits eight bits
between the start and stop bits (eight Data Bits or seven Data Bits and one
Parity Bit). Odd parity generation and detection is supported.
The SIO Register and its associated Mode Control Registers are mapped
into the Standard Z8 Register File as shown in Table 23. The organization
allows the software to access the UART as general-purpose registers,
eliminating the requirement for special instructions.
Table 23. UART Register Map
Register Name
Port 3 Mode
T0 Prescaler
Timer/Counter0
Timer Mode
UART
Identifier
P3M
Hex Address
F7
F5
F4
F1
F0
PRE0
T0
TMR
SIO
UART Bit-Rate Generation
When Port 3 Mode Register bit 6 is set to 1, the UART is enabled and T0
automatically becomes the bit rate generator (see Figure 106). The end-
of-count signal of T0 no longer generates Interrupt Request IRQ4.
Instead, the signal is used as the input to the divide-by-16 counters (one
each for the receiver and the transmitter) that clock the data stream.
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Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
0 P30 Input and P37 = Output
1 P30 Serial In and P37 = Serial Out
Figure 106. Port 3 Mode Register and Bit-Rate Generation
The divide chain that generates the bit rate is shown in Figure 107. The bit
rate is given by the following equation:
Bit Rate = XTAL Frequency ÷ (2 x 4 x p x t x 16)
where p and t are the initial values in Prescaler0 and Counter/Timer0,
respectively. The final divide-by-16 is required because T0 runs at 16
times the bit rate in order to synchronize on the incoming data.
Bit Rate
Clock
P
÷4
÷2
t
f
÷16
XTAL
T0
PRE0
Figure 107. Bit Rate Divide Chain
®
To configure the Z8 CPU for a specific bit rate, appropriate values as
determined by the above equation must be loaded into registers PRE0
(F5h) and T0 (F4h). PRE0 also controls the counting mode for T0 and
should therefore be set to CONTINUOUS mode (D0 = 1).
For example, given an input clock frequency (XTAL) of 11.9808MHz
and a selected bit rate of 1200 bits per second, the equation is satisfied by
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p = 39 and t = 2. Counter/Timer T0 should be set to 02h. With T0 in Con-
tinuous Mode, the value of PRE0 becomes 9Dh(see Figure 108).
Table 24 lists several commonly used bit rates and the values of XTAL, p,
and t required to derive them. This list is presented for convenience and is
not intended to be exhaustive.
Table 24. Bit Rates
7,3728
7,9872
9,8304
11,0592 11,6736 11,9808 12,2880
Bit Rate
19200
9600
4800
2400
1200
600
p
3
3
3
3
3
3
3
3
3
t
p
–
t
p
4
4
4
4
4
4
4
4
4
t
1
p
–
9
9
9
9
9
9
9
5
t
p
–
t
p
–
t
p
5
5
5
5
5
5
5
5
8
t
1
1
2
4
8
–
–
1
2
4
8
–
1
2
4
8
–
–
1
2
4
8
–
–
–
1
2
4
8
–
2
–
–
2
13
13
4
19
19
19
–
4
8
39
39
39
8
16 13
32 13
16
32
64
128
175
16
32
64
128
109
16 19
300
64 13 16
128 13 32
32 19 16 39
150
64 19 32 39 16
157 207 17 50
110
175
3
189
4
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Register F5h
Prescalar 0 Register (PRE0)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 = T Single Pass
0
1 = T Modulo-n
0
(Range: 1-64 decimal, 01h–00h)
(Range: 1-64)
Figure 108. Prescaler 0 Register Bit-Rate Generation
The bit rate generator is started by setting the Timer Mode Register
(TMR) (F1h) bit 1 and bit 0 both to 1 (see Figure 109). This transfers the
contents of the Prescaler 0 Register and Counter/Timer0 Register to their
corresponding down counters. In addition, counting is enabled so that
UART operations begin.
Register F1h
Timer Mode Register (TMR)
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
0 = No Function
1 = Load T
0
0 = Disable T Count
0
1 = Enable T Count
0
Figure 109. Timer Mode Register Bit Rate Generation
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UART Receiver Operation
The receiver consists of a receiver buffer (SIO Register [F0h]), a serial-in,
parallel-out shift register, parity checking, and data synchronizing logic.
The receiver block diagram is shown as part of Figure 105 on page 165.
Receiver Shift Register
After a hardware reset or after a character has been received, the Receiver
Shift Register is initialized to all 1s and the shift clock is stopped. Serial
data, input through Port 3 bit 0, is synchronized to the internal clock by
two D-type flip-flops before being input to the Shift Register and the start
bit detection circuitry.
The start bit detection circuitry monitors the incoming data stream, look-
ing for a start bit (a High-to-Low input transition). When a start bit is
detected, the shift clock logic is enabled. The T0 input is divided-by-16
and, when the count equals eight, the divider outputs a shift clock. This
clock shifts the start bit into the Receiver Shift Register at the center of
the bit time. Before the shift actually occurs, the input is rechecked to
ensure that the start bit is valid. If the detected start bit is false, the
receiver is reset and the process of looking for a start bit is repeated. If the
start bit is valid, the data is shifted into the Shift Register every sixteen
counts until a full character is assembled (see Figure 110).
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Stop Bit
One or More
Start Bit Transition Detected
(R)
RCVR
Data
Shift
Clock
Eight T0 Counts Later Shifting Starts
RCVR
IRQ3
Shift register Contents
Transferred to Receive Buffer
and IRQ3 is Generated
Figure 110. Receiver Timing
After a full character has been assembled in the receiver’s buffer, SIO
Register (F0h), Interrupt Request IRQ3 is generated. The shift clock is
stopped and the Shift Register reset to all 1s. The start bit detection cir-
cuitry begins monitoring the data input for the next start bit. This cycle
allows the receiver to synchronize on the center of the bit time for each
incoming character.
Overwrites
Although the receiver is single buffered, it is not protected from being
overwritten, so the software must read the SIO Register (F0h) within one
®
character time after the interrupt request (IRQ3). the Z8 CPU does not
have a flag to indicate this overrun condition. If polling is used, the IRQ3
bit in the Interrupt Request Register must be reset by software.
Framing Errors
Framing error detection is not supported by the receiver hardware, but by
responding to the interrupt request within one character bit time, the soft-
ware can test for a stop bit on P30. Port 3 bits are always readable, which
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facilitates break detection. For example, if a null character is received,
testing P30 results in a 0 being read.
Parity
The data format supported by the receiver must have a start bit, eight data
bits, and at least one stop bit. If parity is on, bit 7 of the data received will
be replaced by a Parity Error Flag. A parity error sets bit 7 to 1, otherwise,
bit D7 is set to 0. Figure 111 shows these data formats.
Received Data
(No Parity)
SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
One Stop Bit
Received Data
(With Parity)
SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Seven Data Bits
Parity Error Flag
One Stop Bit
Figure 111. Receiver Data Formats
®
The Z8 CPU hardware supports odd parity only, that is enabled by set-
ting the Port 3 Mode Register bit 7 to 1 (see Figure 112). If even parity is
required, PARITY mode should be disabled (P3M bit 7 set to 0), and soft-
ware must calculate the received data’s parity.
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Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
0 = Parity OFF
1 = Parity ON
Figure 112. Port 3 Mode Register Parity
Transmitter Operation
The transmitter consists of a transmitter buffer (SIO Register [F0h]), a
parity generator, and associated control logic. The transmitter block dia-
gram is shown as part of Figure 105 on page 165.
After a hardware reset or after a character has been transmitted, the trans-
mitter is forced to a marking state (output always High) until a character
is loaded into the transmitter buffer, SIO Register (F0h). The transmitter
is loaded by specifying the SIO Register as the destination register of any
instruction.
T0’s output drives a divide-by-16 counter that in turn generates a shift
clock every 16 counts. This counter is reset when the transmitter buffer is
written by an instruction. This reset synchronizes the shift clock to the
software. The transmitter then outputs one bit per shift clock, through Port
3 bit 7, until a start bit, the character written to the buffer, and two stop
bits have been transmitted. After the second stop bit has been transmitted,
the output is again forced to a marking state. Interrupt request IRQ4 is
generated at this time to notify the processor that the transmitter is ready
to accept another character.
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Overwrites
The user is not protected from overwriting the transmitter, so it is up to
the software to respond to IRQ4 appropriately. If polling is used, the
IRQ4 bit in the Interrupt Request Register must be reset.
Parity
The data format supported by the transmitter has a start bit, eight data
bits, and at least two stop bits. If parity is on, bit 7 of the data transmitted
will be replaced by an odd parity bit. Figure 113 shows the transmitter
data formats.
Parity is enabled by setting Port 3 Mode Register bit 7 to 1. If even parity
is required, PARITY mode should be disabled (P3M bit 7 reset to 0), and
software must modify the data to include even parity.
Because the transmitter can be overwritten, the user is able to generate a
break signal. This is done by writing null characters to the transmitter
buffer (SIO Register [F0h]) at a rate that does not allow the stop bits to be
output. Each time the SIO Register is loaded, the divide-by-16 counter is
resynchronized and a new start bit is output followed by data.
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Transmitted Data
(No Parity)
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
Two Stop Bit
Transmitted Data
(With Parity)
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Seven Data Bits
Odd Parity
Two Stop Bit
Figure 113. Transmitter Data Formats
UART Reset Conditions
After a hardware reset, the SIO Register contents are undefined, and
Serial Mode and parity are disabled. Figures 114 and 115 show the binary
reset values of the SIO Register and its associated mode register P3M.
Register RF0h
Serial I/O Register (SIO)
(Read/Write)
U
U
U
U
U
U
U
U
Serial Data (D = LSB)
0
Figure 114. SIO Register Reset
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Register F7h
Port 3 Mode Register (P3M)
(Write-Only)
0
0
0
0
0
0
0
0
0 Port 2 Pull-Ups Open-Drain
1 Port 2 Pull-Ups Active
0 P32 = Input
P35 = Output
1 P32 = DAV0/RDY0 P35 = RDY0/DAV0
00 P33 = Input
01 P33 = Input
10 P33 = Input
P34 = Output
P34 = DM
P34 = DM
11 P33 = DAV1/RDY1 P34 = RDY1/DAV1
0 P31 = Input (T )
P36 = Output (T
)
IN
OUT
1 P32 = DAV2/RDY2 P36 = RDY2/DAV2
0 P30 = Input
1 P30 = Serial In
P37 = Output
P37 = Serial Out
0 Parity ON
1 Parity OFF
Figure 115. P3M Register Reset
Serial Peripheral Interface
Select Z8 microcontrollers incorporate a Serial Peripheral Interface (SPI)
for communication with other microcontrollers and peripherals. The SPI
includes features such as Stop-Mode Recovery, Master/Slave selection,
and Compare mode. Table 25 contains the pin configuration for the SPI
feature when it is enabled. The SPI consists of four registers: SPI Control
Register (SCON), SPI Compare Register (SCOMP), SPI Receive/Buffer
Register (RxBUF), and SPI Shift Register. SCON is located in bank (C)
of the Expanded Register File at address 02.
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Table 25. SPI Pin Configuration
Name
DI
Function
Data-In
Pin Location
P20
DO
SS
Data-Out
Slave Select
SPI Clock
P27
P35
SK
P34
The SPI Control Register (SCON; see Figure 116), is a read/write register
that controls Master/Slave selection, interrupts, clock source and phase
selection, and error flag. Bit 0 enables/disables the SPI with the default
being SPI disabled. A 1 in this location will enable the SPI, and a 0 will
disable the SPI. Bits 1 and 2 of the SCON register in Master Mode select
the clock rate. The user may choose whether internal clock is divide-by-2,
4, 8, or 16. In Slave Mode, Bit 1 of this register flags the user if an overrun
of the RxBUF Register has occurred. The RxCharOverrun flag is only
reset by writing a 0 to this bit. In slave mode, bit 2 of the Control Register
disables the data-out I/O function. If a 1 is written to this bit, the data-out
pin is released to its original port configuration. If a 0 is written to this bit,
the SPI shifts out one bit for each bit received. Bit 3 of the SCON Register
enables the compare feature of the SPI, with the default being disabled.
When the compare feature is enabled, a comparison of the value in the
SCOMP Register is made with the value in the RxBUF Register. Bit 4 sig-
nals that a receive character is available in the RxBUF Register.
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SCON (C) 02
D7 D6 D5 D4 D3 D2 D1 D0
SPI Enable
0 Disable *
1 Enable
RxCharOverrun (S)
0 Reset
1 Overrun
CLK Divide (M)
00 TCLK/2
01 TCLK/4
10 TCLK/8
11 TCLK/16
DO SPI Port Enable (S)
0 SPI DO Port Enable
1 Do Port to I/O
Compare Enable
0 Enable
1 Disable *
RxCharAvail
0 Reset
1 Char. Avail
Clock Phase
0 Trans/Fall
1 Trans/Rise
CLK Source
0 TCLK
1 Timer 0 Output
Master Slave
0 Slave
1 Master
(S) Used with Bit D7 equal to 0
(M) Used with Bit D7 equal to 1
* Default setting after Reset
Figure 116. SPI Control Register
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If the associated IRQ3 is enabled, an interrupt is generated. Bit 5 controls
the clock phase of the SPI. A 1 in bit 5 allows for receiving data on the
clock’s falling edge and transmitting data on the clock’s rising edge. A 0
allows receiving data on the clock’s rising edge and transmitting on the
clock’s falling edge. The SPI clock source is defined in bit 6. A 1 uses
Timer0 output for the SPI clock, and a 0 uses TCLK for clocking the SPI.
Finally, bit 7 determines whether the SPI is used as a Master or a Slave. A
1 puts the SPI into Master mode and a 0 puts the SPI into Slave mode.
SPI Operation
The SPI is used in one of two modes: either as system slave, or as system
master. Several of the possible system configurations are shown in
Figure 117. In slave mode, data transfer starts when the slave select (SS)
pin goes active. Data is transferred into the slave’s SPI Shift Register
through the DI pin, which has the same address as the RxBUF Register.
After a byte of data has been received by the SPI Shift Register, a Receive
Character Available (RCA/IRQ3) flag and interrupt is generated. The next
byte of data will be received at this time. The RxBUF Register must be
cleared, or a Receive Character Overrun (RxCharOverrun) flag will be set
in the SCON Register, and the data in the RxBUF Register will be over-
written. When the communication between the master and slave is com-
plete, the SS goes inactive.When the SPI is activated as a slave, it operates
in all system modes: STOP, HALT, and RUN.
Unless disconnected, for every bit that is transferred into the slave
through the DI pin, a bit is transferred out through the D0 pin on the oppo-
site clock edge. During slave operation, the SPI clock pin (SK) is an
input. In master mode, the CPU must first activate a SS through one of its
I/O ports. Next, data is transferred through the master’s D0 pin one bit per
master clock cycle. Loading data into the shift register initiates the trans-
fer. In master mode, the master’s clock will drive the slave’s clock. At the
conclusion of a transfer, a Receive Character Available (RCA/IRQ3) flag
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and interrupt is generated. Before data is transferred via the D0 pin, the
SPI Enable bit in the SCON Register must be enabled.
SPI Compare
When the SPI Compare Enable bit, D3 of the SCON Register is set to 1,
the SPI Compare feature is enabled. The compare feature is only valid for
slave mode. A compare transaction begins when the (SS) line goes active.
Data is received as if it were a normal transaction, but there is no data
transmitted to avoid bus contention with other slave devices. When the
compare byte is received, IRQ3 is not generated. Instead, the data is com-
pared with the contents of the SCOMP Register. If the data does not
match, DO remains inactive and the slave ignores all data until the (SS)
signal is reset. If the data received matches the data in the SCOMP regis-
ter, then a SMR signal is generated. DO is activated if it is not tri-stated by
D2 in the SCON Register, and data is received the same as any other SPI
slave transaction.
Slaves’ not comparing remain in their current mode, whereas slaves’
comparing wake from a STOP mode by means of an SMR
SPI Clock
The SPI clock maybe driven by three sources: Timer0, a division of the
internal system clock, or the external master when in slave mode. Bit D6
of the SCON Register controls what source drives the SPI clock. A 0 in bit
D6 of the SCON Register determines the division of the internal system
clock if this is used as the SPI clock source. Divide by 2, 4, 8, or 16 is
chosen as the scaler.
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Standard Serial Setup
ss
sk
Master
do
di
ss sk do di ss sk do di
ss sk do di ss sk do di
Slave
Slave
Slave
Slave
Standard Parallel Setup
ss1
ss2
ss3
ss4
Master
sk
do
di
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
Setup For Compare
ss
sk
Master
do
di
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
(1)
(2)
(255)
(256)
Up to 256 slaves per SS line
Three Wire Compare Setup
ss
sk
do
di
Master
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
ss sk do di
Slave
Multiple slaves may have the same address
Figure 117. SPI System Configuration
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Receive Character Available and Overrun
When a complete data stream is received, an interrupt is generated and the
RxCharAvail bit in the SCON Register is set. Bit 4 in the SCON Register
is for enabling or disabling the RxCharAvail interrupt. The RxCharAvail
bit is available for interrupt polling purposes and is reset when the
RxBUF Register is read. RxCharAvail is generated in both master and
slave modes. While in slave mode, if the RxBUF is not read before the
next data stream is received and loaded into the RxBUF Register, Receive
Character Overrun (RxCharOverrun) occurs. Because there is no require-
ment for clock control in slave mode, bit D1 in the SPI Control Register is
used to log any RxCharOverrun (see Figures 118 and 119).
TSK
SK
3
SS
2
4
D0
DI
1
5
Figure 118. SPI Timing
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SK
D0
Port
Control
DI
SPI Compare Register (SCOMP)
SPI Shift Register
Bit Control
/Interrupt
Control
SS
SMR
SPI Receive Buffer (RxBUF)
SPI Control
SPI
Clock
IRQ
SCLK + n
TCLK
3
Figure 119. SPI Logic
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OPEN-DRAIN
P20 OE
SPI EN
P20
PIN
P20 IN
or
SPI DI
Autolatch
R ≈ 500 KΩ
OPEN-DRAIN
Standard
P27 OUT
SPI
P27
PIN
SPI DO
Standard
P27 OE
SPI
SPI Active
SCON
0 SOI D0 Enable
D2
1 P27 OUT
*SPI must be enabled with D0
P27 IN
Autolatch
R ≈ 500 KΩ
Figure 120. SPI Data In/Out Configuration
Serial Input/Output
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SK IN
SPI EN
SPI MSTR
P34
PIN
SPI EN
SK OUT
P34 OUT
P31
MUX
+
-
SS
REF
SPI EN
SPI MSTR
P35
PIN
P35 OUT
P32
+
-
REF
PCON
0 P34, P35 Standard Output
1 P34, P35 Comparator Output
D0
Figure 121. SPI Clock/SPI Slave Select Output Configuration
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Serial Input/Output
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External Interface
Introduction
®
The Z8 CPU can be a microcontroller with 20 pins for external memory
®
interfacing. The external memory interface on the Z8 CPU is generally
for either RAM or ROM; this features is only available for devices featur-
ing Port 0, Port 1, R/W, DM, AS, and DS. Please refer to specific product
specifications for availability of these features.
®
The Z8 CPU offers a multiplexed external memory interface. In multi-
plexed mode, eight pins from Port 1 form an Address/Data Bus (AD7–
AD0), eight pins from Port 0 form a High Address Bus (A15–A8). Three
additional pins provide the Address Strobe, Data Strobe, and the Read/
®
Write Signal. Figure 122 shows the Z8 CPU external interface pins.
(Port 1) AD7–AD0
(Port 0) AD15–AD8
External
Program/Data
64KB
Each
AS
Z8 CPU
DS
R/W
DM
®
Figure 122. Z8 CPU External Interface Pins
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Pin Descriptions
®
The following sections briefly describe the pins associated with the Z8
CPU external memory interface.
Address Strobe (output, active Low). Address Strobe (AS) is pulsed
Low once at the beginning of each machine cycle. The rising edge of AS
indicates the address, Read/Write (R/W), and data memory (DM) signals
®
are valid for program or data memory transfers. In some cases, the Z8
CPU address strobe is pulsed low regardless of accessing external or
internal memory. Please refer to specific product specifications for AS
operation.
Data Strobe (Output, Active Low). Data Strobe (DS) provides the tim-
ing for data movement to or from the Address/Data bus for each external
memory transfer. During a Write Cycle, data out is valid at the leading
edge of the DS. During a Read Cycle, data in must be valid prior to the
trailing edge of the DS.
Read/Write (Output). Read/Write (R/W) determines the direction of
data transfer for memory transactions. R/W is Low when writing to pro-
gram or data memory, and High for all other transactions.
Data Memory (Output). Data memory (DM) provides a signal to sepa-
rate external program memory from external data memory. It is a pro-
grammable function on pin P34. Data memory is active low for external
data memory accesses and high for external program memory accesses.
High Address Lines A15–A8. A15–A8 provide the High Address lines
for the memory interface. The Port 0–1 mode registers must have bits D7
and D1 set equal to 1 to configure Port 0 as A15–A8. Outputs can be
CMOS- or TTL-compatible. Please refer to product specifications for
actual type. See Figure 123.
Address/Data Lines AD7–AD0. AD7–AD0 is a multiplexed Address/
Data memory interface. The lower eight Address lines (A7–A0) are multi-
plexed with Data lines (D7–D0). Port 0–1 mode registers must have bits
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D4 set equal to 1 and D3 set equal to 0 to configure Port 1 as AD7–AD0.
Inputs and outputs are TTL-compatible. See Figure 123.
®
Reset. RESET (input, active Low) initializes the Z8 CPU. When
RESET is deactivated, program execution begins from program location
000Ch. If held Low, RESET acts as a register file protect during power-
down and power-up sequences. To avoid asynchronous and noisy reset
®
problems, the Z8 CPU is equipped with a reset filter of four external
clocks (4T C). If the external RESET signal is less than 4T C in duration,
P
P
no reset will occur. On the fifth clock after the RESET is detected, an
internal reset signal is latched and held for an internal register count of 18
or more external clocks, or for the duration of the external RESET, which-
ever is longer. Please refer to specific product specifications for length of
reset delay time.
Crystal1, Crystal2 (Oscillator Input and Output). These pins connect
a parallel-resonant crystal, ceramic resonator, LC, RC network, or exter-
nal single-phase clock to the on-chip oscillator input. Please refer to the
device product specifications for information on availability of RC oscil-
lator features.
External Addressing Configuration
The minimum bus configuration uses Port 1 as a multiplexed address/data
port (AD7–AD0), allowing access to 256 bytes of external memory. In
this configuration, the eight low-order bits (A0–A7) are multiplexed with
the data (D7–D0).
Port 0 can be programmed to provide either four additional address lines
(A11–A8), which increases the addressable memory to 4KB, or eight
additional address lines (A15–A8), which increases the addressable exter-
nal memory up to 64KB. It is required to add a NOP after configuring
Port 0/Port 1 for external addressing before jumping to external memory
execution.
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Register F8h (P01M)
Port 0–1 Mode Register (P01M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
P00–P07 Mode
00 = Output
01 = Input
1X = A8–A11
P10–P17 Mode
00 = Byte Output
01 = Byte Output
10 = AD0-AD7
11 = High Impedance AD0–AD7,
A8–A15, AS, DS, R/W
P04–P07 Mode
00 = Output
01 = Input
1X = A12–A15
Figure 123. External Address Configuration
External Stacks
®
®
The Z8 CPU architecture supports stack operations in either the Z8
Standard Register File or external data memory. A stack’s location is
determined by bit 2 in the Port 0–1 Mode Register (F8h). If bit 2 is set to
0, the stack is in external data memory (see Figure 124).
The instruction used to change the stack selection bit should not be imme-
diately followed by the instructions RET or IRET, because this will cause
indeterminate program flow. After a RESET, the internal stack is selected.
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Please note that if Port 0 is configured as A15–A8 and the stack is
selected as internal, any stack operation will cause the contents in register
FEhto be displayed on Port 0.
Register F8h (P01M)
Port 0–1 Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Z8 Stack Selection
0 = External
1 = Internal
Figure 124. Z8 Stack Selection
Data Memory
The two Z8 external memory spaces, data and program, are addressed as
two separate spaces of up to 64KB each. External program memory and
external data memory are logically selected by the data memory select
output (DM). DM is made available on Port 3, bit 4 (P34) by setting bit 4
and bit 3 in the Port 3 Mode Register (F7h) to 10 or 01 (see Figure 125).
DM is active Low during the execution of the LDE, LDEI instructions,
and High for the execution of program instructions. DM is also active
Low during the execution of CALL, POP, PUSH, RET and IRET instruc-
tions if the stack resides in external data memory. After a RESET, DM is
not selected.
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Register F7h (P3M)
Port 3 Mode Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Bits
Configuration
00 P33 = Input
01 P33 = Input
10 P33 = Input
P34 = Output
P34 = DM
P34 = DM
11 P33 = DAV1/RDY1 P34 = RDY1/DAV1
Figure 125. Port 3 Data Memory Operation
Bus Operation
®
Typical data transfers between the Z8 CPU and external memory are
illustrated in Figures 126 and 127. Machine cycles can vary from six to 12
clock periods depending on the operation being performed. The notations
®
used to describe the basic timing periods of the Z8 CPU are machine
cycles (Mn), timing states (Tn), and clock periods. All timing references
are made with respect to the output signals AS and DS. The clock is
shown for clarity only and does not have a specific timing relationship
with other signals.
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Machine Cycle
T2*
T3
T1
Clock
A15-A8
A8-A15
D7–D0 IN
AD7–AD0
A7–A0
AS
DS
R/W
DM
Read Cycle
*Port inputs are strobed during T2, which is two internal systems clocks
before the execution cycle of the current instruction.
Figure 126. External Instruction Fetch or Memory Read Cycle
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Machine Cycle
T2
T3
T1
Clock
A15-A8
A8-A15
D7–D0 OUT
AD7–AD0
A7–A0
AS
DS
R/W
DM
Write Cycle
Figure 127. External Memory Write Cycle
Address Strobe
All transactions start with AS driven Low and then raised High by the
®
Z8 CPU. The rising edge of AS indicates that R/W, DM (if used), and
the address outputs are valid. The address outputs (AD7–AD0), remain
valid only during MnT1 and typically must be latched using AS. Address
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outputs (A15–A8) remain stable throughout the machine cycle, regardless
of the addressing mode.
Data Strobe
®
The Z8 CPU uses DS to time the actual data transfer. For Write opera-
tions (R/W = Low), a Low on DS indicates that valid data is on the AD7–
AD0 lines. For Read operations (R/W = High), the bus is placed in a high-
impedance state before driving DS Low, so the addressed device can put
®
its data on the bus. The Z8 CPU samples this data prior to raising DS
High.
Extended Bus Timing
Some products can accommodate slow memory access time by automati-
cally inserting an additional software controlled state time (Tx). This
stretches the DS timing by two clock periods. Figures 128 and 129 illus-
trate extended external memory Read and Write cycles.
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Machine Cycle
T2*
T1
T3
TX
Clock
A15-A8
A15-A8
D7–D0 IN
AD7–AD0
A7–A0
AS
DS
R/W
DM
Read Cycle
*Port inputs are strobed during T2, which is two internal system clocks
before the execution of the current instruction.
Figure 128. Extended External Instruction Fetch or Memory Read Cycle
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Machine Cycle
T1
T3
T2
TX
Clock
A15-A8
A15–A8
AD7–AD0
A7–A0
D7–D0 OUT
AS
DS
R/W
DM
Write Cycle
Figure 129. Extended External Memory Write Cycle
Timing is extended by setting bit D5 in the Port 0–1 Mode Register (F8h)
to 1 (see Figure 130). After a RESET, this bit is set to 0.
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Register F8h (P01M)
Port 0–1 Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
External Memory Timing
0 = Normal
1 = Extended
Figure 130. Extended Bus Timing
Instruction Timing
®
The High throughput of the Z8 CPU is due, in part, to the use of an
instruction pipeline, in which the instruction fetch and execution cycles
are overlapped. During the execution of the current instruction, the
opcode of the next instruction is fetched. Instruction pipelining is illus-
trated in Figure 131.
Figures 131 and 132 show typical instruction cycle timing for instructions
fetched from memory. For those instructions that require execution time
longer than that of the overlapped fetch, or reference program or data
memory as part of their execution, the pipe must be flushed.
Figures 131 and 132 assume the XTAL ÷ 2 clock mode is selected.
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M1
T2
M3
T2
M2
T2
T1
T3
T3
T1
T1
T3
Clock
A15–A8
A15–A8
A15–A8
A7–A0
A7–A0
A7–A0
A7–A0
A7–A0
AS
DS
R/W
Fetch 1st Byte
Fetch 1st Byte Of Next Instruction
* Port inputs are strobed during T2, which is two internal system clocks
before the execution cycle of the current installation
Figure 131. Instruction Cycle Timing (1-Byte Instructions)
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M1
M3
T2
M2
T2
T1
T3
T3
T1
T1
T2
T3
Clock
A15–A8
A15–A8
A15–A8
A15–A8
A7–A0
A7–A0
A7–A0
A7–A0
A7–A0
A7–A0
A7–A0
AS
DS
R/W
Fetch 2nd Byte
Fetch 3rd Byte
Fetch 1st Byte
(3-Byte Instruction)
Fetch 1st Byte (1- or 2-Byte Instruction)
*Port inputs are strobed during T2, which is two internal system clocks before
the execution cycle of the current instruction.
Figure 132. Instruction Cycle Timing (2- and 3-Byte Instructions)
Z8 Reset Conditions
After a hardware reset, extended timing is set to accommodate slow mem-
ory access during the configuration routine, DM is inactive, the stack
resides in the register file. Port 0, 1, and 2 are reset to input mode. Port 2
is set to Open-Drain Mode.
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Instruction Set
Z8 instructions can be divided functionally into the following eight
groups:
•
•
•
•
•
•
•
•
Load
Bit Manipulation
Arithmetic
Block Transfer
Logical
Rotate and Shift
Program Control
CPU Control
The following summary shows the instructions belonging to each group
and the number of operands required for each. The source operand is src,
the destination operand is dst, and a condition code is cc.
Table 26. Load Instructions
Mnemonic
CLR
Operands
dst
Instruction
Clear
LD
dst, src
dst, src
dst, src
dst
Load
LDC
Load Constant
Load External
Pop
LDE
POP
PUSH
src
Push
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Table 27. Arithmetic Instructions
Mnemonic
ADC
Operands
dst, src
dst, src
dst, src
dst
Instruction
Add with Carry
Add
ADD
CP
Compare
DA
Decimal Adjust
Decrement
DEC
dst
DECW
INC
dst
Decrement Word
Increment
dst
INCW
SBC
dst
Increment Word
Subtract with Carry
Subtract
dst, src
dst, src
SUB
Table 28. Logical Instructions
Mnemonic
AND
Operands
dst, src
dst
Instruction
Logical AND
COM
Complement
Logical OR
OR
dst, src
dst, src
XOR
Logical Exclusive OR
Table 29. Program Control Instructions
Mnemonic
CALL
Operands
dst
Instruction
Call Procedure
DJNZ
dst, src
Decrement and Jump Non-Zero
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Table 29. Program Control Instructions (Continued)
Mnemonic
IRET
JP
Operands
Instruction
Interrupt Return
Jump
cc, dst
cc, dst
JR
Jump Relative
Return
RET
Table 30. Bit Manipulation Instructions
Mnemonic
TCM
Operands
dst, src
dst, src
dst, src
dst, src
dst, src
Instruction
Test Complement Under Mask
Test Under Mask
Bit Clear
TM
AND
OR
Bit Set
XOR
Bit Complement
Table 31. Block Transfer Instructions
Mnemonic
LDCI
Operands
dst, src
Instruction
Load Constant Auto Increment
Load External Auto Increment
LDEI
dst, src
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Table 32. Rotate and Shift Instructions
Mnemonic
RL
Operands
dst
Instruction
Rotate Left
RLC
dst
Rotate Left Through Carry
Rotate Right
RR
dst
RRC
dst
Rotate Right Through Carry
Shift Right Arithmetic
Swap Nibbles
SRA
dst
SWAP
dst
Table 33. CPU Control Instructions
Mnemonic
CCF
DI
Operands
Instruction
Complement Carry Flag
Disable Interrupts
Enable Interrupts
Halt
EI
HALT
NOP
RCF
SCF
No Operation
Reset Carry Flag
Set Carry Flag
SRP
STOP
WDh
WDT
src
Set Register Pointer
Stop
WDT Enable During HALT
WDT Enable or Refresh
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Processor Flags
®
The Flag Register (FCh) informs the user of the current status of the Z8
CPU. The flags and their bit positions in the Flag Register are shown in
Figure 133.
®
The Z8 Flag Register contains six bits of status information which are
set or cleared by CPU operations. Four of the bits (C, V, Z and S) can be
tested for use with conditional Jump instructions. Two flags (H and D)
cannot be tested and are used for BCD arithmetic. The two remaining bits
in the Flag Register (F1 and F2) are available to the user, but they must be
set or cleared by instructions and are not usable with conditional Jumps.
As with bits in the other control registers, the Flag Register bits can be set
or reset by instructions; however, only those instructions that do not affect
the flags as an outcome of the execution should be used (Load Immedi-
ate).
Note: The Watch–Dog Timer (WDT) instruction affects the Flags accordingly: Z
= 1, S = 0, V = 0.
Register FCh (Flags)
Flag Register (Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
User Flag (F1)
User Flag (F2)
Half Carry Flag (H)
Decimal Adjust Flag (D)
Overflow Flag (V)
Sign Flag (S)
Zero Flag (Z)
Carry Flag (C)
Figure 133. Z8 Flag Register
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Carry Flag
The Carry Flag (C) is set to 1 whenever the result of an arithmetic opera-
tion generates a carry or a borrow the high order bit 7. Otherwise, the
Carry Flag is cleared to 0.
Following Rotate and Shift instructions, the Carry Flag contains the last
value shifted out of the specified register.
An instruction can set, reset, or complement the Carry Flag.
IRET may change the value of the Carry Flag when the Flag Register,
saved in the Stack, is restored.
Zero Flag
For arithmetic and logical operations, the Zero Flag (Z) is set to 1 if the
result is zero. Otherwise, the Zero Flag is cleared to 0.
If the result of testing bits in a register is 00h, the Zero Flag is set to 1.
Otherwise the Zero Flag is cleared to 0.
If the result of a Rotate or Shift operation is 00h, the Zero Flag is set to 1.
Otherwise, the Zero Flag is cleared to 0.
IRET changes the value of the Zero Flag when the Flag Register saved in
the Stack is restored. The WDT Instruction sets the Zero Flag to a 1.
Sign Flag
The Sign Flag (S) stores the value of the most significant bit of a result
following an arithmetic, logical, Rotate, or Shift operation.
When performing arithmetic operations on signed numbers, binary two’s-
complement notation is used to represent and process information. A pos-
itive number is identified by a 0 in the most significant bit position (bit 7);
therefore, the Sign Flag is also 0.
A negative number is identified by a 1 in the most significant bit position
(bit 7); therefore, the Sign Flag is also 1.
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IRET changes the value of the Sign Flag when the Flag Register saved in
the Stack is restored.
Overflow Flag
For signed arithmetic, Rotate, and Shift operations, the Overflow Flag (V)
is set to 1 when the result is greater than the maximum possible number
(> 127) or less than the minimum possible number (< –128) that can be
represented in two’s-complement form. The Overflow Flag is set to 0 if no
overflow occurs.
Following logical operations the Overflow Flag is set to 0.
IRET changes the value of the Overflow Flag when the Flag Register
saved in the Stack is restored.
Decimal Adjust Flag
The Decimal Adjust Flag (D) is used for BCD arithmetic. Because the
algorithm for correcting BCD operations is different for addition and sub-
traction, this flag specifies what type of instruction was last executed so
that the subsequent Decimal Adjust (DA) operation can function properly.
Normally, the Decimal Adjust Flag cannot be used as a test condition.
After a subtraction, the Decimal Adjust Flag is set to 1. Following an
addition it is cleared to 0.
IRET changes the value of the Decimal Adjust Flag when the Flag Regis-
ter saved in the Stack is restored.
Half Carry Flag
The Half Carry Flag (H) is set to 1 whenever an addition generates a carry
bit 3 (Overflow) or a subtraction generates a borrow bit 3. The Half Carry
Flag is used by the Decimal Adjust (DA) instruction to convert the binary
result of a previous addition or subtraction into the correct decimal (BCD)
result. As in the case of the Decimal Adjust Flag, the user does not nor-
mally access this flag.
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IRET changes the value of the Half Carry Flag when the Flag Register
saved in the Stack is restored.
Condition Codes
The C, Z, S, and V Flags control the operation of the ‘Conditional’ Jump
instructions. Sixteen frequently useful functions of the flag settings are
encoded in a 4-bit field called the condition code (cc), which forms bits 4-
7 of the conditional instructions.
Table 34. Z8 Flag Definitions
Flag
C
Description
Carry Flag
Z
Zero Flag
S
Sign Flag
V
Overflow Flag
Decimal Adjust Flag
Half Carry Flag
D
H
Condition codes and flag settings are summarized in Tables 34 through
36. Notation for the flags and how they are affected are as follows:
Table 35. Flag Settings Definitions
Symbol Definition
0
1
*
Cleared to 0
Set to 1
Set or cleared according to operation
Unaffected
–
X
Undefined
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Table 36. Condition Codes
Binary
0000
1000
0111
1111
Hex
0
Mnemonic
Definition
Always False
Always True
Carry
Flag Settings
F
—
8
(blank)
C
—
7
C = 1
F
6
NC
Z
No Carry
C = 0
0110
1110
1101
0101
0100
1100
0110
1110
1001
0001
1010
0010
1111
Zero
Z = 1
E
D
5
NZ
PL
Non-Zero
Plus
Z = 0
S = 0
Ml
Minus
S = 1
4
OV
NOV
EQ
NE
GE
LT
Overflow
V = 1
C
6
No Overflow
Equal
V = 0
Z = 1
E
9
Not Equal
Greater Than or Equal
Less Than
Greater Than
Less Than or Equal
Z = 0
(S XOR V) = 0
(S XOR V) = 1
(Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1
C = 0
1
A
2
GT
LE
F
UGE
Unsigned Greater Than
or Equal
0111
1011
0011
7
B
3
ULT
UGT
ULE
Unsigned Less Than
C = 1
Unsigned Greater Than
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
Unsigned Less Than or
Equal
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Notation and Binary Encoding
In the detailed instruction descriptions that make up the rest of this chap-
ter, operands and status flags are represented by a notational shorthand.
Operands, condition codes, address modes, and their notations are as fol-
lows (Table 37).
Table 37. Notational Shorthand
Notation
Address Mode
Condition Code
Working Register
Register
Operand
Range *
cc
r
See condition codes
n = 0–15
Rn
R
Reg
Reg. represents a number in the
range of 00h to FFh
or
Working Register
Rn
n = 0–15
RR
Register Pair
Reg
Reg. represents an even number
in the range of 00h to FEh
or
Working Register Pair
RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14
n = 0 –15
Ir
Indirect Working Register @Rn
IR
Indirect Register
@Reg
Reg. represents a number in the
range of 00h to FFh
or
Indirect Working Register @Rn
n = 0– 15
Irr
Indirect Working Register @RRp
Pair
p = 0, 2, 4, 6, 8, 10, 12, or 14
IRR
Indirect Register Pair
@Reg
Reg. represents an even number
in the range 00h to FFh
*Note: *See the device product specification to determine the exact register file range available. The register file size varies by
the device type.
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Table 37. Notational Shorthand
Notation
Address Mode
or
Operand
Range *
Working Register Pair
Indexed
@RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14
X
Reg (Rn)
Reg. represents a number in the
range of 00h to FFh and n = 0–15
DA
RA
Direct Address
Addrs
Addrs
Addrs. represents a number in the
range of 00h to FFh
Relative Address
Addrs. represents a number in the
range of +127 to –128 which is an
offset relative to the address of
the next instruction
IM
Immediate
#Data
Data is a number between 00h to
FFh
*Note: *See the device product specification to determine the exact register file range available. The register file size varies by
the device type.
Additional symbols used are listed in Table 38.
Table 38. Additional Symbols
Symbol
dst
Definition
Destination Operand
Source Operand
Indirect Address Prefix
Stack Pointer
src
@
SP
PC
Program Counter
Flag Register (FCh)
Register Pointer (FDh)
FLAGS
RP
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Table 38. Additional Symbols
Symbol
Definition
IMR
#
Interrupt Mask Register (FBh)
Immediate Operand Prefix
Hexadecimal Number Prefix
Hexadecimal Number Suffix
Binary Number Suffix
Opcode
%
H
B
OPC
Assignment of a value is indicated by the symbol “←”. For example,
dst ← dst + src
indicates the source data is added to the destination data and the result is
stored in the destination location.
The notation 'addr(n)' is used to refer to bit'n' of a given location. For
example,
dst (7)
refers to bit 7 of the destination operand.
Assembly Language Syntax
For proper instruction execution, Z8 assembly language syntax requires
‘dst, src’be specified, in that order. The following instruction descriptions
show the format of the object code produced by the assembler. This
binary format should be followed by users who prefer manual program
coding or who intend to implement their own assembler.
Example: If the contents of registers 43hand 08hare added and the
result is stored in 43h, the assembly syntax and resulting object code is:
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ASM:
OBJ:
ADD
04
43h,
08
08h
43
(ADD dst, src)
(OPC src, dst)
In general, whenever an instruction format requires an 8-bit register
address, that address can specify any register location in the range 0–255
or a Working Register R0–R15. If, in the above example, register 08his a
Working Register, the assembly syntax and resulting object code would
be:
ASM:
OBJ:
ADD
04
43h,
08
08h
43
(ADD dst, src)
(OPC src, dst)
See the device product specification to determine the exact register file
range available. The register file size varies by device type.
Z8 Instruction Summary
Table 39. Summary of Z8 Instruction Set
Address
Mode
Op Code
Byte
Flags Affected
Instruction and
Operation
dst src
(Hex)
C
Z
S
V
D
H
ADC dst, src
†
1[ ]
[
[
[
[
0
[
dst ← dst + src +C
ADD dst, src
dst ← dst + src
†
†
0[ ]
5[ ]
[
[
[
[
[
[
0
–
[
AND dst, src
–
0
–
dst ← dst AND src
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
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Table 39. Summary of Z8 Instruction Set
Address
Mode
Op Code
Byte
(Hex)
Flags Affected
Instruction and
Operation
dst src
DA
C
Z
S
V
D
H
CALL dst
D6
D4
–
–
–
–
–
–
SP ← SP–2
IRR
and PC ← dst
or @ SP ← PC
CCF
C ←NOT C
EF
[
–
–
–
–
–
–
–
–
–
–
CLR dst
R
IR
R
B0
B1
60
–
dst ← 0
COM dst
–
[
[
0
–
–
dst ← NOT dst
IR
†
61
CP dst, src
dst − src
A[ ]
[
[
[
[
[
[
[
–
–
–
–
DA dst
R
IR
40
41
00
01
80
81
8 F
X
dst ← DA dst
DEC dst
R
–
–
–
[
[
[
[
[
[
–
–
–
–
–
–
dst ← dst–1
DECW dst
dst ← dst–1
IR
R R
IR
DI dst
–
–
–
IMR(7) ← 0
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
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Table 39. Summary of Z8 Instruction Set
Address
Op Code
Byte
Mode
Flags Affected
Instruction and
Operation
dst src
(Hex)
C
Z
S
V
D
H
DJNZr, dst
RA
rA
–
–
–
–
–
–
r ← r–1
r = 0-F
if r ≠ 0
PC ← PC + dst
Range:+127, –128
EI
9 F
–
–
–
–
–
–
IMR(7) ← 1
HALT
7 F
rE
–
–
–
[
–
[
–
[
–
–
–
–
INC dst
r
dst ← dst + 1
r = 0-F
20
R
IR
21
INCW dst
RR
IR
A0
–
[
[
[
–
–
dst ← dst + 1
A1
Address
Mode
Instruction
and Operation
Op Code
Byte
Flags Affected
dst
src
(Hex)
C
Z
S
V
D
H
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
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Table 39. Summary of Z8 Instruction Set
Address
Mode
Op Code
Byte
(Hex)
Flags Affected
Instruction and
Operation
dst src
C
Z
S
V
D
H
IRET
B F
[
[
[
[
[
[
FLAGS←@SP;
SP ← SP + 1
PC ← @SP;
SP ← SP + 2;
and IMR(7)–1
JP cc, dst
DA
cD
c = 0–F
30
–
–
–
–
–
–
–
–
–
–
–
–
if cc is true,
then PC ← dst
JR cc, dst
IRR
RA
cB
if cc is true,
c = 0–F
PC ← PC + dst
Range: +127, –128
LD dst, src
r
Im
r C
–
–
–
–
–
–
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
Instruction Set
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Table 39. Summary of Z8 Instruction Set
Address
Op Code
Byte
Mode
Flags Affected
Instruction and
Operation
dst src
(Hex)
C
Z
S
V
D
H
dst ← src
r
R
r
r 8
r 9
R
r = 0–F
C 7
D 7
E 3
F 3
r
X
r
X
r
Ir
Ir
r
R
R
R
IR
IR
r
R
IR
IM
IM
R
Irr
r
E 4
E 5
E 6
E 7
F 5
LDC dst, src
dst ← src
C 2
D 2
C 3
D 3
–
–
–
–
–
–
–
–
–
–
–
–
lrr
Ir
LDCI dst, src
Irr
Ir
dst ← src
r ← r + 1 or
rr ←rr + 1
lrr
LDE dst, src
r
Irr
82
–
–
–
–
–
–
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
UM001602-0904
Instruction Set
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User Manual
218
Table 39. Summary of Z8 Instruction Set
Address
Mode
Op Code
Byte
(Hex)
Flags Affected
Instruction and
Operation
dst src
C
Z
S
V
D
H
dst ← src
lrr
Ir
r
92
83
93
LDEI dst, src
Irr
Ir
–
–
–
–
–
–
dst ← src and
r ← r + 1 or
rr ←rr + 1
lrr
NOP
FF
–
–
–
[
–
[
–
0
–
–
–
–
OR dst, src
†
4[ ]
dst ← dst OR src
POP dst
R
50
51
–
–
–
–
–
–
–
–
–
–
–
–
dst ← @SP
and SP ← SP + 1
IR
PUSH src
R
70
71
SP ← SP–1
IR
and @SP ← src
RCF
C ← 0
C F
A F
0
–
–
–
–
–
–
–
–
–
–
–
RET
PC ← @SP;
SP ← SP + 2
RL dst
R
IR
90
91
[
[
[
[
–
–
7
0
C
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
Instruction Set
UM001602-0904
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Table 39. Summary of Z8 Instruction Set
Address
Op Code
Byte
Mode
Flags Affected
Instruction and
Operation
dst src
(Hex)
C
Z
S
V
D
H
RLC dst
R
IR
10
11
[
[
[
[
–
–
7
0
C
RR dst
R
IR
E 0
E 1
[
[
[
[
[
[
[
[
–
–
–
–
7
0
C
RRC dst
R
C 0
C 1
IR
7
0
C
SBC dst, src
dst ← dst–src–C
†
3[ ]
[
1
[
[
–
[
[
–
[
[
1
–
–
[
SCF
C ← 1
D F
–
0
–
–
SRA dst
R
D 0
D 1
7
0
IR
C
SRP dst
Im
31
–
–
–
–
–
–
RP ← src
STOP
6 F
2[ ]
–
[
–
[
–
[
–
[
–
1
–
[
SUB dst, src
dst ← dst–src
†
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
UM001602-0904
Instruction Set
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User Manual
220
Table 39. Summary of Z8 Instruction Set
Address
Mode
Op Code
Byte
(Hex)
Flags Affected
Instruction and
Operation
dst src
C
Z
S
V
D
H
SWAP dst
R
IR
F0
F1
X
[
[
X
–
–
7
4 3
0
TCM dst, src
(NOT dst) AND src
†
†
6[ ]
7[ ]
–
–
[
[
[
[
0
0
–
–
–
–
TM dst, src
dst AND src
WDh
4 F
5 F
7[ ]
–
–
–
X
X
[
X
X
[
X
X
0
–
–
–
–
–
–
WDT
XOR dst, src
dst AND src
XOR src
†
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
Instruction Set
UM001602-0904
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221
®
Table 40. Summary of Z8 Address Modes
Address Mode
Lower
dst
src
Op Code Nibble
r
r
[2]
[3]
[4]
[5]
[6]
[7]
r
Ir
R
R
R
IR
R
IR
IM
IM
UM001602-0904
Instruction Set
Z8 Family of Microcontrollers
User Manual
222
Op Code Map
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
6.5
DEC
6.5
DEC
6.5
ADD
6.5
ADD
10.5
ADD
10.5
ADD
10.5
ADD
10.5
ADD
6.5
LD
6.5
LD
12/10.5 12/10.0 6.5
DJNZ JR LD
12.10.0
JP
6.5
INC
0
1
R1
6.5
RLC
IR1
6.5
RLC
r1, r2
6.5
ADC
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM r1, R2 r2, R1 r1, RA cc, RA r1, IM cc, DA
6.5
ADC
r1
10.5
ADC
10.5
ADC
10.5
ADC
10.5
ADC
R1
6.5
INC
IR1
6.5
INC
r1, r2
6.5
SUB
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
10.5
10.5
10.5
10.5
2
SUB
SUB
SUB
SUB
SUB
R1
8.0
JP
IR1
6.1
SRP
r1, r2
6.5
SBC
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
10.5
10.5
10.5
10.5
3
SBC
SBC
SBC
SBC
SBC
IRR1
8.5
DA
IM
r1, r2
6.5
OR
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
8.5
DA
IR1
6.5
10.5
10.5
10.5
10.5
6.0
WDh
4
OR
OR
OR
OR
OR
R1
r1, r2
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
10.5
POP
10.5
POP
6.5
AND
6.5
AND
10.5
AND
10.5
AND
10.5
AND
10.5
AND
6.0
WDT
5
R1
6.5
IR1
6.5
r1, r2
6.5
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
10.5
10.5
10.5
10.5
6.0
6
COM
COM
TCM
TCM
TCM
TCM
TCM
TCM
STOP
R1
IR1
r1, r2
6.5
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
10/12.1 12/14.1
6.5
10.5
10.5
10.5
10.5
7.0
7
PUSH PUSH
TM
TM
TM
TM
TM
TM
HALT
R2
IR2
r1, r2
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
10.5
DECW DECW
10.5
6.1
DI
12.0
LDE
18.0
LDEI
8
r1, lrr2 lr1, lrr2
RR1
6.5
RL
IR1
6.5
RL
6.1
12.0
LDE
18.0
LDEI
9
EI
R1
IR1
r2, lrr1
lr2, lrr1
10.5
INCW INCW
10.5
6.5
CP
6.5
CP
10.5
CP
10.5
CP
10.5
CP
10.5
CP
14.0
RET
A
B
C
D
E
F
RR1
6.5
CLR
IR1
6.5
CLR
r1, r2
6.5
XOR
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
XOR
10.5
XOR
10.5
XOR
10.5
XOR
10.5
XOR
16.0
IRET
R1
6.5
RRC
IR1
6.5
RRC
r1, r2
12.0
LDC
r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM
18.0
LDCI
10.5
LD
6.5
RCF
Ir1, Irr2
R1
6.5
SRA
IR1
6.5
SRA
r1, Irr2
r1,x,R2
10.5
LD
20.0
CALL*
20.0
CALL
6.5
SCF
12.0
LDC
lrr1, r2
18.0
LDCI
lrr1, Ir2
6.5
LD
R1
6.5
RR
R1
8.5
IR1
6.5
RR
IR1
8.5
IRR1
10.5
LD
DA
10.5
LD
r2,x,R1
10.5
LD
10.5
LD
6.5
CCF
r1, IR2 R2, R1 IR2, R1 R1, IM IR1, IM
6.5
LD
10.5
LD
6.0
NOP
SWAP SWAP
Ir1, r2
R2, IR1
R1
IR1
2
3
2
3
1
Bytes per Instruction
Legend:
R = 8-Bit Addr ess
r = 4-Bit Addr ess
Lower
Op Code
Nibble
R1 or r1 = Dst Address
R2 or r2 = Src Address
Fetch
Cycles
Pipeline
Cycles
4
Sequence:
Upper
Op Code
Nibble
10.5
CP
R2, R1
Opcode, First Operand,
Second Operand
A
Mnemonic
Note: Blank areas are reserved.
First
Operand
Second
Operand
*2-byte instruction appears as
a 3-byte instruction
Figure 134. Op Code Map
Instruction Set
UM001602-0904
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User Manual
223
Instruction Description
Table 41 contains a brief description of each of the ZTP process manipu-
lation functions. Use the hyperlinks in Table 41 to jump quickly to more
complete descriptions.
Table 41. Process Manipulation Functions
Add
Logical OR
Logical Exclusive OR
Pop
Add With Carry
Call Procedure
Complement Carry Flag
Clear
Push
Reset Carry Flag
Return
Complement
Compare
Rotate Left
Decimal Adjust
Decrement
Rotate Left Through Carry
Rotate Right
Decrement and Jump if Non-Zero
Decrement Word
Disable Interrupts
Enable Interrupts
Halt
Rotate Right Through Carry
Set Carry Flag
Set Register Pointer
Shift Right Arithmetic
Rotate Right Through Carry
Set Carry Flag
Increment
Increment Word
Interrupt Return
Jump
Set Register Pointer
Shift Right Arithmetic
Stop
Jump Relative
Load
Subtract
Subtract With Carry
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
224
Table 41. Process Manipulation Functions (Continued)
Load Constant
Swap Nibbles
Load Constant Autoincrement
Load External Data
Load External Data Autoincrement
No Operation
Test Complement Under Mask
Test Under Mask
Watch-Dog Timer
Watch-Dog Timer Enable During Halt Mode
Logical AND
Instruction Description
UM001602-0904
Z8 CPU
User Manual
225
Add
ADD dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
r
r
src
r
lr
6
6
02
03
OPC
OPC
OPC
dst src
src
10
10
04
05
R
R
R
IR
dst
src
10
10
06
07
R
IR
IM
IM
dst
Operation
dst ← dst + src
The source operand is added to the destination operand. Two’s comple-
ment addition is performed. The sum is stored in the destination operand.
The contents of the source operand are not affected.
Flags Description
C
Set if there is a carry from the most significant bit of the result;
cleared otherwise.
Z
S
V
Set if the result is zero; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if an arithmetic overflow occurs, that is, if both operands are
of the same sign and the result is of the opposite sign; cleared
otherwise.
D
H
Always cleared.
Set if there is a carry from the most significant bit of the low
order four bits of the result; cleared otherwise.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
226
Address modes R or IR can be used to specify a 4-bit Working Register. In
Note:
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
If Working Register R3 contains 16hand Working Register R11 contains
20h, the statement:
ADD R3, R11
Op Code: 02 3B
leaves the value 36hin Working Register R3. The C, Z, S, V, D, and H
Flags are all cleared.
Example
If Working Register R16 contains 16h, Working Register R10 contains
20h, and Register 20hcontains 11h, the statement:
ADD R16, @R10
Op Code: 03 FA
leaves the value 27hin Working Register R16. The C, Z, S, V, D, and H
Flags are all cleared.
Example
If Register 34hcontains 2Ehand Register 12hcontains 1Bh, the state-
ment:
ADD 34h, 12h
Op Code: 04 12 34
leaves the value 49hin Register 34h. The H Flag is set, and the C, Z, S, V,
and D flags are cleared.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
227
Example
If Register 4Bhcontains 82h, Working Register R3 contains 10h, and
Register 10hcontains 01h, the statement:
ADD 3Eh, @R3
Op Code: 05 E3 4B
leaves the value 83hin Register 4Bh. The S Flag is set, and the C, Z, V, D,
and H flags are cleared.
Example
If Register 6Chcontains 2Ah, the statement:
ADD 6Ch, #03h
Op Code: 06 6C 03
leaves the value 2Dhin Register 6Ch. The C, Z, S, V, D, and H Flags are
all cleared.
Example
If Register D4hcontains 5Fhand Register 5Fhcontains 4Ch, the state-
ment:
ADD @D4h, #02h
Op Code: 07 D4 02
leaves the value 4Ehin Register 5Fh. The C, Z, S, V, D, and H Flags are
all cleared.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
228
Add With Carry
Syntax
ADC dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
src
6
6
02
03
r
r
r
lr
OPC
OPC
OPC
dst src
10
10
04
05
R
R
R
IR
src
dst
dst
src
10
10
06
07
R
IR
IM
IM
Operation
dst ← dst + src + C
The source operand, along with the setting of the Carry (C) Flag, is added
to the destination operand. Two’s complement addition is performed. The
sum is stored in the destination operand. The contents of the source oper-
and are not affected. In multiple precision arithmetic, this instruction per-
mits the carry from the addition of low order operands to be carried into
the addition of high order operands.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
229
Flag
Description
C
Set if there is a carry from the most significant bit of the result;
cleared otherwise.
Z
S
V
Set if the result is zero; cleared otherwise.
Set if the result is negative; cleared otherwise.
Set if an arithmetic overflow occurs, that is, if both operands are
of the same sign and the result is of the opposite sign; cleared
otherwise.
D
H
Always cleared.
Set if there is a carry from the most significant bit of the low
order four bits of the result; cleared otherwise.
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
If Working Register R3 contains 16h, the C Flag is set to 1, and Working
Register R11 contains 20h, the statement:
ADC R3, R11
Op Code: 12 3B
leaves the value 37hin Working Register R3. The C, Z, S, V, D, and H
Flags are all cleared.
Example
If Working Register R16 contains 16h, the C Flag is not set, Working
Register R10 contains 20h, and Register 20hcontains 11h, the statement:
ADC R16, @R10
Op Code: 13 FA
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
230
leaves the value 27hin Working Register R16. The C, Z, S, V, D, and H
Flags are all cleared.
Example
If Register 34hcontains 2Eh, the C Flag is set, and Register 12hcontains
1Bh, the statement:
ADC 34h, 12h
Op Code: 14 12 34
leaves the value 4Ahin Register 34h. The H Flag is set, and the C, Z, S, V,
and D flags are cleared.
Example
If Register 4Bhcontains 82h, the C Flag is set, Working Register R3 con-
tains 10h, and Register 10hcontains 01h, the statement:
ADC 4Bh, @R3
Op Code: 15 E3 4B
leaves the value 84hin Register 4Bh. The S Flag is set, and the C, Z, V, D,
and H flags are cleared.
Example
If Register 6Chcontains 2Ah, and the C Flag is not set, the statement:
ADC 6Ch, #03h
Op Code: 16 6C 03
leaves the value 2Dhin Register 6Ch. The C, Z, S, V, D, and H Flags are
all cleared.
Example
If Register D4hcontains 5Fh, Register 5Fhcontains 4Ch, and the C Flag
is set, the statement:
ADC @D4h, #02h
Op Code: 17 D4 02
Instruction Description
UM001602-0904
Z8 CPU
User Manual
231
leaves the value 4Fhin Register 5Fh. The C, Z, S, V, D, and H Flags are
all cleared.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
232
Call Procedure
CALL dst
Instruction Format
OPC Address Mode
Cycles (Hex)
dst
OPC
dst
20
D6
D4
DA
OPC
dst
20
IRR
Operation
SP ← SP–2
@SP ← PC
PC ← dst
The Stack pointer is decremented by two, the current contents of the Pro-
gram Counter (PC) (address of the first instruction following the CALL
instruction) are pushed onto the top of the Stack, and the specified desti-
nation address is then loaded into the PC. The PC now points to the first
instruction of the procedure.
At the end of the procedure a RET (return) instruction can be used to
return to the original program flow. RET will pop the top of the Stack and
replace the original value into the PC.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Instruction Description
UM001602-0904
Z8 CPU
User Manual
233
Address mode IRR can be used to specify a 4-bit Working Register Pair. In
this format, the destination Working Register Pair operand is specified by
adding 1110b(Eh) to the high nibble of the operand. For example, if
Working Register Pair RR12 (CH) is the destination operand, then ECh
will be used as the destination operand in the Op Code.
Note:
E
src
or
E
dst
Example
If the contents of the PC are 1A47h and the contents of the SP (Registers
FEhand FFh) are 3002h, the statement:
CALL 3521h
Op Code: D6 35 21
causes the SP to be decremented to 3000h, 1A4Ah(the address following
the CALL instruction) to be stored in external data memory 3000 and
3001h, and the PC to be loaded with 3521h. The PC now points to the
address of the first statement in the procedure to be executed.
Example
If the contents of the PC are 1A47h, the contents of the SP (Register FFh)
are 72h, the contents of Register A4h are 34h, and the contents of Regis-
ter Pair 34hare 3521h, the statement:
CALL @A4h
Op Code: D4 A4
causes the SP to be decremented to 70h, 1A4Ah(the address following
the CALL instruction) to be stored in R70hand 71h, and the PC to be
loaded with 3521h. The PC now points to the address of the first state-
ment in the procedure to be executed.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
234
Complement Carry Flag
CCF
Instruction Format
OPC
Cycles
(Hex)
OPC
6
EF
Operation
C ← NOT C
The C Flag is complemented. If C = 1, then it is changed to C = 0; or, if C
= 0, then it is changed to C = 1.
Flag
C
Z
S
V
Description
Complemented
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Example
If the C Flag contains a 0, the statement:
CCF
Op Code: EF
will change the C Flag from C = 0 to C = 1.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
235
Clear
CLR dst
Instruction Format
OPC
(Hex)
80
Address
Cycles
dst
R
IR
6
6
OPC
dst
81
Operation
dst ← 0
The destination operand is cleared to 00h.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If Working Register R6 contains AFh, the statement:
CLR R6
Op Code: B0 E6
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
236
will leave the value 00hin Working Register R6.
If Register A5hcontains the value 23h, and Register 23hcontains the
value FCh, the statement:
CLR @A5h
Op Code: B1 A5
will leave the value 00hin Register 23h.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
237
Complement
COM dst
Instruction Format
OPC
(Hex)
60
Address Mode
Cycles
dst
R
IR
6
6
OPC
dst
61
Operation
dst ← NOT dst
The contents of the destination operand are complemented (one’s comple-
ment). All 1 bits are changed to 0, and all 0 bits are changed to 1.
Flag
C
Description
Unaffected
Z
S
V
Set if the result is zero; cleared otherwise.
Set if result bit 7 is set; cleared otherwise.
Always reset to 0.
D
Unaffected
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If Register 08hcontains 24h(00100100b), the statement:
UM001602-0904
Instruction Description
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238
COM 08h
Op Code: 60 08
leaves the value DBh(11011011) in Register 08h. The S Flag is set, and
the Z and V flags are cleared.
Example
If Register 08hcontains 24h, and Register 24hcontains FFh
(11111111b), the statement:
COM @08h
Op Code: 61 08
leaves the value 00h(00000000b) in Register 24h. The Z Flag is set, and
the V and S flags are cleared.
Instruction Description
UM001602-0904
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239
Compare
CP dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
r
r
src
r
lr
6
6
A2
A3
OPC
OPC
OPC
dst src
src
10
10
A4
A5
R
R
R
IR
dst
src
10
10
A6
A7
R
IR
IM
IM
dst
Operation
dst–src
The source operand is compared to (subtracted from) the destination
operand, and the appropriate flags are set accordingly. The contents of
both operands are unaffected.
Flag
Description
C
Cleared if there is a carry from the most significant bit of the
result. Set otherwise indicating a borrow.
Set if the result is zero; cleared otherwise.
Set if result bit 7 is set (negative); cleared otherwise.
Set if arithmetic overflow occurs; cleared otherwise.
Unaffected
Z
S
V
D
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
UM001602-0904
Instruction Description
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240
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
Example
E
src
or
E
dst
If Working Register R3 contains 16hand Working Register R11 contains
20h, the statement:
CP R3, R11
Op Code: A2 3B
sets the C and S Flags, and the Z and V flags are cleared.
Example
If Working Register R15 contains 16h, Working Register R10 contains
20h, and Register 20hcontains 11h, the statement:
CP R16, @R10
Op Code: A3 FA
clears the C, Z, S, and V Flags.
Example
If Register 34hcontains 2Ehand Register 12hcontains 1Bh, the state-
ment:
CP 34h,12h
Op Code: A4 12 34
clears the C, Z, S, and V Flags.
Example
If Register 4Bhcontains 82h, Working Register R3 contains 10h, and
Register 10hcontains 01h, the statement:
CP 4Bh, @R3
Op Code: A5 E3 4B
Instruction Description
UM001602-0904
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241
sets the S Flag, and clears the C, Z, and V Flags.
Example
If Register 6Chcontains 2Ah, the statement:
CP 6Ch, #2Ah
Op Code: A6 6C 2A
sets the Z Flag, and the C, S, and V Flags are all cleared.
Example
If Register D4hcontains FCh, and Register FChcontains 8Fh, the state-
ment:
CP @D4h, 7Fh
Op Code: A7 D4 FF
sets the V Flag, and the C, Z, and S Flags are all cleared.
UM001602-0904
Instruction Description
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User Manual
242
Decimal Adjust
DA dst
Instruction Format
OPC
(Hex)
40
Address Mode
Cycles
dst
R
IR
8
8
OPC
dst
41
Operation
dst ← DA dst
The destination operand is adjusted to form two 4-bit BCD digits follow-
ing a binary addition or subtraction operation on BCD encoded bytes. For
addition (ADD and ADC) or subtraction (SUB and SBC), the following
table indicates the operation performed.
Bits 7–4
Value
(Hex)
Bits 3–0
Value
(Hex)
Number
Added To
Byte
Carry
Before DA
H Flag
Before DA
Carry
After DA
Instruction
0
0
0
0
0
0
1
1
1
0
0
0–9
0–8
0–9
A–F
9–F
A–F
0–2
0–2
0–3
0–9
0–8
0
0
1
0
0
1
0
0
1
0
1
0–9
A–F
0–3
0–9
A–F
0–3
0–9
A–F
0–3
0–9
6–F
00
06
06
60
66
66
60
66
66
00
FA
0
0
0
1
1
1
1
1
1
0
0
ADD
ADC
SUB
Instruction Description
UM001602-0904
Z8 CPU
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243
Bits 7–4
Value
(Hex)
Bits 3–0
Value
(Hex)
Number
Added To
Carry
Before DA
H Flag
Before DA
Car
After
Instruction
Byte
SBC
1
1
7–F
6–F
0
1
0–9
6–F
A0
1
1
9A
If the destination operand is not the result of a valid addition or subtrac-
tion of BCD digits, the operation is undefined.
Flag
Description
C
Set if there is a carry from the most significant bit; cleared
otherwise (see table above).
Set if the result is zero; cleared otherwise.
Set if result bit 7 is set (negative); cleared otherwise.
Unaffected
Z
S
D
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If addition is performed using the BCD value 15 and 27, the result should
be 42. The sum is incorrect, however, when the binary representations are
added in the destination location using standard binary arithmetic.
0001 0101 = 15h
+ 0010 0111 = 27h
0011 1100 = 3Ch
UM001602-0904
Instruction Description
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244
If the result of the addition is stored in Register 5Fh, the statement:
DA 5Fh
Op Code: 40 5F
adjusts this result so the correct BCD representation is obtained.
0011 1100 = 3Ch
0000 0110 = 06h
0100 0010 = 42h
Register 5Fhnow contains the value 42h. The C, Z, and S flags are
cleared, and V is undefined.
Example
If addition is performed using the BCD value 15 and 27, the result should
be 42. The sum is incorrect, however, when the binary representations are
added in the destination location using standard binary arithmetic.
0001 0101 = 15h
+ 0010 0111 = 27h
0011 1100 = 3Ch
Register 45Fcontains the value 5Fh, and the result of the addition is
stored in Register 5Fh, the statement:
DA @45h
Op Code: 40 45
adjusts this result so the correct BCD representation is obtained.
0011 1100 = 3Ch
0000 0110 = 06h
0100 0010 = 42h
Register 5Fhnow contains the value 42h. The C, Z, and S flags are
cleared, and V is undefined.
Instruction Description
UM001602-0904
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245
Decrement
DEC dst
Instruction Format
OPC
Address
Cycles
(Hex) Mode dst
6
6
00
01
R
IR
OPC
dst
Operation
dst ← dst–1
The contents of the destination operand are decremented by one.
Flag
C
Description
Unaffected
Z
S
V
D
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set (negative); cleared otherwise
Set if arithmetic overflow occurs; cleared otherwise
Unaffected
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If Working Register R10 contains 2A%, the statement:
DEC R10
Op Code: 00 EA
UM001602-0904
Instruction Description
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246
leaves the value 29hin Working Register R10. The Z, V, and S flags are
cleared.
Example
If Register B3hcontains CBh, and Register CBhcontains 01h, the state-
ment:
DEC @B3h
Op Code: 01 B3
leaves the value 00hin Register CBh. The Z Flag is set, and the V and S
flags are cleared.
Instruction Description
UM001602-0904
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247
Decrement and Jump if Non-Zero
DJNZ r, dst
Instruction Format
Address Mode
Cycles
12 If jump taken
10 if jump not taken (R = 0 to F)
OPC (Hex)
dst
r
r
rA
r
OPC
dst
Operation
r ← r–1;
If r <> 0, PC ← PC + dst
The specified Working Register being used as a counter is decremented. If
the contents of the specified Working Register are not zero after decre-
menting, then the relative address is added to the Program Counter (PC)
and control passes to the statement whose address is now in the PC. The
range of the relative address is +127 to –128. The original value of the PC
is the address of the instruction byte following the DJNZ statement. When
the specified Working Register counter reaches zero, control falls through
to the statement following the DJNZ instruction.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: The Working Register being used as a counter must be one of the Registers
from 04hto EFh. Use of one of the I/O ports, control or peripheral regis-
ters will have undefined results.
UM001602-0904
Instruction Description
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User Manual
248
Example
DJNZ is typically used to control a loop of instructions. In this example,
12 bytes are moved from one buffer area in the register file to another. The
steps involved are:
•
•
•
Load 12 into the counter (Working Register R6)
Set up the loop to perform the moves
End the loop with DJNZ
The assembly listing required for this routine is as follows:
LD R6, 12
LOOP: LD R9, @R6
LD @R6, R9
;Load Counter
;Move one byte to
;new location
DJNZ R6, LOOP ;Decrement and Loop until counter
;= 0
Instruction Description
UM001602-0904
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249
Decrement Word
DECW dst
Instruction Format
OPC
(Hex)
80
Address Mode
Cycles
10
dst
RR
IR
OPC
dst
10
81
Operation
dst ← dst–1
The contents of the destination (which must be an even address) operand
are decremented by one. The destination operand can be a Register Pair or
a Working Register Pair.
Flag
C
Description
Unaffected
Z
S
V
D
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set (negative); cleared otherwise
Set if arithmetic overflow occurs; cleared otherwise
Unaffected
H
Unaffected
Note: Address modes RR or IR can be used to specify a 4-bit Working Register
Pair. In this format, the destination Working Register Pair operand is spec-
ified by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register Pair R12 (CH) is the destination operand, then ECh
will be used as the destination operand in the Op Code.
E
dst
Example
If Register Pair 30hand 31hcontain the value 0AF2h, the statement:
UM001602-0904
Instruction Description
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User Manual
250
DECW 30h
Op Code: 80 30
leaves the value 0AF1hin Register Pair 30hand 31h. The Z, V, and S
flags are cleared.
Example
If Working Register R0 contains 30hand Register Pairs 30hand 31h
contain the value FAF3h, the statement:
DECW @R0
Op Code: 81 E0
leaves the value FAF2hin Register Pair 30hand 31h. The S Flag is set,
and the Z and V flags are cleared.
Instruction Description
UM001602-0904
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User Manual
251
Disable Interrupts
Dl
Instruction Format
OPC
Cycles
(Hex)
OPC
6
8F
Operation
IMR (7) ← 0
Bit 7 of Control Register FBh(the Interrupt Mask Register) is reset to 0.
All interrupts are disabled, although they remain potentially enabled. (For
instance, the Global Interrupt Enable is cleared, but not the individual
interrupt level enables.)
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Example
If Control Register FBhcontains 8Ah(10001010) (interrupts IRQ1 and
IRQ3 are enabled), the statement:
DI
Op Code: 8F
sets Control Register FBhto 0Ah(00001010b) and disables these inter-
rupts.
UM001602-0904
Instruction Description
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User Manual
252
Enable Interrupts
EI
Instruction Format
OPC
Cycles
(Hex)
OPC
6
9F
Operation
IMR (7) ← 0
Bit 7 of Control Register FBh(the Interrupt Mask Register) is set to 1.
This allows potentially enabled interrupts to become enabled.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Example
If Control Register FBhcontains 0Ah(00001010) (interrupts IRQ1 and
IRQ3 are selected), the statement:
EI
Op Code: 9F
sets Control Register FBhto 8Ah(10001010b) and enables IRQ1 and
IRQ3.
Instruction Description
UM001602-0904
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User Manual
253
Halt
HALT
Instruction Format
OPC
Cycles
(Hex)
OPC
6
7F
Operation
The HALT instruction turns off the internal CPU clock, but not the XTAL
oscillation. The counter/timers and the external interrupts IRQ1, IRQ2,
and IRQ3 remain active. The devices are recovered by interrupts, either
externally or internally generated.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: In order to enter HALT mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction. The user must
execute a NOP immediately before the execution of the HALT instruction.
Example
®
Assuming the Z8 CPU is in normal operation, the statements:
NOP
HALT
Op Codes: FF 7F
®
place the Z8 CPU into HALT mode.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
254
Increment
Instruction Format
OPC
(Hex)
Address Mode
dst
Cycles
dst OPC
OPC
6
rE
r
6
6
20
21
R
IR
dst
Operation
dst ← dst + 1
The contents of the destination operand are incremented by one.
Flag
C
Description
Unaffected
Z
S
V
D
Set if the result is zero; cleared otherwise.
Set if the result of bit 7 is set (negative); cleared otherwise.
Set if arithmetic overflow occurs; cleared otherwise.
Unaffected
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If Working Register R10 contains 2Ah, the statement:
Instruction Description
UM001602-0904
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255
INC R10
Op Code: AE
leaves the value 2Bh in Working Register R10. The Z, V, and S flags are
cleared.
Example
If Register B3hcontains CBh, the statement:
INC B3h
Op Code: 20 B3
leaves the value CCh in Register CBh. The S Flag is set, and the Z and V
flags are cleared.
Example
If Register B3hcontains CBhand Register BChcontains FFh, the state-
ment:
INC @B3h
Op Code: 21 B3
leaves the value 00hin Register CBh. The Z Flag is set, and the V and S
flags are cleared.
UM001602-0904
Instruction Description
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User Manual
256
Increment Word
INCW dst
Instruction Format
OPC
(Hex)
A0
Address Mode
Cycles
10
dst
RR
IR
OPC
dst
10
A1
10
A0
R
Operation
dst ← dst–1
The contents of the destination (which must be an even address) operand
is decremented by one. The destination operand can be a Register Pair or
a Working Register Pair.
Flag
C
Description
Unaffected
Z
S
V
D
Set if the result is zero; cleared otherwise.
Set if the result of bit 7 is set (negative); cleared otherwise.
Set if arithmetic overflow occurs; cleared otherwise.
Unaffected
H
Unaffected
Note: Address modes RR or IR can be used to specify a 4-bit Working Register
Pair. In this format, the destination Working Register Pair operand is spec-
ified by adding 1110b(Eh) to the high nibble of the operand. For exam-
ple, if Working Register Pair R12 (CH) is the destination operand, then
EChwill be used as the destination operand in the Op Code
E
dst
Example
If Register Pairs 30hand 31hcontain the value 0AF2h, the statement:
Instruction Description
UM001602-0904
Z8 CPU
User Manual
257
INCW 30h
Op Code: A0 30
leaves the value 0AF3hin Register Pair 30hand 31h. The Z, V, and S
flags are cleared.
Example
If Working Register R0 contains 30h, and Register Pairs 30hand 31h
contain the value FAF3h, the statement:
INCW @R0
Op Code: A1 E0
leaves the value FAF4hin Register Pair 30hand 31h. The S Flag is set,
and the Z and V flags are cleared.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
258
Interrupt Return
IRET
Instruction Format
OPC
Cycles
16
(Hex)
OPC
8F
Operation
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
SP ← SP + 2
IMR (7) ← 1
This instruction is issued at the end of an interrupt service routine. It
restores the Flag Register (Control Register FCh) and the PC. It also re-
enables any interrupts that are potentially enabled.
Flag
C
Z
S
V
Description
Restored to original setting before the interrupt occurred.
Restored to original setting before the interrupt occurred.
Restored to original setting before the interrupt occurred.
Restored to original setting before the interrupt occurred.
Restored to original setting before the interrupt occurred.
Restored to original setting before the interrupt occurred.
D
H
Example
If Stack Pointer Low Register FFhcurrently contains the value 45h, Reg-
ister 45hcontains the value 00h, Register 46hcontains 6Fh, and Register
47 contains E4h, the statement:
IRET
Op Code: BF
Instruction Description
UM001602-0904
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259
restores the FLAG Register FChwith the value 00h, restores the PC with
the value 6FE4h, re-enables the interrupts, and sets the Stack Pointer Low
to 48h. The next instruction to be executed will be at location 6FE4h.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
260
Jump
JP cc, dst
Instruction Format
Address Mode
Cycles
OPC (Hex)
dst
12 If jump taken
10 if jump not taken cc = 0 to F
ccD
DA
cc OPC
dst
dst
dst
8
30
IRR
Operation
If cc (condition code) is true, then PC ← dst
A conditional jump transfers Program Control to the destination address
if the condition specified by cc (condition code) is true. Otherwise, the
instruction following the JP instruction is executed. See Section 12.3 for a
list of condition codes.
The unconditional jump simply replaces the contents of the Program
Counter with the contents of the register pair specified by the destination
operand. Program Control then passes to the instruction addressed by the
PC.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: Address mode IRR can be used to specify a 4-bit Working Register. In this
format, the destination Working Register operand is specified by adding
1110b(Eh) to the high nibble of the operand. For example, if Working
Instruction Description
UM001602-0904
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261
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If the Carry Flag is set, the statement:
JP C, 1520h
Op Code: 7D 15 20
replaces the contents of the Program Counter with 1520h and transfers
program control to that location. If the Carry Flag had not been set, con-
trol would have fallen through to the statement following the JP instruc-
tion.
Example
If Working Register Pair RR2 contains the value 3F45h, the statement:
JP @RR2
Op Code: 30 E2
replaces the contents of the PC with the value 3F45hand transfers pro-
gram control to that location.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
262
Jump Relative
JR cc, dst
Instruction Format
Address Mode
Cycles
OPC (Hex)
dst
12 If jump taken
10 if jump not taken cc = 0 to F
ccB
RR
cc OPC
dst
Operation
If cc is true, PC ← PC + dst
If the condition specified by the cc is true, the relative address is added to
the PC and control passes to the instruction located at the address speci-
fied by the PC (See Section 12.3 for a list of condition codes). Otherwise,
the instruction following the JR instruction is executed. The range of the
relative address is +127 to –128, and the original value of the PC is taken
to be the address of the first instruction byte following the JR instruction.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Example
If the result of the last arithmetic operation executed is negative, the next
four statements (which occupy a total of seven bytes) are skipped with the
statement:
JR Ml, #9
Op Code: 5B 09
Instruction Description
UM001602-0904
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263
If the result was not negative, execution would have continued with the
instruction following the JR instruction.
Example
A short form of a jump –45 is:
JR #–45
Op Code: 8B D3
The condition code is blank in this case, and is assumed to be always true.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
264
Load
LD dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
src
6
6
rC
r8
r
r
IM
R
dst OPC
src OPC
OPC
src
dst
6
r9
R*
r
r = 0 to F
6
6
E3
F3
r
Ir
Ir
r
dst OPC
src
10
10
E4
E5
R
R
R
IR
OPC
dst
src
dst
src
dst
10
10
E6
E7
R
IR
IM
IM
OPC
dst
OPC
src
10
10
10
F5
C7
D7
IR
r
R
X
r
OPC
dst
src
X
X
OPC
X
Operation
dst ← src
The contents of the source operand are loaded into the destination oper-
and. The contents of the source operand are not affected.
Instruction Description
UM001602-0904
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265
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
The statement:
LD R15, #34h
Op Code: FC 34
loads the value 34hinto Working Register R15.
Example
If Register 34hcontains the value FCh, the statement:
LD R14, 34h
Op Code: F8 34
loads the value FChinto Working Register R15. The contents of Register
34hare not affected.
Example
If Working Register R14 contains the value 45h, the statement:
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
266
LD 34h, R14
Op Code: E9 34
loads the value 45hinto Register 34h. The contents of Working Register
R14 are not affected.
Example
If Working Register R12 contains the value 34h, and Register 34hcon-
tains the value FFh, the statement:
LD R13, @R12
Op Code: E3 DC
loads the value FFhinto Working Register R13. The contents of Working
Register R12 and Register R34 are not affected.
Example
If Working Register R13 contains the value 45h, and Working Register
R12 contains the value 00hthe statement:
LD @R13, R12
Op Code: F3 DC
loads the value 00hinto Register 45h. The contents of Working Register
R12 and Working Register R13 are not affected.
Example
If Register 45hcontains the value CFh, the statement:
LD 34h, 45h
Op Code: E4 45 34
loads the value CFhinto Register 34h. The contents of Register 45hare
not affected.
Example
If Register 45hcontains the value CFhand Register CFhcontains the
value FFh, the statement:
Instruction Description
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LD 34h, @45h
Op Code: E5 45 34
loads the value FFhinto Register 34h. The contents of Register 45hand
Register CFhare not affected.
Example
The statement:
LD 34h, #A4h
Op Code: E6 34 A4
loads the value A4h into Register 34h.
Example
If Working Register R14 contains the value 7Fh, the statement:
LD @R14, #FCh
Op Code: E7 EE FC
loads the value FChinto Register 7Fh. The contents of Working Register
R14 are not affected.
Example
If Register 34hcontains the value CFhand Register 45hcontains the
value FFh, the statement:
LD @34h, 45h
Op Code: F5 45 34
loads the value FFhinto Register CFh. The contents of Register 34hand
Register 45hare not affected.
Example
IIf Working Register R0 contains the value 08hand Register 2Ch(24h+
08h= 2Ch) contains the value 4Fh, the statement:
LD R10, 24h(R0)
Op Code: C7 A0 24
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loads Working Register R10 with the value 4Fh. The contents of Working
Register R0 and Register 2Chare not affected.
Example
If Working Register R0 contains the value 0Bhand Working Register R10
contains 83hthe statement:
LD F0h(R0), R10
Op Code: D7 A0 F0
loads the value 83hinto Register FBh(F0h+ 0Bh= FBh). Because this is
the Interrupt Mask Register, the LOAD statement has the effect of
enabling IRQ0 and IRQ1. The contents of Working Registers R0 and R10
are unaffected by the load.
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Load Constant
LDC dst, src
Instruction Format
Address Mode
OPC
Cycles
(Hex)
dst
src
OPC
OPC
dst src
dst src
12
C2
r
Irr
12
D2
Irr
r
Operation
dst ← src
This instruction is used to load a byte constant from program memory
into a Working Register, or vice versa. The address of the program mem-
ory location is specified by a Working Register Pair. The contents of the
source operand are not affected.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Example
If Working Register Pair R6 and R7 contain the value 30A2hand program
memory location 30A2hcontains the value 22h, the statement:
LDC R2, @RR6
Op Code: C2 26
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loads the value 22hinto Working Register R2. The value of program
memory location 30A2his unchanged by the load.
Example
If Working Register R2 contains the value 22h, and Working Register Pair
R6 and R7 contains the value 10A2h, the statement:
LDC @RR6, R2
Op Code: D2 26
loads the value 22hinto program memory location 10A2h. The value of
Working Register R2 is unchanged by the load.
Note: This instruction format is valid only for MCUs which can address external
program memory.
Instruction Description
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Load Constant Autoincrement
LDCI dst, src
Instruction Format
Address Mode
OPC
Cycles
(Hex)
dst
src
OPC
OPC
dst src
dst src
18
C3
Ir
Irr
18
D3
Irr
Ir
Operation
dst ← src
r ← r + 1
rr ← rr + 1
This instruction is used for block transfers of data between program mem-
ory and the Register File. The address of the program memory location is
specified by a Working Register Pair, and the address of the Register File
location is specified by Working Register. The contents of the source loca-
tion are loaded into the destination location. Both addresses in the Work-
ing Registers are then incremented automatically. The contents of the
source operand are not affected.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
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Example
If Working Register Pair R6–R7 contains 30A2h, program memory loca-
tion 30A2hand 30A3hcontain 22hand BChrespectively, and Working
Register R2 contains 20h, the statement:
LDCI @R2, @RR6
Op Code: C3 26
loads the value 22hinto Register 20h. Working Register Pair RR6 is
incremented to 30A3hand Working Register R2 is incremented to 21h. A
second
LDCI @R2, @RR6
Op Code: C3 26
loads the value BChinto Register 21h. Working Register Pair RR6 is
incremented to 30A4hand Working Register R2 is incremented to 22h.
Example
If Working Register R2 contains 20h, Register 20hcontains 22h, Regis-
ter 21hcontains BCh, and Working Register Pair R6–R7 contains 30A2h,
the statement:
LDCI @RR6, @R2
Op Code: D3 26
loads the value 22hinto program memory location 30A2h. Working Reg-
ister R2 is incremented to 21hand Working Register Pair R6–R7 is incre-
mented to 30A3h. A second
LDCI @RR6, @R2
Op Code: D3 26
loads the value BChinto program memory location 30A3h. Working Reg-
ister R2 is incremented to 22hand Working Register Pair R6–R7 is incre-
mented to 30A4h.
Instruction Description
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Load External Data
LDE dst, src
Instruction Format
Address Mode
OPC
Cycles
(Hex)
dst
src
OPC
OPC
dst src
src dst
12
82
r
Irr
12
92
Irr
r
Operation
dst ← src
This instruction is used to load a byte from external data memory into a
Working Register or vice versa. The address of the external data memory
location is specified by a Working Register Pair. The contents of the
source operand are not affected.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Example
If Working Register Pair R6 and R7 contain the value 40A2hand external
data memory location 40A2hcontains the value 22h, the statement:
LDE R2, @RR6
Op Code: 82 26
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loads the value 22hinto Working Register R2. The value of external data
memory location 40A2his unchanged by the load.
Example
If Working Register Pair R6 and R7 contain the value 404Ahand Working
Register R2 contains the value 22h, the statement:
LDE @RR6, R2
Op Code: 92 26
loads the value 22hinto external data memory location 404Ah
Note: This instruction format is valid only for MCUs which can address external
data memory.
Instruction Description
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Load External Data Autoincrement
LDEI dst, src
Instruction Format
Address Mode
OPC
Cycles
(Hex)
dst
src
OPC
OPC
dst src
src dst
18
83
Ir
Irr
18
93
Irr
Ir
Operation
dst ← src
r ← r + 1
rr ← rr + 1
This instruction is used for block transfers of data between external data
memory and the Register File. The address of the external data memory
location is specified by a Working Register Pair, and the address of the
Register File location is specified by a Working Register. The contents of
the source location are loaded into the destination location. Both
addresses in the Working Registers are then incremented automatically.
The contents of the source are not affected.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
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Example
If Working Register Pair R6 and R7 contains 404Ah, external data mem-
ory location 404Ahand 404Bhcontain ABhand C3hrespectively, and
Working Register R2 contains 22h, the statement:
LDEI @R2, @RR6
Op Code: 83 26
loads the value ABhinto Register 22h. Working Register Pair RR6 is
incremented to 404Bhand Working Register R2 is incremented to 23h. A
second
LDEI @R2, @RR6
Op Code: 83 26
loads the value C3hinto Register 23h. Working Register Pair RR6 is
incremented to 404Chand Working Register R2 is incremented to 24h.
Example
If Working Register R2 contains 22h, Register 22hcontains ABh, Regis-
ter 23hcontains C3h, and Working Register Pair R6 and R7 contains
404Ah, the statement:
LDEI @RR6, @R2
Op Code: 93 26
loads the value ABhinto external data memory location 404Ah. Working
Register R2 is incremented to 23hand Working Register Pair RR6 is
incremented to 404Bh. A second
LDEI @RR6, @R2
Op Code: 93 26
loads the value C3hinto external data memory location 404Bh. Working
Register R2 is incremented to 24hand Working Register Pair RR6 is
incremented to 404Ch.
Note: This instruction format is valid only for MCUs which can address external
data memory.
Instruction Description
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No Operation
NOP
Instruction Format
OPC
Cycles
(Hex)
OPC
6
FF
Operation
No action is performed by this instruction. It is typically used for timing
delays or clearing the pipeline.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
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Logical AND
AND dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
src
6
6
42
43
r
r
r
lr
OPC
OPC
OPC
dst src
10
10
44
45
R
R
R
IR
src
dst
dst
src
10
10
46
47
R
IR
IM
IM
Operation
dst ← dst AND src
The source operand is logically ANDed with the destination operand. The
AND operation results in a 1 being stored whenever the corresponding
bits in the two operands are both 1, otherwise a 0 is stored. The result is
stored in the destination operand. The contents of the source bit are not
affected.
Flag
C
Description
Unaffected
Z
S
V
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set; cleared otherwise
Always reset to 0
D
Unaffected
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
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fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
If Working Register R1 contains 34h(00111000b) and Working Register
R14 contains 4Dh(10001101), the statement:
AND R1, R14
Op Code: 52 1E
Example
If Working Register R4 contains F9h(11111001b), Working Register
R13 contains 7Bh, and Register 7Bhcontains 6Ah(01101010b), the
statement:
AND R4, @R13
Op Code: 53 4D
leaves the value 68h(01101000b) in Working Register R4. The Z, V, and
S flags are cleared.
Example
If Register 3Ahcontains the value F5h(11110101b) and Register 42h
contains the value 0Ah(00001010), the statement:
AND 3Ah, 42h
Op Code: 54 42 3A
leaves the value 00h(00000000b) in Register 3Ah. The Z Flag is set, and
the V and S flags are cleared.
Example
If Working Register R5 contains F0h(11110000b), Register 45hcon-
tains 3Ah, and Register 3Ahcontains 7Fh(01111111b), the statement:
UM001602-0904
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AND R5, @45h
Op Code: 55 45 E5
leaves the value 70h(01110000b) in Working Register R5. The Z, V, and
S flags are cleared.
Example
If Register 7Ahcontains the value F7h(11110111b), the statement:
AND 7Ah, #F0h
Op Code: 56 7A F0
leaves the value F0h(11110000b) in Register 7Ah. The S Flag is set, and
the Z and V flags are cleared.
Example
If Working Register R3 contains the value 3Ehand Register 3Ehcontains
the value ECh(11101100b), the statement:
AND @R3, #05h
Op Code: 57 E3 05
leaves the value 04h(00000100b) in Register 3Eh. The Z, V, and S flags
are cleared.
Instruction Description
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Logical OR
OR dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
r
r
src
r
lr
6
6
02
03
OPC
OPC
dst src
src
10
10
04
05
R
R
R
IR
dst
src
10
10
06
07
R
IR
IM
IM
OPC
dst
Operation
dst ← dst OR src
The source operand is logically ORed with the destination operand and
the result is stored in the destination operand. The contents of the source
operand are not affected. The OR operation results in a one bit being
stored whenever either of the corresponding bits in the two operands is a
one. Otherwise, a zero bit is stored.
Flag
C
Description
Unaffected
Z
S
V
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set; cleared otherwise
Always reset to 0
D
Unaffected
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
UM001602-0904
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fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (Ch) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
If Working Register R1 contains 34h(00111000b) and Working Register
R14 contains 4Dh(10001101), the statement:
OR R1, R14
Op Code: 42 1E
leaves the value BDh(10111101b) in Working Register R1. The S Flag is
set, and the Z and V flags are cleared.
Example
If Working Register R4 contains F9h(11111001b), Working Register
R13 contains 7Bh, and Register 7B contains 6Ah(01101010b), the state-
ment:
OR R4, @R13
Op Code: 43 4D
leaves the value FBh(11111011b) in Working Register R4. The S Flag is
set, and the Z and V flags are cleared.
Example
If Register 3Ahcontains the value F5h(11110101b) and Register 42h
contains the value 0Ah(00001010), the statement:
OR 3Ah, 42h
Op Code: 44 42 3A
leaves the value FFh(11111111b) in Register 3Ah. The S Flag is set, and
the Z and V flags are cleared.
Instruction Description
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Example
If Working Register R5 contains 70h(01110000b), Register 45hcon-
tains 3Ah, and Register 3Ahcontains 7Fh(01111111b), the statement:
OR R5, @45h
Op Code: 45 45 E5
leaves the value 7Fh(01111111b) in Working Register R5. The Z, V, and
S flags are cleared.
Example
If Register 7Ahcontains the value F3h(11110111b), the statement:
OR 7Ah, #F0h
Op Code: 46 7A F0
leaves the value F3h(11110111b) in Register 7Ah. The S Flag is set, and
the Z and V flags are cleared.
Example
If Working Register R3 contains the value 3Ehand Register 3Ehcontains
the value 0Ch(00001100b), the statement:
OR @R3, #05h
Op Code: 57 E3 05
leaves the value 0Dh(00001101b) in Register 3Eh. The Z, V, and S flags
are cleared.
UM001602-0904
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Logical Exclusive OR
XOR dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
src
6
6
82
83
r
r
r
lr
OPC
OPC
OPC
dst src
10
10
84
85
R
R
R
IR
src
dst
dst
src
10
10
86
87
R
IR
IM
IM
Operation
dst ← dst XOR src
The source operand is logically EXCLUSIVE ORed with the destination
operand. The XOR operation results in a 1 being stored in the destination
operand whenever the corresponding bits in the two operands are differ-
ent, otherwise a 0 is stored. The contents of the source operand are not
affected.
C
Z
S
V
D
H
Unaffected
Set if the result is zero; cleared otherwise.
Set if the result of bit 7 is set; cleared otherwise.
Always reset to 0
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
Instruction Description
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if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
If Working Register R1 contains 34h(00111000b) and Working Register
R14 contains 4Dh(10001101b), the statement:
XOR R1, R14
Op Code: B2 1E
leaves the value BDh(10111101b) in Working Register R1. The Z, and V
flags are cleared, and the S Flag is set.
Example
If Working Register R4 contains F9h(11111001b), Working Register
R13 contains 7Bh, and Register 7Bhcontains 6Ah(01101010b), the
statement:
XOR R4, @R13
Op Code: B3 4D
leaves the value 93h(10010011b) in Working Register R4. The S Flag is
set, and the Z, and V flags are cleared.
Example
If Register 3Ahcontains the value F5h(11110101b) and Register 42h
contains the value 0Ah(00001010b), the statement:
XOR 3Ah, 42h
Op Code: B4 42 3A
leaves the value FFh(11111111b) in Register 3Ah. The S Flag is set, and
the C and V flags are cleared.
UM001602-0904
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Example
If Working Register R5 contains F0h(11110000b), Register 45hcon-
tains 3Ah, and Register 3Ahcontains 7Fh(01111111b), the statement:
XOR R5, @45h
Op Code: B5 45 E5
leaves the value 8Fh(10001111b) in Working Register R5. The S Flag is
set, and the C and V flags are cleared.
Example
If Register 7Ahcontains the value F7h(11110111b), the statement:
XOR 7Ah, #F0h
Op Code: B6 7A F0
leaves the value 07h(00000111b) in Register 7Ah. The Z, V and S flags
are cleared.
Example
If Working Register R3 contains the value 3Ehand Register 3Ehcontains
the value 6Ch(01101100b), the statement:
XOR @R3, #05h
Op Code: B7 E3 05
leaves the value 69h(01101001b) in Register 3Eh. The Z, V, and S flags
are cleared.
Instruction Description
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Pop
POP dst
Instruction Format
OPC
(Hex)
50
Address Mode
Cycles
10
dst
R
IR
OPC
dst
10
51
Operation
dst ← @SP
SP ← SP + 1
The contents of the location specified by the SP (Stack Pointer) are loaded
into the destination operand. The SP is then incremented automatically.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
UM001602-0904
Instruction Description
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Example
If the SP (Control Registers FEhand FFh) contains the value 70hand
Register 70hcontains 44h, the statement:
POP 34h
Op Code: 50 34
loads the value 44hinto Register 34h. After the POP operation, the SP
contains 71h. The contents of Register 70 are not affected.
Example
If the SP (Control Registers FEhand FFh) contains the value 1000h,
external data memory location 1000hcontains 55h, and Working Regis-
ter R6 contains 22h, the statement:
POP @R6
Op Code: 51 E6
loads the value 55hinto Register 22h. After the POP operation, the SP
contains 1001h. The contents of Working Register R6 are not affected.
Instruction Description
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Push
PUSH src
Instruction Format
OPC Address Mode
Cycles
(Hex)
dst
10 Internal Stack
12 External Stack
10 Internal Stack
10 External Stack
70
R
IR
OPC
src
71
Operation
SP ← SP–1
@SP ← src
The contents of the SP (stack pointer) are decremented by one, then the
contents of the source operand are loaded into the location addressed by
the decremented SP, thus adding a new element to the stack.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
UM001602-0904
Instruction Description
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Example
If the SP contains 1001h, the statement:
PUSH FCh
Op Code: 70 FC
stores the contents of Register FCh(the Flag Register) in location 1000h.
After the PUSH operation, the SP contains 1000h.
Example
If the SP contains 61hand Working Register R4 contains FCh, the state-
ment:
PUSH @R4
Op Code: 71 E4
stores the contents of Register FCh(the Flag Register) in location 60h.
After the PUSH operation, the SP contains 60h.
Instruction Description
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Reset Carry Flag
RCF
Instruction Format
OPC
Cycles
(Hex)
OPC
6
CF
Operation
C ← 0
The C Flag is reset to 0, regardless of its previous value.
Flag
C
Z
S
V
Description
Reset to 0
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Example
If the C Flag is currently set, the statement:
RCF
Op Code: CF
resets the Carry Flag to 0.
UM001602-0904
Instruction Description
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Return
RET
Instruction Format
OPC
Cycles
(Hex)
OPC
14
AF
Operation
PC ← @SP
SP ← SP + 2
This instruction is normally used to return from a procedure entered by a
CALL instruction. The contents of the location addressed by the SP are
popped into the PC. The next statement executed is the one addressed by
the new contents of the PC. The stack pointer is also incremented by two.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: Each PUSH instruction executed within the subroutine should be coun-
tered with a POP instruction in order to guarantee the SP is at the correct
location when the RET instruction is executed. Otherwise the wrong
address will be loaded into the PC and the program will not operate as
appropriate .
Instruction Description
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Example
If SP contains 2000h, external data memory location 2000hcontains
18h, and location 2001hcontains B5h, the statement:
RET
Op Code: AF
leaves the value 2002hin the SP, and the PC contains 18B5h, the address
of the next instruction to be executed.
UM001602-0904
Instruction Description
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Rotate Left
RL dst
Instruction Format
OPC
(Hex)
90
Address Mode
Cycles
dst
R
IR
6
6
OPC
dst
91
Operation
C ← dst(7)
dst(0) ← dst(7)
dst(1) ← dst(0)
dst(2) ← dst(1)
dst(3) ← dst(2)
dst(4) ← dst(3)
dst(5) ← dst(4)
dst(6) ← dst(5)
dst(7) ← dst(6)
The contents of the destination operand are rotated left by one bit posi-
tion. The initial value of bit 7 is moved to the bit 0 position and also into
the Carry Flag, as shown below.
C
D7 D6 D5 D4 D3 D2 D1 D0
Instruction Description
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Flag
Description
C
Set if the bit rotated from the most significant bit position was 1 (
i.e., bit 7 was 1).
Z
S
V
Set if the result is zero; cleared otherwise.
Set if the result in bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected.
D
H
Unaffected.
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If the contents of Register C6hare 88h(10001000b), the statement:
RL C6h
Op Code: 80 C6
leaves the value 11h(00010001b) in Register C6h. The C and V Flags
are set, and the S and Z flags are cleared.
Example
If the contents of Register C6hare 88h, and the contents of Register 88h
are 44h(01000100b), the statement:
RL @C6h
Op Code: 81 C6
leaves the value 88hin Register 88h(10001000b). The S and V Flags
are set, and the C and Z flags are cleared.
UM001602-0904
Instruction Description
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User Manual
296
Rotate Left Through Carry
RLC dst
Instruction Format
OPC
(Hex)
10
Address Mode
Cycles
dst
R
IR
6
6
OPC
dst
11
Operation
C← dst(7)
dst(0) ← C
dst(1) ← dst(0)
dst(2) ← dst(1)
dst(3) ← dst(2)
dst(4) ← dst(3)
dst(5) ← dst(4)
dst(6) ← dst(5)
dst(7) ← dst(6)
The contents of the destination operand along with the C Flag are rotated
left by one bit position. The initial value of bit 7 replaces the C Flag and
the initial value of the C Flag replaces bit 0, as shown below.
C
D7 D6 D5 D4 D3 D2 D1 D0
Instruction Description
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297
Flag
Description
C
Set if the bit rotated from the most significant bit position was 1
(i.e., bit 7 was 1).
Z
S
V
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected
D
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If the C Flag is reset and Register C6 contains 8Fh(10001111b), the
statement:
RLC C6
Op Code: 10 C6
leaves Register C6 with the value 1Eh(00011110b). The C and V Flags
are set, and S and Z flags are cleared.
Example
If the C Flag is reset, Working Register R4 contains C6h, and Register C6
contains 8Fh(10001111b), the statement:
RLC @R4
Op Code: 11 E4
leaves Register C6 with the value 1Eh(00011110b). The C and V Flags
are set, and S and Z flags are cleared.
UM001602-0904
Instruction Description
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User Manual
298
Rotate Right
RR dst
Instruction Format
OPC
(Hex)
E0
Address Mode
Cycles
dst
R
IR
6
6
OPC
dst
E1
Operation
C ← dst(0)
dst(0) ← dst(1)
dst(1) ← dst(2)
dst(2) ← dst(3)
dst(3) ← dst(4)
dst(4) ← dst(5)
dst(5) ← dst(6)
dst(6) ← dst(7)
dst(7) ← dst(0)
The contents of the destination operand are rotated to the right by one bit
position. The initial value of bit 0 is moved to bit 7 and also into the C
Flag, as shown below.
D7 D6 D5 D4 D3 D2 D1 D0
C
Instruction Description
UM001602-0904
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299
Flag
Description
C
Set if the bit rotated from the least significant bit position was 1 (
i.e., bit 0 was 1).
Z
S
V
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected
D
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If the contents of Working Register R6 are 31h(00110001B), the state-
ment:
RR R6
Op Code: E0 E6
leaves the value 98h(10011000) in Working Register R6. The C, V, and
S Flags are set, and the Z Flag is cleared.
Example
If the contents of Register C6 are 31hand the contents of Register 31h
are 7Eh(01111110b), the statement:
RR @C6
Op Code: E1 C6
leaves the value 4Fh(00111111) in Register 31h. The C, Z, V, and S
flags are cleared.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
300
Rotate Right Through Carry
RRC dst
Instruction Format
OPC
(Hex)
C0
Address Mode
Cycles
dst
R
IR
6
6
OPC
dst
C1
Operation
C ← dst(0)
dst(0) ← dst(1)
dst(1) ← dst(2)
dst(2) ← dst(3)
dst(3) ← dst(4)
dst(4) ← dst(5)
dst(5) ← dst(6)
dst(6) ← dst(7)
dst(7) ← C
The contents of the destination operand with the C Flag are rotated right
by one bit position. The initial value of bit 0 replaces the C Flag and the
initial value of the C Flag replaces bit 7, as shown below.
D7 D6 D5 D4 D3 D2 D1 D0
C
Instruction Description
UM001602-0904
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301
Flag
Description
C
Set if the bit rotated from the least significant bit position was 1
(i.e., bit 0 was 1).
Z
S
V
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected
D
H
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If the contents of Register C6hare DDh(11011101b) and the C Flag is
reset, the statement:
RRC C6h
Op Code: C0 C6
leaves the value 6Eh(01101110b) in register C6h. The C and V Flags are
set, and the Z and S flags are cleared.
Example
If the contents of Register 2Chare EDh, the contents of Register EDhis ←
(00000000b), and the C Flag is reset, the statement:
RRC @2Ch
Op Code: C1 2C
leaves the value 02h(00000010b) in Register EDh. The C, Z, S, and V
Flags are reset.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
302
Set Carry Flag
SRC
Instruction Format
OPC
Cycles
(Hex)
OPC
6
DF
Operation
C ← 1
The C Flag is set to 1, regardless of its previous value.
Flag
C
Description
Set to 1
Z
S
V
D
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
H
Example
If the C Flag is currently reset, the statement:
SCF
Op Code: DF
sets the Carry Flag to 1.
Instruction Description
UM001602-0904
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303
Set Register Pointer
SRP src
Instruction Format
OPC
Address Mode
Cycles
(Hex)
dst
OPC
src
6
31
IM
Operation
RP ← src
The specified value is loaded into the Register Pointer (RP) (Control Reg-
ister FDh). Bits 7-4 determine the Working Register Group. Bits 3-0
selects the Expanded Register Bank. Addressing of un-implemented
Working Register Group, while using Expanded Register Banks, will
point to Bank 0.
Example
SRP TD addresses Working Register Group 7 of Bank 0.
Working
Register Pointer
(FDh)
Register
Group
Actual
Registers
Contents (Bin)
1111 0000
1110 0000
1101 0000
1100 0000
1011 0000
1010 0000
1001 0000
(Hex)
(Hex)
F0–FF
E0–EF
D0–DF
C0–CF
B0–BF
A0–AF
90–9F
F
E
D
C
B
A
9
UM001602-0904
Instruction Description
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304
Working
Register
Group
Register Pointer
(FDh)
Actual
Registers
Contents (Bin)
1000 0000
0111 0000
0110 0000
0101 0000
0100 0000
0011 0000
0010 0000
0001 0000
0000 0000
(Hex)
(Hex)
80–8F
70–7F
60–6F
50–5F
40–4F
30–3F
20–2F
10–1F
00–0F
8
7
6
5
4
3
2
1
0
Register Pointer (FDh)
Expanded Register
Bank (Hex)
Contents (Hex)
xxxx 1111
xxxx 1110
xxxx 1101
xxxx 1100
xxxx 1011
xxxx 1010
xxxx 1001
xxxx 1000
xxxx 0111
xxxx 0110
xxxx 0101
xxxx 0100
xxxx 0011
xxxx 0010
F
E
D
C
B
A
9
8
7
6
5
4
3
2
Instruction Description
UM001602-0904
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305
Register Pointer (FDh)
Contents (Hex)
Expanded Register
Bank (Hex)
xxxx 0001
xxxx 0000
1
0
Flag
C
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Z
S
V
D
H
Note: When an Expanded Register Bank , other than Bank 0 is selected, access
®
to the Z8 Standard Register File is possible except for the Port Register
and general purpose registers 04hto 0Fh.
fpr Register Addresses 0h to Fh
Example
The statement:
SRP F0h Op Code: 31 F0
sets the Register Pointer to access expanded Register Bank 0 and Working
®
Register Group F in the Z8 Standard Register File. All references to
Working Registers now affect this group of 16 registers. Registers F0hto
FFhcan be accessed as Working Registers R0 to R15.
Example
The statement:
SRP 0Fh
Op Code: 31 0F
UM001602-0904
Instruction Description
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306
sets the Register Pointer to access Expanded Register Bank F, Reg ← to
Reg 0Fh, as the current Working Registers. All references to Working
Registers now affect this group of 16 registers. These registers are now
accessed as Working Registers R0 to R15. Port Registers are now not
accessable.
Example
Assume the RP currently addresses the Control and Peripheral Working
Register Group and the program has just entered an interrupt service rou-
tine. The statement:
SRP 70h
Op Code: 31 70
retains the contents of the Control and Peripheral Registers by setting the
RP to 70h(01110000b). Any reference to Working Registers in the inter-
rupt routine will point to registers 70hto 7Fh.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
307
Shift Right Arithmetic
SRA dst
Instruction Format
OPC
(Hex)
D0
Address Mode
Cycles
dst
R
IR
6
6
OPC
dst
D1
Operation
C ← dst(0)
dst(0) ← dst(1)
dst(1) ← dst(2)
dst(2) ← dst(3)
dst(3) ← dst(4)
dst(4) ← dst(5)
dst(5) ← dst(6)
dst(6) ← dst(7)
dst(7) ← dst(7)
An arithmetic shift right by one bit position is performed on the destina-
tion operand. Bit 0 replaces the C Flag. Bit 7 (the Sign bit) is unchanged
and its value is shifted into bit 6, as shown below.
D7 D6 D5 D4 D3 D2 D1 D0
C
UM001602-0904
Instruction Description
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308
Flag
Description
C
Set if the bit rotated from the least significant bit position was 1
(i.e., bit 0 was 1).
Z
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to 0.
Unaffected
Unaffected
S
V
D
H
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, destination Working Register operand is specified by adding
1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If the contents of Working Register R6 are 31h(00110001B), the state-
ment:
SRA R6
Op Code: D0 E6
leaves the value 98h(00011000) in Working Register R6. The C Flag is
set, and the Z, V, and S flags are cleared.
Example
If Register C6 contains the value DFh, and Register DFhcontains the
value B8h (10111000B), the statement:
SRA @C6
Op Code: D1 C6
leaves the value DCh (11011100B) in Register DFh. The C, Z, and V
Flags are reset, and the S Flag is set.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
309
Stop
STOP
Instruction Format
OPC
Cycles
(Hex)
OPC
6
6F
Operation
This instruction turns off the internal system clock (SCLK) and external
crystal (XTAL) oscillation, and reduces the standby current. STOP mode
is terminated by a RESET which causes the processor to restart the appli-
cation program at address 000Ch.
Flag
C
Z
S
V
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
D
H
Note: In order to enter STOP mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction. The user must
execute a NOP immediately before the execution of the STOP instruction.
Example
The statements:
NOP
STOP
Op Codes: FF 6F
®
place the Z8 CPU into STOP mode.
UM001602-0904
Instruction Description
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User Manual
310
Subtract
SUB dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
src
6
6
22
23
r
r
r
lr
OPC
OPC
OPC
dst src
10
10
24
25
R
R
R
IR
src
dst
dst
src
10
10
26
27
R
IR
IM
IM
Operation
dst ← dst–src
The source operand is subtracted from the destination operand and the
result is stored in the destination operand. The contents of the source
operand are not affected. Subtraction is performed by adding the two’s
complement of the source operand to the destination operand.
Flag
Description
C
Cleared if there is a carry from the most significant bit of the
result; set otherwise, indicating a borrow.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred (if the operands were of
opposite sign and the sign of the result is the same as the sign of
the source); reset otherwise.
Z
V
S
H
Set if the result is negative; cleared otherwise.
Cleared if there is a carry from the most significant bit of the low
order four bits of the result; set otherwise indicating a borrow.
Always set to 1.
D
Instruction Description
UM001602-0904
Z8 CPU
User Manual
311
Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
Note:
E
src
or
E
dst
Example
]If Working Register R3 contains 16h, and Working Register R11 con-
tains 20h, the statement:
SUB R3, R11
Op Code: 22 3B
leaves the value F6h in Working Register R3. The C, S, and D Flags are
set, and the Z, V, and H flags are cleared.
Example
If Working Register R15 contains 16h, Working Register R10 contains
20h, and Register 20hcontains 11h, the statement:
SUB R16, @R10
Op Code: 23 FA
leaves the value 05hin Working Register R15. The D Flag is set, and the
C, Z, S, V, and H flags are cleared.
Example
If Register 34hcontains 2Eh, and Register 12hcontains 1Bh, the state-
ment:
SUB 34h, 12h
Op Code: 24 12 34
leaves the value 13hin Register 34h. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
312
Example
If Register 4Bhcontains 82h, Working Register R3 contains 10h, and
Register 10hcontains 01h, the statement:
SUB 4Bh, @R3
Op Code: 25 E3 4B
leaves the value 81h in Register 4Bh. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
Example
If Register 6Chcontains 2Ah, the statement:
SUB 6Ch, #03h
Op Code: 26 6C 03
leaves the value 27hin Register 6Ch. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
Example
If Register D4hcontains 5Fh, Register 5Fhcontains 4Ch, the statement:
SUB @D4h, #02h
Op Code: 17 D4 02
leaves the value 4Ahin Register 5Fh. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
313
Subtract With Carry
SBC dst, src
Instruction Format
Address
Mode
OPC
Cycles (Hex)
dst
r
r
src
r
lr
6
6
32
33
OPC
OPC
dst src
src
10
10
34
35
R
R
R
IR
dst
src
10
10
36
37
R
IR
IM
IM
OPC
dst
Operation
dst ← dst–src–C
The source operand, along with the setting of the C Flag, is subtracted
from the destination operand and the result is stored in the destination
operand. The contents of the source operand are not affected. Subtraction
is performed by adding the two’s complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction
permits the carry (borrow) from the subtraction of low order operands to
be subtracted from the subtraction of high order operands.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
314
Flag
Description
C
Cleared if there is a carry from the most significant bit of the
result; set otherwise, indicating a borrow.
Set if the result is 0; cleared otherwise.
Set if arithmetic overflow occurred (if the operands were of
opposite sign and the sign of the result is the same as the sign of
the source); reset otherwise.
Z
V
S
H
Set if the result is negative; cleared otherwise.
Cleared if there is a carry from the most significant bit of the low
order four bits of the result; set otherwise indicating a borrow.
Always set to 1.
D
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
Working Register R3 contains 16h, the C Flag is set to 1, and Working
Register R11 contains 20h, the statement:
SBC R3, R11
Op Code: 32 3B
leaves the value F5hin Working Register R3. The C, S, and D Flags are
set, and the Z, V, and H Flags are all cleared.
Example
If Working Register R15 contains 16h, the C Flag is not set, Working
Register R10 contains 20h, and Register 20hcontains 11h, the statement:
SBC R16, @R10
Op Code: 33 FA
Instruction Description
UM001602-0904
Z8 CPU
User Manual
315
leaves the value 05hin Working Register R15. The D Flag is set, and the
C, Z, S, V, and H flags are cleared.
Example
:If Register 34hcontains 2Eh, the C Flag is set, and Register 12hcon-
tains 1Bh, the statement:
SBC 34h, 12h
Op Code: 34 12 34
leaves the value 13hin Register 34h. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
Example
If Register 4Bhcontains 82h, the C Flag is set, Working Register R3 con-
tains 10h, and Register 10hcontains 01h, the statement:
SBC 4Bh, @R3
Op Code: 35 E3 4B
leaves the value 80hin Register 4Bh. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
Example
If Register 6Chcontains 2Ah, and the C Flag is not set, the statement:
SBC 6Ch, #03h
Op Code: 36 6C 03
leaves the value 27hin Register 6Ch. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
Example
If Register D4hcontains 5Fh, Register 5Fhcontains 4Ch, and the C Flag
is set, the statement:
SBC @D4h, #02h
Op Code: 37 D4 02
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
316
leaves the value 4Ahin Register 5Fh. The D Flag is set, and the C, Z, S, V,
and H flags are cleared.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
317
Swap Nibbles
SWAP dst
Instruction Format
OPC
(Hex)
F0
Address Mode
Cycles
dst
R
IR
6
6
OPC
dst
F1
Operation
dst(7-4) ↔ dst(3-0)
The contents of the lower four bits and upper four bits of the destination
operand are swapped.
Flag
C
Description
Unaffected
Z
Set if the result is zero; cleared otherwise.
S
Set if the result bit 7 is set; cleared otherwise.
V
D
H
Undefined
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, destination Working Register operand is specified by adding
1110b(Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then EChwill be used as the
destination operand in the Op Code.
E
dst
Example
If Register BChcontains B3h(10110011B), the statement:
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
318
SWAP B3h
Op Code: F0 B3
will leave the value 3Bh(00111011B) in Register BCh. The Z and S flags
are cleared.
Example
If Working Register R5 contains BChand Register BChcontains B3h
(10110011B), the statement:
SWAP @R5h
Op Code: F1 E5
will leave the value 3Bh(00111011B) in Register BCh. The Z and S flags
are cleared.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
319
Test Complement Under Mask
TCM dst, src
Instruction Format
Address Mode
OPC
Cycles (Hex)
dst
r
r
src
r
lr
6
6
62
63
OPC
OPC
OPC
dst src
src
10
10
64
65
R
R
R
IR
dst
src
10
10
66
67
R
IR
IM
IM
dst
Operation
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logical
1 value. The bits to be tested are specified by setting a 1 bit in the corre-
sponding bit position in the source operand (the mask). The TCM instruc-
tion complements the destination operand, and then ANDs it with the
source mask (operand). The Zero (Z) Flag can then be checked to deter-
mine the result. If the Z Flag is set, then the tested bits were 1. When the
TCM operation is complete, the destination and source operands still con-
tain their original values.
Flag
Z
S
Description
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to 0.
V
D
Unaffected
H
Unaffected
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
320
Address modes R or IR can be used to specify a 4-bit Working Register. In
Note:
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
E
src
or
E
dst
Example
If Working Register R3 contains 45h(01000101b) and Working Register
R7 contains the value 01h(00000001b) (bit 0 is being tested if it is 1),
the statement:
TCM R3, R7
Op Code: 62 37
will set the Z Flag indicating bit 0 in the destination operand is 1. The V
and S flags are cleared.
Example
If Working Register R14 contains the value F3h(11110011b), Working
Register R5 contains CBh, and Register CBhcontains 88h(10001000b)
(bit 7 and bit 3 are being tested if they are 1), the statement:
TCM R14, @R5
Op Code: 63 E5
will reset the Z Flag, because bit 3 in the destination operand is not a 1.
The V and S Flags are also cleared.
Example
If Register D4hcontains the value 04h(000001000b), and Working Reg-
ister R0 contains the value 80h(10000000b) (bit 7 is being tested if it is
1), the statement:
TCM D4h, R0
Op Code: 64 E0 D4
Instruction Description
UM001602-0904
Z8 CPU
User Manual
321
will reset the Z Flag, because bit 7 in the destination operand is not a 1.
The S flag will be set, and the V flag will be cleared.
Example
If Register DFhcontains the value FFh(11111111b), Register 07hcon-
tains the value 1Fh, and Register 1Fhcontains the value BDh
(10111101b) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if
they are 1), the statement:
TCM DFh, @07h
Op Code: 65 07 DF
will set the Z Flag indicating the tested bits in the destination operand are
1. The S and V flags are cleared.
Example
If Working Register R13 contains the value F2h(11110010b), the state-
ment:
TCM R13, #02h
Op Code: 66 ED, 02
tests bit 1 of the destination operand for 1. The Z flag will be set indicat-
ing bit 1 in the destination operand was 1. The S and V flags are cleared.
Example
If Register 5Dhcontains A0h, and Register A0hcontains 0Fh
(00001111b), the statement:
TCM @5D, #10h
Op Code: 67 5D 10
tests bit 4 of the Register A0hfor 1. The Z flag will be reset indicating bit
1 in the destination operand was not 1. The S and V flags are cleared.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
322
Test Under Mask
TM dst, src
Instruction Format
Address Mode
OPC
Cycles (Hex)
dst
r
r
src
r
lr
6
6
72
73
OPC
OPC
OPC
dst src
10
10
74
75
R
R
R
IR
src
dst
dst
src
10
10
76
77
R
IR
IM
IM
Operation
dst AND src
This instruction tests selected bits in the destination operand for a 0 logi-
cal value. The bits to be tested are specified by setting a 1 bit in the corre-
sponding bit position in the source operand (the mask). The TM
instruction ANDs the destination operand with the source operand (the
mask). The Zero (Z) Flag can then be checked to determine the result. If
the Z Flag is set, then the tested bits were 0. When the TM operation is
complete, the destination and source operands still contain their original
values.
Flag
Z
S
Description
Set if the result is zero; cleared otherwise.
Set if the result bit 7 is set; cleared otherwise.
Always reset to 0.
V
D
Unaffected
H
Unaffected
Instruction Description
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Z8 CPU
User Manual
323
Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
fied by adding 1110b(Eh) to the high nibble of the operand. For example,
if Working Register R12 (CH) is the destination operand, then EChwill be
used as the destination operand in the Op Code.
Note:
E
src
or
E
dst
Example
If Working Register R3 contains 45h(01000101b) and Working Register
R7 contains the value 02h(00000010b) (bit 1 is being tested if it is 0),
the statement:
TM R3, R7
Op Code: 72 37
will set the Z Flag indicating bit 1 in the destination operand is 0. The V
and S flags are cleared.
Example
Working Register R14 contains the value F3h(11110011b), Working
Register R5 contains CBh, and Register CBhcontains 88h(10001000b)
(bit 7 a bit 3 are being tested if they are 0), the statement:
TM R14, @R5
Op Code: 73 E5
will reset the Z Flag, because bit 7 iin the destination operand is not a 0.
The S flag will be set, and the V Flag is cleared.
Example
If Register D4hcontains the value 08h(00001000b), and Working Reg-
ister R0 contains the value 04h(00000100b) (bit 2 is being tested if it is
0), the statement:
TM D4h, R0
Op Code: 74 E0 D4
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
324
will set the Z Flag, because bit 2 in the destination operand is a 0. The S
and V Flags will be cleared.
Example
If Register DFhcontains the value ← (00000000b), Register 07hcon-
tains the value 1Fh, and Register 1Fhcontains the value BDh
(10111101b) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if
they are 0), the statement:
TM DFh, @07h
Op Code: 75 07 DF
will set the Z Flag indicating the tested bits in the destination operand are
0. The S is set, and the V Flag is cleared.
Example
If Working Register R13 contains the value F1h(11110001b), the state-
ment:
TM R13, #02h
Op Code: 76 ED, 02
tests bit 1 of the destination operand for 0. The Z flag will be set indicat-
ing bit 1 in the destination operand was 0. The S and V flags are cleared.
Example
If Register 5Dhcontains A0h, and Register A0hcontains 0Fh
(00001111b), the statement:
TM @5D, #10h
Op Code: 77 5D 10
tests bit 4 of the Register A0hfor 0. The Z flag will be set indicating bit 4
in the destination operand was 0. The S and V flags are cleared.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
325
Watch-Dog Timer
WDT
Instruction Format
OPC
Cycles
(Hex)
OPC
6
5F
Operation
The WDT (Watch–Dog Timer) is a retriggerable one shot timer that will
®
reset the Z8 CPU if it reaches its terminal count. The WDT is initially
enabled by executing the WDT instruction. Each subsequent execution of
the WDT instruction refreshes the timer and prevents the WDT from tim-
ing out.
Flag
Z
S
V
D
Description
Undefined
Undefined
Undefined
Unaffected
Unaffected
H
Note: The WDT instruction should not be used following any instruction in
which the condition of the flags is important.
Example
If the WDT is enabled, the statement:
WDT
Op Code: .BYTE 5Fh
refreshes the Watch–Dog Timer.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
326
Example
The first execution of the statement:
WDT
Op Code: .BYTE 5Fh
enables the Watch–Dog Timer.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
327
Watch-Dog Timer Enable During Halt Mode
WDh
Instruction Format
OPC
Cycles
(Hex)
OPC
6
4F
Operation
When this instruction is executed it will enable the WDT (Watch–Dog
Timer) during HALT mode. If this instruction is not executed the WDT
will stop when entering HALT mode. This instruction does not clear the
counter, it just makes it possible to have the WDT function running during
HALT mode. A WDh instruction executed without executing WDT (5Fh)
has no effect.
Flag
Z
S
V
D
Description
Undefined
Undefined
Undefined
Unaffected
Unaffected
H
Note: The WDh instruction should not be used following any instruction in
which the condition of the flags is important.
Example
If the WDT is enabled, the statement:
WDh
Op Code: .BYTE 4Fh
will enable the WDT in HALT mode.
UM001602-0904
Instruction Description
Z8 Family of Microcontrollers
User Manual
328
Note: This instruction format is valid only for the Z86C04, Z86C08, Z86E04,
Z86E07, and Z86E08 MCUs.
Instruction Description
UM001602-0904
Z8 CPU
User Manual
329
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Product Information
Z8 CPU
Serial # or Board Fab #/Rev. #
Software Version
1.1.0
Document Number
UM001602-0904
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