Z87001_技术文档

PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION

1

Z87001/Z87L01

1

ROMLESS SPREAD SPECTRUM

CORDLESS PHONE CONTROLLER

FEATURES

■ Transceiver Circuitry Provides Primary Cordless Phone

ROM *

RAM

I/O

Package

Communications Functions

Device (KWords) (Words) Lines Information

–

Digital Downconversion with Automatic Frequency

Control (AFC) Loop

Z87001

Z87L01

64

512

32

144-Pin QFP

–

FSK Demodulator

FSK Modulator

Note: *Maximum accessible external ROM

Symbol Synchronizer

■ Transceiver/Controller Chip Optimized for Implement-

Time Division Duplex (TDD) Transmit and Receive

Buffers

ation of 900 MHz Spread Spectrum Cordless Telephone

–

Adaptive Frequency Hopping

Transmit Power Control

■ On-Chip A/D and D/A to Support 10.7 MHz IF Interface

Error Control Signaling

■ Up to 64 Kw of External Program Memory Accessible by

Handset Power Management

the DSP Core

Support of 32 kbps ADPCM Speech Coding for

High Voice Quality

■ Bus Interface to Z87010 ADPCM Processor

■ Static CMOS for Low Power Consumption

■ DSP Core Acts as Phone Controller

–

Zilog-Provided Embedded Transceiver Software to

Control Transceiver Operation and Base Station-

Handset Communications Protocol

■ 3.0V to 3.6V, -20°C to +70°C, Z87L01

4.5V to 5.5V, -20°C to +70°C, Z87001

–

User-Modiﬁable Software Governs Telephone

Features

■ 16.384 MHz Base Clock

GENERAL DESCRIPTION

The Z87001 /Z87L01 FHSS Cordless Telephone Trans-

ceiver/Controller is expressly designed to implement a 900

MHz frequency hopping spread spectrum cordless tele-

phone compliant with US FCC regulations for unlicensed

operation. The Z87001 and Z87L01 are distinct 5V and

3.3V versions, respectively, of the core device. For the

sake of brevity, all subsequent references to the Z87001 in

this document also apply to the Z87L01 unless specifically

noted.

The Z87001 supports a specific cordless phone system

design that uses frequency hopping and digital modulation

to provide extended range, high voice quality, and low sys-

tem costs.

The Z87001 uses a Zilog 16-bit fixed-point two’s comple-

ment static CMOS Digital Signal Processor core as the

phone and RF section controller. The Z87001’s DSP core

processor further supports control of the RF section’s fre-

quency synthesizer for frequency hopping and the genera-

tion of the control messages needed to coordinate incorpo-

ration of the phone’s handset and base station. Additional

on-chip transceiver circuitry supports Frequency Shift Key-

ing modulation/demodulation and multiplexing/demulti-

The Z87001 is the ROMless version of the Z87000 Spread

Spectrum Controller IC. Specifically intended to facilitate

user specific software development, the Z87001 can ac-

cess up to 64 kwords of external program ROM.

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

GENERAL DESCRIPTION (Continued)

plexing of the 32 kbps voice data and 4 kbps command

data between handset and base station. The Z87001 pro-

vides thirty-two I/O pins, including four wake-up inputs and

two CPU interrupt inputs. These programmable I/O pins al-

low a variety of user-determined phone features and board

layout configurations. Additionally, the pins may be used

so that phone features and interfaces are supported by an

optional microcontroller rather than by the Z87001’s DSP

core.

In combination with an RF section designed according to

the system specifications, Zilog’s Z87010/Z87L10 ADPCM

Processor, a standard 8-bit PCM telephone codec and

minimal additional phone circuity, the Z87001 and its em-

bedded software provide a total system solution.

Codec

Z87010

Z87001

Z87010

RF Section

ADPCM

Processor

Spread

Spectrum

Controller

Spread

Spectrum

Controller

ADPCM

Processor

Telephone

Line

Interface

Handset

Base Station

Figure 1. System Block Diagram of a Z87001/Z87010 Based Phone

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P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

FSK Demodulator

Receive

RX

VREF

ADC

(1-bit)

(downconverter, limiter discriminator,

AFC, bit sync, frame sync, SNR

detector)

VXDATA[7..0]

Rate

1

Buffer

VXADD[2..0]

Z87010

VXSTRB

VXRWB

VXRDYB

Interface

CLKOUT

CODCLK

Transmit

Rate

Buffer

DAC

(4-bit)

FSK Modulator

TX

RXSW

TXSW

PAON

256 Word

RAM 0

256 Word

RAM 1

Port 0

RFEON

SYLE

P0[15..0]

P1[15..0]

Frame Counter(s),

Event Trigger,

T/R Switch Ctrl,

Power On/Off Ctrl,

Antenna Select

ADC

RSSI

DSP Core

(8-bit)

DAC

(4-bit)

PWLV

Port 1

ANT0

ANT1

Addr[15..0]

Data[15..0]

AVDD

HBSW

RESETB

TEST

Analog

Power

AGND

VDD

GND

Digital

Power

Figure 2. Z87001 Functional Block Diagram

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P R E L I M I N A R Y

3

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

PIN DESCRIPTION

VXDATA0

data0

VXDATA1

data1

VXDATA2

data2

VDD

VXDATA3

data3

VXDATA4

data4

VXDATA5

data5

VXDATA6

VXDATA7

data6

TX

109

1

AGND

RX

AVDD

VREF

RFEON

addr12

P115

addr11

GND

addr10

P114

addr9

P113

addr8

P112

CLKOUT

data7

HBSW

data8

GND

TEST

Z87001

addr7

VDD

addr6

P111

addr5

P110

VDD

data9

ANT0

data10

ANT1

data11

P00

addr4

P19

addr3

GND

addr2

P18

addr1

P17

addr0

P01

data12

P16

idata15

VDD

GND

data13

P02

data14

idata14

73

37

P15

P03

Figure 3. 144 Pin QFP Pin Conﬁguration

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 1. 144 Pin QFP Pin Conﬁguration

Symbol Function

No

Direction

1

TX

AGND

RX

Analog transmit IF signal

Analog ground

Output

1

2,141

3

–

Input

–

Analog receive IF signal

Analog power supply

4,144

AV

DD

5

6

VREF

RFEON

Analog reference voltage for RX signal

RF on/off control

–

Output

7,9,11,13,15,17,19,

21,23,25,27,29,31,

136,138,140

addr[15..0]

DSP core program address bus

8,12,14,16,20,22,24,

28,30,32,36,37,39,

41,44,46

P1[15..0]

GND

General-purpose I/O port 1

Input/Output

10,26,43,60,77,88,

109,128

Digital ground

–

18,34,51,68,86,102,

116,131

V

Digital power supply

DSP core internal data bus

DD

33,35,38,40,42,45,

47,49,52,54,56,59,

61,63,66,69

idata[15..0]

P0[15..0]

Output

48,50,53,55,57,58,

62,64,65,67,70,72,

73,75,79,80

General-purpose I/O port 0

DSP core program data bus

Input/Output

Input

71,74,76,78,81,83,

85,89,91,93,96,98,

100,103,105,107

data[15..0]

82,84

87

ANT[1..0]

TEST

RF antenna diversity control

Test mode select

Output

Input

90

HBSW

Handset/base mode select

Clock, ADPCM processor (16.384 MHz)

ADPCM processor data bus

Input

92

CLKOUT

VXDATA[7..0]

Output

Input

94,95,97,99,101,

104,106,108

110

111

112

VXRDYB

eib

ADPCM processor ready

Output

Input

External register data strobe

ADPCM processor data strobe

External register address bus

VXSTRB

iaddr[4..0]

113,117,119,121,

123

Output

114

VXRWB

trice

ADPCM processor read/write control

ROMless mode select

Input

115

118,120,122

124

VXADD[2..0]

CODCLK

irwb

ADPCM processor address bus

Clock to codec (2.048 MHz)

External register read/write control

Master reset

Input

Output

Input

125

126

/RESETB

intenb

127

Interrupt enable

Input

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

PIN DESCRIPTION (Continued)

Table 1. 144 Pin QFP Pin Conﬁguration

No

Symbol

Function

Direction

129

130

132

133

134

135

137

139

142

143

halt

Halt/ single step control

Master clock (16.384 MHz)

Program address bus enable

RF transmit enable

Input

MCLK

triadd

PAON

dspclk

SYLE

RXSW

TXSW

PWLV

RSSI

Input

Output

Input

DSP core clock

RF synthesizer load enable

Demodulator “on” indication

RF receive enable

RF transmit power level

RF receive signal strength indicator

Input

6

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This is a stress rating only; operation of the device at

any condition above those indicated in the operational sec-

tions of these specifications is not implied. Exposure to ab-

solute maximum rating conditions for extended period may

affect device reliability.

Symbol Parameter

, AV DC Supply

Min

Max

Units

1

V

-0.5

7.0

V

DD

Voltage(1)

V

Input Voltage(2)

-0.5 V + 0.5

V

IN

DD

Output Voltage(3)

-0.5 V + 0.5

DD

OUT

T

Operating

-20

+70

°C

A

Temperature

T

Storage

-65

+150

°C

STG

Temperature

Notes:

1. Voltage on all pins with respect to GND.

2. Voltage on all inputs WRT VDD

3. Voltage on all outputs WRT VDD

STANDARD TEST CONDITIONS

The electrical characteristics listed below apply for the fol-

lowing standard test conditions, unless otherwise noted.

All voltages are referenced to GND. Positive current flows

into the referenced pins. Standard test conditions are as

follows:

IoL

Output

■ 3.0V < V < 3.6V (Z87L01)

Threshold

Under

DD

Voltage

Test

■ 4.5V < V < 5.5V (Z87001)

DD

50pF

■ GND = 0V

■ T = -20 to +70 °C

A

IoH

Figure 5. Test Load Diagram

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7

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

RECOMMENDED OPERATING CONDITIONS

Table 3. 5V ± 0.5V Operation (Z87001)

Symbol

, AV

Parameter

Min

4.5

Max

Units

V

Supply Voltage

5.5

V

DD

IH

IL

DD

Input High Voltage

Input Low Voltage

2.0

V

+ 0.3

V

DD

GND -0.3

0.8

-2.0

-0.5

4.0

V

I

Output High Current

mA

°C

OH

Output High Current, ICE pins (1)

Output Low Current

OHICE

OL1

Output Low Current, GPIO (limited usage, 2)

Output Low Current, ICE pins (1)

Operating Temperature

12.0

0.5

OL2

OLICE

T

-20

+70

A

Notes:

1. ICE pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb

2. Maximum 3 pins total from P0[15..0] and P1[15..0]

Table 4. 3.3V ± 0.3V Operation (Z87L01)

Symbol

Parameter

Min

Max

Units

V

Supply Voltage

3.0

3.6

DD

IH

IL

Input High Voltage

0.7 V

V

+0.3

V

DD

Input Low Voltage

GND -0.3

0.1 V

V

DD

I

Output High Current

-1.0

-0.5

2.0

mA

°C

OH

Output High Current, ICE pins (1)

Output Low Current

OHICE

OL1

Output Low Current, Ports (limited usage, 2)

Output Low Current, ICE pins (1))

Operating Temperature

6.0

OL2

0.5

OLICE

T

-20

+70

A

Notes:

1. ICE pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb

2. Maximum 3 pins total from P0[15..0] and P1[15..0]

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P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

DC ELECTRICAL CHARACTERISTICS

Conditions for DC characteristics are corresponding oper-

ating conditions, and standard test conditions, unless oth-

erwise specified.

1

Table 5. 5V ± 0.5V Operation (Z87001)

Test Condition

min, I max

Symbol

Parameter

Min

2.4

Max

Units

V

Output High Voltage

V

DD

OH

V

Output High Voltage, ICE pins (1) V min, I max

OHICE

V

OHICE

OL1

DD

Output Low Voltage

V

min, I

max

0.6

1.2

0.4

2

V

DD

OL1

Output Low Voltage, GPIO (2)

max

V

OL2

Output Low Voltage, ICE pins (1) V min, I

max

V

OLICE

DD

OLICE

I

Input Leakage

V

= 0V, V

DD

-2

µA

mA

L

IN

Supply Current

80

4

CC

Standby Mode Current (3)

CC2

Notes:

1. ICE pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb

2. Maximum 3 pins total from P0[15..0] and P1[15..0]

3. 2.3 mA typical at 25°C, 5 volts.

Table 6. 3.3V ± 0.3V Operation (Z87L01)

Test Condition Min

min, I max

Symbol

Parameter

Max

Units

V

Output High Voltage

V

1.6

OH

DD

OH

Output High Voltage, ICE pins (1)V min, I max

OHICE

V

OHICE

OL1

DD

Output Low Voltage

V

min, I

max

0.4

1.2

0.4

2

V

DD

OL1

Output Low Voltage, Ports(2)

max

V

OL2

Output Low Voltage, ICE pins (1) V min, I

max

V

OLICE

DD

OLICE

I

Input Leakage

V

= 0V, V

DD

-2

µA

mA

L

IN

Supply Current

55

CC

Standby Mode Current(2)

1.4

CC2

Notes:

1. ICE pins are addr[15..0], iaddr[15..0], idata[15..0], eib and irwb

2. Maximum 3 pins total from P0[15..0] and P1[15..0]

3. 1.6 mA typical at 25°C, 3.3 volts.

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

ANALOG CHARACTERISTICS

Table 7. 1-Bit ADC (Temperature: -20/+70°C)

Parameter

Minimum

Typical

Maximum

Units

Resolution

-

1

-

bit

Power dissipation

0.54

1.0

2.75

mW

(70°c)

(40°c)

(-20°c)

Power dissipation, Stop mode

0.06

0.2

1.1

mW

(70°c)

(40°c)

(-20°c)

Sample frequency

Sample window(1)

Bandwidth

-

29

-

8.192

31

-

33

-

MHz

ns

60

MHz

Supply Range(=AV

)

DD

3.0

4.5

3.6

5.5

V

Z87L01

Z87001

Acquisition time

Settling time

2

8

3

10

6

8

18

ns

Conversion time

Aperture delay

4

18

ns

2

3

8.5

0.5

1200

ns

Aperture uncertainty(2)

Input voltage range (p-p)

-

ns

800

1000

mV

Reference voltage

Z87L01

Z87001

1.7 (AV = 3V) 1.9 (AV = 3.3V) 2.1 (AV = 3.6V)

V

DD

2.7 (AV =4.5V) 3.0 (AV = 5V) 3.3 (AV = 5.5V)

DD

10

-

DD

25

-

Input resistance

Input capacitance

Notes:

18

10

KOhm

pF

Window of time while input signal is applied to sampling capacitor; see next figure.

Uncertainty in sampling time due to random variations such as thermal noise.

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

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CLK (16.384MHz)

1

Aperture

Delay

Sampling

SAMPLING

WINDOW

Latched

Output

INPUT

SIGNAL

Conversion

Acquisition

Time

Settling

Time

+

Time (for

digital output)

Figure 6. 1-Bit ADC Deﬁnition of Terms

Table 8. 8-bit ADC (Temperature -20/+70°C)

Parameter

Minimum

Typical

Maximum

Units

Resolution

-

6

0.5

-

1

bit

LSB

mW

ns

Integral non-linearity

Differential non-linearity

Power Dissipation (peak)

Sample window

0.5

70

120

2

35

-

5

-

Bandwidth

-

Msps

Supply Range (=AV

)

DD

3.0

4.5

3.3

5.0

3.6

5.5

V

Z87L01

Z87001

Input voltage range

0-AV

V

DD

Conversion time

Aperture delay

0.5

-

3

-

8.5

1

µs

ns

2

-

Aperture uncertainty

Input resistance

Input capacitance

Notes:

ns

-

25

10

-

Kohm

pF

-

1. 8-bit ADC only tested for 6-bit resolution.

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 9. 4-bit DAC (Temperature: -20/+70°C)

Parameter

Minimum

Typical

Maximum

Units

Resolution

-

4

0.25

-

0.5

1

bit

LSB

ns

Integral non-linearity

Differential non-linearity

Settling time (1/2 LSB)

Zero error at 25°C

-

22.5

2

-

1

mV

ns

Conversion time (input change to output change)

Power dissipation, 25 pF load

14

19

76

1.2

20

24.1

mW

(70°c)

(40°c)

(-20°c)

Power dissipation, 25 pF load, Stop mode

0.18

1.0

1.1

mW

(70°c)

(40°c)

(-20°c)

Conversion time (input change to output change)

Rise time (full swing)

14.5

11

8

19.1

15

75.8

71

96

-

ns

Output slew rate

67

V/µs

V

Output voltage range

-

0.2 AV to 0.6AV

DD

Supply Range (=AV

)

DD

3.0

4.5

3.3

5.0

3.6

5.5

V

Z87L01

Z87001

Output load resistance

Output load capacitance

330

25

Ohm

pF

-

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DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

INPUT/OUTPUT PIN CHARACTERISTICS

All digital pins (all pins except V , AV , GND, AGND,

The RX analog input pin has an input capacitance of 10

pF.

DD

V

, RX, TX, RSSI and PWLV) have an internal capaci-

REF

1

tance of 5 pF.

The RSSI analog input pin has an input capacitance of 10

pF.

AC ELECTRICAL CHARACTERISTICS

Clocks, Reset and RF Interface

Table 10. Clocks, Reset and RF Interface

Parameter

MCLK input clock period (1)

No.

Symbol

Min

Max

Units

1

TpC

TwC

61

20

61

40

15

6

ns

2

MCLK input clock pulse width

MCLK input clock rise/fall time

CLKOUT output clock rise/fall time

CODCLK output clock rise/fall time

RESETB input low width

3

TrC, TfC

ns

4

TrCC, TfCC

TrCO, TfCO

TwR

2

ns

5

6

ns

6

7

18

2

TpC

ns

TrRF, TfRF

RF output controls rise/fall time (2)

6

Notes:

1. MCLK is 16.384 MHz ± 25 ppm

2. RF Controls are PAON, TXSW, RFEON, SYLE.

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

READ CYCLES refer to data transfers from the Z87001 to

the ADPCM Processor.

ADPCM Processor Interface

The Z87001 is a peripheral device for the ADPCM Proces-

sor. The interface from the Z87001 perspective is com-

posed of an input address bus, a bidirectional data bus,

strobe and read/write input control signals and a

ready/wait output control signal.

WRITE CYCLES refer to data transfers from the ADPCM

Processor to the Z87001.

Table 11. Read Cycles

Signal Name

Function

Direction

VXADD[2..0]

VXDATA[7..0]

VXSTRB

Address Bus

Data Bus

ADPCM Proc. to Z87001

Bidirectional

Strobe Control Signal

Read/Write Control Signal

Ready Control Signal

ADPCM Proc. to Z87001

Z87001 to ADPCM Proc.

VXRWB

VXRDYB

Table 12. Write Cycles

Parameter

No.

Symbol

Min

Max

Units

8

9

TsAS

ThSA

Address, Read/Write setup time before Strobe falls

Address, Read/Write hold time after Strobe rises

Data read access time after Strobe falls

Data read hold time after Strobe rises

Strobe pulse width

10

3

ns

10

TaDrS

ThDrS

TwS

30 (1)

40 (2)

11

8.5

20

10

3

12

13

TsDwS

ThDwS

TaDrRY

TdSRY

Data write setup time before Strobe rises

Data write hold time after Strobe rises

Data read valid before Ready falls

ns

14

15

22

0

16

Strobe high after Ready falls

Notes:

1. Requires wait state on ADPCM Processor read cycles

2. Requires no write cycle directly following read cycle on ADPCM Processor

14

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

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AC TIMING DIAGRAMS

TwC(2)

1

MCLK

TrC(3)

TfC(3)

TpC (1)

CLKOUT

CODCLK

TfCC(4)

TrCC(4)

TrCO(5)

TfCO(5)

4

16

18

1

2

3

17

MCLK

RESETB

TwR(6)

PAON

TXSW

RXSW

RFEON

SYLE

TfRF(7)

TrRF(7)

Figure 7. Transceiver Output Signal

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15

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

TsAS(8)

ThSA(9)

VXADD

VXRWB

VXSTRB

TaDrS(10)

ThDrS(11)

VXDATA

VXRDYB

VXDATA Read Cycle

TsAS(8)

ThSA(9)

VXADD

VXRWB

TwS(12)

VXSTRB

VXDATA

ThDwS(14)

TsDwS(13)

VXRDYB

VXDATA Write Cycle

Figure 8. Read/Write Cycle TImings

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Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

TsAS(8)

ThSA(9)

1

VXADD

VXRWB

VXSTRB

VXDATA

ThDrS(11)

TaDrRY(15)

TdSRY(16)

VXRDYB

VXDATA Read Cycle with Wait State

TsAS(8)

ThSA(9)

VXADD

VXRWB

TwS(12)

VXSTRB

ThDwS(14)

TsDwS(13)

VXDATA

VXRDYB

TdSRY(16)

VXDATA Write Cycle with Wait State

Figure 9. Read/Write Cycle Timing with Wait StatE

DS96WRL0800

P R E L I M I N A R Y

17

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

PIN FUNCTIONS

V

Digital power supply.

CLKOUT (output). Clock output for external ADPCM pro-

DD.

cessor.

GND. Digital ground.

CODCLK (output). Clock output for external voice codec.

/RESETB (input, active low). Reset signal.

AV . Analog power supply.

DD

AGND. Analog ground.

VXADD[2..0] (input). Address bus controlled by external

ADPCM processor. The Z87001 acts as peripheral of the

Z87010 ADPCM processor.

V

(analog reference). This signal is the reference volt-

REF

age used by the high speed analog comparator to sample

the RX input signal.

VXDATA[7..0](input/output). Read/write data bus con-

trolled by external Z87010 ADPCM processor.

RX (analog input). This is the RX IF receive signal from

the RF module, input to the analog comparator and FSK

demodulator. It is internally biased to the V

DC voltage.

VXSTRB (input). Data strobe signal for the VXDATA bus,

REF

The IF signal from the RF module should be AC coupled

to the RX pin.

controlled by external Z87010.

VXRWB (input). Read/write control for the VXDATA bus,

TX (analog output). This is the IF transmit signal to the RF

module, output from the FSK modulator and transmit 4-bit

D/A converter.

controlled by external Z87010.

VXRDYB (output, active low). Ready control for the VX-

DATA bus. This signal is driven high (de-asserted) by the

Z87001 to insert wait states in the Z87010 ADPCM proces-

sor accesses.

RXSW (output; active high or low programmable). This

pin reflects the programming of the demodulator turn-on

time.

TEST (input, active high). Main test mode control. Must be

TXSW (output; active high or low programmable). Con-

trol for the receive switch on the RF module. Active during

receive periods.

set to GND.

HBSW (input with internal pull-up). Control for hand-

set/base configuration. Must be driven high or not connect-

ed for handset, low for base.

PAON (output; active high or low programmable). Con-

trol for the transmit switch on the RF module. Active during

transmit periods.

P0[15..0] (input/output). General-purpose I/O port. Direc-

tion is bit-programmable. Pins P0[3..0],when configured in

input mode, can also be individually programmed as wake-

up pins for the Z87001 (wake-up active low; signal internal-

ly debounced and synchronized to the bit clock).

RFEON (output; active high or low programmable).

On/off control for the RF module. Active (on) during wake

periods. Inactive (off) during sleep periods on the handset.

RSSI (analog input). Receive signal strength indicator

from RF module, input to the RSSI 8-bit ADC.

P0 0

P0 1

P0 2

P0 3

WAKEUP0

WAKEUP1

WAKEUP2

WAKEUP3

PWLV (analog output). Power level control for RF module,

output from the transmit power 4-bit DAC.

SYLE (output). RF synthesizer load enable: latches new

frequency hopping control word of external RF synthesiz-

er. Programmable polarity.

P1[15..0] (input/output).General-purpose I/O port. Direc-

tion is bit-programmable. Pins P114 and P115, when con-

figured in input mode, also behave as individually

maskable interrupt pins for the core processor (positive

edge-triggered).

ANT[1..0] (output). Control for optional antenna diversity

on the RF module.

P1 14

P1 15

INT0

INT2

MCLK (input). Master clock input.

18

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

FUNCTIONAL DESCRIPTION

The functional partitioning of the Z87001 is shown in Fig-

ure 2. The chip consists of a receiver, a transmitter, and

several additional functional blocks.The receiver consists

of the following blocks:

■ Transmit 4-Bit DAC

In Addition, there are the following Shared Blocks.

■ Event Trigger Block, Controlling:

–

Transmit/Receive Switch

■ Receive 1-bit ADC

Power On/Off Switches (Modulator, Demodulator,

RF Module)

■ Demodulator, including:

–

Antenna Switch Control (used on Base Station

only for Antenna Diversity)

–

IF Downconverter

AFC (Automatic Frequency Control)

Limiter-Discriminator

Matched Filter

■ 4-Bit DAC for Setting Transmit Power Level

■ 8-Bit ADC for Sampling the Received Signal Strength

Bit Synchronizer

Indicator (RSSI)

Bit Inversion

■ DSP Core Processor

Frame Synchronizer (unique word detector)

SNR Detector

■ Two 16-Bit General-Purpose I/O Ports

■ Z87010 ADPCM Processor Interface

Basic Operation

■ Receive Frame Timing Counter

■ Receive Buffer and Voice Interface

The Transmitter Consists of the Following Blocks:

The transmitter and receiver operate in time-division du-

plex (TDD): handset and base station transmit and receive

alternately. The TDD duty cycle lasts 4 ms and consists of

the following events:

■ Transmit Buffer and Voice Interface

■ Transmit Frame Timing Counter (used on base station

only)

■ At the beginning of the cycle, the frequency is changed

■ Modulator, including:

(hopping)

–

NCO

■ The base station transmits a frame of 144 bits while the

Bit Inversion

handset receives

■ The handset then transmits a frame of 148 bits while the

base receives.

4ms frame

HOP

148 bits

144 bits

BASE

TX

RX

Frequency

TDD switching

guard time

Hopping

guard time

HANDSET

RX

TX

Figure 1. Basic Time Duplex Timing

19

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Receive 1-Bit ADC

Demodulator

The incoming receive signal at the RX analog input pin is

sampled by a 1-bit analog-to-digital converter at 8.192

MHz.

The demodulator includes a two-stage IF downconverter

that brings the sampled receive signal to baseband.

The narrow-band 10.7 MHz receive signal, sampled at

8.192 MHz by the 1-bit ADC, provides a 2.508 MHz useful

image. The first local oscillator used to downconvert this IF

signal is obtained from a Numerically Controlled Oscillator

(NCO) internal to the Z87001, at the nominal frequency of

460 kHz. The resulting signal is thus at 2.048 MHz (= 2.508

MHz - 460 kHz). A second downconversion by a 2.048

MHz signal brings the receive signal to baseband.

The receive signal is FSK-modulated (Frequency Shift

Keying) with a carrier frequency of 10.7 MHz (Intermediate

Frequency, or IF). The instantaneous frequency varies be-

tween 10.7 MHz plus or minus 32.58 kHz. Since the data

rate is 93.09 kbps, there are 88 samples per data bit. This

oversampled data is further processed by the demodulator

to retrieve the baseband information.

The 1-bit converter is implemented with a fast comparator,

which determines whether the RX signal is larger or small-

er than a reference signal (VREF). The Z87001 internally

generates the DC level of both VREF and RX input pins.

The received signal at 10.7 MHz should thus be AC cou-

pled to the RX pin via a coupling capacitor. To ensure ac-

curate operation of the converter, the user should also at-

tach to the VREF pin a network whose impedance

matches the DC impedance seen by the RX pin.

The exact frequency of the 460 kHz NCO is slightly adjust-

ed by the Automatic Frequency Control (AFC) loop for ex-

act downconversion of the end signal to the zero frequen-

cy. The AFC circuit detects any DC component in the

output of the limiter-discriminator (see below) when receiv-

ing a known sequence of data (preamble). This DC com-

ponent is called the “frequency bias”. The bias estimate

out of the AFC can be read by the DSP processor on every

frame and subsequently filtered. The processor then adds

or subtract this filtered bias to/from the NCO control word

to correct the NCO frequency output.

SNR

SSB

Rx signal

1-bit

Limiter-

Discriminator

Bit

Sync

Frame

Sync

Filter

ADC

460 kHz

+ bias

2.048 MHz

Rx

Buffer

NCO

AFC

Figure 2. Demodulator Block Diagram

The main element of the demodulator is its limiter-discrim-

inator. The limiter-discriminator detects the frequency vari-

ations (ideally up to ± 32.58 kHz) and converts them to “0”

or “1” information bits. First, the data is processed through

low-pass filters to eliminate high frequency spurious com-

ponents introduced by the 1-bit ADC. The resulting signal

is then differentiated and fed to a matched filter. In the

matched filter, an integrate-and-dump operation is per-

formed to extract the digital information from its back-

ground noise.

in the incoming data stream in order to synchronize a dig-

ital phase-lock loop (DPLL). The PLL output is the recov-

ered bit clock, used to time the receiver on the base sta-

tion, and both receiver and transmitter on the handset.

To ensure enough transitions in the voice data stream, a

pseudo-random bit inversion operation is performed on the

outgoing voice data. The inversion is then reversed on the

demodulated data.

Since the data is packed in frames sent alternately from

base and handset every 4 ms (TDD), additional synchroni-

zation means are necessary. This is realized in a frame

The symbol clock is provided by the bit synchronizer. The

bit synchronizer circuit detects 0-to-1 and 1-to-0 transitions

20

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

FUNCTIONAL DESCRIPTION (Continued)

synchronizer, based on detection of a “unique word” fol-

lowing the preamble.

Transmit Rate Buffer and Voice Interface

The transmit rate buffer stores the data to be modulated.

The data is sourced from the Z87010 or the Z87001 core

processor. As for the receive rate buffer, the Z87010 sees

a unique pipe to write to, while the Z87001 DSP core ac-

cesses the rate buffer as random-access memory. The

modulator reads from the rate buffer as from a circular

buffer.

The receiver also features a signal-to-noise ratio detector,

which allows the DSP software to detect noisy channels

and eliminate them from the frequency hopping cycle. The

SNR information is also used by the Z87001 software as a

measure the current range between handset and base sta-

tion. This information allows the adaptive power control al-

gorithm to provide sufficient output power to the RF trans-

mitter.

Transmit Frame Timing Counter

On the handset, transmission does not start until the re-

ceiver has synchronized itself to the signal received from

the base station. The transmission timing is based on the

recovered clock. No additional counter is necessary.

Receive Frame Counter

The receive frame counter is responsible to keep track of

time within the frame. It is initialized by the frame synchro-

nizer logic on detection of the unique word. It is then

clocked by the recovered bit clock from the bit synchroniz-

er.

On the base station, the situation is different. Transmission

timing is based on a local clock, while the reception’s tim-

ing is based on the clock recovered from the incoming re-

ceived signal. Two counters, respectively clocked by local

and recovered clocks, are necessary to track the transmit

and receive signals.

On the base station, the receive frame counter is used as

time base for the receiver. On the handset, it is used as

time base for both receiver and transmitter.

Note that the receive clock on the base station tracks the

handset’s transmit clock, which is also the handset’s re-

ceive clock and tracks the transmit clock of the base sta-

tion. As a result, receive and transmit clocks of the base

station have exactly the same frequency; only their phases

differ.

Receive Rate Buffer and Voice Interface

The voice signal is generated at the fixed rate of 32 kips by

the Z87010 processor, and transmitted/received in bursts

of 93.09 kips across the air. Data buffers in the transmitter

and receiver are thus necessary to absorb the rate differ-

ences over time. These buffers are called “rate buffers”.

They can store up to 144 data bits and are organized as an

array of 36 4-bit nibbles.

Modulator

The modulator consists of a numerically controlled oscilla-

tor (NCO) which generates an FSK (Frequency Shift Key-

ing) signal at the carrier frequency of 2.508 MHz. The car-

rier frequency is shifted plus or minus 32.58 kHz for a “1”

or a “0” data bit. To facilitate conformance to FCC regula-

tions, the transitions from “1” to “0” or vice-versa are

smoothed in order to decrease the amplitude of the side

lobes of the transmit signal. In practice, the jump from one

frequency to the next is performed in several smaller

steps.

The receive rate buffer stores the received data from the

demodulator. Incoming bits are arranged in 4-bit nibbles

and transferred to successive locations of the rate buffer.

When the last location is reached, transfers resume from

the beginning (circular buffer). The system design guaran-

tees that no buffer overrun nor enduring can occur.

The receive rate buffer can be read by the DSP core pro-

cessor of the Z87001 or by the Z87010 chip. On the

Z87001 side, the buffer can be read as a random-access

memory: the processor writes the nibble address in an ad-

dress register and reads the 4-bit data from a data register.

On the Z87010 side, a voice processor interface logic han-

dles the addressing to automatically present the succes-

sive voice nibbles to the Z87010 in the order they were re-

ceived.

The carrier frequency is adjustable by the DSP core pro-

cessor in order to provide additional frequency adjustment

between base and handset. This is provided in case of a

frequency offset too large for possible correction by the

AFC.

The modulator also includes bit inversion logic as dis-

cussed in the receiver section.

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P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Tx signal

4-bit DAC

NCO

Tx Buffer

Spectral

Shaping

Figure 3. Modulator Block Diagram

rectly controlled by the Z87001 software through an output

register.

Transmit 4-Bit DAC

The transmit DAC clocks one new NCO value out of the

Z87001 every 8.192 MHz period. Only the 10.7 MHz alias

frequency component of the transmit signal (2.508 + 8.192

MHz image) is filtered, amplified and upconverted to the

900 MHz ISM band by the companion RF module.

8-Bit ADC for Sampling the Received Signal

Strength Indicator (RSSI)

RSSI information is typically generated from the last stage

of the RF receiver. The RSSI is sampled once per frame

by the 8-bit ADC and used by the Z87001 software to com-

pute the necessary Transmit Power Level voltages.

Event Trigger Block

The event trigger block is responsible for scheduling the

different events happening at the bit and frame levels. The

event trigger block receives input from the frame counters

as well as the register interface of the DSP core processor.

DSP Core Processor

A DSP core processor constitutes the heart of the Z87001.

The DSP runs the application software which performs the

following functions:

The event trigger schedules the following events:

■ Start of the 4 ms frame: a synthesizer load enable pulse

■ Register initialization

is issued on the SYLE pin

■ Implementation of high-level phone features; control of

■ Power-up of the modulator section and transmission of

phone user interface (keypad, Led, etc.)

the frame on handset and base station

■ Control of the Z87010 ADPCM Processor

■ Control of the phone line interface

■ Ring detection by DSP processing

■ Use of the bit inversion as function of mode

■ Power-up of the demodulator section and reception of

the frame on handset and base station

■ Communication protocol between handset and base

■ Control of PAON and TXSW output pins, to be used as

TDD control signals for the T/R switch as well as the

transmitter and receiver chains on the RF module

station supporting voice and signalling channels

■ Control of the RF synthesizer and adaptive frequency

hopping algorithm

■ Control of RFEON pin, to be used as general on/off

switch on the RF module

■ Control of the RF power and adaptive power algorithm

■ Control of the Z87001 sleep mode

■ Control of the demodulator (bit synchronizer loop filter,

AFC bias estimate filtering)

4-Bit DAC for Setting Transmit Power Level

In order to save battery life, the Z87001 only transmits the

amount of RF power needed to reach the remote receiver

with a sufficient SNR margin. The on-board transmit power

4-bit DAC provides 4 different voltage levels to the power

amplifier in the RF module for that purpose. This DAC is di-

■ Control of the modulator (carrier frequency) and

adaptive frequency alignment

■ Signalling between base and handset to support above

features

22

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

FUNCTIONAL DESCRIPTION (Continued)

The DSP core is characterized by an efficient hardware ar-

chitecture that allows fast arithmetic operations such as

multiplication, addition, subtraction and multiply-accumu-

late of two 16-bit operands. Most instructions are executed

in one clock cycle.

■ Control of battery charging and detection of low battery

conditions

■ Implementation of additional features for customizing of

the phone

Z87010 Interface

The DSP core is operated at the internal speed of 8.192

MHz. It has an internal RAM memory of 512 16-bit words

divided in two banks. Six register pointers provide circular

buffering capabilities and dual operand fetching. Three

vectored interrupts are complemented by a six-level stack.

One interrupt is used by the transceiver, while the two re-

maining vectors are mapped into port P1. In the phone

system, one of these interrupts is customarily reserved for

the Z87010 ADPCM Processor. The other interrupt can be

used for custom purposes.

In addition to providing clock signals to the Z87010 proces-

sor, the Z87001 interfaces to the Z87010 through two dif-

ferent paths:

■ A command/status interface

■ A data interface

The command/status interface consists of two dual-port

registers accessible by both Z87001 and Z87010 DSP

core processors. On the Z87001 side, the registers are

mapped into the DSP core processor’s register interface.

To allow access by the Z87010, the internal command/sta-

tus registers can also be decoded on the pinto of the

Z87001. Arbitration logic resolves access contentions.

The Z87001 may access up to 64K 16 bit words of external

ROM including 4 words for interrupt and reset vectors. The

ROM is mapped at addresses 0000h to 3FFFh, as shown

in Figure 13.

The data interface allows the Z87010 processor direct ac-

cess to the Z87001’s receive and transmit rate buffers. The

rate buffers are decoded on the pin to of the Z87001, and

dedicated voice processor interface logic handles the ad-

dressing within the rate buffers.

3FFFh

3FFEh

3FFDh

3FFCh

Int. Vector 0

Int. Vector 1

Int. Vector 2

Reset Vector

3FFFh

The physical interface between Z87001 and Z87010 con-

sists of an 8-bit data bus, a 3-bit address bus and control

signals, as summarized in the following:

64K

USER ROM

(EXTERNAL)

VXDATA[7.0]

VXADD[2.0]

VXSTRB

Data bus

Address bus

Data Strobe

VXRWB

Read/Write Control

Read Control

VXRDYB

This bus is controlled by the Z87010. Although in the sys-

tem the Z87010 is enslaved to the Z87001 master, at the

physical level the Z87001 acts as a peripheral of the

Z87010.

0000h

Figure 4. ROM Mapping

The mapping of the command status and data interfaces

from the Z87010 side is given below.

Two 16-Bit General-Purpose I/O Ports

Address

Interface (VXADD [2.0])

Read

/Write

Data

(VXDATA[7.0])

Two 16-bit general-purpose I/O ports are directly accessi-

ble by the DSP core. These input and output pins are typ-

ically used for:

Transmit

1

W

----3210

rate buffer

■ Implementation of the phone’s user interface (keypad,

Receive

rate buffer

1

R

----3210

LED, optional display, etc.)

Command

Status

0

R

76543210

■ Control of phone line interface (on/off hook, ring detect)

W

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P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

OPERATION

The accumulated bias, available in BIAS_ERROR_DATA,

can be used directly to correct the NCO frequency. Alter-

nately, the estimated bias can be read by the DSP, further

processed, and written to the CORE_BIAS_DATA field.

The DSP controls which value is used by setting the

USE_CORE_BIAS field. The selected value is added to

the 460 kHz signal which downconverts the receive IF sig-

nal.

Automatic Frequency Control Loop

(Receiver) and Modulator

AFC Loop

The AFC loop consists of a bias estimator block, which de-

termines frequency offsets in the incoming signal, an

adder, to add this bias to the 460 kHz frequency control

word driving the NCO, and various interface points to the

DSP core processor. In particular, the DSP can read the

bias estimate data and substitute its own calculated bias

value to the NCO.

The CORE_BIAS_DATA and BIAS_ERROR_DATA are

two’s complement numbers in units of 125 Hz.

In addition to correcting the difference in clock frequencies

on the receiver using the AFC loop, a Z87001-base system

can also modify the frequency of the remote transmit IF

signals. The software has access to this frequency through

the MOD_FREQ register fields.

The bias estimator accumulates the discriminator output

values (image of instantaneous frequency) that exceed a

programmable threshold (BIAS_THRESHOLD). The pro-

cessor can freeze the bias calculation any time by reset-

ting the BIAS_ENABLE control bit.

Discriminator

Output

Rx signal

Second down-

convertor,

Discriminator

Bias estimator

460 kHz

+ bias

“0”

BIAS_THRESHOLD

BIAS_ENABLE

BIAS_ERROR_DATA

Downconverter

NCO and bias

adder

DSP Core

Processor

CORE_BIAS_DATA

USE_CORE_BIAS

Figure 5. AFC Loop and Processor Control

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DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

OPERATION (Continued)

Modulator Control

Bit Synchronizer

The MOD_FREQ fields specify the carrier center frequen-

cy (should be programmed to 2.508 MHz) and deviation for

the FSK signal (should be programmed to ± 32.58 kHz). In

addition, wave shaping is performed on bit transitions, in

order to satisfy FCC regulations. Up to four different inter-

mediate deviation values are programmable for each of

the two FSK states. The MOD_FREQ fields are program-

mable in units of 62.5 Hz.

The bit synchronizer circuit is an implementation of the

Data-Transition-Tracking Loop (DTTL), best described in

“Telecommunications Systems Engineering”, by W. Lind-

sey and M. Simon (Dover 1973; oh. 9 p. 442). Its operation

is summarized in the following block diagram.

Table 1. AFC and Modulator Control Fields

Field

Register

CONFIG1

Bank

EXT

BIAS_THRESHOLD

BIAS_ENABLE

3

2

EXT0

EXT2

EXT4

SSPSTATE

BIAS_ERROR_DATA

CORE_BIAS_DATA

BIAS_ERROR

CORE_BIAS

Discriminator

Output

In-phase

Matched

Filter

Transition

Detection

Signed

Error

Mid-phase

Matched

Filter

Error

Magnitude

Loop Filter

division

“by 1”

“by 64”

INT_SYM_ERR0

INT_SYM_ERR1

Clock

Generator

ﬁrst order

Recovered

Bit clock

SECOND_ORDER

BSYNC_GAIN

DSP Core

Processor

Figure 6. Bit Synchronizer Loop and Processor Control

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P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

The loop filter is controlled by the DSP core processor. The

DSP core can implement a first order loop by setting the

SECOND_ORDER field to zero. Typically, the

BSYNC_GAIN would then be set to “divide-by-1” operation

to provide a wide closed loop bandwidth and thus a quick

acquisition of the bit clock. When the bit clock is in phase

with the input data, the loop bandwidth can be narrowed to

maintain tracking of the receive clock with minimum impact

from signal noise. To reduce the loop bandwidth, the

BSYNC_GAIN can be set to “divide-by-64” the first order

gain, while the integrated tracking error (available to the

DSP in fields INT_SYM_ERR0 and INT_SYM_ERR1) can

be used by the DSP software to adjust the

SECOND_ORDER term.

Each frame lasts 4 ms, which corresponds to (372 + 8/22)

bits; the frame counters count from 0 to 371, with the last

count lasting a bad longer than the other ones; at the end

of count 371, the counters wrap around to 0.

The “hop” command pulse is asserted to pin SYLE during

count “0” of the frame counter (transmit frame counter on

the base station).

Frame Synchronizer, Timings and

RF Interface

The frame synchronizer tracks the received frames and re-

sets the receive frame counter. The synchronization is per-

formed by recognizing certain data patterns present in the

receive bit stream: a comparison is done on the fly be-

tween the data pattern and the incoming bit stream; when

the data match, the frame counter is reset.

The bit synchronizer relies on transitions in the received bit

stream to operate. The bit inversion logic guarantees

enough transitions for all transferred data.

Two possible 16-bit data patterns are pre-programmed in

the Z87001. One is named UW (Unique Word) and is used

in acquisition mode for first-time synchronization to an in-

coming signal. UW can also be used to track an acquired

signal. The second pattern is named SYNC_D and is used

to track the received data frames while voice is being

transferred. The transition from tracking UW to tracking

SYNC_D is controlled by the DSP processor through the

SYNC_SEARCH_WORD field.

At the handset, the bit synchronizer must track both fre-

quency and phase of the receive signal’s data clock. At the

base, only the phase must be tracked. The frequency is in-

herently correct since the base is the source of the sys-

tem’s data clock.

Table 2. Bit Synchronizer Control Fields

Field

Register

SSPSTATE

Bank

EXT

BYSNC_GAIN

3

1

0

1

EXT2

EXT6

EXT2

UW Synchronization

INT_SYM_ERR1

INT_SYM_ERR0

BIT_SYNC

When the Z87001 matches the UW, the receive frame

counter is reset to the value of UW_LOCATION. This value

is programmable by the DSP processor. On the handset,

where the receive frame counter is used to derive all tim-

ings, UW_LOCATION actually defines the guard time be-

tween the frequency hop command and the beginning of

data reception, which starts at FRAME_COUNTER =

(UW_LOCATION - 84) as shown in the next figure.

INT_SYM-ERR0

SECOND_ORDER BIT_SYNC

Frame Counters

The handset only has one frame counter, which times all

receive and transmit events. The base station has distinct

transmit and receive frame counters. When used in this

document without any explicit reference to either base or

handset, the terms “receive frame counter” and “transmit

frame counter” refer to both sides. For the handset, both

terms refer to the same unique counter.

On the base station, data reception starts when the receive

frame counter equals (UW_LOCATION - 84), but this has

less significance since the hop pulse is synchronized with

the transmit frame counter and there is no fixed relation-

ship between transmit and receive frame counters. On the

base station, the UW_LOCATION should be set to 301.

The frame counters are clocked at the bit rate, or 93.09

kHz (2.048 MHz/22). Each count lasts one bit =

1000/93.09 = 10.74 µs.

26

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

OPERATION (Continued)

UW_LOCATION-84

Handset

FRAME_COUNTER

0

1

2

SYLE timing

Receive data at RX pin

Figure 7. Frame Counter and UW_LOCATION on Handset

Two modes of search are programmable through the

SYNC_SEARCH_MODE field: “full search” and “window

search”. The full search is used by the handset when first

acquiring the signal from the base station. In full search,

the handset is in receive mode and continuously looks for

a match with the UW. When a match is found and the time

reference established (UW_LOCATION is set), the DSP

processor on the handset detects the synchronization (see

below), switches to Time Division Duplex mode (TDD) and

starts receiving and transmitting alternately. The search

mode should also be switched to “window search” by the

DSP software.

The transition to voice mode proceeds in two steps,

through an intermediate mode. The mode is set by the

DSP

processor

by

programming

the

MULTIPLEX_SWITCH field. The three modes are:

■ SMUX: initial mode. This mode allows acquisition, AFC

operation, UW synchronization and signalling; ADPCM

Processor access disabled; bit inversion disabled.

■ STMUX: intermediate mode. This mode allows

SYNC_D frame synchronization and signalling; ADPCM

Processor access disabled; bit inversion enabled.

■ TMUX: voice mode. This mode allows voice

transmission, SYNC_D frame synchronization and

signalling; ADPCM Processor access enabled; bit

inversion enabled.

The window search mode only searches for a match in a

certain time window centered around the expected match

time. The window size is programmable by the DSP pro-

cessor in the WINDOW_SIZE field. If the matching does

not occur at the expected time, due to so-called “bit slips”,

the receive frame counter timing is adjusted. Note: al-

though the bit synchronizer is meant to keep track of time

and prevent bit slips when the phone is operating continu-

ously in TDD mode, bit slips are still possible when the

handset is in standby mode, and only receives once in a

while (see description of sleep mode).

In order to detect synchronizations, the software has ac-

cess to the SYNC_ACQ_IND status field. This field is set

by the Z87001 matching hardware every time a match is

detected within the right time window. The software must

reset the “IND” bit by setting the SYNC_ACQ_CLEAR

field.

In addition, the software can track the frame timing by

reading the frame counter value, available in the

FRAME_COUNTER field. On the base station, where two

frame counters are in use, this field returns the value of the

transmit frame counter.

SYNC_D Synchronization

When the DSP processor switches the Z87001 operation

to voice mode, the frame synchronization parameters

should be modified by the DSP software to:

Every time the frame counter wraps around to 0, a frame

start indicator bit is set (FRAME_START_IND status field).

The software must reset this “IND” bit by setting the

FRAME_START_CLEAR field. If the FS_INT_ENABLE bit

is set, frame starts also trigger interrupts to the DSP pro-

cessor.

■ SYNC_SEARCH_MODE = window search

■ SYNC_SEARCH_WORD = SYNC_D pattern

In this mode, the receiver searches for the SYNC_D pat-

tern in windows of the incoming data stream. The window

size is determined by the WINDOW_SIZE field.

27

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

The following table summarizes the fields allowing control

of frame synchronization and basic frame timing.

In addition to the SYLE signal, the interface to the most RF

synthesizers includes two more input lines, “data” and

“clock”, for serial programming of the data values defining

the RF channel. In order to allow interfacing to various

popular synthesizers, the Z87001 does not have dedicated

clock and data lines with fixed timing. Instead, two general

I/O pins from ports P0 and P1 can be controlled in software

by the DSP core to realize any particular interface timing.

This flexibility is made possible by the high speed, single-

cycle architecture of the DSP core.

Table 3. Frame Synchronizer Control Fields

Field

Register

Bank Ext

SYNC_SEARCH-MODE

SYNC_SEARCH_WORD

UW_LOCATION

SSPSTATE

3

2

3

1

3

EXT2

EXT1

EXT0

EXT2

EXT3

EXT2

EXT3

EXT6

EXT3

EXT2

SSPSTATE

RX_CONTROL

CONFIG1

WINDOW_SIZE

MULTIPLEX_SWITCH

SYNC_ACQ_IND

SSPSTATE

SSPSTATUS

SSPSTATE

SSPSTATUS

CONTROL

SSPSTATUS

SSPSTATE

The transmitter control includes a global enable signal for

all transmit functions: TX_ENABLE. The transmission start

is controlled by the MOD_PWR_ON field. On the base sta-

tion, the value programmed in MOD_PWR_ON is refer-

enced to the transmit frame counter.

SYNC_ACQ_CLEAR

FRAME_COUNTER

FS_INT_ENABLE

FRAME_START_IND

FRAME_START_CLEAR

SYNC_SEARCH-MODE

Two

additional

fields,

RFTX_PWR_ON

and

RFTX_PWR_OFF, define the duty cycle of the PAON out-

put pin. On the base station, these fields are referenced to

the transmit frame counter. The RFTX_POLARITY bit de-

fines the polarity of the PAON pin. This pin can be used to

control the transmit section and power amplifier of the ex-

ternal RF module.

RF Interface

Several control fields are available in the Z87001 register

set to control the timing and polarity of the RF module in-

terface signals.

On the receive side, two fields define the internal timing of

the receiver. The start of reception is controlled by the

DEMOD_PWR_ON field. Stop of reception (and receiver

power down) is controlled by the DEMOD_PWR_OFF

field. On the base station, these fields are referenced to

the receive frame counter. The RXSW output pin follows

the timing defined by the DEMOD_PWR_ON and OFF

fields.

A first field, RFEON_POLARITY, controls the polarity of

the RFEON pin. This pin should be used to control the

power of the RF module. It is asserted by the Z87001 when

the RF module is in use, and de-asserted in sleep mode.

The sleep mode is used by the handset to save battery life

when no phone call is in process (See “Sleep mode”, be-

low).

Two

additional

fields,

RFRX_PWR_ON

and

The SYLE pin (Synthesizer Load Enable), which carries a

“load enable” pulse that tells an external RF synthesizer to

generate the next RF channel, is controlled by two fields.

The HOP_ENABLE field is a global enable signal for the

SYLE signals. The SYLE_POLARITY field defines the po-

larity of the SYLE pin. The system designer should ensure

that the leading edge of the SYLE pulse triggers channel

hopping.

RFRX_PWR_OFF, define the duty cycle of the TXSW out-

put pin. On the base station, these fields are referenced to

the TRANSMIT (!) frame counter. The RFRX_POLARITY

bit defines the polarity of the TXSW and RXSW pins. The

TXSW pin can be used to control the receive section of the

external RF module.

The various timing control registers reviewed in this para-

graph should be programmed differently for handset and

base station. If the same ROM code is used on base and

handset, the software can determine which station it runs

on by reading the HAND_BASE_SEL bit, which reflects

the state of the HBSW pin.

28

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

OPERATION (Continued)

The following figure and table summarize the RF interface

control fields.

HBSW

HAND_BASE_SEL

Sleep Mode

Control

RFEON

RFEON_POLARITY

DSP Core

Processor

HOP_ENABLE

SYLE

PAON

SYLE_POLARITY

RFTX_PWR_ON

RFTX_PWR_OFF

RFTX_POLARITY

MOD_PWR_ON

Modulator

TX_ENABLE

TX

RFRX_PWR_ON

RFRX_PWR_OFF

RFRX_POLARITY

TXSW

DEMOD_PWR_ON

DEMOD_PWR_OFF

RXSW

Demodulator

RX,VREF

Figure 8. RF interface Control

Table 4. Timing and RF Interface Control Fields

Register

Field

RFEON_POLARITY

Bank

Ext

RX_PWR_CTRL

SSPSTATE

2

3

2

0

2

0

2

3

EXT6

EXT2

EXT0

EXT2

EXT5

EXT7

EXT6

EXT7

EXT3

HOP_ENABLE

SYLE_POLARITY

TX_ENABLE

CONFIG1

SSPSTATE

MOD_PWR_ON

MOD_PWR_CTRL

RFRX_PWR_CTRL

DEMOD_PWR_CTRL

RFRX_PWR_CTRL

RFTX_PWR_CTRL

SSP_STATUS

RFRX_PWR_ON/OFF

DEMOD_PWR_ON/OFF

RFRX_POLARITY

RFTX_PWR_ON/OFF

RFTX_POLARITY

HAND_BASE_SEL

29

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Sleep Mode

Clock Interface

To save the phone’s battery life on the handset, the

Z87001 can be operated in sleep mode while the phone is

not in use. The sleep mode is entered by software com-

mand. The sleep mode first needs to be enabled by setting

the SLEEP_WAKE field. Then a GO_TO_SLEEP com-

mand puts the processor to sleep by temporarily stopping

its clock. The sleep period can be set to last between 4 ms

and 1.02 s by programming the SLEEP_PERIOD field. In

sleep mode, the RFEON pin is de-asserted.

The Z87001 generates the Z87010 clock at 16.384 or

8.192 MHz, as set in VP_CLOCK. In addition, the clock

can be stopped and restarted with the VP_STOP_CLOCK

field in order to reduce power consumption (Note: a soft-

ware handshaking between Z87001 and Z87010 is neces-

sary before stopping and after restarting the clock).

In addition to providing the Z87010 main clock, the Z87001

generates a CODCLK signal which will be used by the co-

dec and by the Z87010 to synchronize its data transfers

with the Z87001. On the base station, the CODCLK is sim-

ply obtained by dividing the 16.384 MHz input clock.

The processor comes out of sleep mode in one of two

ways. Either the sleep counter counts down to zero, or one

of the enabled pins from port P0 is asserted prior to normal

expiration of the counter. Four port pins (P0[0..4]) can be

individually enabled to provide the wake-up function by

setting the appropriate bits in P0_WAKE_ENABLE. Typi-

cally, these port pins are connected to the telephone key-

pad.

On the handset, the CODCLK is synchronized to the base

station’s CODCLK signal through the receive bit sync log-

ic. This ensures that production and consumption of voice

data is happening at identical rates on handset and base,

eliminating buffer overrun and underrun situations.

Command/Status Interface

When the processor core wakes up, the software needs to

know how much time it was actually asleep, in order to re-

store synchronization to the base station’s hopping se-

quence. For that purpose, the current value of the sleep

The Z87001 sends commands to the Z87010 through the

VP_COMMAND write-only field. It reads the Z87010 sta-

tus in the VP_STATUS read-only field. Both fields are lo-

cated at the same address in the Z87001 register inter-

face. A communication protocol should be established in

software to ensure correct reception of all commands.

Dedicated hardware ensures data integrity when both

Z87001 and Z87010 simultaneously access the same reg-

ister.

counter

is

available

to

the

processor

in

SLEEP_REMAINING. A value of zero indicates normal ex-

piration of the sleep counter.

In order to guarantee a good operation of the wake-up

pins, the wake-up signals are hardware-denounced by the

Z87001. Furthermore, these signals are internally syn-

chronized to the bit clock. This ensures that the processor

has enough time (one bit time = 10.74 ms) to read a stable

value of the remaining sleep time and synchronize correct-

ly to the base station’s hopping sequence.

Table 6. ADPCM Processor Control Fields

Field

VP_CLOCK

Register

Bank

Ext

CONFIG1

3

2

EXT0

EXT2

EXT0

VP_STOP_CLCOCKS SSPSTATE

Table 5. Sleep Mode Control Fields

VP_COMMAND

VP_STATUS

VP_INOUT

Field

Register

SSPSTATE

CONFIG2

Bank

Ext

SLEEP_EAKE

3

1

EXT2

EXT1

EXT6

GO_TO_SLEEP

Data Interface and Rate Buffers

SLEEP_PERIOD

The digitized voice data is communicated between the

Z87001 and Z87010 through the rate buffers and ADPCM

Processor data interface. The transmit and receive rate

buffers each contain 36 4-bit nibbles.

SLEEP_REMAINING

P0_WAKEUP_ENABLE

CONFIG2

CONTROL

ADPCM Processor Interface and Rate Buffers

To write to the transmit rate buffer, the Z87001 core pro-

cessor must first set the nibble address in the

TX_BUF_ADDR register field, then write the nibble data

through TX_BUF_DATA. If the TX_AUTO_INCREMENT

bit is set, the address is automatically incriminated (modu-

lo 51 = the number of nibbles in rate buffer + 15 additional

data words accessible through TX_BUF_DATA; for more

information, see Register Description) after each data

write. This allows the DSP core to write successive nibbles

without resetting the address each time.

The interface to the ADPCM Processor (Z87010) consists

of clock control, command/status interface and data inter-

face. The data interface gives the ADPCM Processor ac-

cess to the rate buffers.

30

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

OPERATION (Continued)

The operation of the receive rate buffer is identical. The

Z87001 core processor must set the nibble address in

TX_BUF_VP_ADDR and RX_BUF_VP_ADDR register

fields. After the Z87010 writes or reads a nibble to or from

transmit or receive rate buffer, the corresponding

“VP_ADDR” is automatically incriminated (modulo 36) to

the next accessible address. The locations of accessible

addresses are individually controlled by the Z87001 in the

three TX_RX_NIBBLE_MARKER register fields. A marker

bit equal to “1” enables the Z87010 to access the corre-

sponding address; a bit equal to “0” causes the Z87010’s

read or write access to skip to the next nibble that has a

marker bit equal to “1”.

RX_BUF_ADDR,

then

read

the

nibble

from

RX_BUF_DATA. If the RX_AUTO_INCREMENT bit is set,

the read address is automatically incriminated (modulo 36

= number of nibbles in rate buffer) after each data read.

This allows the DSP core to read successive nibbles with-

out resetting the address each time.

Through its register interface, the Z87001 also controls

which rate buffer addresses the Z87010 ADPCM Proces-

sor can access. The nibble addresses are contained in the

Z87001

RX RATE BUFFER

Demodulator

RX_BUF_VP_ADDR

TX_RX_NIBBLE_

MARKER

Address

Decoder

TX_BUF_VP_ADDR

TX RATE BUFFER

Modulator

Data

ADPCM Proc.

Interface

RX_BUF_ADDR

RX_AUTO_INCR.

Addr

Ctrl

TX_BUF_ADDR

TX_AUTO_INCR.

RX_BUF_DATA

TX_BUF_DATA

DSP Core

Processor

VP_COMMAND

VP_STATUS

Figure 9. Rate Buffers Access and ADPCM Processor Interface

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P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 7. Data and Control Access to Rate Buffers

Field

Register

Bank

RX_AUTO_INCREMENT

RX_BUF_ADDR

RATE_BUF_ADDR

RATE_BUF_DATA

RATE_BUF_ADDR

RATE_BUF_DATA

1

EXT0

EXT1

TX_AUTO_INCREMENT

TX_BUF_ADDR

RX_BUF_DATA

TX_BUF_DATA

RX_BUF_VP_ADDR

TX_BUF_VP_ADDR

TX_RX_NIBBLE_MARKER

ADDITIONAL FEATURES

Power Control

General-Purpose I/O Ports

The Z87001 features several means of measuring and

controlling power levels. One input pin (RSSI) connects an

external “receive signal strength indicator” to a half flash 8-

bit ADC in the Z87001. This ADC is sampled once per

frame during the receive portion of the TDD cycle. The

RSSI value can be accessed in software in the

RSSI_DATA register field. With external multiplexing, the

8-bit ADC can be used for additional purposes.

The Z87001 includes two general-purpose input/output

ports, P0 and P1, of 16 bit each. The direction of each bit

is independently programmable by setting the register

fields DIRECTION0 and DIRECTION1. Then, the software

can access the input and output values by accessing

DATA0 and DATA1.

Two pins of port P1 (pins 14 and 15), when configured in

input mode, also behave as interrupt pins for the core pro-

cessor. The software can enable or disable each interrupt

The RSSI data is used by the software to implement adap-

tive power control. In order to determine whether the RSSI

information is made of signal or noise, the Z87001 includes

logic to measure the signal-to-noise ratio (SNR) of the re-

ceive signal. This SNR value is available at the end of ev-

ery frame in the SNR_ESTIMATE register field. It is also

used by the adaptive frequency hopping algorithm to de-

termine and avoid the noisy channels.

by

setting

the

INTERRUPT_0_ENABLE

and

INTERRUPT_2_ENABLE fields. The interrupts are posi-

tive edge-triggered.

Number

Interrupt

Number

DSP Interrupt

Vector

P1 14

P1 15

INT0

INT2

3FFFh

3FFDh

Finally, a 4-bit DAC (resistive ladder) is provided to control

RF power output level. The DAC is under software control

through register field TX_PWR_DAC_DATA.

Table 8. Power Control

Table 9. General-Purpose I/O Ports

Field Register Bank

Field

Register

Bank Ext

Ext

RSSI_DATA

RSSI

2

1

2

EXT3

EXT1

EXT6

EXT3

DIRECTION0

GPI00DIR

GPI00DATA

GPI0IDIR

3

1

EXT4

EXT5

EXT6

EXT7

EXT6

SNR_ESTIMATE

TX_PWR_DAC_DATA

RSSI_DATA

RX_CONTROL

CONTROL

RSSI

DATA0

DIRECTION1

DATA1

GPI0IDATA

SNR_ESTIMATE

RX_CONTROL

INTERRUPT_0_ENABLE CONTROL

INTERRUPT_1_ENABLE CONTROL

Four pins of port P0 (pins 0 to 3), when configured in input

mode, can also be individually programmed as wake-up

pins for the Z87001 (See “Sleep mode”, above).

32

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

REGISTER DESCRIPTION

The Z87001 DSP core processor has four banks of eight

registers mapped in the core processor’s “external regis-

ter” space, as summarized in the following table.

1

Table 10. Register Summary

BANK ADDRESS

REGISTER

CONFIG1

READ DESCRIPTION

WRITE DESCRIPTION

TABLE #

Bank 3

EXT0

Clock Dividers, Use Core Bias, Table 25

SYLE polarity, search window

size, Bias Threshold

EXT1

EXT2

CONFIG2

Remaining Sleep time

ANT0/1 control, Sleep Period Table 26

SSPSTATE

Stop VP clock, Absent gain, Bias Enable, Tx Enable, Sync

Search control, Hop Enable, Frame Start control, Multiplex

control, Sleep mode control

Table 27

EXT3

SSPSTATUS

Frame Counter, Handset/Base,

Sync Search control, Frame

Start control

Table 28

EXT4

EXT5

EXT6

EXT7

EXT0

EXT1

EXT2

EXT3

EXT4

EXT5

EXT6

EXT7

EXT0

EXT1

GPIO0DIR

General-Purpose I/O port 0 direction control

General-Purpose I/O port 0 data

Table 29

Table 30

Table 31

Table 32

GPIO0DATA

GPIO1DIR

General-Purpose I/O port 1 direction control

General-Purpose I/O port 1 data

GPIO1DATA

Bank 2

VP_INOUT

ADPCM Processor Status

SNR estimate

ADPCM Processor Command Table 33

RX_CONTROL

BIAS_ERROR

RSSI

UW location

Table 34

Table 35

Table 36

Table 37

Table 38

FCW value

8-bit ADC data (RSSI)

CORE_BIAS

Core Bias data

MOD_PWR_CTRL

DEMOD_PWR_CTRL

RFTX_PWR_CTRL

RATE_BUF_ADDR

RATE_BUF_DATA

MOD_PWR control

RXSW, RFEON pin control Table 39

PAON pin control

Table 40

Table 41

Bank 1

Rate Buffer address

Re Rate Buffer data

Bit Sync monitoring

Tx Rate Buffer data, control Table 42

data

EXT2

EXT3

EXT4

EXT5

EXT6

EXT7

EXT0

EXT1

EXT2

EXT3

EXT4

EXT5

EXT6

EXT7

BIT_SYNC

Bit Sync control

Table 43

Table 44

Table 45

Table 46

Table 47

Table 49

RESERVED

CONTROL

INT, WAKEUP pin control, 4-bit DAC data (PWLV)

RESERVED

INT_SYM_ERR0

RFRX_PWR_CTRL

Bank 0

Bit Sync monitoring

TXSW, RXSW pin control

DS96WRL0800

P R E L I M I N A R Y

33

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

REGISTER DESCRIPTION (Continued)

The bank is selectable in software by writing to the core’s

status register (see Table 24). Once a bank is selected,

each of the eight external registers (EXT0 through EXT7)

can be accessed by a single-cycle software instruction.

Table 11. Bank Switching

Bank

Status Register

Bank Function

Bank 0

Bank 1

Bank 2

Bank 3

xxxx xxxx x00x xxxx b

xxxx xxxx x01x xxxx b

xxxx xxxx x10x xxxx b

xxxx xxxx x11x xxxx b

Test point access, TDD switching control

Rate buffer access, miscellaneous

ADPCM processor interface, RF interface, etc.

Conﬁguration, status, general-purpose port data and direction

Bank 3 Registers

Table 12. Bank 3 Registers

EXT0

Conﬁg 1

Field

Bank 3

Bit Position

R/W

Data Description

RESERVED

f---------------

R

Returns 0

W

Must be set to 1

VP_CLOCK

-e--------------

Controls CLKOUT output pin (clock for ADPCM Processor).

Returns 0

0

1

CLOCKOUT=16.384 MHz

CLOCKOUT = 8.192

USE_CORE_BIAS --d-------------

SYLE_POLARITY ---c------------

Controls which bias value is used by the downconverter’s

NCO as part of the automatic frequency control loop (AFC)

Returns 0

R

W

0* Uses BIAS_ERROR_DATA value from AFC hardware

1

Uses CORE_BIAS_DATA value from DSP core

Controls the polarity of the SYLE output pin (hop pulse)

Returns 0

R

W

0

1

SYLE is a positive pulse

SYLE is a negative pulse

WINDOW_SIZE

----ba98--------

Deﬁnes the search window size (in bits) for windowed search

mode (for Unique Word or SYNC_D words).

Returns 0

R

W

0000 Window size=1

0001 Window size =3 (1±1)

•••

1111 Window size = 31 (1± 15)

BIAS_THRESHOL -------76543210

D

Bias estimator threshold value

Returns 0

R

W

XXh Sets the bias value

Notes:

1. VP_CLOCK. Internally synchronized to avoid glitches. Changes to this bit take effect immediately.

2. SYLE_POLARITY. Changes to this bit take effect immediately.

3. BIAS_THRESHOLD. The bias threshold must be coded as a negative value

(opposite of the threshold value) coded in 2’s complement. The nominal value for the

threshold is -46 (=D3h). Internally, this value is sign-extended to 13 bits.

34

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 13. Bank 3 Register EXT1

Conﬁg 2

Field

Bank 3

Bit Position

EXT1

R/W Data

Description

1

ANTENNA_SW_DEFEAT f---------------

Controls optional antenna switching

(ANT0 and ANT1 pins)

Returns 0

R

W

0

1

Enables antenna switching

Disables antenna switching

ANTENNA_SW_OFFSET -edcba98--------

Controls antenna switching time advancement

Returns 0

R

Offset in number of 2.048 MHz clock cycles

W

xXh (<108)

SLEEP_PERIOD

--------76543210

W

00h Programs sleep duration in sleep mode Illegal

01h Sleep period=1 frame (4 ms)

•••

FFh Sleep period = 255 frames (1.020s)

SLEEP_REMAINING

Returns value of sleep counter when sleep mode

is interrupted by a “wake” signal

R

00h Normal expiration of sleep counter

01h One frame left before normal expiration

•••

FFh 255 frames left before normal expiration

Notes:

1. SLEEP_PERIOD. In sleep mode, the RFEON pin is active. Changes to this bit take effect immediately.

2. SLEEP_REMAINING. A non-zero value indicates that the Z87001 was awakened by a key press activating one of the wake-up

pins on port 0. In this case, the processor should immediately reset the SLEEP_WAKE field in SSPSTATE to prevent the pro-

cess from going back to sleep when the user key press ceases.

DS96WRL0800

P R E L I M I N A R Y

35

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

REGISTER DESCRIPTION (Continued)

Table 14. Bank 3 Register Description

SSPSTATE

Field

Bank 3

Bit Position

EXT2

R/W Data Description

SW_SYLE

f---------------

-e--------------

--d-------------

Controls accelerated synthesizer programming after sleep

Not Active

Active

R/W 0*

1

STOP_CODCLK

DBP_STOP_CLOCK

Inhibits toggling of codec clock output during sleep

CODCLK is free running

CODCLK is frozen high

R/W 0*

1

Controls toggling of CLKOUT output pin (clock for ADPCM

Processor).

R/W 0*

1

CLKOUT is free running

CLKOUT is frozen high

BSYNC_GAIN

BIAS_ENABLE

TX_ENABLE

---c------------

----b-----------

-----a----------

Selects gain for ﬁrst order loop of the bit synchronizer

Nominal gain

Gain divided by 64

R/W 0*

1

Controls closed-loop AFC circuit

No new bias estimation is performed (latest estimate used)

Enables BIAS_ERROR_DATA updates

R/W 0*

1

Global enable for all transmit functions

Transmitter disabled

Transmitter enabled

R/W 0*

1

SYNC_SEARCH_WORD ------9---------

Controls the word searched for in search mode

Search for UW pattern (Unique Word)

Search for SYNC_D pattern

R/W 0*

1

SYNC_SEARCH_MODE -------87-------

Controls the search mode (and frame synchronization)

No search

R/W 00*

01

10

11

Window search (<= UW_LOCATION & WINDOW_SIZE)

Full search (during whole frame)

Not used

HOP_ENABLE

---------6------

----------5-----

Enables transmission of the hop pulse on SYLE pin

Hop pulse disabled

Hop pulse enabled

R/W 0

1

SYNC_ACQ_CLEAR

Clears the SYNC_ACQ_IND ﬂag.

Returns last value written

R

W

1->0 A transition from 1 to 0 clears the ﬂag

FRAME_START_CLEAR -----------4----

Clears the FRAME_START_IND ﬂag

Returns last value written

R

W

1->0 A transition from 1 to 0 clears the ﬂag

SLEEP_WAKE

------------3---

Enable bit for entering sleep mode

R/W 0

1

Wake mode only

Sleep mode can be activated by GO_TO_SLEEP

command

MULTIPLEX_SWITCH

-------------21-

Controls operation of the transceiver

SMUX (bit inversion and ADPCM Processor access

disabled)

STMUX (bit inv. enabled; ADPCM Proc. access disabled)

Reserved

R/W 00*

01

10

11

TMUX (bit inversion and ADPCM Processor access

enabled)

36

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 14. Bank 3 Register Description

SSPSTATE

Field

Bank 3

Bit Position

EXT2

R/W Data Description

1

GO_TO_SLEEP

--------------0

Command bit to place the Z87001 in sleep mode

Returns last value written

R

W

0->1 A transition from 0 to 1 causes Z87001 sleep mode

TX_ENABLE

-----a----------

------9---------

-------87-------

Global enable for all transmit functions

Transmitter disabled

Transmitter enabled

R/W 0*

1

SYNC_SEARCH_WORD

SYNC_SEARCH_MODE

Controls the word searched for in search mode

Search for UW pattern (Unique Word)

Search for SYNC_D pattern

R/W 0*

1

Controls the search mode (and frame synchronization)

No search

R/W 00*

01

10

11

Window search (<= UW_LOCATION & WINDOW_SIZE)

Full search (during whole frame)

Not used

HOP_ENABLE

---------6------

----------5-----

-----------4----

------------3---

-------------21-

Enables transmission of the hop pulse on SYLE pin

Hop pulse disabled

Hop pulse enabled

R/W

0

1

SYNC_ACQ_CLEAR

FRAME_START_CLEAR

SLEEP_WAKE

Clears the SYNC_ACQ_IND ﬂag.

Returns last value written

A transition from 1 to 0 clears the ﬂag

R

W

1->0

Clears the FRAME_START_IND ﬂag

Returns last value written

A transition from 1 to 0 clears the ﬂag

R

W

Enable bit for entering sleep mode

Wake mode only

Sleep mode can be activated by GO_TO_SLEEP command

R/W

0

1

MULTIPLEX_SWITCH

Controls operation of the transceiver

R/W 00*

SMUX (bit inversion and ADPCM Processor access disabled)

STMUX (bit inv. enabled; ADPCM Proc. access disabled)

Reserved

01

10

11

TMUX (bit inversion and ADPCM Processor access enabled)

GO_TO_SLEEP

---------------0

Command bit to place the Z87001 in sleep mode

Returns last value written

R

W

0->1

A transition from 0 to 1 causes Z87001 sleep mode

Notes:

1. DBP_STOP_CLOCK. When this bit is set to 1, the ADPCM Processor clock (CLKOUT) is stopped within two clock periods. When

this bit is set to 0, the ADPCM Processor clock restarts within two clock periods; in every case, the ADPCM Processor clock min-

imum specifications for high time and low time are respected.

2. BSYNC_GAIN. Changes to this bit take effect immediately.

BIAS_ENABLE. This bit is a global enable for the Automatic Frequency Control. When the bit is set, the AFC hardware updates

the current BIAS_ERROR_DATA during specific time windows, controlled by the event trigger hardware and suitable for a good

operation of the AFC. When the bit is reset, the AFC operation is suspended. However, the current BIAS_ERROR_DATA, result-

ing from previous bias estimations, can still be used to bias the downconverter NCO. Changes to the BIAS_ENABLE bit take effect

at the beginning of the frame following the change.

3. TX_ENABLE. Global control for all system transmit functions, including PAON pin control (timing set by the RFTX_PWR_ON/OFF

register fields) and power to the modulator and NCO (timing set by MOD_PWR_ON and the wake/sleep modes).

4. Changes to this bit take effect immediately.

5. HOP_ENABLE. Changes to this bit take effect immediately.

6. SLEEP_WAKE. This bit must be set to enable the core to put itself to sleep via the GO_TO_SLEEP command. The SLEEP_WAKE

bit must be reset to prevent the core to fall back to sleep after it is awaken by one of the Port 0 Wake-up pins when the sleep period

has not expired. If the bit is not reset, the core will fall right back to sleep when the wake-up input is de-asserted (note that by

design, a wake-up input has a minimum of 10 ms duration, to allow the software enough time to safely reset the SLEEP_WAKE

bit).

7. SYNC_AQC_CLEAR. This bit must be set to “1” again after every “clear” operation to allow for the next “clear”.

8. FRAME_START_CLEAR. This bit must be set to “1” again after every “clear” operation to allow for the next ?“clear”.

DS96WRL0800

P R E L I M I N A R Y

37

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

REGISTER DESCRIPTION (Continued)

Table 15. Bank 3 Register Description

EXT3

SSPSTATUS

Field

Bank 3

Bit Position

R/W

Data

Description

FRAME_COUNTER

fedcba987------

Current frame counter value

R

00h First value at beginning of frame (0)

...

173h Last value at end of frame (371)

...

Illegal values

No effect

W

RESERVED

---------65----

-----------4---

R

W

Returns 0

No effect

HAND_BASE_SEL

Reﬂects status of Handset/Base select pin (HBSW)

Base (HBSW = 0)

Handset (HBSW = 1)

R

0

1

W

No effect

SYNC_ACQ_IND

------------3--

Indicates detection of a Sync word (UW or SYNC_D

depending on SYNC_SEARCH_WORD search mode)

No sync word detected

Sync word detected

R

W

0

1

No effect

FRAME_START_IND ------------2--

Indicates start of a new frame

No start of new frame (1 written to

FRAME_START_CLR)

New frame started

R

0

1

W

No effect

RESERVED

-------------10

R

W

Returns 0

No effect

Notes:

FRAME_COUNTER. Read the double-buffered current value of the Frame Counter.

On the handset, a single frame counter is used to clock transmit and receive events.

On the base station, the transmit frame counter value is returned

Table 16. Bank 3 Register Description

GPIO0DIR

Field

Bit 3

Bit Position

EXT4

R/W

Data Description

Independent control of Port 0 pin direction

DIRECTION0

fedcba9876543210

R/W

..0. Sets pin in input mode

..1. Sets pin in output mode

38

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 17. Bank 3 Register Description

GPIO0DATA

Field

Bank 3

Bit Position

EXT5

R/W

Data

Description

Access to Port 0 data

XXXXh Reads pin values

XXXXh Writes output pin values

1

DATA0

fedcba9876543210

R

W

Notes:

DATA0. The read value returns the actual pin values and does not depend on the pin directions

(i.e. for output pins, the output value is returned unless a contention occurs).

Table 18. Bank 3 Register Description

GPIO1DIR

Field

Bank 3

Bit Position

EXT6

R/W

Data

Description

DIRECTION1

fedcba9876543210

Independent control of Port 1 pin direction

R/W

..0. Pin in input mode

..1. Pin in output mode

Table 19. Bank 3 Register Description

EXT7

GPIO1DATA

Field

Bank 3

Bit Position

R/W

Data

Description

Access to Port 1 data

XXXXh Reads pin values

XXXXh Writes output pin values

DATA1

fedcba9876543210

R

W

Notes:

DATA1. The read value returns the actual pin values and does not depend on the pin directions

(i.e. for output pins, the output value is returned unless a contention occurs)

DS96WRL0800

P R E L I M I N A R Y

39

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Bank 2 Registers

Table 20. Bank 2 Register Description

EXT0

VP_INOUT

Field

Bank 2

Bit Position

R/W

Data

Description

RESERVED

fedcba98--------

R

W

Returns 0

No effect

VP_STATUS

--------76543210

Access to ADPCM Processor’s Command/Status

mailbox

R

XXh Reads Status byte from ADPCM Processor

VP_COMMAND

--------76543210

Access to ADPCM Processor’s Command/Status

mailbox

W

XXh Writes Command byte to ADPCM Processor

Table 21. Bank 2 Register Description

EXT1

RX_CONTROL

Field

Bank 2

Bit Position

R/W

Data

Description

SNR_ESTIMATE

UW_LOCATION

Notes:

fedcba9876543210

Access to channel measurement (SNR) estimate

Returns the SNR value

R

XXXXh

-------876543210

Location of the Unique Word

XXXXh Initializes the value that the receive frame counter

is set to on detection of the Unique Word

W

SNR_ESTIMATE. This value is updated every frame. It should be read by

the software during the frequency hopping guard time of the next frame.

Table 22. Bank 2 Register Description

BIAS_ERROR

Field

Bank 2

Bit Position

EXT2

R/W

Data

Description

BIAS_ERROR_DATA

fedcba9876543210

Access to the bias estimate from the AFC loop.

R

W

XXXXh Current bias estimate value

No effect

Notes:

BIAS_ERROR_DATA. This value is used to bias the downconverter’s NCO if the USE_CORE_BIAS register field is reset. It is en-

coded as a 2’s complement number. The unit is 125 Hz

.

40

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 23. Bank 2 Register Description

RSSI

Field

Bank 2

Bit Position

EXT3

R/W

Data

Description

1

RESERVED

fedcba98--------

R

W

Returns 0

No effect

RSSI_DATA

-------76543210

Access to 8-bit ADC (can be used for RSSI data)

R

W

XXh Returns latest value on 8-bit DAC

No effect

Note:

RSSI_DATA. This value is sampled once per frame (4ms) approximately at bit 72 (middle) of the received data.

Table 24. Bank 2 Register Description

CORE_BIAS

Field

Bank 2

Bit Position

EXT4

R/W

Data

Description

RESERVED

fed-------------

R

W

Returns 0

No effect

CORE_BIAS_DATA

---cba9876543210

Stores bias value for correction of downconverter’s

NCO.

R

Returns 0

W

xXXXh Updates bias value

Notes:

CORE_BIAS_DATA.This value is used if the USE_CORE_BIAS register field is set. It is encoded as a 2’s complement number.

The unit is 125 Hz.

Table 25. Bank 2 Register Description

MOD_PWR_CTRL

Field

Bank 2

Bit Position

EXT5

R/W

Data

Description

RESERVED

f---------------

R

W

Returns 0

No effect

MOD_PWR_ON

-edcba98--------

Determines modulator turn-on time referenced to the

transmit frame counter

R

Returns 0

W

xXh Bits 6-0 of turn-on time (=(x modulo 128) -1)

RESERVED

--------76543210

R

W

Returns 0

No effect

Notes:

1. MOD_PWR_ON. Controls the turn-on time for the internal modulator and NCO. Only the 7 LSBits of the 9-bit value necessary

to encode an event (from frame counter 0 to 371) are programmable. The two MSBits have fixed values which depend on

whether base station or handset is selected: “00” on the base and “01” on the handset. The modulator’s turn-off time occurs

a fixed time (number of bits) after the turn-on time: 144 bits on the base station, 148 bits on the handset.

2. Changes to this value take effect immediately.

3. To disable the modulator continuously, clear TX_ENABLE

DS96WRL0800

P R E L I M I N A R Y

41

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

REGISTER DESCRIPTION (Continued)

Table 26. Bank 2 Register Description

DEMOD_PWR_CTRL Bank 2

EXT6

Field

Bit Position

R/W

Data

Description

RFEON_POLARITY

f---------------

Controls the polarity of the RFEON output pin

R

W

Returns 0

Active high

Active Low

0

1

DEMOD_PWR_ON

-edcba98--------

Determines internal power up of demodulator and turn

on time of RXSW pin, referenced to the receive frame

counter

R

Returns 0

W

xXh Bits 6-0 of turn-on time (=(x modulo 128) -1)

RESERVED

--------7-------

---------6543210

R

W

Returns 0

No effect

DEMOD_PWR_OFF

Determine internal power down of demodulator and

turn off time of RXSW pin, referenced to the receive

frame counter

R

Returns 0

W

XXh Bits 6-0 of turn-off time (=(x modulo 128) -1)

Notes:

1. DEMOD_PWR_ON, DEMOD_PWR_OFF. Controls internal receive hardware and the RXSW output pin. The turn-on and off times

are given in number of received bit periods and are referenced to the Receive Frame Counter. Only the 7 LSBits of the 9-bit value

are programmable. The two MSBits have fixed values which depend on whether base station or handset is selected. For

DEMOD_PWR_ON, the two bits are “01” on the base and “00” on the handset. For DEMOD_PWR_OFF, the two bits are “10” on

the base and “01” on the handset

2. Changes to these values take effect immediately.

3. To enable receive power continuously, clear TX_ENABLE and set SYNC_SEARCH_MODE to FULL_SEARCH (this is the case

in acquisition mode).

4. The polarity of the RXSW output pin is controlled by the RFRX_POLARITY bit in the RFRX_PWR_CTRL register

.

42

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 27. Bank 2 Register Description

RFTX_PWR_CTRL

Field

Bank 2

Bit Position

EXT7

R/W

Data

Description

1

RFTX_POLARITY

f---------------

-edcba98--------

Controls the polarity of the PAON output pin

R

W

Returns 0

Active high

Active Low

0

1

RFTX_PWR_ON

Determines PAON output pin turn-on time

referenced to the transmit frame counter

Returns 0

R

W

xXh Bits 6-0 of turn-on time (=(x modulo 128) -1)

RESERVED

--------7-------

---------6543210

R

W

Returns 0

No effect

RFTX_PWR_OFF

Determine PAON output pin turn-off time

referenced to the transmit frame counter

Returns 0

R

W

xXh Bits 6-0 of turn-off time (=(x modulo 128) -1)

Notes:

1. RFTX_PWR_ON, RFTX_PWR_OFF. Controls the PAON output pin, and thereby the external RF module’s transmitter.

The turn-on and off times are given in number of transmitted bit periods and are referenced to the transmit Frame Counter.

Only the 7 LSBits of the 9-bit value are programmable. The two MSBits have fixed values which depend on whether base

station or handset is selected. For RFTX_PWR_ON, the two bits are “00” on the base and “01” on the handset. For

RFTX_PWR_OFF, the two bits are “01” on the base and “10” on the handset.

2. Changes to these values take effect immediately.

3. To disable the transmitter continuously, clear TX_ENABLE in SSP_STATE.

DS96WRL0800

P R E L I M I N A R Y

43

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Bank 1 Registers

Table 28. Bank 1 Register Description

EXT0

RATE_BUF_ADDR

Field

Bank 1

Bit Position

R/W Data

Description

RESERVED

f--------------

R

W

Returns 0

No effect

RX_AUTO_INCREMENT -e-------------

Controls the auto-increment feature of the Rx rate

R

buffer

W

0

1

Returns 0

Disables auto-increment

Enables auto-increment

RX_BUF_ADDR

--dcba98--------

Access to Rx rate buffer address

Returns 0

R

W

00h Address 0

... ...

23h Address 23h = 35

... Illegal

RESERVED

--------7-------

R

W

Returns 0

No effect

TX_AUTO_INCREMENT ---------6------

Controls the auto-increment feature of the Tx rate

R

buffer

W

0

1

Returns 0

Disables auto-increment

Enables auto-increment

TX_BUF_ADDR

----------543210

Access to Tx rate buffer address

Returns 0

R

W

00h Address 0

... ...

23h Address 23h = 35

24h Tx/Rx rate buffer address for ADPCM Processor

25h accesses

26h Tx/Rx Nibble Marker bits [15..0]

27h Tx/Rx Nibble Marker bits [31..16]

28h Tx/Rx Nibble Marker bits [35..32]

29h MOD_FREQ_DEV 0

2Ah MOD_FREQ_DEV 1

2Bh MOD_FREQ_DEV 2

2Ch MOD_FREQ_DEV 3

2Dh MOD_FREQ_DEV 4

2Eh MOD_FREQ_DEV 5

2Fh MOD_FREQ_DEV 6

30h MOD_FREQ_DEV 7

31h MOD_FREQ_DEV 8

32h MOD_FREQ_DEV 9

... MOD_CENTER_FREQ

Illegal

44

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

REGISTER DESCRIPTION (Continued)

Table 29. Bank 1 Register Description

RATE_BUF_DATA

Field

Bank 1 EXT1

Bit Position

R/W

Data

Description

RX_BUF_DATA

------------3210

Access to the Rx rate buffer data

R

Xh Reads value at current RX_BUF_ADDR

address (0 to 23h)

TX_BUF_DATA

------------3210

--dcba98--------

Access to the Tx rate buffer data

XXXXh Writes value at current TX_BUF_ADDR address

(0 to 23h)

W

TX_BUF_VP_ADDR

Sets the initialization value of the Tx rate buffer

address used for ADPCM Processor accesses

XXh Writes initialization value (TX_BUF_ADDR

address= 24h)

W

RX_BUF_VP_ADDR

----------543210

Sets the initialization value of the Rx rate buffer

address used for ADPCM Processor accesses

XXh Writes initialization value (TX_BUF_ADDR

address= 24h)

TX_RX_NIBBLE_MARKER fedcba9876543210

Sets the Nibble Marker register for Tx and Rx

rate buffer accesses by ADPCM Processor

XXXXh Write nibble marker value (TX_BUF_ADDR=

25h to 27h)

W

MOD_FREQ

fedcba9876543210

Access to modulator settings

XXXXh Writes modulator setting value

(TX_BUF_ADDR=28h to 32h)

Note:

The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register.

MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz.

These words are encoded as 2’s complement numbers.

The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register.

MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz.

These words are encoded as 2’s complement numbers.

Table 30. Bank 1 Register Description

BIT_SYNC

Field

Bank 1

Bit Position

EXT2

R/W

Data

Description

INT_SYM_ERR1

fedcba9876543210

Read access to the integrated symbol error from the bit

synchronizer’s second order loop

R

XXXXh Reads error data bits [23..8] (bits [7..0] are in bank 0,

EXT6)

SECOND_ORDER fedcba9876543210

Write access to the bit synchronizer’s second-order loop

XXXXh Writes second order loop’s 16-bit value

W

45

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 31. Bank 1 Register Description

EXT3

RESERVED

Field

Bank 1

Bit Position

EXT4

EXT5R/W Data

Description

RESERVED

fedcba9876543210

R

Returns 0

W

0000h Must be left alone or written to 0000h (or

unpredictable results may occur)

Table 32. Bank 1 Register Description

Bank 1 EXT6

CONTROL

Field

Bit Position

R/W

Data

Description

RESERVED

fedcb-----------

R

W

Returns 0

No effect

FS_INT_ENABLE

-----a----------

Controls frame start interrupt (INT1)

Disables frame start interrupt

Enables frame start interrupt

R/W

0*

1

INTERRUPT_0_ENABLE ------9---------

INTERRUPT_2_ENABLE -------8--------

Controls interrupt 0 (INT0 on P114)

Disables interrupt 0

Enables interrupt 0

0*

1

Controls interrupt 2 (INT2 on P115)

Disables interrupt 2

Enables interrupt 2

0*

1

P0_WAKEUP_ENABLE

--------7654----

Controls wake-up pins (P0[3..0])

R/W 0000* Disables all wake-up pins

1xxx Enables P03 as wake-up pin (if in input mode)

x1xx Enables P02 as wake-up pin (if in input mode)

xx1x Enables P01 as wake-up pin (if in input mode)

xxx1 Enables P00 as wake-up pin (if in input mode)

TX_PWR_DAC_DATA

------------3210

Access to Tx power 4-bit DAC output data

R/W

Xh Sets output value

Note:

P0_WAKEUP_ENABLE. When enabled, pins P0[3..0] are active low wake-up pins for the Z87001 sleep mode.

The input signal is internally debounced and synchronized to the bit clock. It is internally given a minimum duration of one bit to

allow the software to exit sleep mode safely.

Table 33. Bank 1 Register Description

RESERVED

Field

Bank 1

Bit Position

EXT7

R/W

Data

Description

RESERVED

fedcba9876543210

R

W

Returns 0

No effect

46

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Bank 0 Registers

Table 34. Bank 0 Register Description

1

EXT0

EXT1

EXT2

EXT3

EXT4

EXT5

R/W

RESERVED

Field

Bank 0

Bit Position

Data

Description

RESERVED

fedcba9876543210

R

W

Returns 0

No effect

Table 35. Bank 0 Register Description

EXT6

INT_SYM_ERR0

Field

Bank 0

Bit Position

R/W

Data

Description

RESERVED

fedcba98--------

R

W

Returns 0

No effect

INT_SYM_ERR0

--------76543210

Read access to the integrated symbol error from the

bit synchronizer’s second order loop

R

XXh Reads error data bits [7..0] (bits [23..8] are in bank1,

EXT2)

W

No effect

DS96WRL0800

P R E L I M I N A R Y

47

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 36. Bank 0 Register Description

EXT7

RFRX_PWR_CTRL

Field

Bank 0

Bit Position

R/W

Data

Description

RFRX_POLARITY

f---------------

Controls the polarity of the TXSW (and RXSW)

output pins

R

Returns 0

W

0

1

TXSW active Low and RXSW active High

TXSW active High and RXSW active Low

RFRX_PWR_ON

-edcba98--------

Determines TXSW output pin turn-on time

referenced to the transmit frame counter

Returns 0

R

W

xXh Bits 6-0 of turn-on time (=(x modulo 128) -1)

RESERVED

--------7-------

---------6543210

R

W

Returns 0

No effect

RFRX_PWR_OFF

Determine TXSW output pin turn-off time

referenced to the transmit frame counter

Returns 0

R

W

xXh Bits 6-0 of turn-off time (=(x modulo 128) -1)

Notes:

1. RFRX_POLARITY. Caution: notice the inverse polarity of the TXSW pin.

2. RFRX_PWR_ON, RFRX_PWR_OFF. Controls the TXSW output pin. The turn-on and off times are given in number of trans-

mitted bit periods and are referenced to the TRANSMIT (!) Frame Counter. Only the 7 LSBits of the 9-bit value are program-

mable. The two MSBits have fixed values which depend on whether base station or handset is selected. For

RFRX_PWR_ON, the two bits are “00” on the base and “01” on the handset. For RFRX_PWR_OFF, the two bits are “01”

on the base and “10” on the handset.

3. Changes to these values take effect immediately.

4. To disable transmit power continuously, clear TX_ENABLE.

48

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

INSTRUCTION SET DESCRIPTION

Refer to Zilog’s Z89C00 User’s Manual, Chapter 5 (In-

struction Set Features) and Chapter 6 (Assembly Lan-

guage Instruction Set), for a complete description of the

core processor’s instruction set.

1

Table 37. Instruction Set Summary

#

Instruction Description Opcode

Synopsis

Operands

Words Cycles

Example

ABS

Absolute Value

ABS[<cc>,]<src>

1001000

<cc>,A

A

1

ABS NC,A

ABS A

ADD

Addition

ADD<dest>,<src>

AND<dest>,<src>

CALL

1001001

1000001

1000100

1000101

1000011

1000001

1000000

A,<pregs>

A,<dregs>

A,<limm>

A,<memind>

A,<direct>

A,<regind>

A,<hwregs>

1

2

1

2

3

1

ADD A,P0:0

ADD A,D0:0

ADD A,#%1234

ADD A,@@P0:0

ADD A,%F2

ADD A, @P1:1

ADD A,X

AND

Bitwise AND

1011001

1010001

1010100

1010101

1010001

1010000

A,<pregs>

A,<dregs>

A,<limm>

A,<memind>

A,<direct>

A,<regind>

A,<hwregs>

1

2

1

2

3

1

AND A,P2:0

AND A,D0:1

AND A,#%1234

AND A,@@P1:0

AND A, %2C

AND A,@P1:2+LOOP

AND A, EXT3

CALL

Subroutine call

0010100 [<cc>,]<address>

0010100

2

CALL sub1

CALL Z,sub2

CCF

CIEF

COPF

CP

Clear carry ﬂag

Clear Carry Flag

Clear OP ﬂag

Comparison

CCF

1001010

None

1

CCF

CIEF

1001010

CIEF

COPF

1001010

CP<src1>,<src2>

0111001

A,<pregs>

A,<dregs>

A,<memind>

A,<direct>

A,<regind>

A,<hwregs>

A,<limm>

1

2

1

3

1

2

CP A,P0:0

CP A,D3:1

0110001

0110101

0110011

0110001

0110000

0110100

CP A,@@P0:0

CP A,%FF

CP A,@P2:1+

CP A,STACK

CP A,#%FFCF

DEC

INC

JP

Decrement

Increment

Jump

DEC [<cc>,]<dest>

1001000

<cc>A,

A

1

DEC NZ,A

DEC A

INC [<cc>,] <dest>

1001000

<cc>,A

A

1

INC PL,A

INC A

JP [<cc>,]<address>

0100110

2

JP NIE,Label

JP Label

DS96WRL0800

P R E L I M I N A R Y

49

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 37. Instruction Set Summary

#

Instruction Description Opcode

Synopsis

Operands

Words Cycles

Example

LD

Loaddestination

with source

LD<dest>,<src>

0000000

0000001

0001001

0000001

0000101

0000011

0000111

0000100

0001100

0001010

0000110

0000010

0001001

0000001

0000100

0100101

0000101

0000001

0000000

A,<hwregs>

A,<dregs>

A,<pregs>

A,<regind>

A,<memind>

A,<direct>

<direct>,A

1

2

1

3

1

2

3

1

LD A,X

LD A,D0:0

LD A,P0:1

LD A,@P1:1

LD A,@D0:0

LD A, 124

LD 124, A

LD DO:0, EXT7

LD P1:1,#%FA

LD P1:1,EXT1

LD @P1:1,#%1234

LD @P1:1+,X

LD Y,P0:0

LD SR,D0:0

LD PC,#%1234

LD X,@A

LD Y,@D0:0

LD A,@P0:0-LOOP

LD X, EXT6

MLD

Multiply

1010010 MLD<srcl>,<srcl>

1010010 [,<bank switch>]

1011011

<hwregs>,<regind>,<ban

k switch>

<regind>,<regind>,<bank

switch>

1

MLD A,@P0:0+LOOP

MLD A,@P1:0,OFF

MLD @P1:1,@P2:0

MLD@P0:1,@P1:0,O

N

1011011

MPYA

MPYS

NEG

Multiply and add

MPYA <srcl>,<src2>

1010010 [,<bank switch>]

1010010

1011011

<hwregs>,<regind>,<ban

k switch>

<regind>,<regind>,<bank

switch>

1

MPYA A@P0:0

MPYA A,@P1:0,OFF

MPYA @P1:1,@P2:0

MPYA@P0:1,@P1:0,

ON

Multiply and

subtract

MPYS<src1>,<src2>

0010010 [,<bank switch>]

0010010

0011011

<hwregs>,<regind>,<ban

k switch>

<regind>,<regind>,<bank

switch>

1

MPYS A,@P0:0

MPYS A,@P1:0,OFF

MPYS @P1:1,@P2:0

MPYS@P0:1,@P1:0,

ON

Negate

NEG <cc>,A

1001000

<cc>, A

A

1

NEG NZ,A

NEG A

NOP

OR

No operation

Bitwise OR

NOP

0000000

None

1

NOP

OR <dest>,<src>

1101001

A, <pregs>

A, <dregs>

A, <limm>

A, <memind>

A, <direct>

A, <regind>

A, <hwregs>

1

2

1

2

3

1

OR A, P0:1

OR A, D0:1

1100001

1100100

1100101

1100011

1100001

1100000

OR A,#%202

OR A,@@P2:1+

OR A, %2C

OR A, @P1:0-LOOP

OR A, EXT6

50

P R E L I M I N A R Y

DS96WRL0800

Z87001/Z87L01

ROMless Spread Spectrum Cordless Phone Controller

Zilog

Table 37. Instruction Set Summary

#

Instruction Description Opcode

Synopsis

Operands

Words Cycles

Example

1

POP

Pop value

from stack

POP <dest>

0001010

0000100

0000010

0000000

<pregs>

1

POP P0:0

<regs>

POP D0:1

POP @P0:0

POP A

PUSH

Push value

onto stack

PUSH <src>

0001001

0000001

0000000

0000100

0100101

0000101

<pregs>

<dregs>

<limm>

1

2

1

2

3

PUSH P0:0

PUSH D0:1

PUSH @P0:0

PUSH BU5

PUSH #12345

PUSH @A

PUSH @@P0:0

RET

RL

Return from

subroutine

RET

0000000

None

1

2

RET

Rotate Left

RL <cc>,A

1001000

<cc>,A

A

1

RL NZ,A

RL A

RR

Rotate Right

RR <cc>,A

1001000

<cc>,A

A

1

RR C,A

RR A

SCF

SIEF

SLL

Set C ﬂag

SCF

SIEF

SLL

1001010

None

1

SCF

Set IE ﬂag

SIEF

Shift left logical

1001000

[<cc>,]A

A

1

SLL NZ,A

SLL A

SOPF

SRA

Set OP ﬂag

SOPF

1001010

None

1

SOPF

Shift right

arithmetic

SRA<cc>,A

1001000

<cc>,A

A

1

SRA NZ,A

SRA A

SUB

Subtract

SUB<dest>,<src>

0011001

0010011

0010100

0010101

0010011

0010001

0010000

A,<pregs>

A,<dregs>

A,<limm>

A, <memind>

A, <direct>

A, <regind>

A, <hwregs>

1

2

1

2

3

1

SUB A,P1:1

SUB A,D0:1

SUB A,#%2C2C

SUB A,@D0:1

SUB A,%15

SUB A, @P2:0-LOOP

SUB A, STACK

XOR

Bitwise

exclusive

OR

XOR <dest>,<src>

1111001

1110001

1110100

1110001

1110011

1110001

1110000

A, <pregs>

A, <dregs>

A, <limm>

A, <memind>

A, <direct>

A, <regind>

A, <hwregs>

1

2

1

2

3

1

XOR A, P2:0

XOR A,D0:1

XOR A,#13933

XOR A,@P2:1+

XOR A, %2F

XOR A, @P2:0

XOR A, BUS

DS96WRL0800

P R E L I M I N A R Y

51


型号：	Z87001
厂家：	ZILOG, INC.
描述：	ROMless Spread Spectrum Cordless Phone Controller 无ROM扩频无绳电话控制器无绳电话集成电路电信集成电路电信电路无绳技术控制器
文件：	总51页 (文件大小：204K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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