Z90365 [ZILOG]
Digital Television Controller; 数字电视控制器
| 型号： | Z90365 |
| 厂家： | 
ZILOG, INC. |
| 描述： | Digital Television Controller |
| 文件： | 总8页 (文件大小：38K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z90365
1
DIGITAL TELEVISION CONTROLLER
FEATURES
■ Character-Control and Closed-Caption Modes
■ Keypad User Control
ROM
(KW)
RAM*
(Words) (8-Bit)
640
PWM
Voltage
Range
Device
Z90365
32
8
4.5 to 5.5V
■ TV Tuner Serial Interface
■ Direct Video Signals
Note: *General-Purpose
■ 42-Pin SDIP
■ Supports Violence Blocking
■ Speed: 12 MHz
■ 0°C to +70°C Temperature Range
■ Fully Customized Character Set
GENERAL DESCRIPTION
The Z90365 Digital Television Controller is designed to
provide complete audio and video control of television re-
ceivers, video recorders, and advanced on-screen display
facilities. The television controller features a Z89C00 RISC
processor core that controls the on-board peripheral func-
tions and registers using the standard processor instruc-
tion set.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tuning adjustments, may be accessed
2
through the industry-standard I C port.
User control can be monitored through the keypad scan-
ning port, or the 16-bit remote control capture register. Re-
ceiver functions such as color and volume can be directly
controlled by eight 8-bit pulse width modulated ports.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode pro-
vides access to the full set of attribute controls, allowing the
modification of attributes on a character-by-character ba-
sis. The insertion of control characters permits direction of
other character attributes. Closed-caption text can be de-
coded directly from the composite video signal and dis-
played on-screen with the assistance of the processor's
digital signal processing (DSP) capabilities.
Notes: All Signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Circuit
Device
V
V
DD
CC
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of dis-
play attributes that include underlining, italics, blinking,
eight foreground/background colors, character position off-
set delay, and background transparency.
Ground
GND
V
SS
CP97TEL2800
P R E L I M I N A R Y
1
Z90365
Digital Television Controller
Zilog
GENERAL DESCRIPTION (Continued)
PWM
Capture
IRIN
PWM1
PWM2
PWM3
PWM4
PWM5
PWM9
PWM10
ADC
ADC0
Port 17
Port 00
ADC1
ADC2
ADC3
ADC4
Port 0
Port1
Port 00
Port 01
Port 02
Port 03
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0F
Control
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
OSD
V1
Register Addr/Data
V2
V3
CPU
VBLANK
HALFBLNK
Port0F
RAM
640 x 16
Address
ROM Addr
ROM Data
ROM
32K x 16
Data
Figure 1. Functional Block Diagram
2
P R E L I M I N A R Y
CP97TEL2800
Z90365
Digital Television Controller
Zilog
PIN DESCRIPTION
1
1
2
3
4
5
6
42
41
40
39
38
37
36
35
34
Port12/I2MSD
P11/I2MSC
PWM10
PWM9
PWM5
Port02/I2SSD
PWM4
PWM3
Port01/I2SSC
Port09
PWM2
Port08/R<1>
PWM1
Port03
7
IRIN
Port07/CSync
8
9
Vcc
Port04/ADC4
Port05/ADC3
Port00/ADC2
/Reset
XTAL2
10
11
12
13
14
15
16
17
18
19
20
21
33
32
31
30
Z90365
Shrink
DIP
Port17/ADC1
GND
XTAL1
ANGND
LPF
Port10/R<0>
29
28
27
26
25
24
CVI/ADC0
VSync
Port06/Counter
Port18/G<0>
Port13/G<1>
HSync
Port14/B<0>
Port15/B<1>
VBlank
V1
Port16/SCLK
23
22
V2
V3
Port0F/Half Blank
Figure 2. 42-Pin Shrink DIP
CP97TEL2800
P R E L I M I N A R Y
3
Z90365
Digital Television Controller
Zilog
PIN DESCRIPTION (Continued)
Table 1. 42-Pin SDIP Pin Identification
Name
Function
+ 5 Volts
0 Volts
Z90365
Direction
Reset
Notes
V
34
PWR
–
CC
GND
IRIN
13, 30
36
PWR
I
–
I
Infrared Remote Capture
Input
ADC[4:0]
4-Bit A/D Converter Input
9, 10, 11, 12, 28
1, 2
AI
O
I
PWM10, PWM9
14-Bit Pulse Width
Modulator Output
O
PWM[5:1]
Port0[F:0]
8-Bit Pulse Width Modulator
Output
3, 4, 5, 6, 7
O
B
O
I
Bit Programmable
Input/Output Ports
21, -, -, -, -, -, 38, 37,
35, -, -, 15, 8, 40, 39,
11
1
Port1[8:0]
Bit Programmable
Input/Output Ports
16, 12, 20, 19, 18, 17,
42, 41, 14
B
I
2
SCL
SCD
39 or 41
40 or 42
BOD
BOD
2
3
I C Clock I/O
2
I C Data I/O
XTAL1
XTAL2
LPF
Crystal Oscillator Input
Crystal Oscillator Output
Loop Filter
31
AI
AO
AB
B
I
O
O
I
32
29
26
HSYNC
VSYNC
/Reset
V[3:1]
H_SYNC
V_SYNC
27
B
I
Device Reset
33
I
I
OSD Video Output Typically
Drive B, G, and R Outputs
22, 23, 24
O
O
Blank
OSD Blank Output
25
21
O
O
O
O
HalfBlank
OSD HalfBlank Output
4
5
RGB Digital
Outputs
R[1:0], G[1:0], and B[1:0] 37, 14, 17, 16, 19, 18
Outputs of the RGB Matrix
SCLK
Internal Processor SCLK
20
O
6
Notes:
1. SCL I/O pin is shared with Port 0 or Port 11.
2. SCD I/O pin is shared with Port 02 or Port 12.
3. Half Blank output is a function shared with Port 0F.
4. Digital RGB outputs and the internal SCLK are shared with Port 1 [5:0].
5. Internal processor SCLK is shared with Port 16.
PWM outputs are push/pull
4
P R E L I M I N A R Y
CP97TEL2800
Z90365
Digital Television Controller
Zilog
V1, V2, V3 (R, G, B) ANALOG OUTPUT (PRELIMINARY)
T = 0°C to 70°C
A
1
Output Voltage (30 kΩ load)
Settling Time
70% of DC level, 10pF load
‹ 50 ns
V
= 4.75
5.00V
5.25V
CC
data = 00
data = 01
data = 10
data = 11
0.00v .. 0.65v
1.70v ± 0.20v
2.80v ± 0.25v
3.90v ± 0.3v
0.00v .. 0.70v
1.80v ± 0.20v
2.90v ± 0.25v
4.0v ± 0.30v
0.00v .. 0.75v
1.90v ± 0.20v
3.00v ± 0.25v
4.10v ± 0.30v
Z90365
XTAL1
22 pF
XTAL2
68 KΩ
47 pF
Figure 3. 32 kHz Oscillator Recommended Circuit
Z90365
510 Ω
0.1 µF
47 µF
Figure 4. Recommended Low Pass Filter Circuit
CP97TEL2800
P R E L I M I N A R Y
5
Z90365
Digital Television Controller
Zilog
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
0
Max
Units Conditions
V
V
V
Power Supply Voltage
Input Voltage
7
V
CC
ID
IA
O
–0.3
–0.3
–0.3
–0.3
V
V
V
V
+0.3
V
V
Digital Inputs
CC
CC
CC
CC
Input Voltage
+0.3
+0.3
+0.3
Analog Inputs (A/D0...A/D4)
All Push-Pull Digital Output
V
Output Voltage
V
V
Output Voltage
V
Push/Pull PWM Outputs (PWM1...PMW8)
O
I
I
I
I
Output Current High
Output Current High
Output Current Low
Output Current Low
Operating Temperature
Storage Temperature
–10
mA
mA
mA
mA
°C
°C
One Pin
All Pins
One Pin
All Pins
OH
–100
20
OH
OL
OL
200
70
T
0
A
T
–65
150
A
DC CHARACTERISTICS
T = 0°C to + 70°C; V = 4.5V to + 5.5V; F
= 32.768 kHz
A
CC
OSC
Symbol
Parameter
Min
Max
Typical
Units Conditions
V
V
V
V
V
V
V
V
Input Voltage Low
Input Voltage High
Max. Pull-Up Voltage
Output Voltage Low
Output Voltage High
Input Voltage XTAL1 Low
Input Voltage XTAL1 High
Schmitt Hysteresis
Reset Input Current
Input Leakage
0
0.2 V
0.4
3.6
V
V
IL
CC
0.7 V
V
IH
CC
CC
V
+0.3
V
V
All Pins
@ I = 1 mA
PU
OL
OH
XL
XH
HY
CC
0.4
0.16
4.75
1.0
OL
V
V
–0.4
–2.0
V
@ I = 0.75 mA
CC
OL
0.3 V
V
External Clock
CC
3.5
V
Generator Driven
On XTAL1 Input Pin
CC
3.0
0.75
150
3.0
0.5
V
I
I
I
I
90
µA
µA
mA
µA
V
= 0V
IR
RL
–3.0
0.01
60
@ 0V and V
CC
IL
Supply Current
100
10
CC
ADC
Input Current
Notes:
1. The Z90365 should not be operated for extended periods with the crystal oscillator disconnected, except in the defined power-
down modes. In the event that the Z90365 is operated with the oscillator disconnected, the device may draw higher than typical
current.
2. Each line of the on-screen display can consist of any number of characters, up to a maximum of 30 characters.
6
P R E L I M I N A R Y
CP97TEL2800
Z90365
Digital Television Controller
Zilog
AC CHARACTERISTICS
T = 0°C to 70°C; V = 4.5V to 5.25V; F
= 32.768 kHz
A
CC
OSC
1
Symbol
Parameter
Min
Typical Max
Units
µS
nS
S
T
T
Input Clock Period
16
32
12
100
PC
,T
Clock Input Rise and Fall
Power-On Reset Delay
Power-On Reset Minimum Width
H-SYNC Incoming Signal Width
V-SyYNC Incoming Signal Width
RC FC
TD
0.8
1.2
POR
TW
5 TPC
15
µS
µS
µS
µS
RES
HS
TD
1
1
10
200
0
TD
TD
10,000
+12
VS
Time Delay Between Leading Edge of V-SYNC and H-SYNC in –12
EVEN Field
ES
TD
Time Delay Between Leading Edge of H-SYNC in ODD Field 20
H_Sync/V_Sync Edge Width
32
44
µS
µS
OS
TW
0.5
2.0
HVS
2
2
Note: All timing of the I C bus interface are defined by related specifications of the I C bus interface.
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
CP97TEL2800
P R E L I M I N A R Y
7
Z90365
Digital Television Controller
Zilog
8
P R E L I M I N A R Y
CP97TEL2800
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