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ZGR323LAP2832G [ZILOG]

IC 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP28, GREEN, PLASTIC, DIP-28, Microcontroller;
ZGR323LAP2832G
型号： ZGR323LAP2832G
厂家： ZILOG, INC.    ZILOG, INC.
描述：

IC 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP28, GREEN, PLASTIC, DIP-28, Microcontroller

可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路
文件： 总101页 (文件大小：1885K)
中文：  中文翻译
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Z8 GPTM Microcontrollers  
ZGR323L ROM MCU  
Family  
Product Specification  
PS023910-0408  
®
Copyright ©2008 by Zilog , Inc. All rights reserved.  
www.zilog.com  
Warning: DO NOT USE IN LIFE SUPPORT  
LIFE SUPPORT POLICY  
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE  
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF  
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.  
As used herein  
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)  
support or sustain life and whose failure to perform when properly used in accordance with instructions for  
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A  
critical component is any component in a life support device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support device or system or to affect its safety or  
effectiveness.  
Document Disclaimer  
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,  
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,  
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY  
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.  
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY  
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR  
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this  
document has been verified according to the general principles of electrical and mechanical engineering.  
Z8, Z8 Encore!, Crimzon, and ZNEO are trademarks or registered trademarks of Zilog, Inc. All other  
product or service names are the property of their respective owners.  
PS023910-0408  
ZGR323L  
Product Specification  
iii  
Revision History  
Each instance in Revision History reflects a change to this document from its previous  
revision. For more details, refer to the corresponding pages and appropriate links in the  
table below.  
Revision  
Level  
Page  
No  
Date  
Description  
April 2008  
10  
Updated Part Number Description section.  
92  
All  
September 09  
2007  
Replaced OTP with ROM and EPROM with MASK throughout the  
document.  
July  
08  
Updated Disclaimer section.  
ii  
2007  
May  
07  
Added Pin 22 in SMR Input, Figure 33.  
52  
2006  
November 06  
2005  
Updated “Ordering Information” on page 89, added Caution for I/O  
ports 0, 1 and 2 on pages 17 and 18, and added new Clock information  
on pages 53 and 54.  
53, 54  
PS023910-0408  
Revision History  
ZGR323L  
Product Specification  
iv  
Table of Contents  
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Port 3 (P37–P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33  
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42  
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46  
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47  
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 58  
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 63  
Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74  
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75  
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83  
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93  
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97  
PS023910-0408  
Table of Contents  
ZGR323L  
Product Specification  
1
Architectural Overview  
Zilog’s ZGR323L is an ROM-based member of the MCU family of infrared  
microcontrollers. With 237 B of general-purpose RAM and 8 KB to 32 KB of ROM,  
Zilog’s CMOS microcontrollers offer fast-executing, efficient use of memory,  
sophisticated interrupts, input/output bit manipulation capabilities, automated pulse  
generation/reception, and internal key-scan pull-up transistors.  
The ZGR323L architecture (see Figure 1) is based on Zilog’s 8-bit microcontroller core  
with an Expanded Register File allowing access to register-mapped peripherals, input/  
output (I/O) circuits, and powerful counter/timer circuitry. The Z8® CPU offers a flexible  
I/O scheme, an efficient register and address space structure, and a number of ancillary  
features that are useful in many consumer, automotive, computer peripheral, and battery-  
operated hand-held applications.  
There are three basic address spaces available to support a wide range of configurations:  
Program Memory, Register File and Expanded Register File. The register file is composed  
of 256 Bytes of RAM. It includes 4 I/O port registers, 16 control and status registers, and  
236 general-purpose registers. The Expanded Register File consists of two additional  
register groups (F and D).  
To unburden the program from coping with such real-time problems as generating  
complex waveforms or receiving and demodulating complex waveform/pulses, the  
ZGR323L offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/  
timers (see Figure 2). Also included are a large number of user-selectable modes and two  
on-board comparators to process analog signals with separate reference voltages.  
All signals with an overline, “ ”, are active Low. For example, B/W, in which WORD is  
active Low, and B/W, in which BYTE is active Low.  
Note:  
Power connections use the conventional descriptions listed in Table 1.  
Table 1. Power Connections  
Connection  
Power  
Circuit  
Device  
V
V
V
CC  
DD  
SS  
Ground  
GND  
PS023910-0408  
Architectural Overview  
ZGR323L  
Product Specification  
2
Development Features  
Table 2 lists the features of ZGR323L members.  
Table 2. ZGR323L MCU Features  
Device  
ROM (KB) RAM* (Bytes) I/O Lines  
Voltage Range  
ZGR323L ROM MCU 8, 16, 32  
*General-purpose  
237  
32, 24 or 16 2.0 V–3.6 V  
•
•
Low power consumption—5 mW (typical)  
T = Temperature  
S = Standard 0 °C to +70 °C  
E = Extended -40 °C to +105 °C  
A = Automotive -40 °C to +125 °C  
•
•
Three standby modes:  
–
–
–
STOP—1.4 μA (typical)  
HALT—0.5 mA (typical)  
Low-voltage reset  
Special architecture to automate both generation and reception of complex pulses or  
signals:  
–
–
–
One programmable 8-bit counter/timer with two capture registers and two load  
registers  
One programmable 16-bit counter/timer with one 16-bit capture register pair and  
one 16-bit load register pair  
Programmable input glitch filter for pulse reception  
•
Six priority interrupts  
–
–
–
Three external  
Two assigned to counter/timers  
One Low-Voltage Detection interrupt  
•
•
•
•
Low-voltage detection and high-voltage detection flags  
Programmable Watchdog Timer/Power-On Reset (WDT/POR) circuits  
Two independent comparators with programmable interrupt polarity  
Programmable MASK options  
PS023910-0408  
Architectural Overview  
ZGR323L  
Product Specification  
3
–
–
–
–
–
–
Port 0: 0–3 pull-up transistors  
Port 0: 4–7 pull-up transistors  
Port 1: 0–3 pull-up transistors  
Port 1: 4–7 pull-up transistors  
Port 2: 0–7 pull-up transistors  
WDT enabled at POR  
Functional Block Diagram  
Figure 1 displays the ZGR323L MCU functional block diagram.  
P00  
P01  
P02  
P03  
Register File  
256 x 8-Bit  
Pref1/P30  
P31  
P32  
P33  
P34  
P35  
P36  
P37  
4
4
I/O Nibble  
Programmable  
Port 0  
Port 1  
Port 2  
Port 3  
P04  
P05  
P06  
P07  
Register Bus  
Internal  
Address Bus  
ROM  
Up to 32K x 8  
®
Z8Core
Internal  
Data Bus  
P10  
P11  
P12  
P13  
P14  
P15  
P16  
P17  
8
XTAL  
I/O Byte  
Programmable  
Machine  
Timing &  
Instruction  
Control  
Expanded  
Register Bus  
RESET  
Expanded  
Register  
File  
P20  
P21  
P22  
P23  
P24  
P25  
P26  
P27  
V
DD  
Power  
V
SS  
I/O Bit  
Programmable  
Power-On  
Reset  
Counter/Timer 16  
16-Bit  
High-Voltage  
Detection  
Watchdog  
Timer  
Counter/Timer 8  
8-Bit  
2-Comparators  
Low-Voltage  
Detection  
Note: Refer to the specific package for available pins.  
Figure 1. Functional Block Diagram  
PS023910-0408  
Architectural Overview  
ZGR323L  
Product Specification  
4
HI16  
8
LO16  
8
16-Bit  
T16  
Timer 16  
16  
2
1
4 8  
8
8
SCLK  
Clock  
Divider  
TC16H  
TC16L  
And/Or  
Logic  
Timer 8/16  
HI8  
8
LO8  
8
Edge  
Detect  
Circuit  
Input  
Glitch  
Filter  
8-Bit  
T8  
Timer 8  
8
8
TC8H  
TC8L  
Figure 2. Counter/Timers Diagram  
PS023910-0408  
Architectural Overview  
ZGR323L  
Product Specification  
5
Pin Description  
The pin configuration for the 20-pin PDIP/SOIC/SSOP is displayed in Figure 3 and  
described in Table 3. The pin configuration for the 28-pin PDIP/SOIC/SSOP are displayed  
in Figure 4 and described in Table 4. The pin configurations for the 40-pin PDIP and  
48-pin SSOP versions are displayed in Figure 5, Figure 6, and described in Table 5.  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
3
4
5
6
7
8
9
10  
P25  
P26  
P27  
P07  
VDD  
P24  
P23  
P22  
P21  
P20  
VSS  
P01  
P00/Pref1/P30  
P36  
20-Pin  
PDIP  
SOIC  
SSOP  
XTAL2  
XTAL1  
P31  
P32  
P33  
P34  
Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration  
Table 3. 20-Pin PDIP/SOIC/SSOP Pin Identification  
Pin No  
Symbol  
P25–P27  
P07  
Function  
Direction  
1–3  
4
Port 2, Bits 5, 6, 7  
Port 0, Bit 7  
Input/Output  
Input/Output  
5
V
Power Supply  
DD  
6
XTAL2  
Crystal Oscillator Clock  
Crystal Oscillator Clock  
Port 3, Bits 1, 2, 3  
Port 3, Bits 4, 6  
Output  
Input  
7
XTAL1  
8–10  
11,12  
13  
P31–P33  
P34, P36  
Input  
Output  
P00/Pref1/P30 Port 0, Bit 0/Analog reference  
input Port 3 Bit 0  
Input/Output for P00  
Input for Pref1/P30  
14  
P01  
Port 0, Bit 1  
Input/Output  
15  
V
Ground  
SS  
16–20  
P20–P24  
Port 2, Bits 0,1, 2, 3, 4  
Input/Output  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
6
1
2
3
4
5
6
7
8
P25  
P26  
P27  
P04  
P05  
P06  
P07  
VDD  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
P24  
P23  
P22  
P21  
P20  
P03  
VSS  
P02  
P01  
P00  
Pref1/P30  
P36  
P37  
28-Pin  
PDIP  
SOIC  
SSOP  
9
XTAL2  
XTAL1  
P31  
10  
11  
12  
13  
14  
P32  
P33  
P34  
P35  
Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration  
Table 4. 28-Pin PDIP/SOIC/SSOP Pin Identification  
Pin No  
1-3  
Symbol  
P25-P27  
P04-P07  
Direction  
Description  
Input/Output  
Input/Output  
Port 2, Bits 5, 6, 7  
Port 0, Bits 4, 5, 6, 7  
Power supply  
4-7  
8
V
DD  
9
XTAL2  
XTAL1  
P31-P33  
P34  
Output  
Input  
Crystal, oscillator clock  
Crystal, oscillator clock  
Port 3, Bits 1, 2, 3  
Port 3, Bit 4  
10  
11-13  
14  
15  
16  
17  
18  
Input  
Output  
Output  
Output  
Output  
Input  
P35  
Port 3, Bit 5  
P37  
Port 3, Bit 7  
P36  
Port 3, Bit 6  
Pref1/P30  
Analog ref input; connect to V if not used  
CC  
Port 3 Bit 0  
Input for Pref1/P30  
Port 0, Bits 0, 1, 2  
Ground  
19-21  
22  
P00-P02  
Input/Output  
V
SS  
23  
P03  
Input/Output  
Input/Output  
Port 0, Bit 3  
24-28  
P20-P24  
Port 2, Bits 0-4  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
7
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
39  
28  
27  
26  
25  
24  
23  
22  
21  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
NC  
P25  
P26  
P27  
P04  
P05  
P06  
P14  
P15  
NC  
P24  
P23  
P22  
P21  
P20  
P03  
P13  
P12  
VSS  
P02  
P11  
P10  
P01  
P00  
Pref1/P30  
P36  
P37  
40-Pin  
PDIP  
P07  
VDD  
P16  
P17  
XTAL2  
XTAL1  
P31  
P32  
P33  
P34  
NC  
P35  
RESET  
Figure 5. 40-Pin PDIP Pin Configuration  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
8
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
NC  
P25  
P26  
P27  
P04  
N/C  
P05  
P06  
P14  
P15  
P07  
VDD  
VDD  
N/C  
P16  
P17  
XTAL2  
XTAL1  
P31  
P32  
P33  
P34  
NC  
NC  
NC  
P24  
P23  
P22  
P21  
P20  
P03  
P13  
P12  
VSS  
VSS  
N/C  
P02  
P11  
P10  
P01  
48-Pin  
SSOP  
P00  
N/C  
PREF1/P30  
P36  
P37  
P35  
RESET  
VSS  
Figure 6. 48-Pin SSOP Pin Configuration  
Table 5. 40- and 48-Pin Configuration  
40-Pin PDIP No  
48-Pin SSOP No  
Symbol  
P00  
P01  
P02  
P03  
P04  
P05  
P06  
P07  
P10  
P11  
P12  
26  
27  
30  
34  
5
31  
32  
35  
41  
5
6
7
7
8
10  
28  
29  
32  
11  
33  
34  
39  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
9
Table 5. 40- and 48-Pin Configuration (Continued)  
40-Pin PDIP No  
48-Pin SSOP No  
Symbol  
P13  
33  
8
40  
9
P14  
9
10  
15  
16  
42  
43  
44  
45  
46  
2
P15  
12  
13  
35  
36  
37  
38  
39  
2
P16  
P17  
P20  
P21  
P22  
P23  
P24  
P25  
3
3
P26  
4
4
P27  
16  
17  
18  
19  
22  
24  
23  
20  
40  
1
19  
20  
21  
22  
26  
28  
27  
23  
47  
1
P31  
P32  
P33  
P34  
P35  
P36  
P37  
NC  
NC  
NC  
21  
15  
14  
11  
31  
25  
25  
18  
17  
12, 13  
24, 37, 38  
29  
48  
6
RESET  
XTAL1  
XTAL2  
V
V
DD  
SS  
Pref1/P30  
NC  
NC  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
10  
Table 5. 40- and 48-Pin Configuration (Continued)  
40-Pin PDIP No  
48-Pin SSOP No  
Symbol  
NC  
14  
30  
36  
NC  
NC  
Pin Functions  
XTAL1 Crystal 1 (Time-Based Input)  
This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator  
input. Additionally, an optional external single-phase clock can be coded to the on-chip  
oscillator input.  
XTAL2 Crystal 2 (Time-Based Output)  
This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator  
output.  
Input/Output Ports  
Input/Output ports are described in the following sections.  
Caution: The CMOS input buffer for each port 0, 1, or 2 pin is always connected to the pin, even  
when the pin is configured as an output. If the pin is configured as an open-drain output  
and no signal is applied, a High output state can cause the CMOS input buffer to float.  
This may lead to excessive leakage current of more than 100 μA. To prevent this leakage,  
connect the pin to an external signal with a defined logic level or ensure its output state  
is Low, especially during STOP mode.  
Internal pull-ups are disabled on any given pin or group of port pins when programmed  
into output mode.  
Port 0, 1 and 2 have both input and output capability. The input logic is always present  
no matter whether the port is configured as input or output. When doing a READ  
instruction, it will read the actual value at the input logic not from the output buffer.  
In addition, the instruction of "OR", "AND", "XOR" are read-modify-write instructions.  
It will first read the port and then modify the value and load back to the port.  
Precaution must be taken if the port is configured as open-drain output or driving some  
circuit that may make the voltage different from the desired output logic. For example,  
pins P00-P07 are not connecting to anything else. If it is configured as open-drain  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
11  
output with outputting logic ONE, it is a floating port and will read back as ZERO.  
The following instruction will set P00-P07 all LOW.  
AND  
P0,#%F0  
Port 0 (P07–P00)  
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are  
configured under software control as a nibble I/O port. The output drivers are push-pull or  
open-drain controlled by bit D2 in the PCON register.  
If one or both nibbles are needed for I/O operation, they must be configured by writing to  
the Port 01 mode register (P01M). After a hardware reset or Stop Mode recovery, Port 0 is  
configured as an input port.  
An optional pull-up transistor is available as a ROM option bit on all Port 0 bits with  
nibble select.  
Note:  
Internal pull-ups are disabled on any given pin or group of port pins when programmed  
into output mode.  
The Port 0 direction is reset to be input following an SMR.  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
12  
4
4
Port 0 (I/O)  
Z8 ROM  
V
CC  
ROM Programming  
Option  
Open-Drain  
I/O  
Resistive  
Transistor  
Pull-up  
Pad  
Out  
In  
Figure 7. Port 0 Configuration  
Port 1 (P17–P10)  
Port 1 (see Figure 8) can be configured for standard port input or output mode. After POR  
or stop mode recovery, Port 1 is configured as an input port. The output drivers are either  
push-pull or open-drain and are controlled by bit D1 in the PCON register.  
Note:  
The Port 1 direction is reset to be input following an SMR.  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
13  
Z8 ROM  
8
Port 1 (I/O)  
V
CC  
ROM Programming  
Option  
Open-Drain  
OEN  
Resistive  
Transistor  
Pull-up  
Pad  
Out  
In  
Figure 8. Port 1 Configuration  
Port 2 (P27–P20)  
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 9). These eight I/O  
lines can be independently configured under software control as inputs or outputs. Port 2  
is always available for I/O operation. A MASK option bit is available to connect eight  
pull-up transistors on this port. Bits programmed as outputs are globally programmed as  
either push-pull or open-drain. The POR resets with the eight bits of Port 2 configured as  
inputs.  
Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up the part.  
P20 can be programmed to access the edge-detection circuitry in DEMODULATION  
mode.  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
14  
Port 2 (I/O)  
Z8 ROM  
V
CC  
ROM Programming  
Option  
Open-Drain  
I/O  
Resistive  
Transistor  
Pull-up  
Pad  
Out  
In  
Figure 9. Port 2 Configuration  
Port 3 (P37–P30)  
Port 3 is an 8-bit, CMOS-compatible fixed I/O port (see Figure 10). Port 3 consists of four  
fixed input (P33–P30) and four fixed output (P37–P34), which can be configured under  
software control for interrupt and as output from the counter/timers. P30, P31, P32, and  
P33 are standard CMOS inputs; P34, P35, P36, and P37 are push-pull outputs.  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
15  
Pref1/P30  
P31  
P32  
P33  
Port 3 (I/O)  
Z8 ROM  
P34  
P35  
P36  
P37  
R247 = P3M  
1 = Analog  
0 = Digital  
D1  
Dig.  
An.  
P31 (AN1)  
IRQ2, P31 Data Latch  
IRQ0, P32 Data Latch  
Comp1  
Comp2  
+
-
Pref1  
P32 (AN2)  
+
-
P33 (REF2)  
IRQ1, P33 Data Latch  
From Stop Mode Recovery Source of SMR  
Figure 10. Port 3 Configuration  
Two on-board comparators process analog signals on P31 and P32, with reference to the  
voltage on Pref1 and P33. The analog function is enabled by programming the Port 3  
Mode Register (bit 1). P31 and P32 are programmable as rising, falling, or both edge  
triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference  
voltage inputs. Access to the Counter Timer edge-detection circuit is through P31 or P20  
(see T8 and T16 Common Functions—CTR1(0D)01h on page 28). Other edge detect and  
IRQ modes are described in Table 6.  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
16  
Note:  
Comparators are powered down by entering STOP Mode. For P31–P33 to be used in a  
Stop Mode Recovery (SMR) source, these inputs must be placed into DIGITAL mode.  
2
Table 6. Port 3 Pin Function Summary  
Pin  
I/O  
Counter/Timers Comparator Interrupt  
Pref1/P30 IN  
RF1  
P31  
P32  
P33  
P34  
P35  
P36  
P37  
P20  
IN  
IN  
AN1  
AN2  
RF2  
AO1  
IRQ2  
IRQ0  
IRQ1  
IN  
IN  
OUT  
OUT  
OUT  
OUT  
I/O  
T8  
T16  
T8/16  
AO2  
IN  
Port 3 also provides output for each of the counter/timers and the AND/OR Logic (see  
Figure 11). Control is performed by programming bits D5–D4 of CTR1, bit 0 of CTR0,  
and bit 0 of CTR2.  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
17  
CTR0, D0  
MUX  
PCON, D0  
MUX  
P34 data  
T8_Out  
V
DD  
Pad  
P34  
P3M D1  
P31  
P31  
P30 (Pref1)  
+
-
Comp1  
CTR2, D0  
MUX  
V
DD  
Out 35  
T16_Out  
Pad  
P35  
CTR1, D6  
MUX  
V
DD  
Out 36  
T8/T16_Out  
Pad  
P36  
PCON, D0  
MUX  
V
DD  
P37 data  
P3M D1  
Pad  
P37  
P32  
P32  
P33  
+
-
Comp2  
Figure 11. Port 3 Counter/Timer Output Configuration  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
18  
Comparator Inputs  
In analog mode, P31 and P32 have a comparator front end. The comparator reference is  
supplied to P33 and Pref1. In this mode, the P33 internal data latch and its corresponding  
IRQ1 are diverted to the SMR sources (excluding P31, P32, and P33) as indicated in  
Figure 10 on page 15. In DIGITAL mode, P33 is used as D3 of the Port 3 input register,  
which then generates IRQ1.  
Note:  
Comparators are powered down by entering STOP Mode. For P31–P33 to be used in a  
Stop Mode Recovery source, these inputs must be placed into digital mode.  
Comparator Outputs  
These channels can be programmed to be output on P34 and P37 through the PCON  
register.  
RESET (Input, Active Low)  
Reset initializes the MCU and is accomplished either through Power-On, Watchdog  
Timer, Stop Mode Recovery, Low-Voltage detection, or external reset. During Power-On  
Reset and Watchdog Timer Reset, the internally generated reset drives the reset pin Low  
for the POR time. Any devices driving the external reset line must be open-drain to avoid  
damage from a possible conflict during reset conditions. Pull-up is provided internally.  
When the Z8 GP ROM MCU asserts (Low) the RESET pin, the internal pull-up is  
disabled. The Z8 GP ROM MCU does not assert the RESET pin when under VBO.  
Note:  
The external Reset does not initiate an exit from STOP mode.  
PS023910-0408  
Pin Description  
ZGR323L  
Product Specification  
19  
Functional Description  
This device incorporates special functions to enhance the functionality of Z8 in consumer  
and battery-operated applications.  
Program Memory  
This device addresses up to 32 KB of ROM memory. The first 12 bytes are reserved for  
interrupt vectors. These locations contain the six 16-bit vectors that correspond to the six  
available interrupts. See Figure 12.  
RAM  
This device features 256 B of RAM.  
Not Accessible  
On-  
Location  
of first  
3276  
Byte of  
instruction  
Reset Start  
IRQ  
1
1
IRQ  
IRQ  
IRQ  
1
9
8
7
IRQ  
IRQ  
Interrupt  
Vector  
6
5
4
IRQ  
IRQ  
IRQ  
Interrupt  
Vector  
3
2
1
IRQ  
IRQ  
IRQ  
0
Figure 12. Program Memory Map (32 K ROM)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
20  
Expanded Register File  
The register file has been expanded to allow for additional system control registers and for  
mapping of additional peripheral devices into the register address area. The Z8 register  
address space (R0 through R15) has been implemented as 16 banks, with 16 registers per  
bank. These register groups are known as the ERF (Expanded Register File). Bits 7–4 of  
register RP select the working register group. Bits 3–0 of register RP select the expanded  
register file bank.  
An expanded register bank is also referred to as an expanded register group  
Note:  
(see Figure 13).  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
21  
Reset Condition  
Z8 Standard Control Registers  
D7 D6 D5 D4 D3 D2 D1 D0  
Expanded Reg. Bank 0/Group 15**  
FF  
SPL  
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
FE  
FD  
FC  
FB  
FA  
F9  
F8  
F7  
F6  
F5  
F4  
F3  
F2  
F1  
F0  
SPH  
RP  
Register Pointer  
FLAGS  
IMR  
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
7
6 5 4 3 2 1 0  
IRQ  
Working Register  
Group Pointer  
Expanded Register  
Bank Pointer  
IPR  
U
1
U
1
U
0
U
0
U
1
U
1
U
1
U
1
P01M  
P3M  
0
0
0
0
0
0
0
0
*
*
P2M  
1
1
1
1
1
1
1
1
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Register File (Bank 0)**  
FF  
F0  
Expanded Reg. Bank F/Group 0**  
(F) 0F WDTMR  
(F) 0E Reserved  
(F) 0D SMR2  
*
U
0
U
0
0
0
0
0
1
0
1
0
0
0
1
0
*
(F) 0C Reserved  
(F) 0B SMR  
U
0 1 0 0 0 U 0  
↑
7F  
(F) 0A Reserved  
(F) 09 Reserved  
(F) 08 Reserved  
(F) 07 Reserved  
(F) 06 Reserved  
(F) 05 Reserved  
(F) 04 Reserved  
(F) 03 Reserved  
(F) 02 Reserved  
(F) 01 Reserved  
(F) 00 PCON  
0F  
00  
*
1
1 1 1 1 1 1 0  
Expanded Reg. Bank 0/Group (0)  
Expanded Reg. Bank D/Group 0  
(0) 03 P3  
(0) 02 P2  
(0) 01 P1  
(0) 00 P0  
0
U
(D) 0C  
(D) 0B  
(D) 0A  
(D) 09  
(D) 08  
(D) 07  
(D) 06  
(D) 05  
(D) 04  
LVD  
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
0
0
0
0
0
0
0
U
U
HI8  
*
*
*
*
LO8  
HI16  
U
LO16  
TC16H  
TC16L  
TC8H  
TC8L  
*
*
*
U = Unknown  
* Is not reset with a Stop Mode Recovery  
** All addresses are in hexadecimal  
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
*
*
↑ Is not reset with a Stop Mode Recovery, except Bit 0  
↑↑ Bit 5 Is not reset with a Stop Mode Recovery  
(D) 03 CTR3  
↑↑  
↑↑↑  
0
0
0
0
0
0
0
0
(D) 02  
(D) 01  
(D) 00  
CTR2  
CTR1  
CTR0  
↑↑↑ Bits 5,4,3,2 not reset with a Stop Mode Recovery  
↑↑↑↑  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↑↑↑↑ Bits 5 and 4 not reset with a Stop Mode Recovery  
↑↑↑↑↑ Bits 5,4,3,2,1 not reset with a Stop Mode Recovery  
↑↑↑↑↑  
Figure 13. Expanded Register File Architecture  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
22  
The upper nibble of the register pointer (see Figure 14) selects which working register  
group, of 16 bytes in the register file, is accessed out of the possible 256. The lower nibble  
selects the expanded register file bank and, in the case of the Z8 GP ROM MCU family,  
banks 0, F, and D are implemented. A 0hin the lower nibble allows the normal register  
file (bank 0) to be addressed. Any other value from 1hto Fhexchanges the lower 16  
registers to an expanded register bank.  
R253 RP  
D7 D6 D5 D4 D3 D2 D1 D0  
Expanded Register  
File Pointer  
Working Register  
Pointer  
Default Setting After Reset = 0000 0000  
Figure 14. Register Pointer  
Example: Z8 GP ROM MCU: (See Figure 13 on page 21)  
R253 RP = 00h  
R0 = Port 0  
R1 = Port 1  
R2 = Port 2  
R3 = Port 3  
But if:  
R253 RP = 0Dh  
R0 = CTR0  
R1 = CTR1  
R2 = CTR2  
R3 = CTR3  
The counter/timers are mapped into ERF group D. Access is easily performed using the  
following:  
LD  
RP, #0Dh  
; Select ERF D  
; (working  
for access to bank D  
register group 0)  
LD  
LD  
R0,#xx  
1, #xx  
; load CTR0  
; load CTR1  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
23  
LD  
R1, 2  
; CTR2→CTR1  
; Select ERF D  
; (working  
LD  
RP, #0Dh  
for access to bank D  
register group 0)  
LD  
RP, #7Dh  
; Select  
expanded register bank D and working  
group 7 of bank 0 for access.  
; register  
LD  
71h, 2  
; CTRL2→register 71h  
LD  
R1, 2  
; CTRL2→register 71h  
Register File  
The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose registers,  
16 control and status registers (R0–R3, R4–R239, and R240–R255, respectively), and two  
expanded registers groups in Banks D (see Table 7) and F. Instructions can access registers  
directly or indirectly through an 8-bit address field, thereby allowing a short, 4-bit  
register address to use the Register Pointer (see Figure 15). In the 4-bit mode, the register  
file is divided into 16 working register groups, each occupying 16 continuous locations.  
The Register Pointer addresses the starting location of the active working register group.  
Note:  
Working register group E0–EF can only be accessed through working registers and  
indirect addressing modes.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
24  
R253  
R R R R  
R R R  
3 2 1  
7
6
5
4
The upper nibble of the register file address  
provided by the register pointer specifies the  
active working-register group.  
FF  
F0  
EF  
E0  
DF  
D0  
The lower nibble of the register  
40  
3F  
file address provided by the  
instruction points to the  
specified register.  
Specified Working  
30  
2F  
Register Group  
Register Group 2  
20  
1F  
Register Group 1  
R15 to R0  
10  
0F  
R15 to R4 *  
R3 to R0 *  
Register Group 0  
I/O Ports  
00  
* RP = 00: Selects Register Bank 0, Working Register Group 0  
Figure 15. Register Pointer—Detail  
Stack  
The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is used  
for the internal stack that resides in the general-purpose registers (R4–R239). SPH (R254)  
can be used as a general-purpose register.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
25  
Timers  
T8_Capture_HI—HI8(D)0Bh  
This register holds the captured data from the output of the 8-bit Counter/Timer0.  
Typically, this register holds the number of counts when the input signal is 1.  
Field  
Bit Position  
Description  
T8_Capture_HI [7:0]  
R/W Captured Data - No Effect  
T8_Capture_LO—L08(D)0Ah  
This register holds the captured data from the output of the 8-bit Counter/Timer0.  
Typically, this register holds the number of counts when the input signal is 0.  
Field  
Bit Position  
Description  
T8_Capture_L0 [7:0]  
R/W Captured Data - No Effect  
T16_Capture_HI—HI16(D)09h  
This register holds the captured data from the output of the 16-bit Counter/Timer16. This  
register holds the MS-Byte of the data.  
Field  
Bit Position  
Description  
T16_Capture_HI [7:0]  
R/W Captured Data - No Effect  
T16_Capture_LO—L016(D)08h  
This register holds the captured data from the output of the 16-bit Counter/Timer16. This  
register holds the LS-Byte of the data.  
Field  
Bit Position  
Description  
T16_Capture_LO [7:0]  
R/W Captured Data - No Effect  
Counter/Timer2 MS-Byte Hold Register—TC16H(D)07h  
Field  
Bit Position  
Description  
R/W Data  
T16_Data_HI  
[7:0]  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
26  
Counter/Timer2 LS-Byte Hold Register—TC16L(D)06h  
Field  
Bit Position  
Description  
R/W Data  
T16_Data_LO  
[7:0]  
Counter/Timer8 High Hold Register—TC8H(D)05h  
Field  
Bit Position  
Description  
R/W Data  
T8_Level_HI  
[7:0]  
Counter/Timer8 Low Hold Register—TC8L(D)04h  
Field  
Bit Position  
Description  
R/W Data  
T8_Level_LO  
[7:0]  
CTR0 Counter/Timer8 Control Register—CTR0(D)00h  
Table 7 lists and briefly describes the fields for this register.  
Table 7. CTR0(D)00h Counter/Timer8 Control Register  
Field  
Bit Position  
Value  
Description  
T8_Enable  
7-------  
R/W  
0*  
1
0
Counter Disabled  
Counter Enabled  
Stop Counter  
1
Enable Counter  
Single/Modulo-N  
Time_Out  
-6-------  
--5------  
R/W  
R/W  
0*  
1
Modulo-N  
Single Pass  
0**  
1
0
No Counter Time-Out  
Counter Time-Out Occurred  
No Effect  
1
Reset Flag to 0  
T8 _Clock  
---43---  
-----2--  
R/W  
R/W  
0 0**  
0 1  
1 0  
SCLK  
SCLK/2  
SCLK/4  
SCLK/8  
1 1  
Capture_INT_Mask  
0**  
1
Disable Data Capture Interrupt  
Enable Data Capture Interrupt  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
27  
Table 7. CTR0(D)00h Counter/Timer8 Control Register (Continued)  
Field  
Bit Position  
Value  
Description  
Counter_INT_Mask  
------1-  
R/W  
R/W  
0**  
1
Disable Time-Out Interrupt  
Enable Time-Out Interrupt  
P34_Out  
-------0  
0*  
1
P34 as Port Output  
T8 Output on P34  
*Indicates the value upon Power-On Reset.  
** Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.  
T8 Enable  
This field enables T8 when set (written) to 1.  
Single/Modulo-N  
When set to 0 (Modulo-N), the counter reloads the initial value when the terminal count is  
reached. When set to 1 (single-pass), the counter stops when the terminal count is reached.  
Timeout  
This bit is set when T8 times out (terminal count reached). To reset this bit, write a 1 to its  
location.  
Caution: Writing a 1 is the only way to reset the Terminal Count status condition. Reset this bit  
before using/enabling the counter/timers.  
The first clock of T8 might not have complete clock width and can occur any time when  
enabled.  
Note:  
Take care when using the OR or AND commands to manipulate CTR0, bit 5 and CTR1,  
bits 0 and 1 (DEMODULATION Mode). These instructions use a Read-Modify-Write  
sequence in which the current status from the CTR0 and CTR1 registers is ORed or  
ANDed with the designated value and then written back into the registers.  
T8 Clock  
These bits define the frequency of the input signal to T8.  
Capture_INT_Mask  
Set this bit to allow an interrupt when data is captured into either LO8 or HI8 on a positive  
or negative edge detection in DEMODULATION mode.  
Counter_INT_Mask  
Set this bit to allow an interrupt when T8 has a timeout.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
28  
P34_Out  
This bit defines whether P34 is used as a normal output pin or the T8 output.  
T8 and T16 Common Functions—CTR1(0D)01h  
This register controls the functions in common with the T8 and T16.  
Table 8 lists and briefly describes the fields for this register.  
Table 8. CTR1(0D)01h T8 and T16 Common Functions  
Field  
Bit Position  
Value  
Description  
Mode  
7-------  
R/W  
R/W  
0*  
1
TRANSMIT Mode  
DEMODULATION Mode  
P36_Out/  
Demodulator_Input  
-6------  
TRANSMIT Mode  
Port Output  
T8/T16 Output  
DEMODULATION Mode  
P31  
0*  
1
0*  
1
P20  
T8/T16_Logic/  
Edge _Detect  
--54----  
R/W  
TRANSMIT Mode  
AND  
OR  
00**  
01  
10  
NOR  
11  
NAND  
DEMODULATION Mode  
Falling Edge  
Rising Edge  
Both Edges  
Reserved  
00**  
01  
10  
11  
Transmit_Submode/  
Glitch_Filter  
----32--  
R/W  
TRANSMIT Mode  
Normal Operation  
PING-PONG Mode  
T16_Out = 0  
00*  
01  
10  
11  
T16_Out = 1  
DEMODULATION Mode  
No Filter  
4 SCLK Cycle  
8 SCLK Cycle  
Reserved  
00*  
01  
10  
11  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
29  
Table 8. CTR1(0D)01h T8 and T16 Common Functions (Continued)  
Field  
Bit Position  
Value  
Description  
Initial_T8_Out/  
Rising Edge  
------1-  
TRANSMIT Mode  
T8_OUT is 0 Initially  
T8_OUT is 1 Initially  
DEMODULATION Mode  
No Rising Edge  
R/W  
0*  
1
R
0*  
1
0
Rising Edge Detected  
No Effect  
W
1
Reset Flag to 0  
Initial_T16_Out/  
Falling_Edge  
-------0  
TRANSMIT Mode  
T16_OUT is 0 Initially  
T16_OUT is 1 Initially  
DEMODULATION Mode  
No Falling Edge  
R/W  
0*  
1
R
0*  
1
0
Falling Edge Detected  
No Effect  
W
1
Reset Flag to 0  
*Default at Power-On Reset.  
**Default at Power-On Reset. Not reset with a Stop Mode Recovery.  
Mode  
If the result is 0, the counter/timers are in TRANSMIT mode; otherwise, they are in  
DEMODULATION mode.  
P36_Out/Demodulator_Input  
In TRANSMIT Mode, this bit defines whether P36 is used as a normal output pin or the  
combined output of T8 and T16.  
In DEMODULATION Mode, this bit defines whether the input signal to the Counter/  
Timers is from P20 or P31.  
If the input signal is from Port 31, a capture event may also generate an IRQ2 interrupt.  
To prevent generating an IRQ2, either disable the IRQ2 interrupt by clearing its IMR bit  
D2 or use P20 as the input.  
T8/T16_Logic/Edge _Detect  
In TRANSMIT Mode, this field defines how the outputs of T8 and T16 are combined  
(AND, OR, NOR, NAND).  
In DEMODULATION Mode, this field defines which edge should be detected by the edge  
detector.  
Transmit_Submode/Glitch Filter  
In TRANSMIT Mode, this field defines whether T8 and T16 are in the PING-PONG  
mode or in independent normal operation mode. Setting this field to “NORMAL OPERA-  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
30  
TION Mode” terminates the PING-PONG Mode operation. When set to 10, T16 is  
immediately forced to a 0; a setting of 11 forces T16 to output a 1.  
In DEMODULATION Mode, this field defines the width of the glitch that must be filtered  
out.  
Initial_T8_Out/Rising_Edge  
In TRANSMIT Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the  
output of T8 is set to 1 when it starts to count. When the counter is not enabled and this bit  
is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This ensures that when the  
clock is enabled, a transition occurs to the initial state set by CTR1, D1.  
In DEMODULATION Mode, this bit is set to 1 when a rising edge is detected in the input  
signal. In order to reset the mode, a 1 must be written to this location.  
Initial_T16 Out/Falling _Edge  
In TRANSMIT Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is  
1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal  
or PING-PONG Mode (CTR1, D3; D2). When the counter is not enabled and this bit is  
set, T16_OUT is set to the opposite state of this bit. This ensures that when the clock is  
enabled, a transition occurs to the initial state set by CTR1, D0.  
In DEMODULATION Mode, this bit is set to 1 when a falling edge is detected in the input  
signal. In order to reset it, a 1 must be written to this location.  
Modifying CTR1 (D1 or D0) while the counters are enabled causes unpredictable output  
from T8/16_OUT.  
Note:  
CTR2 Counter/Timer 16 Control Register—CTR2(D)02h  
Table 9 lists and briefly describes the fields for this register.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
31  
Table 9. CTR2(D)02h: Counter/Timer16 Control Register  
Field  
Bit Position  
Value  
Description  
T16_Enable  
7-------  
R
0*  
1
0
Counter Disabled  
Counter Enabled  
Stop Counter  
W
1
Enable Counter  
Single/Modulo-N  
-6------  
R/W  
TRANSMIT Mode  
Modulo-N  
Single Pass  
0*  
1
DEMODULATION Mode  
T16 Recognizes Edge  
T16 Does Not Recognize  
Edge  
0
1
Time_Out  
--5-----  
---43---  
R
0*  
1
No Counter Timeout  
Counter Timeout  
Occurred  
No Effect  
Reset Flag to 0  
W
0
1
T16 _Clock  
R/W  
00**  
01  
10  
SCLK  
SCLK/2  
SCLK/4  
SCLK/8  
11  
Capture_INT_Mask  
Counter_INT_Mask  
P35_Out  
-----2--  
------1-  
-------0  
R/W  
R/W  
R/W  
0**  
1
Disable Data Capture Int.  
Enable Data Capture Int.  
0
1
Disable Timeout Int.  
Enable Timeout Int.  
0*  
1
P35 as Port Output  
T16 Output on P35  
*Indicates the value upon Power-On Reset.  
**Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.  
T16_Enable  
This field enables T16 when set to 1.  
Single/Modulo-N  
In TRANSMIT Mode, when set to 0, the counter reloads the initial value when it reaches  
the terminal count. When set to 1, the counter stops when the terminal count is reached.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
32  
In DEMODULATION Mode, when set to 0, T16 captures and reloads on detection of all  
the edges. When set to 1, T16 captures and detects on the first edge but ignores the  
subsequent edges. For details, see T16 DEMODULATION Mode on page 40.  
Time_Out  
This bit is set when T16 times out (terminal count reached). To reset the bit, write a 1 to  
this location.  
T16_Clock  
This bit defines the frequency of the input signal to Counter/Timer16.  
Capture_INT_Mask  
This bit is set to allow an interrupt when data is captured into LO16 and HI16.  
Counter_INT_Mask  
Set this bit to allow an interrupt when T16 times out.  
P35_Out  
This bit defines whether P35 is used as a normal output pin or T16 output.  
CTR3 T8/T16 Control Register—CTR3(D)03h  
Table 10 lists and briefly describes the fields for this register. This register allows the T8  
and T16 counters to be synchronized.  
Table 10.CTR3 (D)03h: T8/T16 Control Register  
Field  
Enable  
Bit Position  
Value  
Description  
T
7-------  
R
R
W
W
0*  
1
0
Counter Disabled  
Counter Enabled  
Stop Counter  
16  
1
Enable Counter  
T Enable  
-6------  
--5-----  
R
R
W
W
0*  
1
0
Counter Disabled  
Counter Enabled  
Stop Counter  
8
1
Enable Counter  
Sync Mode  
R/W  
0**  
1
Disable Sync Mode  
Enable Sync Mode  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
33  
Table 10.CTR3 (D)03h: T8/T16 Control Register (Continued)  
Field  
Bit Position  
Value  
Description  
Reserved  
---43210  
R
W
1
x
Always reads 11111  
No Effect  
*Indicates the value upon Power-On Reset.  
**Indicates the value upon Power-On Reset. Not reset with a Stop Mode Recovery.  
Counter/Timer Functional Blocks  
Input Circuit  
The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–D4, a  
pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in  
the input signal that have a width less than specified (CTR1 D3, D2) are filtered out  
(see Figure 16).  
CTR1  
D5,D4  
Pos  
P31  
P20  
Edge  
MUX  
Glitch  
Filter  
Edge  
Detector  
Neg  
Edge  
CTR1  
CTR1  
D6  
D3, D2  
Figure 16. Glitch Filter Circuitry  
T8 TRANSMIT Mode  
Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1; if it  
is 1, T8_OUT is 0. See Figure 17.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
34  
T8 (8-Bit)  
TRANSMIT Mode  
No  
T8_Enable Bit Set  
CTR0, D7  
Yes  
Reset T8_Enable Bit  
1
0
CTR1, D1  
Value  
Load TC8H  
Set T8_OUT  
Load TC8L  
Reset T8_OUT  
Set Timeout Status Bit  
(CTR0 D5) and Generate  
Timeout_Int if Enabled  
Enable T8  
No  
T8_Timeout  
Yes  
Single Pass  
Single  
Pass?  
Modulo-N  
T8_OUT Value  
1
0
Load TC8L  
Reset T8_OUT  
Load TC8H  
Set T8_OUT  
Enable T8  
Set Timeout Status Bit  
(CTR0 D5) and Generate  
Timeout_Int if Enabled  
No  
T8_Timeout  
Yes  
Figure 17. TRANSMIT Mode Flowchart  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
35  
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1). If the  
initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter.  
In SINGLE-PASS Mode (CTR0, D6), T8 counts down to 0 and stops, T8_OUT toggles,  
the timeout status bit (CTR0, D5) is set, and a timeout interrupt can be generated if it is  
enabled (CTR0, D1). In MODULO-N Mode, on reaching terminal count, T8_OUT is  
toggled, but no interrupt is generated. From that point, T8 loads a new count (if the  
T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0,  
toggles T8_OUT, and sets the timeout status bit (CTR0, D5), thereby generating an  
interrupt if enabled (CTR0, D1). One cycle is thus completed. T8 then loads from TC8H  
or TC8L according to the T8_OUT level and repeats the cycle. See Figure 18.  
®
CTR0 D2  
Z8 Data Bus  
Positive Edge  
Negative Edge  
IRQ4  
HI8  
LO8  
CTR0 D1  
CTR0 D4, D3  
Clock  
Clock  
Select  
8-Bit  
Counter T8  
SCLK  
T8_OUT  
TC8H  
TC8L  
®
Z8 Data Bus  
Figure 18. 8-Bit Counter/Timer Circuits  
You can modify the values in TC8H or TC8L at any time. The new values take effect  
when they are loaded.  
To ensure known operation do not write these registers at the time the values are to be  
loaded into the counter/timer. An initial count of 1 is not allowed (a non-function  
occurs). An initial count of 0 causes TC8 to count from 0 to FFhto FEh.  
Caution:  
Note:  
The letter hdenotes hexadecimal values.  
Transition from 0 to FFhis not a timeout condition.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
36  
Using the same instructions for stopping the counter/timers and setting the status bits is  
not recommended.  
Caution:  
Two successive commands are necessary. First, the counter/timers must be stopped.  
Second, the status bits must be reset. These commands are required as it takes one counter/  
timer clock interval for the initiated event to actually occur. See Figure 19 and Figure 20.  
TC8H  
Counts  
Counter Enable Command;  
T8_OUT Switches to Its  
Initial Value (CTR1 D1)  
T8_OUT Toggles;  
Timeout Interrupt  
Figure 19. T8_OUT in SINGLE-PASS Mode  
T8_OUT Toggles  
. . .  
T8_OUT  
TC8L  
TC8H  
TC8L  
TC8H  
TC8L  
Counter Enable Command;  
T8_OUT Switches to Its  
Initial Value (CTR1 D1)  
Timeout  
Interrupt  
Timeout  
Interrupt  
Figure 20. T8_OUT in MODULO-N Mode  
T8 DEMODULATION Mode  
You must program TC8L and TC8H to FFh. After T8 is enabled, when the first edge  
(rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to count down.  
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected  
during counting, the current value of T8 is complemented and put into one of the capture  
registers. If it is a positive edge, data is put into LO8; if it is a negative edge, data is put  
into HI8. From that point, one of the edge detect status bits (CTR1, D1; D0) is set, and an  
interrupt can be generated if enabled (CTR0, D2). Meanwhile, T8 is loaded with FFhand  
starts counting again. If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an  
interrupt can be generated if enabled (CTR0, D1). T8 then continues counting from FFh  
(see Figure 21 and Figure 22).  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
37  
T8 (8-Bit)  
Count Capture  
T8 Enable  
(Set by User)  
No  
No  
Yes  
Edge Present  
Yes  
What Kind  
of Edge  
Positive  
Negative  
T8 HI8  
T8 LO8  
FFhT8  
Figure 21. DEMODULATION Mode Count Capture Flowchart  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
38  
T8 (8-Bit)  
DEMODULATION Mode  
T8 Enable  
CTR0, D7  
No  
Yes  
FFh→ TC8  
First  
Edge Present  
No  
Yes  
Enable TC8  
Disable TC8  
T8_Enable  
Bit Set  
No  
Yes  
No  
Edge Present  
Yes  
No  
T8 Timeout  
Yes  
Set Edge Present Status  
Bit and Trigger Data  
Capture Int. If Enabled  
Set Timeout Status  
Bit and Trigger  
Timeout Int. If Enabled  
Continue Counting  
Figure 22. DEMODULATION Mode Flowchart  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
39  
T16 TRANSMIT Mode  
In NORMAL or PING-PONG mode, the output of T16 when not enabled, is dependent on  
CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can force the output  
of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3; D2 to a 10  
or 11.  
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its  
initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled (in NOR-  
MAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if enabled), and a  
status bit (CTR2, D5) is set. See Figure 23.  
®
CTR2 D2  
Z8 Data Bus  
Positive Edge  
Negative Edge  
IRQ3  
HI16  
LO16  
CTR2 D1  
CTR2 D4, D3  
Clock  
Clock  
Select  
16-Bit  
Counter T16  
SCLK  
T16_OUT  
TC16H  
TC16L  
®
Z8 Data Bus  
Figure 23. 16-Bit Counter/Timer Circuits  
Note:  
Global interrupts override this function as described in Interrupts on page 42.  
If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 24). If it is in  
MODULO-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting continues  
(see Figure 25).  
You can modify the values in TC16H and TC16L at any time. The new values take effect  
when they are loaded.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
40  
Do not load these registers at the time the values are to be loaded into the counter/timer  
to ensure known operation. An initial count of 1 is not allowed. An initial count of 0  
causes T16 to count from 0 to FFFFhto FFFEh. Transition from 0 to FFFFhis not a  
timeout condition.  
Caution:  
TC16H*256+TC16L Counts  
“Counter Enable” Command  
T16_OUT Switches to Its  
Initial Value (CTR1 D0)  
T16_OUT Toggles,  
Timeout Interrupt  
Figure 24. T16_OUT in SINGLE-PASS Mode  
TC16H*256+TC16L  
TC16H*256+TC16L  
TC16H*256+TC16L  
. . .  
TC16_OUT  
“Counter Enable” Command,  
T16_OUT Switches to Its  
Initial Value (CTR1 D0)  
T16_OUT Toggles,  
Timeout Interrupt  
T16_OUT Toggles,  
Timeout Interrupt  
Figure 25. T16_OUT in MODULO-N Mode  
T16 DEMODULATION Mode  
You must program TC16L and TC16H to FFh. After T16 is enabled, and the first edge  
(rising, falling, or both depending on CTR1 D5; D4) is detected, T16 captures HI16 and  
LO16, reloads, and begins counting.  
If D6 of CTR2 Is 0  
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is detected  
during counting, the current count in T16 is complemented and put into HI16 and LO16.  
When data is captured, one of the edge detect status bits (CTR1, D1; D0) is set, and an  
interrupt is generated if enabled (CTR2, D2). T16 is loaded with FFFFhand starts again.  
This T16 mode is generally used to measure space time, the length of time between bursts  
of carrier signal (marks).  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
41  
If D6 of CTR2 Is 1  
T16 ignores the subsequent edges in the input signal and continues counting down. A  
timeout of T8 causes T16 to capture its current value and generate an interrupt if enabled  
(CTR2, D2). In this case, T16 does not reload and continues counting. If the D6 bit of  
CTR2 is toggled (by writing a 0 then a 1 to it), T16 captures and reloads on the next edge  
(rising, falling, or both depending on CTR1, D5; D4), continuing to ignore subsequent  
edges.  
This T16 mode generally measures mark time, the length of an active carrier signal burst.  
If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit (CTR2 D5)  
is set, and an interrupt timeout can be generated if enabled (CTR2 D1).  
PING-PONG Mode  
This operation mode is only valid in TRANSMIT Mode. T8 and T16 must be programmed  
in SINGLE-PASS mode (CTR0, D6; CTR2, D6), and PING-PONG mode must be pro-  
grammed in CTR1, D3; D2. You can begin the operation by enabling either T8 or T16  
(CTR0, D7 or CTR2, D7). For example, if T8 is enabled, T8_OUT is set to this initial  
value (CTR1, D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After  
the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT then switches  
to its initial value (CTR1, D0), data from TC16H and TC16L is loaded, and T16 starts to  
count. After T16 reaches the terminal count, it stops, T8 is enabled again, repeating the  
entire cycle. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0,  
D1; CTR2, D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of CTR1. See  
Figure 26.  
Note:  
Enabling ping-pong operation while the counter/timers are running might cause intermit-  
tent counter/timer function. Disable the counter/timers and reset the status flags before  
instituting this operation.  
Enable  
TC8  
Timeout  
Enable  
Ping-Pong  
CTR1 D3,D2  
TC16  
Timeout  
Figure 26. PING-PONG Mode Diagram  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
42  
Initiating PING-PONG Mode  
First, make sure both counter/timers are not running. Set T8 into SINGLE-PASS mode  
(CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the PING-PONG  
mode (CTR1, D2; D3). These instructions can be in random order. Finally, start PING-  
PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7). See Figure 26.  
P34_Internal  
MUX  
P34  
CTR0 D0  
MUX  
P36_Internal  
P35_Internal  
T8_OUT  
MUX  
P36  
P35  
AND/OR/NOR/NAND  
Logic  
T16_OUT  
CTR1, D2  
CTR1 D6  
MUX  
CTR1 D5, D4  
CTR1 D3  
CTR2 D0  
Figure 27. Output Circuit  
The initial value of T8 or T16 must not be 1. If you stop the timer and restart the timer,  
reload the initial value to avoid an unknown previous value.  
During PING-PONG Mode  
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by  
hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers  
reach the terminal count.  
Timer Output  
The output logic for the timers is displayed in Figure 27. P34 is used to output T8-OUT  
when D0 of CTR0 is set. P35 is used to output the value of TI6-OUT when D0 of CTR2 is  
set. When D6 of CTR1 is set, P36 outputs the logic combination of T8-OUT and T16-  
OUT determined by D5 and D4 of CTR1.  
Interrupts  
The Z8 GP ROM MCU features six different interrupts (see Table 11). The interrupts are  
maskable and prioritized (see Figure 28). The six sources are divided as follows: three  
sources are claimed by Port 3 lines P33–P31, two by the counter/timers (see Table 11) and  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
43  
one for low-voltage detection. The Interrupt Mask Register (globally or individually)  
enables or disables the six interrupt requests.  
The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M). When in  
digital mode, Pin P33 is the source. When in analog mode the output of the Stop Mode  
Recovery source logic is used as the source for the interrupt. See Figure 33, Stop Mode  
Recovery Source, on page 52.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
44  
Stop Mode Recovery Source  
P33  
0
1
D1 of P3M Register  
P31  
P32  
IRQ Register  
D6, D7  
Low-Voltage  
Detection  
Interrupt Edge  
Select  
Timer 8  
Timer 16  
IRQ2  
IRQ0  
IRQ1 IRQ3  
IRQ4  
IRQ5  
IRQ  
IMR  
IPR  
5
Global  
Interrupt  
Enable  
Interrupt  
Request  
Priority  
Logic  
Vector Select  
Figure 28. Interrupt Block Diagram  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
45  
Table 11. Interrupt Types, Sources, and Vectors  
Name  
IRQ0  
IRQ1  
IRQ2  
IRQ3  
IRQ4  
IRQ5  
Source Vector Location Comments  
P32  
P33  
P31, T  
T16  
T8  
0,1  
External (P32), Rising, Falling Edge Triggered  
2,3  
External (P33), Falling Edge Triggered  
4,5  
External (P31), Rising, Falling Edge Triggered  
IN  
6,7  
Internal  
Internal  
Internal  
8,9  
LVD  
10,11  
When more than one interrupt is pending, priorities are resolved by a programmable  
priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle  
activates when an interrupt request is granted. As a result, all subsequent interrupts are  
disabled, and the Program Counter and Status Flags are saved. The cycle then branches to  
the program memory vector location reserved for that interrupt. All Z8 GP ROM MCU  
interrupts are vectored through locations in the program memory. This memory location  
and the next byte contain the 16-bit address of the interrupt service routine for that partic-  
ular interrupt request. To accommodate polled interrupt systems, interrupt inputs are  
masked, and the Interrupt Request register is polled to determine which of the interrupt  
requests require service.  
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is  
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge  
triggered. These interrupts are user-programmable. The software can poll to identify the  
state of the pin.  
Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250),  
bits D7 and D6. The configuration is indicated in Table 12.  
Table 12. IRQ Register  
IRQ  
D6  
Interrupt Edge  
IRQ2 (P31) IRQ0 (P32)  
D7  
0
0
1
0
1
F
F
0
F
R
1
R
F
1
R/F  
R/F  
Note: F = Falling Edge; R = Rising Edge  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
46  
Clock  
The device’s on-chip oscillator has a high-gain, parallel-resonant amplifier, for connection  
to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = Input,  
XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz maximum, with a series  
resistance (RS) less than or equal to 100 Ω. The on-chip oscillator can be driven with a  
suitable external clock source.  
The crystal must be connected across XTAL1 and XTAL2 using the recommended  
capacitors from each pin to ground. The typical capacitor value is 10 pF for 8 MHz. Check  
with the crystal supplier for the optimum capacitance.  
XTAL1  
XTAL1  
XTAL  
C1  
C2  
XTAL  
Crystal  
External Clock  
C1, C2 =10 pF TYP*  
f = 8 MHz  
XTAL1  
XTAL  
* Preliminary value including pin parasitics  
Ceramic Resonator  
f = 8 MHz  
Figure 29. Oscillator Configuration  
Zilog’s ZGR323L supports crystal, resonator, and oscillator. Most resonators have a  
frequency tolerance of less than +/-0.5% which is adequate for remote control applica-  
tions. The typical resonator has a very fast start up time on the order of a few hundred  
microseconds.  
Most crystals have a frequency tolerance of less than 50 ppm (+/-0.005%). Crystal oscilla-  
tors, however, require a much longer start-up time as the large loading capacitance slows  
®
down oscillation start-up. Zilog recommends using loading capacitors of no more than  
10 pF for crystal oscillators. If the stray capacitance of the PCB or the crystal is high, the  
loading capacitance C1 and C2 must be further reduced to ensure stable oscillation before  
T
POR (Power On Reset Time is typically 5-6 ms. See Table 22 on page 82).  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
47  
For Stop Mode Recovery operation, Bit 5 of the SMR register allows you to select the  
Stop Mode Recovery delay (TPOR). If it is not selected, the MCU will execute instruction  
immediately after it wakes up from STOP mode. The Stop Mode Recovery delay must be  
selected (bit 5 of SMR = 1) if resonator or crystal is used as clock source.  
For both resonator and crystal oscillation, the oscillation ground must go directly to the  
ground pin of the microcontroller. It must use the shortest distant and isolate from other  
connection.  
Power-On Reset  
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the Power-On  
Reset (POR) timer function. The POR time allows VDD and the oscillator circuit to  
stabilize before instruction execution begins.  
The POR timer circuit is a one-shot timer triggered by one of three conditions:  
•
•
•
Power Fail to Power OK status, including Waking up from VBO Standby  
Stop Mode Recovery (if D5 of SMR = 1)  
WDT Timeout  
The POR timer is 2.5 ms minimum. Bit 5 of the Stop-Mode Register determines whether  
the POR timer is bypassed after Stop Mode Recovery (typical for external clock).  
HALT Mode  
This instruction turns OFF the internal CPU clock, but not the XTAL oscillation. The  
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5 remain  
active. The devices are recovered by interrupts, either externally or internally generated.  
An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt  
service routine, the program continues from the instruction after HALT Mode.  
STOP Mode  
This instruction turns off the internal clock and external crystal oscillation, reducing the  
standby current to 10 μA or less. STOP mode is terminated only by a reset, such as WDT  
timeout, POR or SMR. This condition causes the processor to restart the application  
program at address 000Ch. To enter STOP (or HALT) mode, first flush the instruction  
pipeline to avoid suspending execution in mid-instruction.  
Execute a NOP (Opcode = FFh) immediately before the appropriate sleep instruction, as  
follows:  
FF  
6F  
NOP  
STOP  
; clear the pipeline  
; enter Stop Mode  
or  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
48  
FF  
7F  
NOP  
HALT  
; clear the pipeline  
; enter HALT Mode  
Port Configuration Register  
The Port Configuration (PCON) register (see Figure 30) configures the comparator output  
on Port 3. It is located in the expanded register 2 at Bank F, location 00.  
PCON(FH)00h  
D7 D6 D5 D4 D3 D2 D1 D0  
Comparator Output Port 3  
0 P34, P37 Standard Output*  
1 P34, P37 Comparator Output  
Port 1  
0: Open-Drain  
1: Push-Pull*  
Port 0  
0: Open-Drain  
1: Push-Pull*  
Reserved (Must be 1)  
* Default setting after reset.  
Figure 30. Port Configuration Register (PCON) (Write Only)  
Comparator Output Port 3 (D0)  
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator  
outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration.  
Port 1 Output Mode (D1)  
Bit 1 controls the output mode of port 1. A 1 in this location sets the output to push-pull,  
and a 0 sets the output to open-drain.  
Port 0 Output Mode (D2)  
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to push-pull,  
and a 0 sets the output to open-drain.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
49  
Stop Mode Recovery Register (SMR)  
This register selects the clock divide value and determines the mode of Stop Mode Recov-  
ery (see Figure 31). All bits are write only except bit 7, which is read only. Bit 7 is a flag  
bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle.  
Bit 6 controls whether a low level or a high level at the XOR-gate input (see Figure 33 on  
page 52) is required from the recovery source. Bit 5 controls the reset delay after recovery.  
Bits D2, D3, and D4 of the SMR register specify the source of the Stop Mode Recovery  
signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located  
in Bank F of the Expanded Register Group at address 0Bh.  
SMR(0F)0Bh  
D7 D6 D5 D4 D3 D2 D1 D0  
SCLK/TCLK Divide-by-16  
0 OFF * *  
1 ON  
Reserved (Must be 0)  
Stop Mode Recovery Source  
000 POR Only *  
001 Reserved  
010 P31  
011 P32  
100 P33  
101 P27  
110 P2 NOR 0-3  
111 P2 NOR 0-7  
Stop Delay  
0 OFF  
1 ON * * * *  
Stop Recovery Level * * *  
0 Low *  
1 High  
Stop Flag  
0 POR *  
1 Stop Recovery * *  
* Default after Power-On Reset or Watchdog Reset.  
* * Default setting after Reset and Stop Mode recovery.  
* * * At the XOR gate input.  
* * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source.  
Figure 31. STOP Mode Recovery Register  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
50  
SCLK/TCLK Divide-by-16 Select (D0)  
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (see Figure 32). This  
control selectively reduces device power consumption during normal processor execution  
(SCLK control) and/or HALT Mode (where TCLK sources interrupt logic). After Stop  
Mode Recovery, this bit is set to a 0.  
OSC  
÷ 2  
SCLK  
÷ 16  
SMR, D0  
TCLK  
Figure 32. SCLK Circuit  
Stop Mode Recovery Source (D2, D3, and D4)  
These three bits of the SMR specify the wake-up source of the Stop recovery (see  
Figure 33 and Table 14).  
Stop Mode Recovery Register 2—SMR2(F)0Dh  
Table 13 lists and briefly describes the fields for this register.  
Table 13. SMR2(F)0Dh:Stop Mode Recovery Register 2*  
Field  
Bit Position  
7-------  
-6------  
Value  
Description  
Reserved  
Recovery Level  
0
Reserved (Must be 0)  
†
W
0
Low  
1
High  
Reserved  
--5-----  
0
Reserved (Must be 0)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
51  
Table 13. SMR2(F)0Dh:Stop Mode Recovery Register 2*  
Field  
Bit Position  
Value  
Description  
†
Source  
---432--  
W
000  
A. POR Only  
001  
010  
011  
100  
101  
110  
111  
B. NAND of P23–P20  
C. NAND of P27–P20  
D. NOR of P33–P31  
E. NAND of P33–P31  
F. NOR of P33–P31, P00, P07  
G. NAND of P33–P31, P00, P07  
H. NAND of P33–P31, P22–P20  
Reserved  
------10  
00  
Reserved (Must be 0)  
* Port pins configured as outputs are ignored as an SMR recovery source.  
† Indicates the value upon Power-On Reset.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
52  
SMR D4 D3 D2  
0 0  
SMR2 D4 D3 D2  
0
0
0 0  
VCC  
SMR2 D4 D3 D2  
0 1  
VCC  
SMR D4 D3 D2  
1 0  
0
0
P20  
P23  
P31  
P32  
SMR2 D4 D3 D2  
1 0  
SMR D4 D3 D2  
1 1  
0
P20  
P27  
0
SMR2 D4 D3 D2  
1 1  
SMR D4 D3 D2  
0 0  
0
1
P31  
P32  
P33  
P33  
P27  
SMR2 D4 D3 D2  
0 0  
SMR D4 D3 D2  
0 1  
1
P31  
P32  
P33  
1
SMR2 D4 D3 D2  
0 1  
SMR D4 D3 D2  
1 0  
P31  
P32  
P33  
P00  
P07  
1
1
P20  
P23  
SMR2 D4 D3 D2  
1 0  
SMR D4 D3 D2  
1 1  
P31  
P32  
P33  
P00  
P07  
1
1
P20  
P27  
SMR2 D4 D3 D2  
1 1  
SMR D6  
P31  
P32  
P33  
P20  
P21  
P22  
1
SMR2 D6  
To RESET and WDT  
Circuitry (Active Low)  
Figure 33. Stop Mode Recovery Source  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
53  
Table 14. Stop Mode Recovery Source  
SMR:432  
Operation  
D4  
0
D3  
0
D2  
0
Description of Action  
POR and/or external reset recovery  
Reserved  
0
0
1
0
1
0
P31 transition  
0
1
1
P32 transition  
1
0
0
P33 transition  
1
0
1
P27 transition  
1
1
0
Logical NOR of P20 through P23  
Logical NOR of P20 through P27  
1
1
1
Note:  
Any Port 2 bit defined as an output drives the corresponding input to the default state. For  
example, if the NOR of P23-P20 is selected as the recovery source and P20 is configured  
as an output, the remaining SMR pins (P23-P21) form the NOR equation. This condition  
allows the remaining inputs to control the AND/OR function. See Stop Mode Recovery  
Register 2 (SMR2) on page 54 for other recover sources.  
Stop Mode Recovery Delay Select (D5)  
This bit, if low, disables the TPOR delay after Stop Mode Recovery. The default configura-  
tion of this bit is 1. If the “fast” wake up is selected, the Stop Mode Recovery source must  
be kept active for at least 10 TpC.  
Note:  
This bit must be set to 1 if using a crystal or resonator clock source. The TPOR delay  
allows the clock source to stabilize before executing instructions.  
Stop Mode Recovery Edge Select (D6)  
A 1 in this bit position indicates that a High level on any one of the recovery sources  
wakes the Z8 GP ROM MCU from Stop Mode. A 0 indicates Low level recovery. The  
default is 0 on POR.  
Cold or Warm Start (D7)  
This bit is read only. It is set to 1 when the device is recovered from Stop Mode. The bit is  
set to 0 when the device reset is other than Stop Mode Recovery.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
54  
Stop Mode Recovery Register 2 (SMR2)  
This register determines the mode of Stop Mode Recovery for SMR2 (see Figure 34).  
SMR2(0F)Dh  
D7 D6 D5 D4 D3 D2 D1 D0  
Reserved (Must be 0)  
Reserved (Must be 0)  
Stop Mode Recovery Source 2  
000 POR Only *  
001 NAND P20, P21, P22, P23  
010 NAND P20, P21, P22, P23, P24, P25, P26, P27  
011 NOR P31, P32, P33  
100 NAND P31, P32, P33  
101 NOR P31, P32, P33, P00, P07  
110 NAND P31, P32, P33, P00, P07  
111 NAND P31, P32, P33, P20, P21, P22  
Reserved (Must be 0)  
Recovery Level * *  
0 Low *  
1 High  
Reserved (Must be 0)  
Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.  
* Default setting after reset.  
* * At the XOR gate input.  
Figure 34. Stop Mode Recovery Register 2 ((0F)DH:D2–D4, D6 Write Only)  
If SMR2 is used in conjunction with SMR, either of the specified events causes a Stop  
Mode Recovery.  
Note:  
Port pins configured as outputs are ignored as an SMR or SMR2 recovery source.  
For example, if the NAND or P23–P20 is selected as the recovery source and P20 is  
configured as an output, the remaining SMR pins (P23–P21) form the NAND equation.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
55  
Watchdog Timer Mode Register (WDTMR)  
The Watchdog Timer (WDT) is a retriggerable one-shot timer that resets the Z8 if it  
reaches its terminal count. The WDT must initially be enabled by executing the WDT  
instruction. On subsequent executions of the WDT instruction, the WDT is refreshed. The  
WDT circuit is driven by an on-board RC-oscillator. The WDT instruction affects the Zero  
(Z), Sign (S), and Overflow (V) flags.  
The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register control  
a tap circuit that determines the minimum timeout period. Bit 2 determines whether the  
WDT is active during HALT, and Bit 3 determines WDT activity during Stop. Bits 4  
through 7 are reserved (see Figure 35). This register is accessible only during the first 60  
processor cycles (120 XTAL clocks) from the execution of the first instruction after  
Power-On-Reset, Watchdog Reset, or a Stop-Mode  
Recovery (see Figure 34). After this point, the register cannot be modified by any means  
(intentional or otherwise). The WDTMR cannot be read. The register is located in Bank F  
of the Expanded Register Group at address location 0Fh. It is organized as shown in  
Figure 35.  
WDTMR(0F)0Fh  
D7 D6 D5 D4 D3 D2 D1 D0  
WDT TAP INT RC OSC  
00  
01*  
10  
11  
5 ms min.  
10 ms min.  
20 ms min.  
80 ms min.  
WDT During HALT  
0 OFF  
1 ON *  
WDT During Stop  
0 OFF  
1 ON *  
Reserved (Must be 0)  
* Default setting after reset.  
Figure 35. Watchdog Timer Mode Register (Write Only)  
WDT Time Select (D0, D1)  
This bit selects the WDT time period. It is configured as indicated in Table 15.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
56  
Table 15. Watchdog Timer Time Select  
D1  
0
D0  
0
Timeout of Internal RC-Oscillator  
5 ms min.  
0
1
10 ms min.  
1
0
20 ms min.  
1
1
80 ms min.  
WDTMR During Halt (D2)  
This bit determines whether or not the WDT is active during HALT Mode. A 1 indicates  
active during HALT. The default is 1. See Figure 36.  
*CLR2  
18 Clock  
5 Clock Filter  
RESET  
Internal  
RESET  
Active  
High  
WDT  
XTAL  
POR 5 ms 10 ms 20 ms 80  
CL  
Internal  
RC  
WDT/POR Counter Chain  
*CLR  
Low Operating  
V
+
-
DD  
VBO  
WDT  
V
DD  
From Stop  
Mode  
Recovery  
12-ns Glitch  
Stop Delay  
Select  
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-High input.  
Figure 36. Resets and WDT  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
57  
WDTMR During STOP (D3)  
This bit determines whether or not the WDT is active during STOP Mode. A 1 indicates  
active during Stop. The default is 1.  
Selectable Options  
There are six Selectable Options to choose from based on ROM code requirements. These  
are listed in Table 16.  
Table 16. Selectable Options  
Port 00–03 Pull-Ups  
Port 04–07 Pull-Ups  
Port 10–13 Pull-Ups  
Port 14–17 Pull-Ups  
Port 20–27 Pull-Ups  
ON/OFF  
ON/OFF  
ON/OFF  
ON/OFF  
ON/OFF  
Watchdog Timer at Power-On Reset ON/OFF  
Voltage Brownout/Standby  
An on-chip Voltage Comparator checks that the VDD is at the required level for correct  
operation of the device. Reset is globally driven when VDD falls below VBO. A small drop  
in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or resonator clock. If  
the VDD is allowed to stay above VRAM, the RAM content is preserved. When the power  
level is returned to above VBO, the device performs a POR and functions normally.  
Low-Voltage Detection Register—LVD(D)0Ch  
Note:  
Voltage detection does not work at STOP mode. It must be disabled during STOP mode in  
order to reduce current.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
58  
Field  
Bit Position  
Description  
LVD  
76543---  
Reserved  
No Effect  
-----2--  
------1-  
-------0  
R
1
0*  
HVD flag set  
HVD flag reset  
R
1
0*  
LVD flag set  
LVD flag reset  
R/W  
1
0*  
Enable VD  
Disable VD  
*Default after POR.  
Do not modify register P01M while checking a low-voltage condition. Switching noise of  
both ports 0 and 1 together might trigger the LVD flag.  
Note:  
Voltage Detection and Flags  
The Voltage Detection register (LVD, register 0Chat the expanded register bank 0Dh)  
offers an option of monitoring the VCC voltage. The Voltage Detection is enabled when bit  
0 of LVD register is set. Once Voltage Detection is enabled, the VCC level is monitored in  
real time. The HVD flag (bit 2 of the LVD register) is set only if VCC is higher than VHVD.  
The LVD flag (bit 1 of the LVD register) is set only if VCC is lower than the VLVD. When  
Voltage Detection is enabled, the LVD flag also triggers IRQ5. The IRQ bit 5 latches the  
low-voltage condition until it is cleared by instructions or reset. The IRQ5 interrupt is  
served if it is enabled in the IMR register. Otherwise, bit 5 of IRQ register is latched as a  
flag only.  
Note:  
If it is necessary to receive an LVD interrupt upon power-up at an operating voltage lower  
than the low battery detect threshold, enable interrupts using the Enable Interrupt  
instruction (EI) prior to enabling the voltage detection.  
Expanded Register File Control Registers (0D)  
The expanded register file control registers (0D) are displayed in Figure 37 through  
Figure 41.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
59  
CTR0(0D)00H  
D7 D6 D5 D4 D3 D2 D1 D0  
0 P34 as Port Output *  
1 Timer8 Output  
0 Disable T8 Timeout Interrupt**  
1 Enable T8 Timeout Interrupt  
0 Disable T8 Data Capture Interrupt**  
1 Enable T8 Data Capture Interrupt  
00 SCLK on T8**  
01 SCLK/2 on T8  
10 SCLK/4 on T8  
11 SCLK/8 on T8  
R 0 No T8 Counter Timeout**  
R 1 T8 Counter Timeout Occurred  
W 0 No Effect  
W 1 Reset Flag to 0  
0 Modulo-N*  
1 Single Pass  
R 0 T8 Disabled *  
R 1 T8 Enabled  
W 0 Stop T8  
W 1 Enable T8  
* Default setting after reset.  
** Default setting after reset. Not reset with a Stop Mode Recovery.  
Figure 37. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
60  
CTR1(0D)01H  
D7 D6 D5 D4 D3 D2 D1 D0  
TRANSMIT Mode*  
R/W 0 T16_OUT is 0 initially*  
1 T16_OUT is 1 initially  
DEMODULATION Mode  
R 0 No Falling Edge Detection  
R 1 Falling Edge Detection  
W 0 No Effect  
W 1 Reset Flag to 0  
TRANSMIT Mode*  
R/W 0 T8_OUT is 0 initially*  
1 T8_OUT is 1 initially  
DEMODULATION Mode  
R 0 No Rising Edge Detection  
R
1 Rising Edge Detection  
W 0 No Effect  
W 1 Reset Flag to 0  
TRANSMIT Mode*  
0 0 Normal Operation*  
0 1 PING-PONG Mode  
1 0 T16_OUT = 0  
1 1 T16_OUT = 1  
DEMODULATION Mode  
0 0 No Filter  
0 1 4 SCLK Cycle Filter  
1 0 8 SCLK Cycle Filter  
1 1 Reserved  
TRANSMIT Mode/T8/T16 Logic  
0 0 AND**  
0 1 OR  
1 0 NOR  
1 1 NAND  
DEMODULATION Mode  
0 0 Falling Edge Detection  
0 1 Rising Edge Detection  
1 0 Both Edge Detection  
1 1 Reserved  
TRANSMIT Mode  
0 P36 as Port Output *  
1 P36 as T8/T16_OUT  
DEMODULATION Mode  
0 P31 as Demodulator Input  
1 P20 as Demodulator Input  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
61  
CTR1(0D)01H  
TRANSMIT/DEMODULATION Mode  
0 TRANSMIT Mode *  
1 DEMODULATION Mode  
* Default setting after reset.  
**Default setting after Reset. Not reset with a Stop  
Mode Recovery.  
Figure 38. T8 and T16 Common Control Functions ((0D)01H: Read/Write)  
Take care in differentiating the TRANSMIT Mode from DEMODULATION Mode. Depend-  
ing on which of these two modes is operating, the CTR1 bit has different functions.  
Note:  
Changing from one mode to another cannot be performed without disabling the counter/  
timers.  
CTR2(0D)02H  
D7 D6 D5 D4 D3 D2 D1 D0  
0 P35 is Port Output *  
1 P35 is TC16 Output  
0 Disable T16 Timeout Interrupt*  
1 Enable T16 Timeout Interrupt  
0 Disable T16 Data Capture Interrupt**  
1 Enable T16 Data Capture Interrupt  
0 0 SCLK on T16**  
0 1 SCLK/2 on T16  
1 0 SCLK/4 on T16  
1 1 SCLK/8 on T16  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
62  
R 0 No T16 Timeout**  
R 1 T16 Timeout Occurs  
W 0 No Effect  
W 1 Reset Flag to 0  
TRANSMIT Mode  
0 Modulo-N for T16*  
1 Single Pass for T16  
DEMODULATOR Mode  
0 T16 Recognizes Edge  
1 T16 Does Not Recognize Edge  
R 0 T16 Disabled *  
R 1 T16 Enabled  
W 0 Stop T16  
* Default setting after reset.  
** Default setting after reset. Not reset with a Stop  
W 1 Enable T16  
Mode Recovery.  
Figure 39. T16 Control Register ((0D) 2H: Read/Write Except Where Noted)  
CTR3(0D)03H  
D7 D6 D5 D4 D3 D2 D1 D0  
Reserved  
No effect when written  
Always reads 11111  
Sync Mode  
0* Disable Sync Mode**  
1 Enable Sync Mode  
T Enable  
8
R 0* T Disabled  
8
R 1 T Enabled  
8
W0 Stop T  
8
W1 Enable T  
8
T
Enable  
16  
R 0* T Disabled  
16  
R 1 T Enabled  
16  
W 0 Stop T  
16  
W 1 Enable T  
16  
* Default setting after reset.  
** Default setting after reset. Not reset with a Stop  
Mode Recovery.  
Figure 40. T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
63  
If Sync Mode is enabled, the first pulse of T8 carrier is always synchronized with T16  
(demodulated signal). It can always provide a full carrier pulse.  
Note:  
LVD(0D)0CH  
D7 D6 D5 D4 D3 D2 D1 D0  
Voltage Detection  
0: Disable *  
1: Enable  
LVD Flag (Read only)  
0: LVD flag reset *  
1: LVD flag set  
HVD Flag (Read only)  
0: HVD flag reset *  
1: HVD flag set  
Reserved (Must be 0)  
* Default setting after reset.  
Figure 41. Voltage Detection Register  
Note:  
Do not modify register P01M while checking a low-voltage condition. Switching noise of  
both ports 0 and 1 together may trigger the LVD flag.  
Expanded Register File Control Registers (0F)  
The expanded register file control registers (0F) are displayed in Figure 42 through  
Figure 55.  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
64  
PCON(0F)00H  
D7 D6 D5 D4 D3 D2 D1 D0  
Comparator Output Port 3  
0 P34, P37 Standard Output *  
1 P34, P37 Comparator Output  
Port 1  
0: Open-Drain  
1: Push-Pull*  
Port 0  
0: Open-Drain  
1: Push-Pull *  
Reserved (Must be 1)  
* Default setting after reset.  
Figure 42. Port Configuration Register (PCON)(0F)00H: Write Only)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
65  
SMR(0F)0BH  
D7 D6 D5 D4 D3 D2 D1 D0  
SCLK/TCLK Divide-by-16  
0 OFF *  
1 ON  
Reserved (Must be 0)  
Stop Mode Recovery Source  
000 POR Only *  
001 Reserved  
010 P31  
011 P32  
100 P33  
101 P27  
110 P2 NOR 0–3  
111 P2 NOR 0–7  
Stop Delay  
0 OFF  
1 ON * * * *  
Stop Recovery Level * * *  
0 Low *  
1 High  
Stop Flag  
0 POR * * * * *  
1 Stop Recovery * *  
* Default setting after Reset.  
* * Set after STOP Mode Recovery.  
* * * At the XOR gate input.  
* * * * Default setting after Reset. Must be 1 if using a crystal or resonator clock source.  
* * * * * Default setting after Power-On Reset. Not Reset with a Stop Mode Recovery.  
Figure 43. Stop Mode Recovery Register ((0F)0BH: D6–D0=Write Only, D7=Read Only)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
66  
SMR2(0F)0DH  
D7 D6 D5 D4 D3 D2 D1 D0  
Reserved (Must be 0)  
Reserved (Must be 0)  
Stop Mode Recovery Source 2  
000 POR Only *  
001 NAND P20, P21, P22, P23  
010 NAND P20, P21, P22, P23, P24, P25, P26, P27  
011 NOR P31, P32, P33  
100 NAND P31, P32, P33  
101 NOR P31, P32, P33, P00, P07  
110 NAND P31, P32, P33, P00, P07  
111 NAND P31, P32, P33, P20, P21, P22  
Reserved (Must be 0)  
Recovery Level * *  
0 Low  
1 High  
Reserved (Must be 0)  
Note: If used in conjunction with SMR, either of the two specified events causes a Stop Mode Recovery.  
* Default setting after reset. Not Reset with a Stop Mode Recovery.  
* * At the XOR gate input.  
Figure 44. Stop Mode Recovery Register 2 ((0F)0DH:D2–D4, D6 Write Only)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
67  
WDTMR(0F)0FH  
D7 D6 D5 D4 D3 D2 D1 D0  
WDT TAP INT RC OSC  
00  
01*  
10  
11  
5 ms min.  
10 ms min.  
20 ms min.  
80 ms min.  
WDT During HALT  
0 OFF  
1 ON *  
WDT During Stop  
0 OFF  
1 ON *  
Reserved (Must be 0)  
* Default setting after reset. Not Reset with a Stop Mode Recovery.  
Figure 45. Watchdog Timer Register ((0F) 0FH: Write Only)  
Standard Control Registers  
R246 P2M(F6H)  
D7 D6 D5 D4 D3 D2 D1 D0  
P27–P20 I/O Definition  
0 Defines bit as OUTPUT  
1 Defines bit as INPUT *  
* Default setting after reset. Not Reset with a Stop Mode Recovery.  
Figure 46. Port 2 Mode Register (F6H: Write Only)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
68  
R247 P3M(F7H)  
D7 D6 D5 D4 D3 D2 D1 D0  
0: Port 2 Open Drain *  
1: Port 2 Push-Pull  
0= P31, P32 Digital Mode*  
1= P31, P32 Analog Mode  
Reserved (Must be 0)  
* Default setting after reset. Not Reset with a Stop Mode Recovery.  
Figure 47. Port 3 Mode Register (F7H: Write Only)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
69  
R248 P01M(F8H)  
D7 D6 D5 D4 D3 D2 D1 D0  
P00–P03 Mode  
0: Output  
1: Input *  
Reserved (Must be 0)  
Reserved (Must be 1)  
P17–P10 Mode  
0: Byte Output  
1: Byte Input*  
Reserved (Must be 0)  
P07–P04 Mode  
0: Output  
1: Input *  
Reserved (Must be 0)  
* Default setting after reset; only P00, P01 and P07 are available on 20-pin configurations.  
Figure 48. Port 0 and 1 Mode Register (F8H: Write Only)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
70  
R249 IPR(F9H)  
D7 D6 D5 D4 D3 D2 D1 D0  
Interrupt Group Priority  
000 Reserved  
001 C > A > B  
010 A > B >C  
011 A > C > B  
100 B > C > A  
101 C > B > A  
110 B > A > C  
111 Reserved  
IRQ1, IRQ4, Priority  
(Group C)  
0: IRQ1 > IRQ4  
1: IRQ4 > IRQ1  
IRQ0, IRQ2, Priority  
(Group B)  
0: IRQ2 > IRQ0  
1: IRQ0 > IRQ2  
IRQ3, IRQ5, Priority  
(Group A)  
0: IRQ5 > IRQ3  
1: IRQ3 > IRQ5  
Reserved; must be 0  
Figure 49. Interrupt Priority Register (F9H: Write Only)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
71  
R250 IRQ(FAH)  
D7 D6 D5 D4 D3 D2 D1 D0  
IRQ0 = P32 Input  
IRQ1 = P33 Input  
IRQ2 = P31 Input  
IRQ3 = T16  
IRQ4 = T8  
IRQ5 = LVD  
Inter Edge  
P31↓  
P31↓  
P31↑  
P32↓ = 00  
P32↑ = 01  
P32↓ = 10  
P31↑↓ P32↑↓ = 11  
Figure 50. Interrupt Request Register (FAH: Read/Write)  
R251 IMR(FBH)  
D7 D6 D5 D4 D3 D2 D1 D0  
1 Enables IRQ5–IRQ0  
(D0 = IRQ0)  
Reserved (Must be 0)  
0 Master Interrupt Disable *  
1 Master Interrupt Enable * *  
* Default setting after reset.  
* * Only by using EI, DI instruction; DI is required before changing the IMR register.  
Figure 51. Interrupt Mask Register (FBH: Read/Write)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
72  
R252 Flags(FCH)  
D7 D6 D5 D4 D3 D2 D1 D0  
User Flag F1  
User Flag F2  
Half Carry Flag  
Decimal Adjust Flag  
Overflow Flag  
Sign Tag  
Zero Flag  
Carry Flag  
Figure 52. Flag Register (FCH: Read/Write)  
R253 RP(FDH)  
D7 D6 D5 D4 D3 D2 D1 D0  
Expanded Register Bank Pointer  
Working Register Pointer  
Default setting after reset = 0000 0000  
Figure 53. Register Pointer (FDH: Read/Write)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
73  
R254 SPH(FEH)  
D7 D6 D5 D4 D3 D2 D1 D0  
General-Purpose Register  
Figure 54. Stack Pointer High (FEH: Read/Write)  
R255 SPL(FFH)  
D7 D6 D5 D4 D3 D2 D1 D0  
Stack Pointer Low  
Byte (SP7–SP0)  
Figure 55. Stack Pointer Low (FFH: Read/Write)  
PS023910-0408  
Functional Description  
ZGR323L  
Product Specification  
74  
Electrical Characteristics  
Absolute Maximum Ratings  
Stresses greater than those listed in Table 17 might cause permanent damage to the device.  
This rating is a stress rating only. Functional operation of the device at any condition  
above those indicated in the operational sections of these specifications is not implied.  
Exposure to absolute maximum rating conditions for an extended period might affect  
device reliability.  
Table 17. Absolute Maximum Ratings  
Parameter  
Minimum Maximum Units  
Notes  
Ambient temperature under bias  
Storage temperature  
–40  
–65  
–0.3  
–0.3  
–5  
+125  
+150  
+5.5  
+3.6  
+5  
C
C
Voltage on any pin with respect to V  
V
1
SS  
Voltage on V pin with respect to V  
V
DD  
SS  
Maximum current on input and/or inactive output pin  
Maximum output current from active output pin  
µA  
mA  
mA  
–25  
+25  
75  
Maximum current into V or out of V  
DD  
SS  
1. This voltage applies to all pins except the following: VDD, P32, P33 and RESET.  
Standard Test Conditions  
The characteristics listed in this product specification apply for standard test conditions as  
noted. All voltages are referenced to GND. Positive current flows into the referenced pin  
(see Figure 56).  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
75  
From Output  
Under Test  
150 pF  
Figure 56. Test Load Diagram  
Capacitance  
Table 18 lists the capacitances.  
Table 18. Capacitance  
Parameter  
Maximum  
Input capacitance  
Output capacitance  
I/O capacitance  
12 pF  
12 pF  
12 pF  
Note: TA = 25 °C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND.  
DC Characteristics  
Table 19. GR323LS DC Characteristics  
TA= 0 °C to +70 °C  
Min Typ(7)  
2.0  
2.0-3.6 0.8 V  
Symbol Parameter  
VCC  
Max Units Conditions  
Notes  
V
V
Supply Voltage  
3.6  
V
See Notes  
5
CC  
CH  
Clock Input High  
Voltage  
V
+0.3 V  
CC  
Driven by External  
Clock Generator  
CC  
V
Clock Input Low  
Voltage  
2.0-3.6  
V
–0.3  
0.5  
V
Driven by External  
Clock Generator  
CL  
SS  
V
V
V
Input High Voltage 2.0-3.6 0.7 V  
V +0.3 V  
CC  
IH  
CC  
Input Low Voltage  
2.0-3.6  
V
V
–0.3  
0.2 V  
CC  
V
V
IL  
SS  
CC  
Output High Voltage 2.0-3.6  
–0.4  
I
= –0.5 mA  
OH  
OH1  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
76  
Table 19. GR323LS DC Characteristics (Continued)  
TA= 0 °C to +70 °C  
Symbol Parameter  
VCC  
Min  
–0.8  
Typ(7)  
Max Units Conditions  
Notes  
V
Output High Voltage 2.0-3.6  
(P36, P37, P00,  
P01)  
V
V
I
= –7 mA  
OH2  
CC  
OH  
V
V
Output Low Voltage 2.0-3.6  
0.4  
0.8  
V
V
I
I
= 4.0 mA  
= 10 mA  
OL1  
OL2  
OL  
OL  
Output Low Voltage 2.0-3.6  
(P00, P01, P36,  
P37)  
V
V
Comparator Input  
Offset Voltage  
2.0-3.6  
25  
mV  
V
OFFSET  
REF  
Comparator  
Reference  
Voltage  
2.0-3.6  
0
V
DD  
-1.75  
I
Input Leakage  
2.0-3.6 –1  
1
μA  
V
= 0 V, V  
CC  
IL  
IN  
Pull-ups disabled  
R
Pull-Up Resistance 2.0V  
3.6V  
225  
75  
675  
275  
KΩ VIN = 0 V; Pullups  
PU  
selected by mask  
KΩ  
option  
I
Output Leakage  
Supply Current  
2.0-3.6 –1  
1
μA  
V
= 0 V, V  
IN CC  
OL  
I
2.0  
3.6  
1.2  
2.2  
3
5
mA at 8.0 MHz  
mA at 8.0 MHz  
1, 2  
1, 2  
CC  
I
Standby Current  
(HALT Mode)  
2.0  
3.6  
0.5  
0.8  
1.6  
2.0  
mA  
mA 8.0 MHz  
Same as above  
= 0 V, V WDT 3  
V
= 0 V, V at  
1, 2, 6  
1, 2, 6  
CC1  
IN  
CC  
I
Standby Current  
(STOP Mode)  
2.0  
3.6  
2.0  
3.6  
1.5  
2.1  
4.7  
7.4  
8
μA  
μA  
μA  
μA  
V
IN  
CC2  
CC  
10  
20  
30  
is not Running  
Same as above  
3
3
3
V
= 0 V, V WDT  
IN  
CC  
is Running  
Same as above  
I
Standby Current  
(Low Voltage)  
1.0  
1.8  
2.4  
2.7  
6
μA  
V
Measured at 1.3 V  
4
LV  
V
V
V
V
Low-Voltage  
CC  
2.0  
8 MHz maximum  
Ext. CLK Freq.  
BO  
Protection  
Vcc Low-Voltage  
Detection  
V
LVD  
HVD  
Vcc High-Voltage  
Detection  
V
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
77  
Table 19. GR323LS DC Characteristics (Continued)  
TA= 0 °C to +70 °C  
Min Typ(7)  
Symbol Parameter  
Notes  
VCC  
Max Units Conditions  
Notes  
1. All outputs unloaded, inputs at rail.  
2. CL1 = CL2 = 100 pF.  
3. Oscillator stopped.  
4. Oscillator stops when VCC falls below VBO limit.  
5. It is strongly recommended to add a filter capacitor (minimum 0.1 μF), physically close to VDD and VSS pins if  
operating voltage fluctuations are anticpated, such as those resulting from driving an infrared LED.  
6. Comparator and Timers are on. Interrupt disabled.  
7. Typical values shown are at 25 °C.  
Table 20. GR323LE DC Characteristics  
TA= –40 °C to +105 °C  
Symbol Parameter  
VCC  
Min  
2.0  
Typ(7)  
Max Units Conditions  
Notes  
V
V
Supply Voltage  
3.6  
V
See Notes  
5
CC  
CH  
Clock Input High 2.0-3.6 0.8 V  
Voltage  
V
+0.3 V  
CC  
Driven by External  
Clock Generator  
CC  
V
V
V
V
V
Clock Input Low 2.0-3.6 V –0.3  
Voltage  
0.5  
V
Driven by External  
Clock Generator  
CL  
SS  
Input High  
Voltage  
2.0-3.6 0.7 V  
V +0.3 V  
CC  
IH  
CC  
Input Low  
Voltage  
2.0-3.6 V –0.3  
0.2 V  
CC  
V
V
V
IL  
SS  
Output High  
Voltage  
2.0-3.6 V –0.4  
I
I
= –0.5 mA  
= –7 mA  
OH1  
OH2  
CC  
OH  
OH  
Output High  
2.0-3.6 V –0.8  
CC  
Voltage (P36,  
P37, P00, P01)  
V
V
Output Low  
Voltage  
2.0-3.6  
2.0-3.6  
0.4  
0.8  
V
V
I
I
= 4.0 mA  
= 8 mA  
OL1  
OL2  
OL  
Output Low  
Voltage  
OL  
(P00, P01, P36,  
P37)  
V
V
Comparator Input 2.0-3.6  
Offset Voltage  
25  
mV  
V
OFFSET  
REF  
Comparator  
Reference  
Voltage  
2.0-3.6 0  
V
DD  
-1.75  
I
Input Leakage  
2.0-3.6 –1  
1
μA  
V
= 0 V, V  
CC  
IL  
IN  
Pull-ups disabled  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
78  
Table 20. GR323LE DC Characteristics (Continued)  
TA= –40 °C to +105 °C  
Symbol Parameter  
VCC  
Min  
Typ(7)  
Max Units Conditions  
Notes  
R
Pull-Up  
Resistance  
2.0 V 200  
3.6 V 50  
700  
300  
1
KΩ VIN = 0 V; Pullups selected  
PU  
by mask option  
KΩ  
μA  
I
Output Leakage 2.0-3.6 –1  
V
IN  
= 0 V, V  
OL  
CC  
I
I
I
Supply Current  
2.0  
3.6  
1.2  
2.2  
3
5
mA at 8.0 MHz  
mA at 8.0 MHz  
1, 2  
1, 2  
CC  
Standby Current 2.0  
(HALT Mode) 3.6  
Standby Current 2.0  
0.5  
0.8  
1.6  
2.0  
mA  
V
= 0V, V at 8.0 MHz  
IN  
1, 2, 6  
1, 2, 6  
CC1  
CC2  
CC  
mA Same as above  
1.5  
2.1  
4.7  
7.4  
12  
15  
30  
40  
μA  
μA  
μA  
μA  
V
= 0 V, V WDT is not  
3
3
3
3
IN  
CC  
(STOP Mode)  
3.6  
2.0  
3.6  
Running  
Same as above  
V
= 0 V, V WDT is  
IN  
CC  
Running  
Same as above  
I
Standby Current  
(Low Voltage)  
1.0  
1.8  
2.4  
2.7  
6
μA  
V
Measured at 1.3 V  
4
LV  
V
V
V
V
Low-Voltage  
CC  
2.15  
8 MHz maximum  
Ext. CLK Freq.  
BO  
Protection  
Vcc Low-Voltage  
Detection  
V
LVD  
HVD  
Vcc High-Voltage  
Detection  
V
Notes  
1. All outputs unloaded, inputs at rail.  
2. CL1 = CL2 = 100 pF.  
3. Oscillator stopped.  
4. Oscillator stops when VCC falls below VBO limit.  
5. It is strongly recommended to add a filter capacitor (minimum 0.1 μF), physically close to VDD and VSS pins if  
operating voltage fluctuations are anticpated, such as those resulting from driving an infrared LED.  
6. Comparator and Timers are on. Interrupt disabled.  
7. Typical values shown are at 25 °C.  
Table 21. GR323LA DC Characteristics  
TA= –40 °C to +125 °C  
Symbol Parameter  
VCC  
Min  
2.0  
Typ(7)  
Max Units Conditions  
Notes  
V
V
Supply Voltage  
3.6  
V
See Notes  
5
CC  
CH  
Clock Input High 2.0-3.6 0.8 V  
Voltage  
V
+0.3 V  
CC  
Driven by External  
Clock Generator  
CC  
V
Clock Input Low 2.0-3.6 V –0.3  
Voltage  
0.5  
V
Driven by External  
Clock Generator  
CL  
SS  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
79  
Table 21. GR323LA DC Characteristics (Continued)  
TA= –40 °C to +125 °C  
Symbol Parameter  
VCC  
Min  
Typ(7)  
Max Units Conditions  
V +0.3 V  
CC  
Notes  
V
Input High  
Voltage  
2.0-3.6 0.7 V  
IH  
CC  
V
V
Input Low Voltage 2.0-3.6 V –0.3  
0.2 V  
CC  
V
V
IL  
SS  
Output High  
Voltage  
2.0-3.6 V –0.4  
I
I
= –0.5 mA  
OH1  
CC  
OH  
V
Output High  
2.0-3.6 V –0.8  
V
= –7 mA  
OH2  
CC  
OH  
Voltage (P36,  
P37, P00, P01)  
V
V
Output Low  
Voltage  
2.0-3.6  
2.0-3.6  
0.4  
0.8  
V
V
I
I
= 4.0 mA  
= 8 mA  
OL1  
OL2  
OL  
OL  
Output Low  
Voltage  
(P00, P01, P36,  
P37)  
V
V
Comparator Input 2.0-3.6  
Offset Voltage  
25  
mV  
V
OFFSET  
REF  
Comparator  
Reference  
Voltage  
2.0-3.6 0  
V
DD  
-1.75  
I
Input Leakage  
2.0-3.6 –1  
1
μA  
V
= 0 V, V  
CC  
IL  
IN  
Pull-ups disabled  
R
Pull-Up  
Resistance  
2.0 V  
3.6 V  
200  
50  
700  
300  
1
KΩ VIN = 0 V; Pullups selected  
PU  
by mask option  
KΩ  
I
Output Leakage 2.0-3.6 –1  
μA  
V
= 0 V, V  
IN CC  
OL  
I
I
I
Supply Current  
2.0  
3.6  
1.2  
2.2  
3
5
mA at 8.0 MHz  
mA at 8.0 MHz  
1, 2  
1, 2  
CC  
Standby Current 2.0  
(HALT Mode) 3.6  
Standby Current 2.0  
0.5  
0.8  
1.6  
2.0  
mA  
mA Same as above  
μA = 0 V, V WDT is not 3  
μA Running  
μA Same as above  
= 0 V, V WDT is  
V
= 0 V, V at 8.0 MHz 1, 2, 6  
CC1  
CC2  
IN  
CC  
1, 2, 6  
1.5  
2.1  
4.7  
7.4  
15  
20  
30  
40  
V
IN  
CC  
(STOP Mode)  
3.6  
2.0  
3.6  
3
3
3
μA  
V
IN  
Running  
CC  
Same as above  
I
Standby Current  
(Low Voltage)  
1.0  
1.8  
2.4  
6
μA Measured at 1.3 V  
4
LV  
V
V
V
Low-Voltage  
CC  
2.15  
V
V
8 MHz maximum  
Ext. CLK Freq.  
BO  
Protection  
Vcc Low-Voltage  
Detection  
LVD  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
80  
Table 21. GR323LA DC Characteristics (Continued)  
TA= –40 °C to +125 °C  
Symbol Parameter  
VCC  
Min  
Typ(7)  
Max Units Conditions  
Notes  
V
Vcc High-Voltage  
Detection  
2.7  
V
HVD  
Notes  
1. All outputs unloaded, inputs at rail.  
2. CL1 = CL2 = 100 pF.  
3. Oscillator stopped.  
4. Oscillator stops when VCC falls below VBO limit.  
5. It is strongly recommended to add a filter capacitor (minimum 0.1 μF), physically close to VDD and VSS pins if  
operating voltage fluctuations are anticpated, such as those resulting from driving an infrared LED.  
6. Comparator and Timers are on. Interrupt disabled.  
7. Typical values shown are at 25 °C.  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
81  
AC Characteristics  
Figure 57 and Table 22 describe the Alternating Current (AC) characteristics.  
1
3
Clock  
2
2
3
7
4
7
T
IN  
5
6
IRQ  
N
8
9
Clock  
Setup  
11  
Stop  
Mode  
Recovery  
Source  
10  
Figure 57. AC Timing Diagram  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
82  
Table 22. AC Characteristics  
T =0 °C to +70 °C (S)  
A
Watchdog  
Timer  
Mode  
–40 °C to +105 °C (E)  
–40 °C to +125 °C (A)  
8.0 MHz  
Register  
No Symbol  
Parameter  
V
Minimum Maximum Units Notes (D1, D0)  
CC  
1
2
TpC  
Input Clock Period  
2.0–3.6  
121  
DC  
25  
ns  
ns  
1
1
TrC,TfC  
Clock Input Rise and 2.0–3.6  
Fall Times  
3
4
TwC  
Input Clock Width  
2.0–3.6  
37  
ns  
ns  
1
1
TwTinL  
Timer Input  
Low Width  
2.0  
3.6  
100  
70  
5
TwTinH  
Timer Input High  
Width  
2.0–3.6  
3TpC  
1
6
7
TpTin  
Timer Input Period 2.0–3.6  
8TpC  
1
1
TrTin,TfTin Timer Input Rise and 2.0–3.6  
Fall Timers  
100  
ns  
ns  
8
9
TwIL  
Interrupt Request  
Low Time  
2.0  
3.6  
100  
70  
1, 2  
1, 2  
3
TwIH  
Interrupt Request  
Input High Time  
2.0–3.6  
5TpC  
10 Twsm  
Stop Mode Recovery 2.0–3.6  
Width Spec  
12  
ns  
10TpC  
4
4
11 Tost  
12 Twdt  
Oscillator  
Start-Up Time  
2.0–3.6  
5TpC  
Watchdog Timer  
Delay Time  
2.0–3.6  
2.0–3.6  
2.0–3.6  
2.0–3.6  
5
ms  
ms  
ms  
ms  
0, 0  
0, 1  
1, 0  
1, 1  
10  
20  
80  
13 T  
Power-On Reset  
2.0–3.6  
2.5  
10  
ms  
POR  
Notes  
1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0.  
2. Interrupt request through Port 3 (P33–P31).  
3. SMR – D5 = 1.  
4. SMR – D5 = 0.  
PS023910-0408  
Electrical Characteristics  
ZGR323L  
Product Specification  
83  
Packaging  
Package information for all versions of Z8 GP ROM MCU is displayed in  
Figure 58 through Figure 65.  
Figure 58. 20-Pin PDIP Package Diagram  
Figure 59. 20-Pin SOIC Package Diagram  
PS023910-0408  
Packaging  
ZGR323L  
Product Specification  
84  
Figure 60. 20-Pin SSOP Package Diagram  
PS023910-0408  
Packaging  
ZGR323L  
Product Specification  
85  
Figure 61. 28-Pin SOIC Package Diagram  
PS023910-0408  
Packaging  
ZGR323L  
Product Specification  
86  
Figure 62. 28-Pin PDIP Package Diagram  
PS023910-0408  
Packaging  
ZGR323L  
Product Specification  
87  
D
C
28  
15  
MILLIMETER  
NOM  
INCH  
SYMBOL  
MIN  
1.73  
0.05  
1.68  
0.25  
0.09  
MAX  
1.99  
0.21  
1.78  
0.38  
0.20  
MIN  
NOM  
0.073  
0.005  
0.068  
MAX  
0.078  
0.008  
0.070  
0.015  
0.008  
A
1.86  
0.068  
0.002  
0.066  
0.010  
0.004  
A1  
A2  
B
0.13  
H
E
1.73  
C
0.006  
1
14  
D
E
e
10.07  
5.20  
10.20  
5.30  
10.33  
5.38  
0.397  
0.205  
0.402  
0.407  
0.212  
DETAIL A  
0.209  
0.65 TYP  
0.0256 TYP  
H
L
7.65  
0.63  
7.80  
0.75  
7.90  
0.95  
0.301  
0.025  
0.307  
0.030  
0.311  
0.037  
A2  
A
B
e
SEATING PLANE  
CONTROLLING DIMENSIONS: MM  
LEADS ARE COPLANAR WITHIN .004 INCHES.  
L
0 - 8  
DETAIL 'A'  
Figure 63. 28-Pin SSOP Package Diagram  
Figure 64. 40-Pin PDIP Package Diagram  
PS023910-0408  
Packaging  
ZGR323L  
Product Specification  
88  
c
D
48  
25  
E
H
1
24  
Detail  
A
A2  
A
CONTROLLING DIMENSIONS  
: MM  
LEADS ARE COPLANAR WITHIN .004 INCH  
A1  
SEATING PLANE  
e
b
L
0-8˚  
Detail  
A
Figure 65. 48-Pin SSOP Package Design  
®
Note:  
Check with Zilog on the actual bonding diagram and coordinate for chip-on-board  
assembly.  
PS023910-0408  
Packaging  
ZGR323L  
Product Specification  
89  
Ordering Information  
32 KB Standard Temperature: 0 °C to +70 °C  
Part Number  
ZGR323LSH4832G 48-pin SSOP 32K ROM ZGR323LSS2832G 28-pin SOIC 32K ROM  
ZGR323LSP4032G 40-pin PDIP 32K ROM ZGR323LSH2032G 20-pin SSOP 32K ROM  
ZGR323LSH2832G 28-pin SSOP 32K ROM ZGR323LSP2032G 20-pin PDIP 32K ROM  
ZGR323LSP2832G 28-pin PDIP 32K ROM ZGR323LSS2032G 20-pin SOIC 32K ROM  
Description  
Part Number  
Description  
32 KB Extended Temperature: –40 °C to +105 °C  
Part Number Description Part Number  
ZGR323LEH4832G 48-pin SSOP 32K ROM ZGR323LES2832G 28-pin SOIC 32K ROM  
ZGR323LEP4032G 40-pin PDIP 32K ROM ZGR323LEH2032G 20-pin SSOP 32K ROM  
ZGR323LEH2832G 28-pin SSOP 32K ROM ZGR323LEP2032G 20-pin PDIP 32K ROM  
ZGR323LEP2832G 28-pin PDIP 32K ROM ZGR323LES2032G 20-pin SOIC 32K ROM  
Description  
32 KB Automotive Temperature: –40 °C to +125 °C  
Part Number Description Part Number  
ZGR323LAH4832G 48-pin SSOP 32K ROM ZGR323LAS2832G 28-pin SOIC 32K ROM  
ZGR323LAP4032G 40-pin PDIP 32K ROM ZGR323LAH2032G 20-pin SSOP 32K ROM  
ZGR323LAH2832G 28-pin SSOP 32K ROM ZGR323LAP2032G 20-pin PDIP 32K ROM  
ZGR323LAP2832G 28-pin PDIP 32K ROM ZGR323LAS2032G 20-pin SOIC 32K ROM  
Description  
PS023910-0408  
Ordering Information  
ZGR323L  
Product Specification  
90  
16 KB Standard Temperature: 0 °C to +70 °C  
Part Number Description  
ZGR323LSH4816G 48-pin SSOP 16 ROM  
ZGR323LSP4016G 40-pin PDIP 16K ROM  
16 KB Extended Temperature: –40 °C to +105 °C  
Part Number  
Description  
ZGR323LEH4816G 48-pin SSOP 16K ROM  
ZGR323LEP4016G 40-pin PDIP 16K ROM  
16 KB Automotive Temperature: –40 °C to +125 °C  
Part Number  
Description  
ZGR323LAH4816G 48-pin SSOP 16K ROM  
ZGR323LAP4016G 40-pin PDIP 16K ROM  
8 KB Standard Temperature: 0 °C to +70 °C  
Part Number  
Description  
ZGR323LSH4808G 48-pin SSOP 8K ROM  
ZGR323LSP4008G 40-pin PDIP 8K ROM  
8 KB Extended Temperature: –40 °C to +105 °C  
Part Number  
Description  
ZGR323LEH4808G 48-pin SSOP 8K ROM  
ZGR323LEP4008G 40-pin PDIP 8K ROM  
8 KB Automotive Temperature: –40 °C to +125 °C  
Part Number  
Description  
ZGR323LAH4808G 48-pin SSOP 8K ROM  
ZGR323LAP4008G 40-pin PDIP 8K ROM  
PS023910-0408  
Ordering Information  
ZGR323L  
Product Specification  
91  
4 KB Standard Temperature: 0 °C to +70 °C  
Part Number Description  
ZGR323LSH4804G 48-pin SSOP 4K ROM  
ZGR323LSP4004G 40-pin PDIP 4K ROM  
4 KB Extended Temperature: –40 °C to +105 °C  
Part Number  
Description  
ZGR323LEH4804G 48-pin SSOP 4K ROM  
ZGR323LEP4004G 40-pin PDIP 4K ROM  
4 KB Automotive Temperature: –40 °C to +125 °C  
Part Number  
Description  
ZGR323LAH4804G 48-pin SSOP 4K ROM  
ZGR323LAP4004G 40-pin PDIP 4K ROM  
Additional Components  
Part Number  
Description  
Part Number  
Description  
Note: Visit the Zilog® web site (www.zilog.com) for ordering information on additional components and devel-  
opment tools for the ZGR323L.  
For fast results, contact your local Zilog sales office for assistance in ordering the part(s)  
desired.  
PS023910-0408  
Ordering Information  
ZGR323L  
Product Specification  
92  
Part Number Description  
Zilog® part numbers consist of a number of components as shown below:  
ZG  
R
323L  
S
P
48 32  
G
Environmental Flow  
G = Lead Free (Green part)  
Memory Size  
32 = 32 KB  
16 = 16 KB  
8 = 8 KB  
4 = 4 KB  
Number of Pins in Package  
48 = 48 Pins  
40 = 40 Pins  
28 = 28 Pins  
20 = 20 Pins  
Package Type  
P = PDIP  
H = SSOP  
S = SOIC  
Temperature Range  
S = Standard 0 °C to 70 °C  
E = Extended -40 °C to 105 °C  
A = Automotive -40 °C to 125 °C  
Family Series  
323L = Family Series  
Memory Type  
R = ROM  
®
ZG = Zilog General-Purpose Family  
PS023910-0408  
Ordering Information  
ZGR323L  
Product Specification  
93  
Index  
counter/timer  
16-bit circuits 39  
8-bit circuits 35  
Numerics  
16-bit counter/timer circuits 39  
20-pin DIP package diagram 83  
20-pin SSOP package diagram 84  
28-pin DIP package diagram 86  
28-pin SOICpackage diagram 85  
28-pin SSOP package diagram 87  
40-pin DIP package diagram 87  
48-pin SSOP package diagram 88  
8-bit counter/timer circuits 35  
brown-out voltage/standby 57  
clock 46  
demodulation mode count capture flowchart 37  
demodulation mode flowchart 38  
EPROM selectable options 57  
glitch filter circuitry 33  
halt instruction 47  
input circuit 33  
interrupt block diagram 44  
interrupt types, sources and vectors 45  
oscillator configuration 46  
output circuit 42  
ping-pong mode 41  
port configuration register 48  
resets and WDT 56  
A
absolute maximum ratings 74  
AC  
characteristics 81  
timing diagram 81  
address spaces, basic 1  
architecture 1  
SCLK circuit 50  
stop instruction 47  
expanded register file 21  
stop mode recovery register 49  
stop mode recovery register 2 54  
stop mode recovery source 52  
T16 demodulation mode 40  
T16 transmit mode 39  
T16_OUT in modulo-N mode 40  
T16_OUT in single-pass mode 40  
T8 demodulation mode 36  
T8 transmit mode 33  
B
basic address spaces 1  
block diagram, ZLP32300 functional 3  
C
capacitance 75  
characteristics  
AC 81  
T8_OUT in modulo-N mode 36  
T8_OUT in single-pass mode 36  
transmit mode flowchart 34  
voltage detection and flags 58  
watchdog timer mode register 55  
watchdog timer time select 56  
CTR(D)01h T8 and T16 Common Functions 28  
DC 75  
clock 46  
comparator inputs/outputs 18  
configuration  
port 0 12  
port 1 13  
port 2 14  
port 3 15  
port 3 counter/timer 17  
D
DC characteristics 75  
PS023910-0408  
Index  
ZGR323L  
Product Specification  
94  
demodulation mode  
count capture flowchart 37  
flowchart 38  
T16 40  
T8 36  
description  
CTR0(D)00h register 26  
CTR2(D)02h register 30  
CTR3(D)03h register 32  
expanded register file 20  
expanded register file architecture 21  
HI16(D)09h register 25  
HI8(D)0Bh register 25  
L08(D)0Ah register 25  
L0I6(D)08h register 25  
program memory map 19  
RAM 19  
functional 19  
general 3  
pin 5  
E
register description 57  
register file 23  
register pointer 22  
EPROM  
selectable options 57  
register pointer detail 24  
SMR2(F)0D1h register 33  
stack 24  
TC16H(D)07h register 25  
TC16L(D)06h register 26  
TC8H(D)05h register 26  
TC8L(D)04h register 26  
expanded register file 20  
expanded register file architecture 21  
expanded register file control registers 63  
flag 72  
interrupt mask register 71  
interrupt priority register 70  
interrupt request register 71  
port 0 and 1 mode register 69  
port 2 configuration register 67  
port 3 mode register 68  
G
port configuration register 67  
register pointer 72  
glitch filter circuitry 33  
stack pointer high register 73  
stack pointer low register 73  
stop-mode recovery register 65  
stop-mode recovery register 2 66  
T16 control register 62  
H
halt instruction, counter/timer 47  
T8 and T16 common control functions register  
61  
T8/T16 control register 63  
TC8 control register 58  
I
input circuit 33  
interrupt block diagram, counter/timer 44  
interrupt types, sources and vectors 45  
watch-dog timer register 67  
L
F
low-voltage detection register 57  
features  
standby modes 2  
functional description  
counter/timer functional blocks 33  
CTR(D)01h register 28  
M
memory, program 19  
PS023910-0408  
Index  
ZGR323L  
Product Specification  
95  
modulo-N mode  
T16_OUT 40  
T8_OUT 36  
port 2 pin function 13  
port 3 configuration 15  
port 3 pin function 14  
port 3counter/timer configuration 17  
port configuration register 48  
power connections 1  
power supply 5  
O
oscillator configuration 46  
program memory 19  
map 19  
output circuit, counter/timer 42  
P
R
package information  
ratings, absolute maximum 74  
register 54  
20-pin DIP package diagram 83  
20-pin SSOP package diagram 84  
28-pin DIP package diagram 86  
28-pin SOIC package diagram 85  
28-pin SSOP package diagram 87  
40-pin DIP package diagram 87  
48-pin SSOP package diagram 88  
pin configuration  
CTR(D)01h 28  
CTR0(D)00h 26  
CTR2(D)02h 30  
CTR3(D)03h 32  
flag 72  
HI16(D)09h 25  
HI8(D)0Bh 25  
interrupt priority 70  
interrupt request 71  
interruptmask 71  
L016(D)08h 25  
L08(D)0Ah 25  
LVD(D)0Ch 57  
pointer 72  
port 0 and 1 69  
port 2 configuration 67  
port 3 mode 68  
20-pin DIP/SOIC/SSOP 5  
28-pin DIP/SOIC/SSOP 6  
40- and 48-pin 8  
40-pin DIP 7  
48-pin SSOP 8  
pin functions  
port 0 (P07 - P00) 11  
port 0 (P17 - P10) 12  
port 0 configuration 12  
port 1 configuration 13  
port 2 (P27 - P20) 13  
port configuration 48, 67  
SMR2(F)0Dh 33  
stack pointer high 73  
stack pointer low 73  
stop mode recovery 49  
stop mode recovery 2 54  
stop-mode recovery 65  
stop-mode recovery 2 66  
T16 control 62  
T8 and T16 common control functions 61  
T8/T16 control 63  
TC16H(D)07h 25  
TC16L(D)06h 26  
port 2 (P37 - P30) 14  
port 2 configuration 14  
port 3 configuration 15  
port 3 counter/timer configuration 17  
reset) 18  
XTAL1 (time-based input 10  
XTAL2 (time-based output) 10  
ping-pong mode 41  
port 0 configuration 12  
port 0 pin function 11  
port 1 configuration 13  
port 1 pin function 12  
port 2 configuration 14  
PS023910-0408  
Index  
ZGR323L  
Product Specification  
96  
TC8 control 58  
TC8H(D)05h 26  
TC8L(D)04h 26  
T16_Capture_HI 25  
T8 transmit mode 33  
T8_Capture_HI 25  
voltage detection 63  
watch-dog timer 67  
test conditions, standard 74  
test load diagram 75  
register description  
timing diagram, AC 81  
transmit mode flowchart 34  
Counter/Timer2 LS-Byte Hold 26  
Counter/Timer2 MS-Byte Hold 25  
Counter/Timer8 Control 26  
Counter/Timer8 High Hold 26  
Counter/Timer8 Low Hold 26  
CTR2 Counter/Timer 16 Control 30  
CTR3 T8/T16 Control 32  
Stop Mode Recovery2 33  
T16_Capture_LO 25  
T8 and T16 Common functions 28  
T8_Capture_HI 25  
V
VCC 5  
voltage  
brown-out/standby 57  
detection and flags 58  
voltage detection register 63  
T8_Capture_LO 25  
register file 23  
expanded 20  
register pointer 22  
W
watchdog timer  
mode registerwatch-dog timer mode register 55  
time select 56  
detail 24  
reset pin function 18  
resets and WDT 56  
X
XTAL1 5  
XTAL1 pin function 10  
XTAL2 5  
XTAL2 pin function 10  
S
SCLK circuit 50  
single-pass mode  
T16_OUT 40  
T8_OUT 36  
stack 24  
standard test conditions 74  
standby modes 2  
stop instruction, counter/timer 47  
stop mode recovery  
2 register 54  
source 52  
stop mode recovery 2 54  
stop mode recovery register 49  
T
T16 transmit mode 39  
PS023910-0408  
Index  
ZGR323L  
Product Specification  
97  
Customer Support  
For answers to technical questions about the product, documentation, or any other issues  
with Zilog’s offerings, please visit Zilog’s Knowledge Base at  
http://www.zilog.com/kb.  
For any comments, detail technical questions, or reporting problems, please visit Zilog’s  
Technical Support at http://support.zilog.com.  
PS023910-0408  
Customer Support  

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