AK4641EN中文资料_数据手册_规格书

ASAHI KASEI

[AK4641EN]

AK4641EN

CODEC with Bluetooth Interface

∆Σ

16-Bit

GENERAL DESCRIPTION

The AK4641EN is targeted at PDA and other low-power, small size applications. It features a 16bit Stereo

CODEC with a built-in Microphone-Amplifier and 16bit Mono CODEC for Bluetooth Interface. Input

circuits include Microphone-Amplifier and ALC (Auto Level Control) circuit. The AK4641EN is available in

a 36pin QFN, utilizing less board space than competitive offerings.

FEATURES

1. Recording Function of 16bit Stereo CODEC

• Mono Input

• 2 to 1 Selector (Internal and External MIC)

• 1^stMIC Amplifier: +20dB or 0dB

• 2^ndAmplifier with ALC: +27.5dB ∼ −8dB, 0.5dB Step

• ADC Performance: S/(N+D): 81dB, S/N: 86dB

• Sampling Rate: 7kHz ∼ 48kHz

• Audio Interface Format: I²S, 16bit MSB justified

2. Playback Function of 16bit Stereo CODEC

• Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)

• Digital Volume (0dB ∼ −127dB, 0.5dB Step, Mute)

• 5 Band Equalizer

• Stereo Line Output

- Performance: S/(N+D): 86dB, S/N: 90dB

• Mono Line Output

- Differential Output

- Performance: S/(N+D): 86dB, S/N: 93dB

• AUX Input

- Differential Input

- +24dB ∼ −21dB, 3dB step

• Sampling Rate: 7kHz ∼ 48kHz

• Audio Interface Format: I²S, 16bit MSB justified, 16bit LSB justified

3. 16bit Mono CODEC

• Analog Mix Path for Bluetooth Interface

• Sample Rate: 8kHz ∼ 16kHz

• Audio Interface Format: Short/Long Frame, I²S, 16bit MSB justified

4. Power Management

5. Master Clock: 1.792MHz ∼ 12.288MHz

6. Control mode: I²C Bus

7. Ta = −20 ∼ 85°C

8. Power Supply: 2.6V∼ 3.6V (typ. 3.3V)

9. Power Supply Current: 17mA

10. Package: 36pin QFN (0.5mm pitch)

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

Block Diagram

AVSS AVDD

DVSS DVDD

MICOUT

AIN

PMMIC

MPE

MPI

INT

MIC Power

Supply

TST2

TST1

MIC Power

Supply

PMADC

ALC1

(IPGA)

HPF

ADC

MCLK

PDN

MIC-AMP

0dB or 20dB

EXT

MDT

Stereo

CODEC

Audio

LRCK

BICK

SDTO

SDTI

0.075 x AVDD

ATT

PMMO

Interface

MOUT+

MOUT-

ATT

DSP

and

uP

PMDAC

PMLO

LOUT

ROUT

5Band DATT

DAC

EQ

SMUTE

PMMIX

SCL

SDA

PMMO2

Control

Register

MOUT2

PMAD2

BBICK

BSYNC

BSDTO

BSDTI

VCOC

PMAUX

ADC HPF

AUXIN+

Mono

Bluetooth

Module

Volume

CODEC

Audio

I/F

PMDA2

AUXIN-

DAC

VCOM

PLL

BVDD BVSS

Figure 1. Block Diagram

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2006/02

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ASAHI KASEI

[AK4641EN]

Ordering Guide

AK4641EN

−20 ∼ +85°C

36pin QFN (0.5mm pitch)

AKD4641EN

Evaluation board for AK4641EN

Pin Layout (36pin QFN)

MPE

ROUT

MOUT2

TST2

1

2

3

4

5

6

7

8

9

27

26

25

24

23

22

21

20

19

MPI

INT

VCOM

AVSS

AVDD

BVDD

BVSS

VCOC

BBICK

BSYNC

BSDTO

BSDTI

DVSS

Top View

DVDD

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2006/02

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ASAHI KASEI

No. Pin Name

[AK4641EN]

PIN/FUNCTION

I/O

O

I

Function

1

2

3

MPE

MPI

INT

MIC Power Supply Pin for External Microphone

MIC Power Supply Pin for Internal Microphone

Internal Microphone Input Pin (Mono Input)

Common Voltage Output Pin, 0.45*AVDD

Bias voltage of ADC inputs and DAC outputs.

Analog Ground Pin

4

VCOM

O

5

6

7

8

9

AVSS

AVDD

BVDD

BVSS

VCOC

-

O

Analog Power Supply Pin

Power Supply Pin for 16bit Mono CODEC of Bluetooth I/F

Ground Pin for 16bit Mono CODEC of Bluetooth I/F

PLL Loop Filter Pin for 16bit Mono CODEC of Bluetooth I/F

Power-Down Mode Pin

10 PDN

I

“H”: Power up, “L”: Power down reset and initializes the control register.

Test Pin. Connect to DVSS.

11 TST1

12 SCL

I

Control Data Clock Pin

13 SDA

I/O Control Data Input Pin

14 SDTI

15 SDTO

16 LRCK

17 BICK

18 MCLK

19 DVDD

20 DVSS

21 BSDTI

22 BSDTO

23 BSYNC

24 BBICK

25 TST2

26 MOUT2

27 ROUT

28 LOUT

I

O

I

-

I

O

I

Audio Serial Data Input Pin

Audio Serial Data Output Pin

Input/Output Channel Clock Pin

Audio Serial Data Clock Pin

External Master Clock Input Pin

Digital Power Supply Pin

Digital Ground Pin

Serial Data Input Pin for 16bit Mono CODEC of Bluetooth I/F

Serial Data Output Pin for 16bit Mono CODEC of Bluetooth I/F

Sync Signal Pin for 16bit Mono CODEC of Bluetooth I/F

Serial Data Clock Pin for 16bit Mono CODEC of Bluetooth I/F

Test Pin. Connect to AVSS.

Mono Line Output 2 Pin

Rch Stereo Line Output Pin

Lch Stereo Line Output Pin

Mono Line Negative Output Pin

I

O

I

29

30 MOUT+

31

MOUT−

Mono Line Positive Output Pin

Mono AUX Negative Input Pin

AUX IN−

32 AUX IN+

I

Mono AUX Positive Input Pin

33 AIN

I

Analog Input Pin

34 MICOUT

35 MDT

36 EXT

O

I

Microphone Analog Output Pin

Microphone Detect Pin (Internal pull down by 500kΩ)

External Microphone Input Pin (Mono Input)

Note: All input pins except analog input pins (INT, EXT, AIN, AUXIN+, AUXIN−, MDT) should not be left floating.

Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

Classification

Analog Input

Pin Name

Setting

These pins should be open.

INT, AUXIN+, AUXIN−, AIN, MDT, EXT

MPE, MPI, MOUT2, ROUT, LOUT, MOUT−, MOUT+,

MICOUT

Analog Output

Digital Input

BSDTI, BSYNC, BBICK

These pins should be connected to DVSS.

These pins should be open.

Digital Output BSDTO

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

ABSOLUTE MAXIMUM RATINGS

(AVSS, DVSS, BVSS =0V; Note 1)

Parameter

Power Supplies:

Symbol

AVDD

DVDD

BVDD

∆GND1

∆GND2

IIN

VINA

VIND

Ta

min

max

4.6

0.3

Units

V

mA

V

°C

Analog

Digital

16bit Mono CODEC

|AVSS – DVSS|

|AVSS – BVSS|

−0.3

-

−0.3

−20

−65

(Note 2)

0.3

±10

AVDD+0.3

DVDD+0.3

85

Input Current, Any Pin Except Supplies

Analog Input Voltage

Digital Input Voltage

Ambient Temperature (powered applied)

Storage Temperature

Tstg

150

Note 1. All voltages with respect to ground.

Note 2. AVSS, DVSS and BVSS must be connected to the same analog ground plane.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AVSS, DVSS, BVSS=0V; Note 1)

Parameter

Power Supplies

(Note 3)

Symbol

AVDD

DVDD

min

2.6

typ

3.3

0

max

3.6

Units

V

Analog

Digital

16bit Mono CODEC

Differences

BVDD

2.6

3.6

+0.1

+0.3

AVDD−BVDD

AVDD−DVDD

BVDD−DVDD

−0.1

−0.3

0

V

Note 1. All voltages with respect to ground.

Note 3. The power up sequence between AVDD, DVDD and BVDD is not critical.

* AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

ANALOG CHARACTERISTICS

(Ta=25°C; AVDD=DVDD=BVDD=3.3V; AVSS=DVSS=BVSS=0V; Signal Frequency=1kHz; 16bit Data;

Stereo CODEC: fs=44.1kHz, BICK=64fs; Measurement frequency=20Hz ∼ 20kHz;

Mono CODEC: Bfs=8kHz; BBICK=32Bfs; Measurement frequency=20Hz ∼ 3.4kHz; unless otherwise specified)

Min

typ

max

Units

Parameter

MIC Amplifier

Input Resistance

20

-

30

0

+20

40

-

kΩ

dB

MGAIN bit = “0”

MGAIN bit = “1”

Gain

MIC Power Supply

Output Voltage

Load Resistance

Load Capacitance

MIC Detection

(Note 4)

2.22

2

-

2.47

-

2.72

-

30

V

kΩ

pF

Comparator Voltage Level

Internal pull down Resistance

Input PGA Characteristics:

(Note 5)

0.165

250

-

0.257

750

V

kΩ

500

Input Resistance

Step Size

(Note 6)

5

0.1

-

10

0.5

+27.5

−8

15

0.9

-

kΩ

dB

Max (IPGA6-0 bits = “47H”)

Min (IPGA6-0 bits = “00H”)

Gain Control Range

-

ADC Analog Input Characteristics of Stereo CODEC: MIC Gain=+20dB, IPGA=0dB, ALC1=OFF, MIC → IPGA

→ ADC of Stereo CODEC

Resolution

-

0.168

71

78

-

0.198

81

86

16

0.228

-

Bits

Vpp

dB

Input Voltage (MIC Gain=+20dB, Note 7)

S/(N+D)

D-Range

(−1dBFS)

(−60dBFS, A-weighted)

MIC Gain=+20dB, A-weighted

MIC Gain=0dB, A-weighted

S/N

-

92

dB

DAC Characteristics of Stereo CODEC:

Resolution

-

16

Bits

Stereo Line Output Characteristics: R_L=10kΩ, DAC of Stereo CODEC → LOUT/ROUT pins

Output Voltage

S/(N+D)

S/N

Interchannel Isolation

Interchannel Gain Mismatch

Load Resistance

(Note 8)

(0dBFS)

(A-weighted)

1.78

76

82

-

10

-

1.98

86

90

100

0.1

-

2.18

-

0.5

-

Vpp

dBFS

dB

kΩ

pF

Load Capacitance

-

30

Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ).

Note 5. Comparator Voltage Level is proportional to AVDD voltage. Vout = 0.05 x AVDD (min), 0.078 x AVDD (max).

Note 6. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ.

Note 7. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD (typ).

Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

Units

Min

Typ

max

Parameter

Mono Line Output Characteristics: R_L=20kΩ, DAC of Stereo CODEC → MOUT+/MOUT− pins

Output Voltage

(Note 9)

-

3.56

-

76

-

83

2

20

-

0.305

3.96

74

86

77

93

-

Vpp

dBFS

dB

kΩ

MOGN bit = “1”, −17dB

MOGN bit = “0”, +6dB

MOGN bit = “1”, −17dB

MOGN bit = “0”, +6dB

MOGN bit = “1”, −17dB

MOGN bit = “0”, +6dB

MOGN bit = “1”, −17dB

MOGN bit = “0”, +6dB

4.36

-

30

S/(N+D) (0dBFS)

S/N (A-weighted)

Load Resistance

Load Capacitance

-

kΩ

pF

AUX Input: AUXIN+, AUXIN− pins: AUXSI bit = “0”

Maximum Input Voltage

Input Resistance

Step Size

(Note 10)

-

25

1

1.98

40

3

-

55

5

Vpp

kΩ

dB

Max (GN3-0 bits = “FH”)

Min (GN3-0 bits = “0H”)

-

+24

−21

-

dB

Gain Control Range

Mono Output: R_L=10kΩ, DAC of Stereo CODEC → MIX → MOUT2 pin

Output Voltage

S/(N+D)

S/N

Load Resistance

Load Capacitance (Note 12)

(Note 11)

(0dBFS)

(A-weighted)

1.78

76

83

10

-

1.98

86

93

-

2.18

-

30

Vpp

dB

kΩ

pF

-

16bit Mono ADC Analog Input Characteristics: AUXIN pin → MIX → ADC of Mono CODEC: AUX Volume = 0dB

Resolution

Input Voltage (Note 13)

S/(N+D)

S/N

-

16

2.28

-

Bits

Vpp

dB

1.68

65

79

1.98

75

89

(−1dBFS)

dB

16bit Mono DAC Analog Output Characteristics: DAC of Mono CODEC → MOUT+/− pins: MOGN = +6dB

Resolution

Output Voltage (Note 14)

S/(N+D)

-

16

4.36

-

Bits

Vpp

dB

3.56

68

82

3.96

78

92

S/N

dB

Power Supplies

Power Up (PDN pin = “H”)

AVDD+DVDD+ BVDD

Power Down (PDN pin = “L”) (Note 15)

AVDD+DVDD+BVDD

-

17

-

27

mA

100

µA

Note 9. Output voltage is proportional to AVDD voltage.

Vout = 1.2 x AVDD (typ) @MOGN bit = “0”, 0.092 x AVDD (typ) @MOGN bit = “1” at differential Output.

Note 10. Maximum Input Voltage is proportional to AVDD voltage.

Vin = (AUXIN+) − (AUXIN−) = 0.6 x AVDD (typ) at AUXSI bit = “0”,

Vin = AUXIN+ = 0.6 x AVDD (typ) at AUXSI bit = “1”.

Note 11. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).

Note 12. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and

capacitive load.

Note 13. Input voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD (typ).

Note 14. Output Voltage is proportional to AVDD voltage. Vout = 0.6 x AVDD (typ).

Note 15. All digital input pins are fixed to DVSS. When the voltage difference among DVDD, BVDD and AVDD is

larger than 0.3V, the power supply current at power down mode increases.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

FILTER CHARACTERISTICS (Stereo CODEC)

(Ta=−20 ∼ 85°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V; fs=44.1kHz; DEM=OFF)

Parameter

Symbol

min

typ

max

Units

ADC Digital Filter (Decimation LPF):

Passband

(Note 16)

PB

0

-

17.4

-

kHz

dB

1/fs

µs

±0.1dB

−1.0dB

−3.0dB

20.0

21.1

-

Stopband

Passband Ripple

Stopband Attenuation

Group Delay

Group Delay Distortion

ADC Digital Filter (HPF):

Frequency Response

(Note 16)

SB

PR

SA

GD

∆GD

25.7

-

68

-

±0.1

-

(Note 17)

17.0

0

-

FR

PB

-

3.4

10

22

-

Hz

−3.0dB

−0.5dB

−0.1dB

DAC Digital Filter:

Passband

(Note 16)

0

-

19.6

-

±0.01

-

kHz

±0.1dB

−0.7dB

−6.0dB

20.0

22.05

-

25.2

-

59

-

Stopband

Passband Ripple

Stopband Attenuation

Group Delay

SB

PR

SA

GD

kHz

dB

(Note 17)

17.9

1/fs

DAC Digital Filter + SCF:

FR

-

dB

Frequency Response: 0 ∼ 20.0kHz

±1.0

Note 16. The passband and stopband frequencies scale with fs (system sampling rate).

For example, ADC is PB=0.454*fs (@-1.0dB), DAC is PB=0.454*fs (@-0.01dB).

Note 17. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the

16bit data of both channels from the input register to the output register of the ADC. This time includes the group

delay of the HPF. For the DAC, this time is from setting the 16bit data of both channels from the input register to

the output of analog signal.

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

FILTER CHARACTERISTICS (16bit Mono CODEC)

(Ta=−20 ∼ 85°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V; Bfs=8kHz)

Parameter

Symbol

min

typ

max

Units

ADC Digital Filter (Decimation LPF):

Passband

(Note 16)

PB

0

-

4.7

-

3.6

3.8

-

3.1

-

kHz

dB

±0.1dB

−1.0dB

−3.0dB

Stopband

Passband Ripple

SB

PR

-

±0.1

Stopband Attenuation

SA

GD

∆GD

68

-

dB

1/Bfs

µs

Group Delay

(Note 17)

17.0

0

Group Delay Distortion

ADC Digital Filter (HPF):

Frequency Response

(Note 16)

FR

PB

-

0.62

1.81

3.99

-

Hz

−3.0dB

−0.5dB

−0.1dB

DAC Digital Filter:

Passband

(Note 16)

0

-

4.6

-

59

-

3.6

4.0

-

3.6

-

±0.01

-

kHz

±0.1dB

−0.7dB

−6.0dB

Stopband

Passband Ripple

Stopband Attenuation

Group Delay

SB

PR

SA

GD

kHz

dB

(Note 17)

15.8

1/Bfs

DAC Digital Filter + SCF:

FR

-

dB

Frequency Response: 0 ∼ 20.0kHz

±1.0

Note 16. The passband and stopband frequencies scale with fs (system sampling rate).

For example, ADC is PB=0.454*Bfs (@-1.0dB), DAC is PB=0.454*Bfs (@-0.01dB).

Note 17. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the

16bit data of both channels from the input register to the output register of the ADC. This time includes the group

delay of the HPF. For the DAC, this time is from setting the 16bit data of both channels from the input register to

the output of analog signal.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

DC CHARACTERISTICS

(Ta=−20 ∼ 85°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V)

Parameter

Symbol

min

typ

Max

Units

High-Level Input Voltage

Low-Level Input Voltage

Input Voltage at AC Coupling

High-Level Output Voltage

Low-Level Output Voltage

VIH

VIL

VAC

70%DVDD

-

50%DVDD

-

V

30%DVDD

V

(Note 18)

(Iout=−200µA)

-

VOH

DVDD−0.2

VOL

Iin

-

0.2

0.4

±10

V

µA

(Except SDA pin: Iout=200µA)

(SDA pin: Iout=3mA)

Input Leakage Current

Note 18. The external clock is input to MCLK pin via AC coupled capacitor.

SWITCHING CHARACTERISTICS

(Ta=−20 ∼ 85°C; AVDD, DVDD, BVDD=2.6 ∼ 3.6V; C_L=20pF)

Parameter

Symbol

min

typ

max

Units

16bit Stereo CODEC Interface Timing:

Master Clock Timing (MCLK pin)

Frequency

fCLK

tCLKL

tCLKH

tACW

1.792

-

12.288

MHz

ns

Pulse Width Low

Pulse Width High

AC Pulse Width (Note 19)

0.3/fCLK

0.4/fCLK

-

ns

LRCK Timing

Frequency

Duty Cycle

fs

Duty

7

45

-

48

55

kHz

%

Audio Interface Timing

BICK Period

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑” (Note 20)

BICK “↑” to LRCK Edge (Note 20)

LRCK to SDTO (MSB) (Except I²S mode)

BICK “↓” to SDTO

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRS

tBSD

tSDH

tSDS

312.5

130

50

-

50

-

80

-

ns

SDTI Hold Time

SDTI Setup Time

-

Note 19. Refer to Figure 3.

Note 20. BICK rising edge must not occur at the same time as LRCK edge.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

Parameter

Symbol

min

typ

max

Units

16bit Mono CODEC Interface Timing:

SYNC Timing

Frequency (PLL Lock Range)

Serial Interface Timing at Short/long Frame Sync

BBICK Frequency

BBICK Period

BBICK duty cycle

BBICK Pulse Width Low

Pulse Width High

BSYNC Edge to BBICK “↓ ”

BBICK “↓ ” to BSYNC Edge

BSYNC to BSDTO (MSB) (Except Short Frame)

BBICK “↑ ” to BSDTO

BSDTI Hold Time

Bfs

8

-

16

kHz

fBBCK

tBBCK

tBDUT

tBBCKL

tBBCKH

tBSYB

tBBSY

tBSYD

tBBSD

tBSDH

tBSDS

tBBSL

tBBSH

128

488

2048

kHz

ns

%

50

200

50

ns

50

80

50

3300

440

BSDTI Setup Time

BSYNC Pulse Width Low

Pulse Width High

Serial Interface Timing at MSB justified and I²S

BBICK Frequency

fBBCK

tBBCK

tBDUT

256

488

2048

kHz

ns

%

BBICK Period

BBICK duty cycle

BBICK Pulse Width Low

50

tBBCKL

tBBCKH

tBSYB2

tBBSY2

tBSYD2

tBBSD2

tBSDH2

BDuty2

200

50

ns

%

Pulse Width High

BSYNC Edge to BBICK “↑ ”

BBICK “↑ ” to BSYNC Edge

BSYNC to BSDTO (MSB) (Except I²S mode)

BBICK “↓ ” to BSDTO

BSDTI Hold Time

50

80

50

45

BSDTI Setup Time

BSYNC Duty Cycle

55

Control Interface Timing (I²C Bus mode):

SCL Clock Frequency

fSCL

tBUF

-

400

-

kHz

µs

ns

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low Time

1.3

0.6

1.3

0.6

0

0.1

-

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

Clock High Time

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling (Note 21)

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

0.3

-

tF

TSU:STO

0.6

0

Pulse Width of Spike Noise Suppressed by Input Filter

tSP

50

Reset Timing

PDN Pulse Width

PMADC “↑” to SDTO valid

PMAD2 “↑” to BSDTO valid

(Note 22)

(Note 23)

(Note 24)

tPD

tPDV

tBPDV

150

ns

1/fs

1/Bfs

2081

1057

Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL.

Note 22. The AK4641EN can be reset by the PDN pin = “L”.

Note 23. This is the count of LRCK “↑” from the PMADC bit = “1”.

Note 24. This is the count of BSYNC “↑” from the PMAD2 bit = “1”.

Purchase of Asahi Kasei Microsystems Co., Ltd I²C components conveys a license under the Philips

I²C patent to use the components in the I²C system, provided the system conform to the I²C

specifications defined by Philips.

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

Timing Diagram

1/fCLK

VIH

VIL

MCLK

tCLKH

tCLKL

1/fs

VIH

LRCK

BICK

VIL

tBCK

VIH

VIL

tBCKH

tBCKL

Figure 2. Clock Timing of Stereo CODEC

1/fCLK

tACW

1000pF

MCLK Input

Monitoring Point

100kΩ

VAC

DVSS

Note. This circuit shows how to monitor MCLK AC Coupling Timing. This circuit is not used in actual system.

Figure 3. MCLK AC Coupling Timing

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ASAHI KASEI

[AK4641EN]

VIH

VIL

LRCK

tBLR

tLRB

VIH

VIL

BICK

SDTO

SDTI

tLRS

tBSD

tSDH

50%DVDD

tSDS

VIH

VIL

Figure 4. Audio Interface Timing of Stereo CODEC

1/Bfs

VIH

VIL

BSYNC

tBBSL

tBBSH

tBBCK

VIH

VIL

BBICK

tBBCKH

tBBCKL

Figure 5. Clock Timing of 16bit Mono CODEC

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

VIH

VIL

BSYNC

BBICK

tBSYB

tBBSY

VIH

VIL

tBSYD

tBBSD

BSDTO

50%DVDD

tBSDS

tBSDH

VIH

VIL

BSDTI

Figure 6. 16bit Mono CODEC Interface Timing at short and long frame sync

VIH

BSYNC

BBICK

VIL

tBBSY2

tBSYD2

tBSYB2

VIH

VIL

tBBSD2

BSDTO

50%DVDD

tBSDS2

tBSDH2

VIH

VIL

BSDTI

Figure 7. 16bit Mono CODEC Interface Timing at MSB justified and I²S

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

VIH

SDA

VIL

tBUF

tLOW

tHIGH

tR

tF

tSP

VIH

VIL

SCL

tHD:STA

Start

tHD:DAT

tSU:DAT

tSU:STA

Start

tSU:STO

Stop

Figure 8. I²C Bus Mode Timing

PMADC bit

SDTO

tPDV

50%DVDD

Figure 9. Power Down & Reset Timing 1

PMAD2 bit

BSDTO

tBPDV

50%DVDD

Figure 10. Power Down & Reset Timing 2

tPD

PDN

VIL

Figure 11. Power Down & Reset Timing 3

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

OPERATION OVERVIEW

System Clock Input

The AK4641EN requires a master clock (MCLK). This master clock is input to the AK4641EN by inputting an external

CMOS-level clock to the MCLK pin or by inputting an external clock that is greater than 50% of the DVDD level to the

MCLK pin through a capacitor. MCKPD and MCKAC bits should be set as shown in Table 1. ADC and DAC of 16bit

Stereo CODEC are powered-down at MCKPD bit = “1”.

Master Clock

Status

MCKAC bit

MCKPD bit

External Clock Direct Input (Figure 12)

Clock is input to MCLK pin.

Clock is not input to MCLK pin.

Clock is input to MCLK pin.

Clock is not input to MCLK pin.

0

1

0

1

0

1

AC Coupling Input

(Figure 13)

Table 1. MCKPD and MCKAC bits Setting for Master Clock Status

(1) External Clock Direct Input

MCLK

MCKAC bit = "0"

MCKPD bit = "0"

External

Clock

AK4641

Figure 12. External Master Clock Input Block

(2) AC Coupling Input

0.1uF

MCLK

MCKAC bit = "1"

MCKPD bit = "0"

External

Clock

AK4641

Figure 13. External Clock mode (Input: ≥ 50%DVDD)

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ASAHI KASEI

[AK4641EN]

The clock required to operate are MCLK, LRCK (fs) and BICK (≥ 32fs). Then the master clock (MCLK) should be

synchronized with LRCK. The phase between these clocks does not matter.

The S/N of the DAC of Stereo CODEC at low sampling frequencies is worse than at high sampling frequencies due to

out-of-band noise. The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the

DAC output of Stereo CODEC through Headphone amp at fs=8kHz is shown in Table 3.

Sampling Frequency

(fs)

MCLK

MCK1

MCK0

0

1

0

1

0

1

256fs

512fs

1024fs

N/A

Default

7kHz∼48kHz

7kHz∼24kHz

7kHz∼12kHz

-

Table 2. Select Master Clock Frequency

MCLK

256fs

512fs

S/N (fs=8kHz, A-weighted)

82dB

90dB

1024fs

Table 3. Relationship between MCLK and S/N of Line Out

When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4641EN

may occur pop noise.

All external clocks (MCLK, BICK and LRCK) should always be present when either ADC or DAC of Stereo CODEC is

power-up. If these clocks are not provided, the AK4641EN may draw excess current and it is not possible to operate

properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4641EN should

be in the power-down mode.

Power up

Input

Power down

Fixed to “L” or “H” externally

BICK pin

LRCK pin

Table 4. Clock Operation

System Reset

Upon power-up, reset the AK4641EN by bringing the PDN pin = “L”. This ensures that all internal registers are reset to

their initial values.

The ADC of Stereo CODEC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The

initialization cycle time is 2081/fs, or 47.2ms@fs=44.1kHz. During the initialization cycle, the ADC digital data output of

Stereo CODEC is forced to a 2's compliment, “0”. The ADC output of Stereo CODEC reflects the analog input signal

after the initialization cycle is complete. The DAC of Stereo CODEC does not require an initialization cycle.

The ADC of Mono CODEC enters an initialization cycle that starts when the PMAD2 bit is changed from “0” to “1”. The

initialization cycle time is 1057/Bfs, or 132ms@Bfs=8kHz. During the initialization cycle, the ADC digital data output of

Mono CODEC is forced to a 2's compliment, “0”. The ADC output of Mono CODEC reflects the analog input signal after

the initialization cycle is complete. The DAC of Mono CODEC does not require an initialization cycle.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

Audio Interface Format of Stereo CODEC

Three types of data formats are available and are selected by setting the DIF1-0 bits. In all modes, the serial data is MSB

first, 2’s complement format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising

edge. LRCK and BICK must be input to the AK4641EN in slave mode. If 16bit data that ADC of Stereo CODEC outputs

is converted to 8bit data by removing LSB 8bit, “−1” at 16bit data is converted to “−1” at 8bit data. And when the DAC of

Stereo CODEC playbacks this 8bit data, “−1” at 8bit data will be converted to “−256” at 16bit data and this is a large

offset. This offset can be removed by adding the offset of “128” to 16bit data before converting to 8bit data.

Mode

DIF1

DIF0

SDTO (ADC)

MSB justified

I²S

SDTI (DAC)

LSB justified

MSB justified

I²S

BICK

Figure

0

1

2

3

0

1

0

1

0

1

Figure 14

Figure 15

Figure 16 Default

-

≥ 32fs

N/A

Table 5. Audio Interface Format of Stereo CODEC

LRCK

0

1

2

3

9 10 11 12 13 14 15 0

1

2

3

9 10 11 12 13 14 15 0 1

BICK(32fs)

SDTO(o)

15 14 13

7

6

5

4

3

2

1

0

15

0 15 14 13

7

6

5

4

3

2

1

0 15

SDTI(i)

0

1

2

3

15 16 17 18

31 0

1

2

3

15 16 17 18

31 0

1

BICK(64fs)

SDTO(o)

15 14 13

1

0

15

Don't Care

15:MSB, 0:LSB

15 14

1

0

Don't Care

15 14

2 1 0

SDTI(i)

Lch Data

Rch Data

Figure 14. Mode 0 Timing

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2006/02

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ASAHI KASEI

[AK4641EN]

LRCK

0

1

2

3

9 10 11 12 13 14 15 0

1

2

3

9 10 11 12 13 14 15 0

1

BICK(32fs)

15 14 13

7

6

5

4

3

2

1

0

15

SDTO(o)

SDTI(i)

0 15 14 13

7

6

5

4

3

2

1

0 15

0

1

2

3

15 16 17 18

31 0

1

2

3

15 16 17 18

31 0

1

BICK(64fs)

SDTO(o)

15 14 13

1

0

15

15 14 13

1

Don't Care

15 14 13

1

0

Don't Care 15

SDTI(i)

15:MSB, 0:LSB

Lch Data

Rch Data

Figure 15. Mode 1 Timing

LRCK

0

1

2

3

9 10 11 12 13 14 15 0

1

2

3

9 10 11 12 13 14 15 0 1

BICK(32fs)

SDTO(o)

15 14

8

7

6

5

4

3

2

1

0

0 15 14

8 7 6 5 4 3 2 1 0

SDTI(i)

0

1

2

3

15 16 17 18

31 0

1

2

3

15 16 17 18

31 0 1

BICK(64fs)

SDTO(o)

15 14

2

1

0

Don't Care

15 14

2

1

0

Don't Care

SDTI(i)

15:MSB, 0:LSB

Lch Data

Rch Data

Figure 16. Mode 2 Timing

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ASAHI KASEI

[AK4641EN]

Audio Interface Format of Mono CODEC

Four types of data formats are available for 16bit Mono CODEC and are selected by setting the BTFMT1-0 bits. In all

modes, the serial data is MSB first, 2’s complement format. In short frame sync and long frame sync modes, the BSDTO

is clocked out on the rising edge of BBICK and the BSDTI is latched on the falling edge. In MSB justified and I²S modes,

the BSDTO is clocked out on the falling edge of BBICK and the BSDTI is latched on the rising edge. BSYNC and

BBICK must be input to the AK4641EN.

Mode

Short Frame Sync

Long Frame Sync

MSB justified

I²S

BTFMT1-0

BBICK

≥ 16Bfs

≥ 32Bfs

Figure

Figure 17 Default

Figure 18

Figure 19

Figure 20

00

01

10

11

Table 6. Audio Interface Format for 16bit Mono CODEC

(1) Short Frame Sync

1/Bfs

BSYNC

BBICK

BSDTO

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15 D14

BSDTI

Don’t Care

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 17. Timing of Short Frame Sync

(2) Long Frame Sync

1/Bfs

BSYNC

BBICK

BSDTO

BSDTI

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

D15 D14 D13

Don’t Care

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 18. Timing of Long Frame Sync

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ASAHI KASEI

[AK4641EN]

(3) MSB justified

BSYNC

0

1

2

3

9 10 11 12 13 14 15 0

1

2

3

9 10 11 12 13 14 15 0

1

BBICK

(32Bfs)

15 14 13

7

6

5

4

3

2

1

0

15

BSDTO(o)

Don't Care

15 16 17 18

BSDTI(i)

0

1

2

3

15 16 17 18

31 0

1

2

3

31 0 1

BBICK

(64Bfs)

15 14 13

1

0

15

BSDTO(o)

15 14 13

1

Don't Care

15

BSDTI(i)

15:MSB, 0:LSB

Figure 19. Timing of MSB justified

(4) I²S

BSYNC

0

1

2

3

9 10 11 12 13 14 15 0

1

2

3

9 10 11 12 13 14 15 0 1

BBICK

(32Bfs)

15 14

8

7

6

5

4

3

2

1

0

BSDTO(o)

BSDTI(i)

Don't Care

15 16 17 18 31 0 1

0

1

2

3

15 16 17 18

31 0

1

2

3

BBICK

(64Bfs)

15 14

2

1

0

BSDTO(o)

BSDTI(i)

Don't Care

15:MSB, 0:LSB

Figure 20. Timing of I²S

Digital High Pass Filter

The ADC of Stereo CODEC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is

3.4Hz (@fs=44.1kHz) and scales with sampling rate (fs).

The ADC of Mono CODEC also has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF

is 0.62Hz (@Bfs=8kHz) and scales with sampling rate (Bfs).

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

MIC Input

MICL bit

MICM bit

Stereo Mixer

Mono Mixer

ATT

DAC of

Mono CODEC

ATT

MICAD bit

IPGA with ALC

ADC of Stereo

CODEC

µP

Mic In

0dB/+20dB

AUXAD bit

DAC2 bit = “0”: Mic Input Signal

“1”: DAC Signal

AUX IN

Figure 21. Microphone Input

The AK4641EN has the following functions for Mic Input.

(1) 1^stMIC Amplifier of 20dB gain that can be selected ON/OFF by “MGAIN” bit.

(2) 2^ndAmplifier that has PGA with ALC. This volume is controlled by “IPGA6-0” bit as Table 7.

While ALC is working, Master Clock must be present.

When Master Clock is not provided or PMMIC bit = “0”, it is invalid to write to “IPGA6-0”.

(3) Attenuator for stereo mixer. This volume is controlled by “ATTS2-0” bit as Table 8.

(4) Attenuator for mono mixer. This attenuator level is 4dB and this ON/OFF is controlled by “ATTM” bit.

IPGA6-0

47H

46H

45H

:

GAIN (dB)

+27.5

+27.0

+26.5

:

STEP

36H

:

+19.0

:

10H

:

+0.0

:

Default

0.5dB

06H

05H

04H

03H

02H

01H

00H

−5.0

−5.5

−6.0

−6.5

−7.0

−7.5

−8.0

Table 7. Microphone Input Gain Setting

ATTS2-0

Attenuation

−6dB

7H

6H

5H

4H

3H

2H

1H

0H

−9dB

Default

−12dB

−15dB

−18dB

−21dB

−24dB

−27dB

Table 8. Attenuator Table

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

MIC Gain Amplifier

The AK4641EN has a Gain Amplifier for Microphone input. This gain is 0dB or +20dB, selected by the MGAIN bit. The

typical input impedance is 30kΩ.

MGAIN bit

Input Gain

0dB

+20dB

0

1

Default

Table 9. Input Gain

MIC Power

The MPI and MPE pins supply power for the Microphone. These output voltages are 0.75 x AVDD (typ) and the load

resistance is 2kΩ(min). No capacitor must be connected directly to MPI and MPE pins. MPWRI/MPWRE bit can control

output from MPI and MPE pin.

MPWRE bit

AK4641

MPE

MPI

INT

MPWRI bit

EXT

MDT

G

M

R

L

Headset

DTMIC bit

or

500k

0.075 x AVDD

G

Headphone

Figure 22. Microphone Power Supply and Mic Detection

MIC Detection Function

The AK4641EN includes the detection function of microphone. The external circuit is showed in Figure 22.

The followings show the example of external microphone detection sequence:

(1) MPWRE bit = “1”.

(2) MPE drives external microphone.

(3) DTMIC bit is set as Table 10. In case of Headset, the input voltage of MDT pin is higher than 0.078 x AVDD because

of the relationship between the bias resistance at MPE pin (typ. 2.2kΩ) and the microphone impedance. In case of

Headphone, the input voltage of MDT pin is 0V because the pin of headphone jack connected to MDT pin is assigned

as ground.

Input Level of DTM

DTMIC

Result

1

0

Mic (Headset)

No Mic (Headphone)

≥ 0.078 x AVDD

< 0.050 x AVDD

Table 10. Microphone Detection Result

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

Manual Mode

The AK4641EN becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below.

1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc)

2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed.

For example; When the change of the sampling frequency.

3. When IPGA is used as a manual volume.

MIC-ALC Operation

The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”.

[1] ALC1 Limiter Operation

When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value

is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically.

When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done

continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into “0” after

completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH.

When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation

function so that the IPGA value is attenuated at the zero-detect points of the waveform.

[2] ALC1 Recovery Operation

The ALC1 recovery refers to the amount of time that the AK4641EN will allow a signal to exceed a predetermined

limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the

wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the “ALC1 Recovery

Waiting Counter Reset Level”, the ALC1 recovery operation starts. The IPGA value increases automatically during this

operation up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0

bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next

recovery operation starts.

During the ALC1 recovery operation, when input signal level exceeds the ALC1 limiter detection level (LMTH), the

ALC1 recovery operation changes immediately into an ALC1 limiter operation.

In the case of “(Recovery waiting counter reset level) ≤ IPGA Output Level < Limiter detection level” during the ALC1

recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of “(Recovery waiting

counter reset level) > IPGA Output Level”, the wait timer for the ALC1 recovery operation starts.

The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation

becomes faster than a normal recovery operation.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

[3] Example of ALC1 Operation

Table 11 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB.

fs=8kHz

fs=16kHz

fs=44.1kHz

Register Name Comment

Data Operation Data Operation Data Operation

LMTH

LTM1-0

ZELM

Limiter detection Level

1

00

0

1

00

0

1

00

0

−4dBFS

Don’t use

Enable

−4dBFS

Don’t use

Enable

−4dBFS

Don’t use

Enable

Limiter operation period at ZELM = 1

Limiter zero crossing detection

Zero crossing timeout period

Recovery waiting period

ZTM1-0

00

16ms

01

16ms

10

11.6ms

WTM1-0

*WTM1-0 bits should be the same data 00

as ZTM1-0 bits

16ms

01

16ms

10

11.6ms

REF6-0

IPGA6-0

LMAT1-0

RATT

Maximum gain at recovery operation

Gain of IPGA at ALC1 operation Start 10H

Limiter ATT Step

Recovery GAIN Step

ALC1 Enable bit

47H

+27.5dB

0dB

1 step

Enable

47H

10H

00

0

+27.5dB

0dB

1 step

Enable

47H

10H

00

0

+27.5dB

0dB

1 step

Enable

00

0

1

ALC1

1

Table 11. Example of the ALC1 setting

The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1

operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.

• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits

IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and

ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.

Example:

Limiter = Zero crossing Enable

Recovery Cycle = 16ms @ fs= 8kHz

Limiter and Recovery Step = 1

Maximum Gain = +27.5dB

Manual Mode

Limiter Detection Level = −4dBFS

WR (ZTM1-0, WTM1-0, LTM1-0)

WR (REF6-0)

(1) Addr=08H, Data=00H

(2) Addr=0AH, Data=47H

(3) Addr=0BH, Data=10H

(4) Addr=09H, Data=21H

* The value of IPGA should be

the same or smaller than REF’s

WR (IPGA6-0)

WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)

* ALC1 bit must be set to “1” at more than zero cross time out period

after the value of IPGA is set (see figure 22).

ALC1 Operation

Note : WR : Write

Figure 23. Registers set-up sequence at ALC1 operation

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

[Setting timing of IPGA and ALC1 bits]

t > zero cross time out period

ZTM1-0 bits

XXH

00H

XXH

BH

IPGA6-0 bits

AH

BH

IPGA

AH

ALC1 bit

(1) (2)

(3) (4)

(5)

Figure 24. Setting timing of IPGA and ALC1 bits

(1) Set the zero cross time out period of IPGA as 128/fs: ZTM1-0 bits = “00”. (Note)

(2) Set the IPGA value of ALC1 operation start by IPGA6-0 bits.

(3) The value of IPGA6-0 bits is reflected to actual gain at zero crossing or zero cross time out.

(4) Set the zero cross time out period of ALC1 operation by ZTM1-0 bits after the zero cross time out period set by (1).

(5) Set ALC1 bit to “1”.

(Note) If ZTM1-0 bits are set to the value except for “00”, ALC1 bit must be set to “1” after this zero cross time out

period.

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ASAHI KASEI

[AK4641EN]

DAC of Stereo CODEC

DACL bit

DACM bit

Stereo Mixer

5 Band

DAC of Stereo

CODEC

DEM

SMUTE

DATT

Mono Mixer

Equalizer

Figure 25. DAC block diagram of Stereo CODEC

The AK4641EN has the following functions for DAC of Stereo CODEC.

(1) 5 Band Equalizer

(2) Soft mute

(3) Digital Attenuator

(4) De-emphasis Filter (32kHz, 44.1kHz and 48kHz)

De-emphasis Filter

The AK4641EN includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the

de-emphasis filter.

DEM1

DEM0

Mode

44.1kHz

OFF

48kHz

32kHz

0

1

0

1

0

1

Default

Table 12. De-emphasis Control

Digital Attenuator

The AK4641EN has a channel-independent digital attenuator (256levels, 0.5dB step, Mute). The ATTL/R7-0 bits set the

attenuation level of each channel (Table 13). When the DATTC bit = “1”, the ATTL7-0 bits control both Lch and Rch

attenuation levels. When the DATTC bit = “0”, the ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level.

This attenuator has a soft transition function. It takes around 1061/fs (24ms@44.1kHz) at TM bit = “0” and 256/fs

(5.8ms@44.1kHz) at TM bit = “1” from 00H to FFH.

ATTL/R7-0

Attenuation

0dB

−0.5dB

−1.0dB

−1.5dB

:

00H

01H

02H

03H

:

Default

:

FDH

FEH

FFH

−126.5dB

−127.0dB

MUTE (−∞)

Table 13. DATT Code Table

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

5 Band Equalizer

The AK4641EN has 5 Band Equalizer before DAC of Stereo CODEC as shown in Figure 25.

The center frequencies and cut/boost amount are the followings.

• Center frequency: 100Hz, 250Hz, 1kHz, 3.5kHz, 10kHz (Note 25, Note 26)

• Cut/Boost amount: Minimum –10.5dB, Maximum +12dB, Step 1.5dB

Note 25: These are the frequencies when the sampling frequency is 44.1kHz. These frequencies are proportional to the

sampling frequency.

Note 26: 100Hz is not center frequency but the frequency component lower than 100Hz is controlled.

Note 27: 10kHz is not center frequency but the frequency component higher than 10kHz is controlled.

EQ5 bit controls ON/OFF of this Equalizer and these Boost amount are set by EQx3-0 bit as shown in Table 14.

EQA3-0: Select the boost level of 100Hz

EQB3-0: Select the boost level of 250Hz

EQC3-0: Select the boost level of 1kHz

EQD3-0: Select the boost level of 3.5kHz

EQE3-0: Select the boost level of 10kHz

EQx3-0

0H

1H

2H

3H

:

Boost amount

+12.0dB

+10.5dB

+9.0dB

+7.5dB

:

8H

:

0dB

:

Default

DH

EH

FH

−7.5dB

−9.0dB

−10.5dB

Table 14. Boost amount of 5 Band Equalizer

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

Soft Mute

Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated

by −∞ (“0”) during the cycle set by the TM bit. When the SMUTE bit is returned to “0”, the mute is cancelled and the

output attenuation gradually changes to the digital attenuator level of ATTL/R7-0 bits during the cycle set by the TM bit.

If the soft mute is cancelled within the cycle set by the TM bit after starting the operation, the attenuation is discontinued

and returned to the digital attenuator level. The soft mute is effective for changing the signal source without stopping the

signal transmission.

Table 15 shows the Soft Mute Time when the digital attenuator level is 0dB (ATTL/R7-0 bits = “0”). As the digital

attenuator level is less than 0dB, the Soft Mute Time becomes shorter.

TM

0

1

Cycle

1061/fs

256/fs

Default

Table 15. Soft Mute Time Setting

SMUTE bit

ATTL/R7-0 bits

Attenuation

TM bit

(1)

TM bit

(3)

−∞

GD

(2)

Analog Output

Figure 26. Soft Mute Function

NOTE:

(1) The output signal is attenuated until −∞ (“0”) by the cycle set by the TM bit.

(2) Analog output corresponding to digital input has the group delay (GD).

(3) If the soft mute is cancelled within the cycle of setting the TM bit, the attenuation is discounted and returned to

0dB(the set value).

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

AUX Input

GN3-0 bits

Volume

AUXL bit

AUXIN+

Stereo Mixer

AUXIN−

Mixer for ADC

of Stereo CODEC

AUXAD bit

Figure 27. AUX Input

AUX input is differential input at AUXSI bit = “0” and single end input at AUXSI bit = “1”. AUXIN+ pin should be used

at single end input (AUXSI bit = “1”). The AK4641EN has a volume for AUX Input. This Volume is controlled by

GN3-0 bits as shown in Table 16. The switching noise occurs when GN3-0 bits are changed.

GN3-0

FH

EH

DH

:

GAIN (dB)

+24.0

+21.0

+18.0

:

7H

:

+0.0

:

Default

2H

1H

0H

−15.0

−18.0

−21.0

Table 16. AUX Input Gain Setting

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

STEREO LINE OUTPUT (LOUT and ROUT pins) and MONO LINE OUTPUT (MOUT2 pin)

DAC of

Mono CODEC

DAC2 bit

ATT

Mic In

IPGA

0dB/+20dB

MICL bit

Stereo Line Out

DACL bit

AUXL bit

ATT +

DAC of Stereo CODEC

External Headphone Amp

External Speaker Amp

AUX In

Mono Line Out(MOUT2)

Volume

Figure 28. Stereo Line Output and Mono Line Out2

Line out path does not have volume but the attenuator of DAC of Stereo CODEC, volume of Mic In and AUX In control

the output signal level. The AK4641EN does not have mute circuits to remove pop noise at power up and down for Line

Output. The signal of the stereo mixer is converted to a mono signal [(L+R)/2] and this signal is output via MOUT2 pin.

MONO LINE OUTPUT (MOUT+/MOUT− pin)

DAC of

Mono CODEC

DAC2 bit

ATT

MIC In

0dB/+20dB

IPGA

MICM bit

MOGN bit

DACM bit

1/2

MOUT+

ATT +

DAC of Stereo CODEC

MOUT−

−17dB/+6dB

Figure 29. Mono Output

Mono mixer mixes signal from MIC In, Lch signal and Rch signal from DAC of Stereo CODEC. This mixed signal is

output from the MOUT+ and MOUT− pins by differential output. Amp for mono output has 6dB gain and −17dB gain

that are set by the MOGN bit.

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

16bit Mono CODEC for Bluetooth I/F

The AK4641EN has the 16bit Mono CODEC to connect with Bluetooth Module that supports 8kHz to 16kHz sample

rate. The AK4641EN includes PLL that generate the master clock for Mono CODEC from input BSYNC signal. The PLL

should be powered-up after BSYNC signal is inputted. The PLL needs 90ms (max) lock time, when the PLL is

powered-up (PMBIF bit = “0” → “1”) and BSYNC is input. PMDA2 bit should be set to “0” or “0” data should be input

to DAC of Mono CODEC during 90ms after PMBIF bit is set to “1”.

BBICK and BSYNC should always be present when either ADC or DAC of Mono CODEC is power-up. If these clocks

are not provided, the AK4641EN may draw excess current and it is not possible to operate properly because utilizes

dynamic refreshed logic internally. If BBICK or BSYNC is not present, ADC and DAC of Mono CODEC should be in

the power-down mode.

ADC

The ADC of Mono CODEC outputs the signal from DAC of Stereo CODEC, Mic In and AUX In. The ADC of Mono

CODEC enters an initialization cycle that starts when the PMAD2 bit is changed from “0” to “1”. The initialization cycle

time is 1057/Bfs, or 132ms@Bfs=8kHz. During the initialization cycle, the ADC digital data output of Mono CODEC are

forced to a 2's compliment, “0”. The ADC output of Mono CODEC reflects the analog input signal after the initialization

cycle is complete.

• ADC full Scale Level: 0.6*AVDD [Vpp](1.98Vpp@3.3V)

Full Scale level of ADC of Mono CODEC is the same as that of DAC of Stereo CODEC.

DAC of

Mono CODEC

DAC2 bit

ATT

AK4641

Mic In

ADC2 bit

0dB/+20dB

ADC of

IPGA

Bluetooth

Module

MICL bit

Mono CODEC

Bth Headset

DACL bit

AUXL bit

ATT +

Stereo DAC

External

HP-Amp

Line Out

AUX In

Headphone

Volume

Figure 30. Path to ADC of Mono CODEC

DAC

The signal that is output from DAC of Mono CODEC is sent to Line Out, Mono Out and ADC of Stereo CODEC.

• DAC full Scale Level: 0.6*AVDD [Vpp](1.98Vpp@3.3V)

Full Scale level of DAC of Mono CODEC is the same as that of ADC of Stereo CODEC.

MICL bit

Line Out through stereo mixer

Mono Out

ATT

AK4641

MICM bit

Microphone

ATT

IPGA with ALC

MICAD bit

ADC of Stereo

CODEC

µP

Mic In

0dB/+20dB

DAC2 bit

AUX In

Bluetooth

Module

DAC of

Bth Headset

Mono CODEC

Figure 31. Path from DAC of Mono CODEC

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

I²C-bus Control Interface

The AK4641EN supports the fast-mode I²C-bus (max: 400kHz).

1. WRITE Operations

Figure 32 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START condition. A

HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 38). After the

START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit

(R/W). The most significant seven bits of the slave address are fixed as “0010010”. If the slave address matches that of the

AK4641EN, the AK4641EN generates an acknowledge and the operation is executed. The master must generate the

acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 39). A

R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be

executed.

The second byte consists of the control register address of the AK4641EN. The format is MSB first, and those most

significant 3-bits are fixed to zeros (Figure 34). The data after the second byte contains control data. The format is MSB

first, 8bits (Figure 35). The AK4641EN generates an acknowledge after each byte has been received. A data transfer is

always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL

is HIGH defines a STOP condition (Figure 38).

The AK4641EN can perform more than one byte write operation per sequence. After receipt of the third byte the

AK4641EN generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of

terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit

address counter is incremented by one, and the next data is automatically taken into the next address. If the address

exceeds 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will

be overwritten.

The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data

line can only change when the clock signal on the SCL line is LOW (Figure 40) except for the START and STOP

conditions.

S

T

O

P

T

A

R

T

R/W="0"

Slave

Address

Sub

Address(n)

S

Data(n)

Data(n+1)

Data(n+x)

P

SDA

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Figure 32. Data Transfer Sequence at the I²C-Bus Mode

0

1

0

1

0

R/W

A0

Figure 33. The First Byte

A4

A3

A2

D2

A1

D1

Figure 34. The Second Byte

D7

D6

D5

D4

D3

D0

Figure 35. Byte Structure after the second byte

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

(2)-2. READ Operations

Set the R/W bit = “1” for the READ operation of the AK4641EN. After transmission of data, the master can read the next

address’s data by generating an acknowledge instead of generating a stop condition after the receipt of the first data word.

After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is

automatically taken into the next address. If the address exceeds 1FH prior to generating a stop condition, the address

counter will “roll over” to 00H and the previous data will be overwritten.

The AK4641EN supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.

(2)-2-1. CURRENT ADDRESS READ

The AK4641EN contains an internal address counter that maintains the address of the last word accessed, incremented by

one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would

access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4641EN generates an

acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal

address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,

the AK4641EN ceases transmission.

S

T

O

P

T

A

R

T

R/W="1"

Slave

Address

S

Data(n)

Data(n+1)

Data(n+2)

Data(n+x)

P

SDA

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Figure 36. CURRENT ADDRESS READ

(2)-2-2. RANDOM ADDRESS READ

The random read operation allows the master to access any memory location at random. Prior to issuing the slave address

with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a

slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master

immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK4641EN then generates an

acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an

acknowledge to the data but instead generates a stop condition, the AK4641EN ceases transmission.

S

T

A

R

T

S

T

A

R

T

S

T

O

P

R/W="0"

R/W="1"

Slave

Address

Sub

Address(n)

Slave

Address

S

Data(n)

Data(n+1)

Data(n+x)

P

SDA

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Figure 37. RANDOM ADDRESS READ

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

SDA

SCL

S

P

start condition

stop condition

Figure 38. START and STOP Conditions

DATA

OUTPUT BY

TRANSMITTER

not acknowledge

DATA

OUTPUT BY

RECEIVER

acknowledge

SCL FROM

MASTER

2

1

8

9

S

clock pulse for

acknowledgement

START

CONDITION

Figure 39. Acknowledge on the I²C-Bus

SDA

SCL

data line

stable;

data valid

change

of data

allowed

Figure 40. Bit Transfer on the I²C-Bus

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

Register Map

Addr Register Name

D7

PMVCM

MCKPD

MOGN

DACL

0

D6

0

PSMO

0

MCK1

TM

0

REF6

IPGA6

ATTL6

ATTR6

ATTS2

0

EQB2

EQD2

0

D5

0

DACM

AUXL

0

MCK0

SMUTE

D4

PMLO

MCKAC PMMO2

MICM

MICL

0

D3

PMMO

D2

D1

D0

00H Power Management 1

01H Power Management 2

02H Signal Select1

03H Signal Select2

04H Mode Control 1

05H Mode Control 2

06H DAC Control

07H MIC Control

08H Timer Select

09H ALC Mode Control 1

0AH ALC Mode Control 2

0BH Input PGA Control

0CH Lch Digital ATT Control

0DH Rch Digital ATT Control

0EH Volume Control

0FH Status

10H EQ Control 250Hz/100Hz

11H EQ Control 3.5kHz/1kHz

12H EQ Control 10kHz

13H BT I/F CODEC Control

PMAUX PMMIC PMADC

0

PMDAC

PSMO2

PSLOR

DIF0

0

AUXSI

0

HPM

EQ

MICAD

WTM0

LMAT0

REF2

IPGA2

ATTL2

ATTR2

GN2

PSLOL

DIF1

0

LOOP

DEM1

MSEL

LTM1

RATT

REF1

IPGA1

ATTL1

ATTR1

GN1

0

DATTC

DEM0

MGAIN

LTM0

LMTH

REF0

IPGA0

ATTL0

ATTR0

GN0

DTMIC

EQA0

EQC0

EQE0

0

AUXAD MPWRE MPWRI

ZTM1

ALC1

REF5

IPGA5

ATTL5

ATTR5

ATTS1

0

ZTM0

ZELM

REF4

IPGA4

ATTL4

ATTR4

ATTS0

0

WTM1

LMAT1

REF3

IPGA3

ATTL3

ATTR3

GN3

ATTL7

ATTR7

ATTM

0

EQB3

EQD3

0

EQB1

EQD1

0

EQB0

EQD0

0

EQA3

EQC3

EQE3

ADC2

EQA2

EQC2

EQE2

PMBIF

EQA1

EQC1

EQE1

PMDA2

BTFMT1

BTFMT0

0

DAC2

PMAD2

*PDN pin = “L” resets the registers to their default values.

*Unused bits must contain a “0” value.

*Only write to address 00H to 13H.

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

D1 D0

Addr Register Name

D7

PMVCM

R/W

0

D6

0

RD

0

D5

0

RD

0

D4

PMLO

R/W

0

D3

D2

00H

Power Management 1

PMMO PMAUX PMMIC PMADC

R/W

Default

R/W

0

R/W

0

R/W

0

R/W

0

PMADC: ADC Block of Stereo CODEC Power Control

0: Power down (Default)

1: Power up

When PMADC bit changes from “0” to “1”, initializing cycle (2081/fs=47.2ms@44.1kHz) starts. After

initializing cycle, digital data of the ADC of Stereo CODEC is output.

PMMIC: MIC In Block Power Control

0: Power down (Default)

1: Power up

PMMO: Mono Out Power Control

0: Power down (Default)

1: Power up

PMLO: Line Out Power Control

0: Power down (Default)

1: Power up

PMAUX: AUX In Power Control

0: Power down (Default)

1: Power up

PMVCM: VCOM Block Power Control

0: Power down (Default)

1: Power up

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

D7

MCKPD

R/W

1

Addr Register Name

D6

0

RD

0

D5

0

RD

0

D4

MCKAC

R/W

0

D3

PMMO2

R/W

D2

0

RD

0

D1

0

RD

0

D0

PMDAC

R/W

01H

Power Management 2

R/W

Default

0

PMDAC: DAC Block of Stereo CODEC Power Control

0: Power down (Default)

1: Power up

PMMO2: Mono Out2 Power Control

0: Power down (Default)

1: Power up

MCKAC: Master Clock input Mode Select

0: C-MOS input (Default)

1: AC-Coupling input

MCKPD: MCLK Input Buffer Control

0: Enable

1: Disable (Default)

When MCLK input with AC coupling is stopped, MCKPD bit should be set to “1”.

ADC and DAC of 16bit Stereo CODEC are powered-down at MCKPD bit = “1”.

Note) The stereo mixer block (PMMIX) is powered down automatically.

PMLO=PMMO2=PMAD2 bits = “0”: Power Down

Others:

Power Up

Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are

powered down.

When all bits except MCKPD bit are “0” in the 00H and 01H addresses, all blocks are powered down. The register

values remain unchanged. IPGA gain is reset when PMMIC bit is “0” (refer to the IPGA6-0 bits description).

When any of the blocks are powered up, the PMVCM bit must be set to “1”.

MCLK, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC bits = “0” or PDN pin = “L”.

BBICK and BSYNC must always be present unless PMAD2=PMDA2=PMBIF bits = “0” or PDN pin = “L”.

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

Addr Register Name

D7

MOGN

R/W

0

D6

PSMO

R/W

0

D5

DACM

R/W

0

D4

MICM

R/W

0

D3

0

RD

0

D2

0

RD

0

D1

0

RD

0

D0

PSMO2

R/W

0

02H

Signal Select1

R/W

Default

PSMO2: Select mono output 2 of MOUT2 pin (Mixing = (L+R)/2)

0: Power Save Mode. Output VCOM voltage. (Default)

1: Normal Operation

(Note) Hi-Z is output at PMMO2 bit = “0”.

MICM: Switch Control from Mic In to Mono Mixer

0: OFF (Default)

1: ON

DACM: Switch Control from DAC of Stereo CODEC to Mono Mixer (Mixing = (L+R)/2)

0: OFF (Default)

1: ON

PSMO: Select mono output of MOUT+/− pins

0: Power Save Mode. Output VCOM voltage. (Default)

1: Normal Operation

(Note) Hi-Z is output at PMMO bit = “0”.

MOGN: Gain control for mono output

0: +6dB (Default)

1: −17dB

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

D1 D0

Addr Register Name

D7

DACL

R/W

1

D6

0

RD

0

D5

AUXL

R/W

0

D4

MICL

R/W

0

D3

0

RD

0

D2

AUXSI

R/W

0

03H

Signal Select2

R/W

PSLOL

R/W

0

PSLOR

R/W

0

Default

PSLOR: Select Rch Line output of ROUT pin

0: Power Save Mode. Output VCOM voltage. (Default)

1: Normal Operation

(Note) Hi-Z is output at PMLO bit = “0”.

PSLOL: Select Lch Line output of LOUT pin

0: Power Save Mode. Output VCOM voltage. (Default)

1: Normal Operation

(Note) Hi-Z is output at PMLO bit = “0”.

MICL: Switch Control from Mic In to Stereo Mixer

0: OFF (Default)

1: ON

AUXL:Switch Control from AUX IN to Stereo Mixer

0: OFF (Default)

1: ON

DACL: Switch Control from DAC of Stereo CODEC to Stereo Mixer

0: OFF

1: ON (Default)

AUXSI: Select AUX Input

0: Differential Input (Default)

1: Single-ended Input. AUXIN+ pin is used for AUX input and AUXIN− pin is not available.

Addr Register Name

D7

0

RD

0

D6

0

RD

0

D5

0

RD

0

D4

0

RD

0

D3

0

RD

0

D2

0

RD

0

D1

DIF1

R/W

1

D0

DIF0

R/W

0

04H

Mode Control 1

R/W

Default

DIF1-0: Digital Audio Interface Format Select (See Table 5.)

Addr Register Name

D7

0

RD

0

D6

MCK1

R/W

0

D5

MCK0

R/W

0

D4

0

RD

0

D3

0

RD

0

D2

HPM

R/W

0

D1

LOOP

R/W

0

D0

0

RD

0

05H

Mode Control 2

R/W

Default

LOOP: Loopback ON/OFF

0: OFF (Default)

1: ON

ADC output data of Stereo CODEC is inputted to both Lch and Rch of DAC of Stereo CODEC.

HPM: Mono output select from DAC of Stereo CODEC

0: Stereo (Default)

1: Mono. (L+R)/2 signal is output from Lch and Rch of DAC of Stereo CODEC

MCK1-0: Input Master Clock Select (See Table 2.)

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

D1 D0

Addr Register Name

D7

0

RD

0

D6

TM

R/W

0

D5

SMUTE

R/W

0

D4

DATTC

R/W

1

D3

0

RD

0

D2

EQ

R/W

0

06H

DAC Control

R/W

DEM1

R/W

0

DEM0

R/W

1

Default

DEM1-0: De-emphases response (See Table 12.)

EQ: Select 5 Band Equalizer.

0: OFF (Default)

1: ON

DATTC: DAC of Stereo CODEC Digital Attenuator Control Mode Select

0: ATTL6-0 and ATTR6-0 bits control attenuator level of Lch and Rch respectively.

1: ATTL6-0 bits control both Lch and Rch at same time. (Default)

When DATTC bit = “1”, the value of ATTR6-0 does not change.

SMUTE: Soft Mute Control

0: Normal Operation (Default)

1: DAC outputs of Stereo CODEC soft-muted

TM: Soft Mute and DATT Transition Time Select (See Table 15.)

Addr Register Name

D7

0

RD

0

D6

0

RD

0

D5

AUXAD

R/W

0

D4

MPWRE

R/W

0

D3

MPWRI

R/W

0

D2

MICAD

R/W

1

D1

MSEL

R/W

0

D0

MGAIN

R/W

1

07H

MIC Control

R/W

Default

MGAIN: 1^stMic Amp Gain control

0: OFF. 0dB

1: ON. +20dB (Default)

MSEL: Microphone select

0: Internal Mic (Default)

1: External Mic

MICAD: Switch Control from Mic In to ADC of Stereo CODEC

0: OFF

1: ON (Default)

MPWRI: Power Supply Control for Internal Microphone

0: OFF (Default)

1: ON

MPWRE: Power Supply for External Microphone

0: OFF (Default)

1: ON

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ASAHI KASEI

[AK4641EN]

AUXAD: Switch Control from AUX In to ADC of Stereo CODEC

0: OFF (default)

1: ON

Addr Register Name

D7

0

RD

0

D6

0

RD

0

D5

ZTM1

R/W

0

D4

ZTM0

R/W

0

D3

WTM1

R/W

0

D2

WTM0

R/W

0

D1

D0

08H

Timer Select

R/W

LTM1

R/W

0

LTM0

R/W

0

Default

LTM1-0: ALC1 limiter operation period at zero crossing disable (ZELM bit = “1”)

The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by

the period specified by LTM1-0 bits.

ALC1 Limiter Operation Period

LTM1

LTM0

8kHz

16kHz

44.1kHz

11µs

23µs

45µs

91µs

0

1

0

1

0

1

0.5/fs

1/fs

2/fs

Default

63µs

31µs

63µs

125µs

250µs

125µs

250µs

500µs

4/fs

Table 17. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit = “1”)

WTM1-0: ALC1 Recovery Waiting Period

WTM1-0 bits set a period of recovery operation when any limiter operation does not occur during ALC1 operation.

When the output signal level exceeds auto recovery waiting counter reset level set by LMTH bit, the auto recovery

waiting counter is reset. The waiting timer starts when the output signal level becomes below the auto recovery

waiting counter reset level.

ALC1 Recovery Operation Waiting Period

WTM1

WTM0

8kHz

16ms

32ms

64ms

128ms

16kHz

8ms

16ms

32ms

64ms

44.1kHz

2.9ms

5.8ms

11.6ms

23.2ms

0

1

0

1

0

1

128/fs

256/fs

512/fs

1024/fs

Default

Table 18. ALC1 Recovery Operation Waiting Period

ZTM1-0: Zero crossing timeout at the write operation by µP, ALC1 recovery operation and zero crossing enable

(ZELM bit = “0”) of the ALC1 operation

When IPGA of each L/R channels perform zero crossing or timeout independently, the IPGA value is changed by

µP WRITE operation or ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”).

Zero Crossing Timeout Period

ZTM1

ZTM0

8kHz

16ms

32ms

64ms

128ms

16kHz

8ms

16ms

32ms

64ms

44.1kHz

2.9ms

0

1

0

1

0

1

128/fs

256/fs

512/fs

1024/fs

Default

5.8ms

11.6ms

23.2ms

Table 19. Zero Crossing Timeout Period

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2006/02

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ASAHI KASEI

[AK4641EN]

D1 D0

Addr Register Name

D7

0

RD

0

D6

0

RD

0

D5

ALC1

R/W

0

D4

ZELM

R/W

0

D3

D2

09H

ALC Mode Control 1

LMAT1 LMAT0

R/W

0

RATT

R/W

0

LMTH

R/W

0

R/W

Default

R/W

0

LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level

The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB.

ALC1 Limiter Detection Level

ADC Input ≥ −6.0dBFS

ADC Input ≥ −4.0dBFS

ALC1 Recovery Waiting Counter Reset Level

−6.0dB > ADC Input ≥ −8.0dBFS

−4.0dB > ADC Input ≥ −6.0dBFS

LMTH

0

1

Default

Table 20. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level

RATT: ALC1 Recovery GAIN Step

During the ALC1 Recovery operation, the number of steps changed from current IPGA value is set. For example,

when the current IPGA value is “30H” and RATT bit = “1” is set, IPGA changes to “32H” by the ALC1 recovery

operation, the output signal level is gained up by 1dB (=0.5dB x 2).

When the IPGA value exceeds the reference level (REF6-0 bits), the IPGA value does not increase.

RATT

GAIN STEP

0

1

2

Default

Table 21. ALC1 Recovery Gain Step Setting

LMAT1-0: ALC1 Limiter ATT Step

During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by

LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA

value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to “43H” when the ALC1 limiter operation starts,

resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation value exceeds IPGA

= “00H” (−8dB), it clips to “00H”.

LMAT1

LMAT0

ATT STEP

0

1

0

1

0

1

2

3

4

Default

Table 22. ALC1 Limiter ATT Step Setting

ZELM: Enable zero crossing detection at ALC1 Limiter operation

0: Enable (Default)

1: Disable

When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently and

the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1 recovery

operation. When the ZELM bit = “1”, the IPGA value is changed immediately.

ALC1: ALC1 Enable

0: ALC1 Disable (Default)

1: ALC1 Enable

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ASAHI KASEI

[AK4641EN]

D1 D0

Addr Register Name

0AH ALC Mode Control 2

R/W

D7

0

RD

0

D6

REF6

R/W

0

D5

REF5

R/W

1

D4

REF4

R/W

1

D3

REF3

R/W

0

D2

REF2

R/W

1

REF1

R/W

1

REF0

R/W

0

Default

REF6-0: Set the Reference value at ALC1 Recovery Operation

During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation, then

the IPGA does not become larger than the reference value. For example, when REF6-0 bits = “30H”, RATT =

2step, IPGA = “2FH”, even if the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset Level”,

the IPGA does not change to “2FH” + 2step = “31H”, but keeps “30H”. Default is “36H”.

REF6-0

47H

46H

45H

:

GAIN (dB)

+27.5

+27.0

+26.5

:

STEP

36H

:

+19.0

:

Default

10H

:

+0.0

:

0.5dB

06H

05H

04H

03H

02H

01H

00H

−5.0

−5.5

−6.0

−6.5

−7.0

−7.5

−8.0

Table 23. Setting Reference Value at ALC1 Recovery Operation

Addr Register Name

0BH Input PGA Control

R/W

D7

0

RD

0

D6

IPGA6

R/W

0

D5

IPGA5

R/W

0

D4

IPGA4

R/W

1

D3

IPGA3

R/W

0

D2

IPGA2

R/W

0

D1

IPGA1

R/W

0

D0

IPGA0

R/W

0

Default

IPGA6-0: Input Analog PGA (See Table 7.)

When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”. IPGA

gain is reset when PMMIC bit is “0”, and then IPGA operation starts from the default value when PMMIC is

changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.

When IPGA6-0 bits are read, the register values written by the last write operation is read out regardless the actual

gain.

Addr Register Name

0CH Lch Digital ATT Control

0DH Rch Digital ATT Control

R/W

D7

ATTL7

ATTR7

R/W

D6

ATTL6

ATTR6

R/W

D5

ATTL5

ATTR5

R/W

D4

ATTL4

ATTR4

R/W

D3

ATTL3

ATTR3

R/W

D2

ATTL2

ATTR2

R/W

D1

ATTL1

ATTR1

R/W

D0

ATTL0

ATTR0

R/W

Default

0

ATTL/R7-0: Digital ATT Output Control

These bits control the attenuation level of DAC output of Stereo CODEC. Step size of ATT is approximately

0.5dB (See Table 13).

Note) Even if DATTC bit = “1”, ATTR7-0 bits are not changed when the ATTL7-0 bits are written.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

Addr Register Name

0EH Volume Control

R/W

D7

ATTM

R/W

0

D6

ATTS2

R/W

1

D5

ATTS1

R/W

0

D4

ATTS0

R/W

1

D3

GN3

R/W

0

D2

GN2

R/W

1

D1

GN1

R/W

1

D0

GN0

R/W

1

Default

GN3-0: Volume of AUX In (see Table 16.)

ATTS2-0: Attenuator select of signal from Mic IN to Stereo Mixer (See Table 8.)

ATTM: Attenuator control for signal from Mic IN to Mono Mixer

0: 0dB (Default)

1: −4dB

Addr Register Name

0FH Status

D7

0

RD

0

D6

0

RD

0

D5

0

RD

0

D4

0

RD

0

D3

0

RD

0

D2

0

RD

0

D1

0

RD

0

D0

DTMIC

RD

R/W

Default

0

DTMIC: Microphone Detection Result

0: Microphone is not detected. (Default)

1: Microphone is detected.

Addr Register Name

D7

EQB3

EQD3

R/W

1

D6

EQB2

EQD2

R/W

0

D5

EQB1

EQD1

R/W

0

D4

EQB0

EQD0

R/W

0

D3

EQA3

EQC3

R/W

1

D2

EQA2

EQC2

R/W

0

D1

D0

10H

11H

EQ Control 250Hz/100Hz

EQ Control 3.5kHz/1kHz

EQA1

EQC1

R/W

0

EQA0

EQC0

R/W

0

R/W

Default

Addr Register Name

D7

0

RD

0

D6

0

RD

0

D5

0

RD

0

D4

0

RD

0

D3

EQE3

R/W

1

D2

EQE2

R/W

0

D1

EQE1

R/W

0

D0

EQE0

R/W

0

12H

EQ Control 10kHz

R/W

Default

EQA3-0: Select the boost level of 100Hz

EQB3-0: Select the boost level of 250Hz

EQC3-0: Select the boost level of 1kHz

EQD3-0: Select the boost level of 3.5kHz

EQE3-0: Select the boost level of 10kHz

See Table 14.

MS0467-E-00

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ASAHI KASEI

[AK4641EN]

D1 D0

Addr Register Name

D7

0

RD

0

D6

BTFMT1

R/W

0

D5

BTFMT0

R/W

0

D4

DAC2

R/W

0

D3

ADC2

R/W

1

D2

13H

BT I/F CODEC Control

PMBIF PMDA2 PMAD2

R/W

Default

R/W

0

R/W

0

R/W

0

PMAD2: ADC Block of Mono CODEC Power Control

0: Power down (Default)

1: Power up

PMDA2: DAC Block of Mono CODEC Power Control

0: Power down (Default)

1: Power up

PMBIF: 16bit Mono Interface and PLL Block Power Control

0: Power down (Default)

1: Power up

ADC and DAC of 16bit Mono CODEC are powered-down at PMBIF bit = “0”.

AD2: Select Signal that is input to ADC of 16bit Mono CODEC

0: OFF

1: ON (Default)

DAC2: Select DAC of Mono CODEC signal (See Figure 21.)

0: MIC Input Signal (Default)

1: DAC signal of Mono CODEC

BTFMT1-0: Digital Audio Interface Format Select for 16bit Mono CODEC (See Table 6.)

MS0467-E-00

2006/02

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ASAHI KASEI

[AK4641EN]

SYSTEM DESIGN

Figure 41 shows the system connection diagram for t the AK4641EN.

1µ 1µ

C

1µ

2.2k

C

1

2

3

4

5

6

7

8

9

MPE

ROUT 27

2.2k

1µ

MPI

MOUT2 26

TST2 25

INT

VCOM

AVSS

AVDD

PVDD

PVSS

VCOC

BBICK 24

BSYNC 23

BSDTO 22

BSDTI 21

DVSS 20

DVDD 19

0.1µ

2.2µ

10µ

Bluetooth

Proccesor

Analog Supply

2.6~ 3.6V

Top View

10µ

0.1µ

5.1kΩ

470n

10

Reset

DSP and uP

Notes:

- AVSS, DVSS and BVSS of the AK4641EN should be distributed separately from the ground of external controllers.

- Values of R and C in Figure 41 should depend on system.

- All digital input pins should not be left floating.

Figure 41. Typical Connection Diagram

MS0467-E-00

2006/02

- 47 -

ASAHI KASEI

[AK4641EN]

1. Grounding and Power Supply Decoupling

The AK4641EN requires careful attention to power supply and grounding arrangements. AVDD, DVDD and BVDD are

usually supplied from the system’s analog supply. If AVDD, DVDD and BVDD are supplied separately, the power up

sequence is not critical. AVSS, DVSS and BVSS of the AK4641EN should be connected to the analog ground plane.

System analog ground and digital ground should be connected together near to where the supplies are brought onto the

printed circuit board. Decoupling capacitors should be as near to the AK4641EN as possible, with the small value ceramic

capacitor being the nearest.

2. Voltage Reference

VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached

to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All

signals, especially clocks, should be kept away from the AVDD and VCOM pins in order to avoid unwanted coupling into

the AK4641EN.

3. Analog Inputs

The AK4641EN has the 16bit Mono CODEC to connect with Bluetooth Module that supports 8kHz to 16kHz sample

rate. The AK4641EN includes PLL that generate the master clock for Mono CODEC from input BSYNC signal. The PLL

should be powered-up after BSYNC signal is inputted. The PLL needs 90ms (max) lock time, when the PLL is

powered-up (PMBIF bit = “0” → “1”).

The Mic inputs are single-ended. AUX input is differential. The input signal range scales with nominally at 0.06 x AVDD

Vpp for the Mic input, 0.6 x AVDD Vpp for AUX input, centered around the internal common voltage (0.45 x AVDD).

Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4641EN can

accept input voltages from AVSS to AVDD.

4. Analog Outputs

The input data format for the DAC of both Stereo and Mono CODEC is 2’s complement. The output voltage is a positive

full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Mono output from the MOUT2 pin, Mono

Line Output from the MOUT+/MOUT− pins and Stereo Line Out from the LOUT/ROUT pins are centered at 0.45 x

AVDD.

MS0467-E-00

2006/02

- 48 -

ASAHI KASEI

[AK4641EN]

PACKAGE

36pin QFN (Unit: mm)

6.00 ± 0.10

5.75 ± 0.10

0.55 ± 0.10

27

19

28

36

18

B

Exposed

Pad

36

10

1

9

C0.40

1

A

3.7

+0.07

0.23 ^-0.05

0.50

AB

0.10 M

C

0.08 C

Note) The exposed pad on the bottom surface of the package must be open or connected to the grournd.

Material & Lead finish

Package molding compound:

Lead frame material:

Epoxy

Cu

Lead frame surface treatment:

Solder (Pb free) plate

MS0467-E-00

2006/02

- 49 -

ASAHI KASEI

[AK4641EN]

MARKING

AKM

4641EN

XXXXXXX

1

XXXXXXX : Date code identifier (7 digits)

Revision History

Date (YY/MM/DD) Revision Reason

06/02/22 00 First Edition

Page

Contents

IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering

any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or

authorized distributor concerning their current status.

• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the

application or use of any information contained herein.

• Any export of these products, or devices or systems containing them, may require an export license

or other official approval under the law and regulations of the country of export pertaining to customs

and tariffs, currency exchange, or strategic materials.

• AKM products are neither intended nor authorized for use as critical components in any safety, life

support, or other hazard related device or system, and AKM assumes no responsibility relating to any

such use, except with the express written consent of the Representative Director of AKM. As used

here:

a. A hazard related device or system is one designed or intended for life support or maintenance of

safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its

failure to function or perform may reasonably be expected to result in loss of life or in significant

injury or damage to person or property.

b. A critical component is one whose failure to function or perform may reasonably be expected to

result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or

system containing it, and which must therefore meet very high standards of performance and

reliability.

• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or

otherwise places the product with a third party to notify that party in advance of the above content

and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability

for and hold AKM harmless from any and all claims arising from the use of said product in the

absence of such notification.

MS0467-E-00

2006/02

- 50 -

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	36
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.83	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-XQCC-N36
长度：	6 mm	功能数量：	1
端子数量：	36	最高工作温度：	85 °C
最低工作温度：	-20 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	0.9 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	2.6 V	表面贴装：	YES
温度等级：	COMMERCIAL EXTENDED	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	6 mm	Base Number Matches：	1

型号	制造商	描述	价格	文档
AK4641VN	AKM	16 BIT CODEC WITH BLUETOOTH INTERFACE	获取价格
AK4642	AKM	16-Bit ÎÎ£ Stereo CODEC with MIC/HP/SPK-AMP	获取价格
AK4642EN	AKM	Stereo CODEC with MIC/HP/SPK-AMP	获取价格
AK4642VN	AKM	16-Bit ÎÎ£ Stereo CODEC with MIC/HP/SPK-AMP	获取价格
AK4643	AKM	Stereo CODEC with MIC/HP/RCV/SPK-AMP	获取价格
AK4643EN	AKM	Stereo CODEC with MIC/HP/RCV/SPK-AMP	获取价格
AK4644	AKM	Stereo CODEC with MIC/HP/RCV-AMP	获取价格
AK4644EN	AKM	Stereo CODEC with MIC/HP/RCV-AMP	获取价格
AK4645	AKM	Stereo CODEC with MIC/HP-AMP	获取价格
AK4645AEZ	AKM	暂无描述	获取价格

AK4641EN

AK4641EN 概述

AK4641EN 规格参数

AK4641EN 数据手册

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