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DS1035M-012

更新时间：2025-07-10 00:48:47

品牌：DALLAS

描述：Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDIP8, DIP-8

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DS1035M-012 概述

Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDIP8, DIP-8

DS1035M-012 数据手册

通过下载DS1035M-012数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

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DS1035

3-in-1 High–Speed Silicon Delay Line

www.dalsemi.com

FEATURES

PIN ASSIGNMENT

ꢀ All-silicon timing circuit

V_CC

IN1

IN2

ꢀ Three independent buffered delays

ꢀ Stable and precise over temperature and

voltage

ꢀ Leading and trailing edge precision preserves

the input symmetry

ꢀ Standard 8-pin DIP and 8-pin SOIC (150 mil)

ꢀ Vapor phasing, IR and wave solderable

ꢀ Available in Tape and Reel

OUT1

OUT2

OUT3

IN3

GND

DS1035M 8-Pin DIP

See Mech. Drawings Section

V_CC

IN1

IN2

OUT1

OUT2

OUT3

IN3

GND

DS1035Z 8-Pin SOIC (150-mil)

See Mech. Drawings Section

PIN DESCRIPTION

IN1-IN3

OUT1-OUT3

V_CC

GND

- Input Signals

- Output Signals

- No Connection

- +5 Volt Supply

- Ground

(Sub)

- Internal substrate

connection, do not make

any external connections

to these pins

DESCRIPTION

The DS1035 series is a low-power +5-volt high-speed version of the popular DS1013 and complements

the DS1033 +3.3 Volt version.

The DS1035 series of delay lines have three independent logic buffered delays in a single package. The

device is Dallas Semiconductor’s fastest 3-in-1 delay line. It is available in a standard 8-pin DIP and 150

Mil 8-pin Mini-SOIC.

The device features precise leading and trailing edge accuracies. It has the inherent reliability of an all-

silicon delay line solution. The DS1035’s initial tolerance is ±1.5 or ±2.0 ns with an additional tolerance

over temperature and voltage of ±1.0 ns or ±1.5 ns, depending on the delay value. Each output is capable

of driving up to 10 LS loads.

Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (982)

371-4348 for further information.

1 of 6

111799

DS1035

LOGIC DIAGRAM Figure 1

PART NUMBER DELAY TABLE (t_PLH, t_PHL) Table 1

TOLERANCE OVER

TEMPERATURE

AND VOLTAGE

±1.0 ns

DELAY PER

PART NUMBER

DS1035-60

DS1035-80

DS1035-10

DS1035-12

DS1035-15

DS1035-20

DS1035-25

DS1035-30

OUTPUT (ns)

INITIAL TOLERANCE

±1.5 ns

6/6/6

8/8/8

±1.5 ns

±2.0 ns

±1.0 ns

±1.5 ns

10/10/10

12/12/12

15/15/15

20/20/20

25/25/25

30/30/30

NOTES:

1. Nominal conditions are +25°C and V_CC=+5.0 volts.

2. Temperature range of 0°C to 70°C and voltage range of 4.75 volts to 5.25 volts.

3. Delay accuracy is for both leading and trailing edges.

2 of 6

DS1035

TEST SETUP DESCRIPTION

Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1035.

The input waveform is produced by a precision pulse generator under software control. Time delays are

measured by a time interval counter (20 ps resolution ) connected to the output. The DS1035 output taps

are selected and connected to the interval counter by a VHF switch control unit. All measurements are

fully automated with each instrument controlled by the computer over an IEEE 488 bus.

DS1035 TEST CIRCUIT Figure 2

3 of 6

DS1035

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground

Operating Temperature

-1.0V to +7.0V

0°C to 70°C

Storage Temperature

Soldering Temperature

Short Circuit Output Current

-55°C to +125°C

260°C for 10 seconds

50 mA for 1 second

* This is a stress rating only and functional operation of the device at these or any other conditions above

those indicated in the operation sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods of time may affect reliability.

DC ELECTRICAL CHARACTERISTICS

(0°C to 70°C; V_CC=+5V ± 5%)

PARAMETER

SYMBOL

TEST

MIN

TYP

MAX

UNITS

CONDITION

Supply Voltage

V_CC

I_CC

V_IH

V_IL

I_L

4.75

5.00

5.25

V_CC=5.25V

Period=1µs

Active Current

V_CC

+0.5

High Level Input Voltage

Low Level Input Voltage

Input Leakage

2.2

-0.5

-1.0

0.8

+1.0

-1.0

0V≤V_I≤V_CC

µA

V_CC=4.75V

V_OH=4V

V_CC=4.75V

V_OL=0.5V

High Level Output Current

Low Level Output Current

I_OH

I_OL

AC ELECTRICAL CHARACTERISTICS

(+25°C; V_CC=5V ± 5%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Period

t_PERIOD

2 (t_WI)

100% of

Tap Delay

Input Pulse Width

t_WI

Input-to-Tap Output Delay

Output Rise or Fall Time

Power-up Time

t_PLH,t_PHL

Table 1

2.0

t_{OR, OF}

2.5

t_PU

100

CAPACITANCE

(T_A=25°C)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS NOTES

Input Capacitance

C_IN

4 of 6

DS1035

TEST CONDITIONS

Ambient Temperature:

Supply Voltage (V_CC):

Input Pulse:

25°C ±=3°C

5.0V ±=0.1V

High: 3.0V ±=0.1V

Low: 0.0V ±=0.1V

Source Impedance: 50Ω=max.

Rise and Fall Time: 3.0 ns max. - Measured between 0.6V and 2.4V.

Pulse Width: 500 ns

Pulse Period: 1 µs

Output Load Capacitance: 15 pF

Output:

Each output is loaded with the equivalent of one 74F04 input gate.

Data is measured at the 1.5V level on the rising and falling edges.

Note: The above conditions are for test only and do not restrict the devices under other data sheet

conditions.

TIMING DIAGRAM

NOTES:

1. All voltages are referenced to ground.

2. @ V_CC=5 volts and 25°C, delay accuracy on both the rising and falling edges within tolerances given

in Table 1.

3. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application

sensitive with respect to decoupling, layout, etc.

5 of 6

DS1035

TERMINOLOGY

Period: The time elapsed between the leading edge of the first pulse and the leading edge of the

following pulse.

t_WI(Pulse Width): The elapsed time on the pulse between the 1.5 volt point on the leading edge and the

1.5 volt point on the trailing edge, or the 1.5 volt point on the trailing edge and the 1.5 volt point on the

leading edge.

t_RISE(Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the

input pulse.

t_FALL(Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the

input pulse.

t_PLH(Time Delay, Rising): The elapsed time between the 1.5 volt point on the leading edge of the input

pulse and the 1.5 volt point on the leading edge of the output pulse.

t_PHL(Time Delay, Falling): The elapsed time between the 1.5 volt point on the falling edge of the input

pulse and the 1.5 volt point on the falling edge of the output pulse.

6 of 6

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