首页 > 逻辑 > 延迟线 > PDU-18F-1M

PDU-18F-1M

更新时间：2024-12-05 03:07:38

品牌：DATADELAY

描述：Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, LOW PROFILE, DIP-40

PDF下载

中文翻译

PCB计价

概述
规格参数
数据手册

如果您发现信息不准确，欢迎纠错

PDU-18F-1M 概述

Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, LOW PROFILE, DIP-40 延迟线

PDU-18F-1M 规格参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DIP
包装说明：	DIP,	针数：	40
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.16	其他特性：	MEETS MIL-D-23859; TEMP. COEFF. SPECIFIED OVER 0 TO 70 DEG. CEL.
系列：	F	输入频率最大值（fmax）：	30.9789 MHz
JESD-30 代码：	R-XDIP-T40	JESD-609代码：	e3
逻辑集成电路类型：	ACTIVE DELAY LINE	功能数量：	1
抽头/阶步数：	255	端子数量：	40
最高工作温度：	125 °C	最低工作温度：	-55 °C
输出极性：	COMPLEMENTARY	封装主体材料：	UNSPECIFIED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
最大电源电流（ICC）：	128 mA	可编程延迟线：	YES
认证状态：	Not Qualified	座面最大高度：	7.493 mm
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	NO
技术：	TTL	温度等级：	MILITARY
端子面层：	Tin (Sn)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	总延迟标称（td）：	269 ns
宽度：	15.24 mm	Base Number Matches：	1

PDU-18F-1M 数据手册

通过下载PDU-18F-1M数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载

PDU18F



8-BIT PROGRAMMABLE

DELAY LINE

data

delay

(SERIES PDU18F)

devices, _inc.

FEATURES

PACKAGES

N/C

OUT/

OUT

EN/

VCC

N/C

VCC

N/C

VCC

N/C

VCC

N/C

•

Digitally programmable in 256 delay steps

Monotonic delay-versus-address variation

Two separate outputs: inverting & non-inverting

Precise and stable delays

PDU18F-xx

DIP

GND

N/C

GND

N/C

GND

N/C

EN/

PDU18F-xxC5

Input & outputs fully TTL interfaced & buffered

Gull-Wing

10 T²L fan-out capability

Fits standard 40-pin DIP socket

Auto-insertable

PDU18F-xxM

Military DIP

PDU18F-xxMC5

Military Gull-Wing

N/C

GND

N/C

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PDU18F-series device is a 8-bit digitally programmable delay line.

The delay, TD_A, from the input pin (IN) to the output pins (OUT, OUT/)

Delay Line Input

OUT Non-inverted Output

OUT/ Inverted Output

A0-A7 Address Bits

EN/ Output Enable

VCC +5 Volts

depends on the address code (A7-A0) according to the following formula:

TD_A= TD₀+ T_INC* A

where A is the address code, T_INCis the incremental delay of the device,

and TD₀is the inherent delay of the device. The incremental delay is

GND Ground

specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The

enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state

and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into

LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal

operation.

DASH NUMBER SPECIFICATIONS

SERIES SPECIFICATIONS

Part

Incremental

Total Delay

•

Programmed delay tolerance: 5% or 2ns,

Number

Delay

Change (ns)

whichever is greater

Per Step (ns)

.5 ± .3

Inherent delay (TD₀): 13ns typical (OUT)

12ns typical (OUT/)

PDU18F-.5

PDU18F-1

PDU18F-2

PDU18F-3

PDU18F-4

PDU18F-5

PDU18F-6

PDU18F-8

PDU18F-10

127.5 ± 6.4

255 ± 12.8

510 ± 25.5

765 ± 38.3

1,020 ± 51.0

1,275 ± 63.8

1,530 ± 76.5

2,040 ± 102.0

2,550 ± 127.5

1 ± .5

Setup time and propagation delay:

Address to input setup (T_AIS): 10ns

Disable to output delay (T_DISO): 6ns typ. (OUT)

Operating temperature: 0° to 70° C

Temperature coefficient: 100PPM/°C (excludes TD₀)

Supply voltage V_CC: 5VDC ± 5%

2 ± .5

3 ± 1.0

4 ± 1.0

5 ± 1.5

•

6 ± 1.5

8 ± 2.0

10 ± 2.0

Supply current:

_CCH= 65ma

NOTE: Any dash number between .5 and 10 not

I_CCL= 128ma

shown is also available.

•

Minimum pulse width: 6% of total delay

1997 Data Delay Devices

Doc #97006

1/30/06

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU18F

APPLICATION NOTES

spurious signals persists until the required T_DISH

ADDRESS UPDATE

has elapsed.

The PDU18F is a memory device. As such,

special precautions must be taken when

changing the delay address in order to prevent

spurious output signals. The timing restrictions

are shown in Figure 1.

INPUT RESTRICTIONS

There are three types of restrictions on input

pulse width and period listed in the AC

Characteristics table. The recommended

conditions are those for which the delay

After the last signal edge to be delayed has

appeared on the OUT pin, a minimum time, T_OAX

is required before the address lines can change.

This time is given by the following relation:

tolerance specifications and monotonicity are

guaranteed. The suggested conditions are

those for which signals will propagate through the

unit without significant distortion. The absolute

conditions are those for which the unit will

produce some type of output for a given input.

T_OAX= max { (A_i- A _i-1) * T_INC, 0 }

where A _i-1and A_iare the old and new address

codes, respectively. Violation of this constraint

When operating the unit between the

may, depending on the history of the input signal,

cause spurious signals to appear on the OUT

pin. The possibility of spurious signals persists

until the required T_OAXhas elapsed.

recommended and absolute conditions, the

delays may deviate from their values at low

frequency. However, these deviations will

remain constant from pulse to pulse if the input

pulse width and period remain fixed. In other

words, the delay of the unit exhibits frequency

and pulse width dependence when operated

beyond the recommended conditions. Please

consult the technical staff at Data Delay Devices

if your application has specific high-frequency

requirements.

A similar situation occurs when using the EN/

signal to disable the output while IN is active. In

this case, the unit must be held in the disabled

state until the device is able to “clear” itself. This

is achieved by holding the EN/ signal high and

the IN signal low for a time given by:

T_DISH= A_i* T_INC

Please note that the increment tolerances listed

represent a design goal. Although most delay

increments will fall within tolerance, they are not

guaranteed throughout the address range of the

unit. Monotonicity is, however, guaranteed over

all addresses.

Violation of this constraint may, depending on the

history of the input signal, cause spurious signals

to appear on the OUT pin. The possibility of

A7-A0

EN/

A _i-1

A_i

T_AENS

T_OAX

T_AIS

T_ENIS

PW_IN

T_DISH

TD_A

PW_OUT

T_DISO

OUT

OUT/

T_SKEW

Figure 1: Timing Diagram

Doc #97006

1/30/06

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

PDU18F

DEVICE SPECIFICATIONS

TABLE 1: AC CHARACTERISTICS

PARAMETER

Total Programmable Delay

Inherent Delay

SYMBOL

TD_T

MIN

TYP

255

14.0

1.5

UNITS

T_INC

TD₀

Output Skew

T_SKEW

T_DISO

T_AENS

T_AIS

T_ENIS

T_OAX

T_DISH

PER_IN

PW_IN

Disable to Output Low Delay

Address to Enable Setup Time

Address to Input Setup Time

Enable to Input Setup Time

Output to Address Change

Disable Hold Time

6.0

2.0

10.0

8.0

See Text

Absolute

% of TD_T

Input Period

Suggested

Recommended

Absolute

200

Input Pulse Width

Suggested

Recommended

100

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER

DC Supply Voltage

Input Pin Voltage

Storage Temperature

Lead Temperature

SYMBOL

V_CC

MIN

-0.3

-55

MAX

7.0

UNITS NOTES

V_IN

V_DD+0.3

150

T_STRG

T_LEAD

300

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 70C, 4.75V to 5.25V)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

High Level Output Voltage

V_OH

2.5

3.4

V_CC= MIN, I_OH= MAX

V_IH= MIN, V_IL= MAX

V_CC= MIN, I_OL= MAX

V_IH= MIN, V_IL= MAX

Low Level Output Voltage

V_OL

0.35

0.5

High Level Output Current

Low Level Output Current

High Level Input Voltage

Low Level Input Voltage

Input Clamp Voltage

Input Current at Maximum

Input Voltage

High Level Input Current

I_OH

I_OL

V_IH

V_IL

V_IK

I_IHH

-1.0

20.0

2.0

-60

0.8

-1.2

0.1

V_CC= MIN, I_I= I_IK

V_CC= MAX, V_I= 7.0V

I_IH

I_IL

I_OS

-0.6

-150

V_CC= MAX, V_I= 2.7V

V_CC= MAX, V_I= 0.5V

V_CC= MAX

µA

Low Level Input Current

Short-circuit Output Current

Output High Fan-out

Unit

Load

Output Low Fan-out

12.5

Doc #97006

1/30/06

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU18F

PACKAGE DIMENSIONS

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

.650

.580

MAX.

.010

±.002

9 10 11 12 13 14 15 16 17 18 19 20

2.100

Lead Material:

Nickel-Iron alloy 42

TIN PLATE

.320

MAX.

.015 TYP.

.070 MAX.

.018 TYP.

.100 TYP.

DIP (PDU18F-xx, PDU18F-xxM)

.020 TYP.

.040 TYP.

.010±.002

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

.882

.710 .590

MAX.

±.00

.007

±.00

10 11 12 13 14 15 16 17 18 19 20

.090

.100

.320

.050

±.01

MAX.

1.100

2.080±.020

Gull-Wing (PDU18F-xxC5, PDU18F-xxMC5)

Doc #97006

1/30/06

DATA DELAY DEVICES, INC.

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

PDU18F

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature: 25^oC ± 3^oC

Supply Voltage (Vcc): 5.0V ± 0.1V

Load:

1 FAST-TTL Gate

C_load

5pf ± 10%

Input Pulse:

High = 3.0V ± 0.1V

Threshold: 1.5V (Rising & Falling)

Low = 0.0V ± 0.1V

50Ω Max.

Source Impedance:

Rise/Fall Time:

3.0 ns Max. (measured

between 0.6V and 2.4V )

PW_IN= 1.5 x Total Delay

PER_IN= 4.5 x Total Delay

Pulse Width:

Period:

NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.

PRINTER

COMPUTER

SYSTEM

REF

PULSE

OUT

TIME INTERVAL

COUNTER

DEVICE UNDER

TEST (DUT)

GENERATOR

TRIG

Test Setup

PER_IN

PW_IN

V_IH

T_RISE

T_FALL

INPUT

2.4V

1.5V

2.4V

1.5V

0.6V

SIGNAL

V_IL

0.6V

TD_AR

TD_AF

OUTPUT

SIGNAL

V_OH

1.5V

V_OL

Timing Diagram For Testing

Doc #97006

1/30/06

DATA DELAY DEVICES, INC.

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU-18F-1M 相关器件

型号	制造商	描述	价格	文档
PDU-18F-2	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, PDIP40, LOW PROFILE, DIP-40	获取价格
PDU-18F-2M	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, LOW PROFILE, DIP-40	获取价格
PDU-18F-2MC5	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL,	获取价格
PDU-18F-3	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, PDIP40, LOW PROFILE, DIP-40	获取价格
PDU-18F-3M	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, LOW PROFILE, DIP-40	获取价格
PDU-18F-4	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, PDIP40, LOW PROFILE, DIP-40	获取价格
PDU-18F-4M	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, LOW PROFILE, DIP-40	获取价格
PDU-18F-4MC5	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL,	获取价格
PDU-18F-5M	DATADELAY	Active Delay Line, Programmable, 1-Func, 255-Tap, Complementary Output, TTL, LOW PROFILE, DIP-40	获取价格
PDU-18F-7	ETC	Programmable Delay Line	获取价格