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CAT24WC01LE-1.8

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CAT24WC01LE-1.8 概述

EEPROM EEPROM\n

CAT24WC01LE-1.8 数据手册

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CAT24WC01/02/04/08/16

1K/2K/4K/8K/16K-Bit Serial EEPROM

FEATURES

■ Self-Timed Write Cycle with Auto-Clear

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ 400 kHz I²C Bus Compatible*

■ 1.8 to 6.0Volt Operation

■ Low Power CMOS Technology

■ 8-pin DIP, 8-pin SOIC or 8 pin TSSOP

- "Green" package option available

■ Write Protect Feature

— Entire Array Protected When WP at V_IH

■ Commercial, Industrial, Automotive and

■ Page Write Buffer

Extended Temperature Ranges

DESCRIPTION

08/16 feature a 16-byte page write buffer. The device

operates via the I²C bus serial interface, has a special

write protection feature, and is available in 8-pin DIP, 8-

pin SOIC or 8-pin TSSOP.

The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-

bit Serial CMOS EEPROM internally organized as 128/

256/512/1024/2048 words of 8 bits each. Catalyst’s

advanced CMOS technology substantially reduces de-

vice power requirements. The the CAT24WC01/02/04/

PIN CONFIGURATION

BLOCK DIAGRAM

SOIC Package (J, W)

DIP Package (P, L)

EXTERNAL LOAD

SENSE AMPS

SHIFT REGISTERS

OUT

ACK

SCL

SDA

SCL

SDA

WORD ADDRESS

BUFFERS

COLUMN

DECODERS

5020 FHD F01

TSSOP Package (U, Y)

START/STOP

(MSOP and TSSOP available for CAT24WC01,

CAT24WC02 and CAT24WC04 only)

MSOP Package (R, Z)

SDA

LOGIC

E²PROM

XDEC

SCL

SDA

CONTROL

LOGIC

SDA

PIN FUNCTIONS

DATA IN STORAGE

Pin Name

Function

A0, A1, A2

SDA

Device Address Inputs

Serial Data/Address

Serial Clock

HIGH VOLTAGE/

TIMING CONTROL

SCL

STATE COUNTERS

Write Protect

SLAVE

ADDRESS

COMPARATORS

V_CC

+1.8V to +6.0V Power Supply

Ground

V_SS

24WCXX F03

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.

Characteristics subject to change without notice

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

Voltage on Any Pin with

Respect to Ground⁽¹⁾........... –2.0V to +V_CC+ 2.0V

V_CCwith Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current⁽²⁾........................ 100mA

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Min.

1,000,000

100

Max.

Units

Cycles/Byte

Years

Reference Test Method

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(3)

N_END

(3)

T_DR

Data Retention

ESD Susceptibility

Latch-up

(3)

V_ZAP

2000

Volts

(3)(4)

I_LTH

100

D.C. OPERATING CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Limits

Typ.

Symbol

I_CC

Parameter

Min.

Max.

Units

µA

Test Conditions

f_SCL= 100 KHz

Power Supply Current

(5)

I_SB

Standby Current (V_CC= 5.0V)

Input Leakage Current

V_IN= GND or V_CC

V_IN= GND to V_CC

V_OUT= GND to V_CC

I_LI

I_LO

V_IL

V_IH

Output Leakage Current

Input Low Voltage

–1

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

V_CCx 0.7

V_OL1

V_OL2

Output Low Voltage (V_CC= 3.0V)

Output Low Voltage (V_CC= 1.8V)

I_OL= 3 mA

0.5

I_OL= 1.5 mA

CAPACITANCE T = 25°C, f = 1.0 MHz, V

= 5V

Symbol

Test

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, SCL, WP)

Max.

Units

Conditions

V_I/O= 0V

V_IN= 0V

(3)

C_I/O

(3)

C_IN

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

(5) Standby Current (I ) = 0µA (<900nA).

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

A.C. CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Read & Write Cycle Limits

Symbol

Parameter

1.8V-6.0V, 2.5V-6.0V

4.5V-5.5V

Min.

Max.

100

Min.

Max.

400

Units

kHz

F_SCL

T_I⁽¹⁾

Clock Frequency

Noise Suppression Time

200

Constant at SCL, SDA Inputs

t_AA

SCL Low to SDA Data Out

and ACK Out

3.5

µs

(1)

t_BUF

Time the Bus Must be Free Before

a New Transmission Can Start

4.7

1.2

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

4.7

0.6

1.2

0.6

µs

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

4.7

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

Data In Hold Time

µs

Data In Setup Time

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

100

(1)(2)

Power-Up Timing

Symbol

t_PUR

Parameter

Max.

Units

Power-up to Read Operation

Power-up to Write Operation

t_PUW

Write Cycle Limits

Symbol

Parameter

Min.

Typ.

Max

Units

t_WR

Write Cycle Time

interface circuits are disabled, SDA is allowed to remain

high, and the device does not respond to its slave

address.

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t

and t

are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The CAT24WC01/02/04/08/16 supports the I²C Bus

data transmission protocol. This Inter-Integrated Circuit

Bus protocol defines any device that sends data to the

bus to be a transmitter and any device receiving data to

be a receiver. Data transfer is controlled by the Master

device which generates the serial clock and all START

andSTOPconditionsforbusaccess.TheCAT24WC01/

02/04/08/16 operates as a Slave device. Both the Mas-

ter and Slave devices can operate as either transmitter

or receiver, but the Master device controls which mode

isactivated. Amaximumof8devices(CAT24WC01and

CAT24WC02), 4 devices (CAT24WC04), 2 devices

(CAT24WC08) and 1 device (CAT24WC16) may be

connected to the bus as determined by the device

address inputs A0, A1, and A2.

SCL: Serial Clock

The CAT24WC01/02/04/08/16 serial clock input pin is

used to clock all data transfers into or out of the device.

This is an input pin.

SDA: Serial Data/Address

The CAT24WC01/02/04/08/16 bidirectional serial data/

address pin is used to transfer data into and out of the

device. The SDA pin is an open drain output and can be

wire-ORed with other open drain or open collector

outputs.

A0, A1, A2: Device Address Inputs

These inputs set device address when cascading mul-

tiple devices. When these pins are left floating the

default values are zeros.

A maximum of eight devices can be cascaded when

Figure 1. Bus Timing

HIGH

LOW

SCL

SU:STA

HD:DAT

HD:STA

SU:DAT

SU:STO

BUF

SDA IN

SDA OUT

5020 FHD F03

Figure 2. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

5020 FHD F04

Figure 3. Start/Stop Timing

SDA

SCL

5020 FHD F05

START BIT

STOP BIT

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

using either CAT24WC01 or CAT24WC02 device. All

three address pins are used for these densities. If only

one CAT24WC01 or CAT24WC02 is addressed on the

bus, all three address pins (A0, A1and A2) can be left

floating or connected to V_SS.

stable whenever the clock line is high. Any changes

in the data line while the clock line is high will be

interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDAwhenSCLisHIGH. TheCAT24WC01/02/04/08/16

monitortheSDAandSCLlinesandwillnotresponduntil

this condition is met.

A total of four devices can be addressed on a single bus

when using CAT24WC04 device. Only A1 and A2

address pins are used with this device. The A0 address

pin is a no connect pin and can be tied to V_SSor left

floating. If only one CAT24WC04 is being addressed on

thebus, theaddresspins(A1andA2)canbeleftfloating

or connected to V_SS.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

Only two devices can be cascaded when using

CAT24WC08. The only address pin used with this

device is A2. The A0 and A1 address pins are no

connectpinsandcanbetiedtoV_SSorleftfloating. Ifonly

one CAT24WC08 is being addressed on the bus, the

addresspin(A2)canbeleftfloatingorconnected toV_SS.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

most significant bits of the 8-bit slave address are fixed

as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).

Thenextthreesignificantbits(A2,A1,A0)arethedevice

addressbitsanddefinewhichdeviceorwhichpartofthe

devicetheMasterisaccessing. UptoeightCAT24WC01/

02, four CAT24WC04, two CAT24WC08, and one

CAT24WC16 may be individually addressed by the

system. The last bit of the slave address specifies

whether a Read or Write operation is to be performed.

When this bit is set to 1, a Read operation is selected,

and when set to 0, a Write operation is selected.

The CAT24WC16 is a stand alone device. In this case,

all address pins (A0, A1and A2) are no connect pins and

can be tied to V_SSor left floating.

WP: Write Protect

If the WP pin is tied to V_CCthe entire memory array

becomes Write Protected (READ only). When the WP

pin is tied to V_SSor left floating normal read/write

operations are allowed to the device.

I²C BUS PROTOCOL

ThefollowingdefinesthefeaturesoftheI²Cbusprotocol:

After the Master sends a START condition and the slave

address byte, the CAT24WC01/02/04/08/16 monitors

the bus and responds with an acknowledge (on the SDA

line) when its address matches the transmitted slave

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

Figure 4. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

5020 FHD F06

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

Figure 5. Slave Address Bits

CAT24WC01/02

A1 A0

R/W

CAT24WC04

CAT24WC08

CAT24WC16

A1 a8 R/W

R/W

a10 a9

a8 R/W

A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.

** a8, a9 and a10 correspond to the address of the memory array address word.

*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).

address. The CAT24WC01/02/04/08/16 then performs

a Read or Write operation depending on the state of the

WRITE OPERATIONS

Byte Write

R/W bit.

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

the Slave generates an acknowledge, the Master sends

the byte address that is to be written into the address

pointer of the CAT24WC01/02/04/08/16. After receiving

another acknowledge from the Slave, the Master device

transmits the data byte to be written into the addressed

memory location. The CAT24WC01/02/04/08/16 ac-

knowledge once more and the Master generates the

STOP condition, at which time the device begins its

internalprogrammingcycletononvolatilememory.While

this internal cycle is in progress, the device will not

respond to any request from the Master device.

Acknowledge

Afterasuccessfuldatatransfer, eachreceivingdeviceis

requiredtogenerateanacknowledge.TheAcknowledg-

ing device pulls down the SDA line during the ninth clock

cycle, signaling that it received the 8 bits of data.

The CAT24WC01/02/04/08/16 responds with an ac-

knowledge after receiving a START condition and its

slave address. If the device has been selected along

with a write operation, it responds with an acknowledge

after receiving each 8-bit byte.

When the CAT24WC01/02/04/08/16 is in a READ mode

it transmits 8 bits of data, releases the SDA line, and

monitors the line for an acknowledge. Once it receives

this acknowledge, the CAT24WC01/02/04/08/16 will

continue to transmit data. If no acknowledge is sent by

theMaster, thedeviceterminatesdatatransmissionand

waits for a STOP condition.

Page Write

The CAT24WC01/02/04/08/16 writes up to 16 bytes of

data in a single write cycle, using the Page Write

operation. The Page Write operation is initiated in the

same manner as the Byte Write operation, however

insteadofterminatingaftertheinitialwordistransmitted,

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

the Master is allowed to send up to fifteen additional

bytes. After each byte has been transmitted the

CAT24WC01/02/04/08/16 will respond with an

acknowledge, and internally increment the low order

address bits by one. The high order bits remain

unchanged.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to V_CC, the entire memory array is

protected and becomes read only. The CAT24WC01/

02/04/08/16 will accept both slave and byte addresses,

but the memory location accessed is protected from

programming by the device’s failure to send an

acknowledge after the first byte of data is received.

If the Master transmits more than sixteen bytes prior to

sendingtheSTOPcondition,theaddresscounter‘wraps

around’, and previously transmitted data will be

overwritten.

Once all sixteen bytes are received and the STOP

condition has been sent by the Master, the internal

programmingcyclebegins.Atthispointallreceiveddata

is written to the CAT24WC01/02/04/08/16 in a single

write cycle.

READ OPERATIONS

The READ operation for the CAT24WC01/02/04/08/16

is initiated in the same manner as the write operation

with the one exception that the R/W bit is set to a one.

ThreedifferentREADoperationsarepossible:Immediate

AddressREAD, SelectiveREADandSequentialREAD.

Acknowledge Polling

Thedisablingoftheinputscanbeusedtotakeadvantage

of the typical write cycle time. Once the stop condition

isissuedtoindicatetheendofthehost’swriteoperation,

the CAT24WC01/02/04/08/16 initiates the internal write

cycle. ACK polling can be initiated immediately. This

involves issuing the start condition followed by the slave

addressforawriteoperation. IftheCAT24WC01/02/04/

08/16isstillbusywiththewriteoperation, noACKwillbe

returned. IftheCAT24WC01/02/04/08/16hascompleted

thewriteoperation, an ACKwillbereturnedandthehost

Immediate Address Read

The CAT24WC01/02/04/08/16’s address counter

contains the address of the last byte accessed,

incremented by one. In other words, if the last READ or

WRITEaccesswastoaddressN,theREADimmediately

following would access data from address N+1. If N=E

(where E = 255 for 24WC02, 511 for 24WC04, 1023 for

24WC08, and 2047 for 24WC16), then the counter will

'wrap around' to address 0 and continue to clock out

data. If N = E (where E = 127 for the CAT24WC01) the

counter will not 'wrap around'.

can then proceed with the next read or write operation.

Figure 6. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS

DATA

SDA LINE

5020 FHD F08

Figure 7. Page Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

DATA n

DATA n+1

DATA n+P

SDA LINE

NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0

P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16

* = Don't care for CAT24WC01

24WCXX F09

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

Selective Read

operations. After the 24WC01/02/04/08/16 sends initial

8-bit byte requested, the Master will respond with an

acknowledge which tells the device it requires more

data. The CAT24WC01/02/04/08/16 will continue to

output an 8-bit byte for each acknowledge sent by the

Master. The operation is terminated when the Master

fails to respond with an acknowledge, thus sending the

STOP condition.

Selective READ operations allow the Master device to

select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte address of the location it wishes to

read. After the CAT24WC01/02/04/08/16 acknowledge

thewordaddress,theMasterdeviceresendstheSTART

condition and the slave address, this time with the R/W

bit set to one. The CAT24WC01/02/04/08/16 then

responds with its acknowledge and sends the 8-bit byte

requested. The master device does not send an

acknowledge but will generate a STOP condition.

The data being transmitted from the CAT24WC01/02/

04/08/16isoutputtedsequentiallywithdatafromaddress

N followed by data from address N+1. The READ

operation address counter increments all of the

CAT24WC01/02/04/08/16addressbitssothattheentire

memory array can be read during one operation. If more

thantheE (whereE=255for24WC02,511for24WC04,

1023for24WC08,and2047for24WC16)bytesareread

out, the counter will “wrap around” and continue to clock

out data bytes. If N = E (where E = 127 for the

CAT24WC01) the counter will not 'wrap around'.

Sequential Read

The Sequential READ operation can be initiated by

either the immediate Address READ or Selective READ

Figure 8. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SDA LINE

DATA

SCL

SDA

8TH BIT

DATA OUT

NO ACK

STOP

5020 FHD F10

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

Figure 9. Selective Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

SLAVE

ADDRESS

SDA LINE

DATA n

24WCXX F11

Figure 10. Sequential Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

5020 FHD F12

ORDERING INFORMATION

Prefix

Device #

24WC02

Suffix

CAT

-1.8

TE13

Temperature Range

Product Number

24WC01: 1K

24WC02: 2K

24WC04: 4K

24WC08: 8K

24WC16: 16K

Tape & Reel

TE13: 2000/Reel

Optional

Company ID

Blank = Commercial (0 to 70 C)

I = Industrial (-40 to 85 C)

A = Automotive (-40 to 105 C)

E = Extended (-40 to 125 C)

Operating Voltage

Blank: 2.5V - 6.0V

1.8: 1.8V - 6.0V

Package

P: PDIP

J: SOIC (JEDEC)

U: TSSOP**

R: MSOP**

L: PDIP (Lead free, Halogen free)

W: SOIC (Lead free, Halogen free)

Z: MSOP (Lead free, Halogen free)**

Y: TSSOP (Lead free, Halogen free)**

** Available for CAT24WC01, CAT24WC02 and CAT24WC04

Notes:

(1) The device used in the above example is a CAT24WC02JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating

Voltage, Tape & Reel)

Doc. No. 1022, Rev. F

CAT24WC01/02/04/08/16

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™

AE²™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Publication #: 1022

Revison:

Issue date:

Type:

9/23/02

Final

Fax: 408.542.1200

www.catalyst-semiconductor.com

Doc. No. 1022, Rev. F

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