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L6237

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L6237 数据手册

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L6237

5V SPINDLE MOTOR DRIVER

PRODUCT PREVIEW

OPERATES FROM 5V SUPPLY

1.5A MAXIMUM START-UP CURRENT

INTEGRATED PHASES COMMUTATION SE-

QUENCER

PROGRAMMABLE SLEW RATE

BACK EMF COMPARATOR OUTPUT

BRAKE FUNCTION INPUT WITH USER CON-

FIGURABLE DELAY

LOW POWER CONSUMPTION MODE

OVER TEMPERATURE PROTECTION

TQFP64L

DESCRIPTION

patible, and an internal TransconductanceLoop is

included for linear motor speed control. Upper N-

Channel DMOS Transistors are driven via an In-

ternal Step-Up Converter. The IC will be manu-

factured in a plastic TQFP64 surface mount

package.

The L6237 is a Triple Half bridge Driver intended

for use in brushless DC motor applications. The

device is designed to drive a Three Phase,

Brushless DC Motor, Typically used in Rigid Disk

Drives. Power drivers are fabricated in DMOS

Technology and feature Fast Internal Recircula-

tion Diodes. All logic inputs are CMOS/TTL com-

BLOCK DIAGRAM

1/11

September 1993

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

L6237

PIN CONNECTION (Top view)

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V_DS(sus)

V_P

Output Sustaining Voltage

Supply Voltage

V_I

Logic Input Voltage Range

-0.3 to V_P

-0.3 to VP

2.0

V_IN

Transconductance Loop Input Voltage Range

Peak Current (Pulsed: T_ON= 5ms; D.C. = 10%) Tj = 25°C

Maximum Junction Temperature

I_PEAK

T_jmax

I_max

Ptot

T_amb

T_stg

145

°C

Maximum Current (D.C.)

1.2

Total Power Dissipation at T_amb= 70°C

Operating Ambient Temperature

0.85

ÉC

°C

-0 to 70

-40 to 150

Storage Temperature

THERMAL DATA

Symbol

Parameter

Thermal Resistance Junction-Ambient (*)

Value

Unit

R_{th j-amb}

°C/W

(*) Mounted on board with minimized copper area.

2/11

L6237

PIN FUNCTIONS

Name

Function

1, 2, 9, 11, 12, 15,

16, 17, 18, 24, 25,

31, 32, 33, 34, 44,

47, 48, 49, 50, 56,

57, 63, 64

N.C.

Not Connected.

3, 4, 13, 14

26, 27

54, 55

OUT B

OUT C

OUT A

The outputs of the three DMOS half bridge drivers.

MUX_SGL Logic input used to configure BEMF output to be multiplexed (high) or a single

output (low).

6, 7, 8, 39, 40, 41, 42

GND

V_DD

Ground.

Power supply for internal circuitry. 5V power supply must be connected directly

to pin.

FREF

BEMF

CTAP

Used as time reference for internal period and mask counters.

Output for BEMF comparator.

Input for center tap of motor.

22, 23, 45, 46

5V power supply for the DMOS drivers. Series Schottky diode may be used in

applications where BEMF voltage must be used for head parking.

V_IN

Input for motor current control voltage.

COMP

A capacitor and resistor are connected to this pin for external compensation of

the transconductance loop.

SLEW

Input for connection of a resistor for configuration of the output slew rate during

commutation.

35, 36, 37, 58, 59

SENSE

Pin for connection of RSENSE, an external resistor used to sense the motor

current

CBOOST

LBOOST

PD_CAP

BRK

Pin for connection of capacitor to ground for the internal step up converter.

Pin for connection of inductor to V_DDfor the internal step up converter.

External capacitor to ground which stores energy for use during braking.

Active LOW logic input that turns off all drivers, and triggers the delayed brake.

Pin for connection of external RC network to configure delay of braking.

BRK_DLY

GAIN

Logic input to configure the gain in the current sense feedback loop (K). Low

state produces gain of 4, high state produces a gain of 16.

CLOCK

RESET

Rising edge triggered input used to increment the commutation sequencer.

Logic input used in conjunction with CLOCK. For CLOCK = Low and RESET =

high the sequencer is forced to state 1. For CLOCK = high and RESET = high

an immediate BRAKE is initiated. An immediate BRAKE implies no delay.

3/11

L6237

ELECTRICAL CHARACTERISTICS (V_P= 5V; Tamb = 25°C; unless otherwise specified.)

Symbol

Parameter

Power Supply voltage

Supply Current

Test Condition

Min.

Typ.

Max.

Unit

V_P

I_P

4.5

5.5

Drivers off

brake = high

brake = low

I_DSX

Output leakage Current

Ω

R_DS(ON)

Sink Output ON Resistance

Source Output ON Resistance

Source Saturation Voltage

Sink Saturation Voltage

T_j= 125°C

0.75

1.3

0.3

V_DS(SAT)

I_DS= 1A T_j= 125°C

V_F

t_PRK

t_BRK

I_er

Body Diode Forward Drop

Maximum Brake Delay Time

Maximum Brake Time

I_DS= 1A

BRK → 0V or V_P→ 0V;

C_PDCAP= 4.7µF; R_DSON≤ 4Ω

Error Amplifier Input Bias

Current

µA

V_EAR

Error Amp. Input Linear Range

Sense Amplifier Gain

Gain = Low

Gain = High

V/V

Sense Amp. Input Bias Current

µA

V_SAR

V_CLO

Sense Amp. Input Linear Range Gain = Low

Gain = High

0.25

Current Loop Total Offset

Voltage

TBD

V_INH

V_INL

I_INH

Logic Input Voltage

0.8

Logic Input Current

V_IN= 5V

V_IN= 0V

Upper

µA

µs

°C

µF

I_INL

t_don1

t_don2

t_doff1

t_doff2

T_sd

Upper/Lower Turn-on Delay

Upper/Lower Turn-off Delay

TBD

160

Lower

Upper

Lower

Shutdown Temperature

Recovery Temperature

T_sdr

120

C_BOOST

Step-up Converter

Storage Capacitor

L_BOOST

Step-up Converter

Charging Inductor

220

150

µH

dv/dt

DMOS Output Turn-off Slew rate R_SLEW= 100K

mV/µs

I_OMAX

BEMF Output Source/Sink

Current

V_DROP= 0.4V

±0.36

T_INC

F_CLK

R_CT

Min. Clock Pulse width to

Increment Sequencer

V_DD= 5V

500

Max. Sequencer Clock

Frequency (50% D.C.)

V_DD= 5V

MHz

KΩ

Value of ”Y” Connected Center

Tap Resistors

F_REF

Max. FREF Clock Frequency

(50% D.C.)

V_DD= 5V

MHz

4/11

L6237

Figure 1: SequencerTiming Diagram.

SEQUENCER STATES

OUTA OUTB OUTC

SEQUENCER TRUTH TABLE

RESET MUX_SGL OPERATING MODE

Single BEMF

CLK

STATE1

STATE2

STATE3

STATE4

STATE5

STATE6

I+

I-

Drivers

Enabled

MUX BEMF

I+

I-

Initialize Sequencer

Tri-State, MUX BEMF

Logic Brake, Initialize Seq.

I-

I+

I-

X = DON’T CARE

↑ Indicates not level sensitive, increments sequencer on positive edge

LOGIC BRK

I-

(SEQ->STATE1)

I+: Upper On, I-:Lower On, 0: Tri-State

will track the current floating phase, as deter-

SPINDLE DRIVE FUNCTIONAL DESCRIPTION

mined by the sequencer state. When SGL mode

is active, only the C output BEMF is provided.

The commutation is accomplished via three logic

inputs (CLOCK, RESET, MUX_SGL). A positive

transition at the clock input will increment the in-

ternal sequencer producing commutation to the

next phase (refer to logic truth table for explana-

tion of sequencer operations).

The L6237 performs internal sensing of the Back

Electromotive Force (BEMF), giving a CMOS

compatible logic output signal that is high or low if

the current BEMF voltage is respectivelyabove or

below the central tap voltage. For application in

which the center tap is not connectable to the

relative input pin, three resistors are internally

available from outputs in a ”Y” configuration to

simulate the presence of the center tap. The

BEMF comparator input is internally switched to

the output phase that is in tristate condition, while

the output is selectable via the MUX_SGL input.

When MUX mode is selected the BEMF output

The L6237 performs an adaptive digital mask to

block unwanted zero crossing generated during

phases commutation. This mask is activated

when a positive CLOCK transition increments the

sequencer, and remains active for a period that is

one fourth of the period between two zero cross-

ing. Considering that a full increment of the se-

quencer(one ”electrical” revolution) gives 6 differ-

ent output states, the period between two

commutation can be considered of 60 electrical

degrees, so that the masking time is 15 electrical

degrees. An input clock signal FREF is requireed

as a time base for the internal mask counters.

The BRK and BRK_DLY inputs offer flexibility to

the system designer in the implementation of the

braking function. The BRK input, when pulled low,

turns off all upper and lower DMOS drivers. This

5/11

L6237

way the outputs are in tristate condition, and

since no brake is applied to the motor, it will con-

tinue its rotation, giving a BEMF voltage propor-

tional to its speed. The low transition at BRK input

will also produce a delayed negative transition at

the BRK_DLY input. This delay is configurable by

connecting a capacitor and resistor from the

BRK_DLY pin to ground. The negative transition

at this pin will initiate the braking of the motor by

turning on all lower DMOS, keeping all upper

DMOS turned off. This feature provides a time in-

terval where the motor acts as a generator,

whose BEMF can be used to power the

Read/Write Parking function. As soon as the head

has been parked, the motor can be really braked,

stopping its rotation in a very short time. The

brake function utilizes the energy stored in an ex-

ternal capacitor to turn on or off the DMOS pow-

ers. This allows the braking procedure even if the

Vp supply has been powered down. Additionally,

while in brake mode, part of the analog circuitry is

turned off and the quiescent current is minimized.

This is useful in battery operated sistems when

disk access is minimal. An immediate brake can

be realized by simultaneously driving RESET and

CLOCK high, and MUX_SGL low. This will turn

off the upper drivers turning on the lower drivers.

Braking occurs regardless of the condition of the

BRK_DLY input.

BRAKE DELAY

The amount of time that a signal transition takes

to propagate from BRK to BRK_DLY pins can be

determined by the espression

Td 1.5 RC

[ms]

where R and C are the values of the resistor an

capacitor connected to BRK_DLY pin. With the

above expression the value of Td is expressed in

milliseconds.

TRANSCONDUCTANCE LOOP GAIN

The transconductanceis given by the expression:

Gm = 1/(K Rsense)

Where K can be 4 or 16 depending on the state

of pin GAIN. If GAIN=0, K=4; if GAIN=1, K=16. As

a result the total current flowing in the motor is:

Im = Gm Vin = Vin/(K Rsense)

where Vin is the voltage applied to pin V .

SLEW RATE CONTROL

By means of an external resistor it is possible to

configure the turn off slew rate following this ex-

pression:

SR = 15/Rslew(KΩ) [V/µs]

Motor current is determined by a voltage imposed

on the VIN input. The SENSE pins are intended

for connection of a resistor in series with the

source of all lower DMOS. The voltage at this pin

provides the feedback signal which is utilized in-

ternally to regulate the motor current. This one

can be determined by the expression Imotor =

Vin/K*Rsense where K is the voltage gain of the

sense amplifier. A value of 4 or 16 is selectable

by the GAIN logic input. The current is regulated

by a linear transconductance loop which drives

the lower DMOS. The control is passed to each

lower DMOS in succession during the commuta-

tion sequence.

Rslew is the resistor connected to pin SLEW and

its value is espressed in Kohms, while the SR

value will be V/µs.

DIGITAL BEMF MASKING: THEORY OF OP-

ERATION

A 9 bit up counter is used to measure the period

between to successive zero crossings. This ”pe-

riod counter” counts

frequency that is

FREF/2E6 = FREF/64. When a new zero crossing

is detected, the period counter will transfer its

contents to the 6 bit down counter that is the real

”mask counter”.

To avoid recirculation of the current flowing in the

coils of the motor when each phase is commu-

tated, the turn off slew rate of the upper an lower

drivers is externally configurable using a single

resitor. This defines a current that is internally

used to discharge a capacitor. The profile of the

voltage across this capacitor will be reproduced at

the output, performing the slew rate control. Be-

cause of this control the current flowing in the

The up counter will then reset to zero and com-

mence the counting of the following period. Since

that the mask counter uses a frequency that is

FREF/2E7 = FREF/128, that is half of the fre-

quency used by the up counter, the final masking

time will be one fourth of the period between to

successive zero crossings or, in other terms, 15

electrical degrees.

switched off coil will decrease to zero with

quadratic slope, while the total current in the mo-

tor is kept constant by the transconductanceloop.

During start up, when the period is quite large, the

period counter will saturate when all bit are in ”1”

state, providing a maximum mask interval. As the

motor speed increases, a fixed masking time will

be applied until the period between two commuta-

tions is less than the maximum time of the period

counter.

Thermal protection circuitry will shut off all drivers

when the chip junction temperature exceeds the

threshold temperature. A small amount of hyster-

esis is included to prevent rapid on/off cycling of

the power stages.

This means that the masking time will be propor-

tional for commutations period that are less than

CIRCUIT OPERATION AND FORMULAS

6/11

L6237

2E9/(FREF/64).

There are three parameters that are affected by

the choice of FREF:

Figure 2: Typical Normalized R_{DS (on)}vs.

Junction Temperature.

1)Maximum masking time, Tmax, that can be

calculated as:

Tmax = 2E6/(FREF/128) = 2E13/FREF

2)Minimum time resolution of the mask counter,

that is 1 bit or:

Tres = 128/FREF

3)Truncation error, Et, coming from the appros-

simation caused by the division by 4, that

will typically generate non integer numbers,

whose decimals will be skipped. This error is

again one bit (with the period of the frequency

used by the down counter) or:

Et = 128/FREF

As a result of the above the maximum error of the

masking time can be up to:

Emax = Tres + Et = 256/FREF

Figure 3: Typical Transient Thermal Impedance

Please note that the truncation error is not fixed,

but depends from the period count and can also

be null if the count between two zero crossings

can be exactly divided by 4.

vs. Time or Pulse Width

As an example, we can consider the case of an

8pole, three phases motor rotating at 5400 rpm.

Let consider FREF = 8MHz.

8 poles → 4 electrical cycles for each mechani-

cal revolution

and

SINGLE PULSE

3 phases → 6 commutations for each electrical

cycle

therefore:

Commutation Frequency

= 5400 rev/min *

1min/60seconds* 24comm/rev = 2160Hz.

This means that the commutation period is about

463 microseconds. Considering the above ex-

pression we will have:

APPLICATION INFORMATION

Tmax = 2E13/8E6 = 1.024ms

A typical application configuration of the L6237

driving a three phase brushless sensorless DC

motor is shown in Fig.6.

The spindle motor typically is a 2.5” Rigid Disk

Driver having 1.3Ω - 0.1mH per phase, star con-

nected.

This kind of load requires a suitable compensa-

tion of the linear control loop that can be achieved

by an RC network of 10K and 10nF, connected to

the ”COMP” pin.

Changing the motor characteristics, the RC net-

work could be modified for the best performances

of the system.

This is a suggestion about how to choose the

value of the RC compensationnetwork of the cur-

rent loop: the following figure shows the entire

control system of the current regulator.

The error amplifier is a transconductance ampli-

fier. It is used in open loop configuration inside

the main control loop and its gain and frequency

This means that the masking time will be propor-

tional starting from a commutation period lower

than 4Tmax = 4.096ms that means a speed

higher than 610 rpm. Additionally we will have:

Tres = 128/FREF = 16µs

Emax = 256/FREF = 32µs

With a commutation period of 463 microseconds,

we should have a masking time of 463/4 = 116µs

so that we obtain:

Accuracy = 32/116 = 27.6%

This is the maximum error. Considering the real

situation and mainly the real truncation error we

will have in this particular situation an Emax=20

microseconds so that the accuracy is about

17.3%

7/11

L6237

Figure 4.

response are determined by a compensationnet-

work connected between its output and ground.

This OTA has a large bandwidth (300KHz) and so

its pole does not interfere with the pole and zero

of the Motor + Power Mos system and of the

compensation network. In the application the RC

network gives an high system gain at low fre-

quency to ensure good precision and a low gain

at high frequency to ensure stability of the sys-

tem. The figure 5 shows the Bode plot of the com-

pensated error amplifier plus power stage and

motor.

To drive the upper DMOS a voltage higher than

the power supply Vp is needed. The step-up inte-

grated in the L6237 keeps the CBOOST storage

capacitor at the correct voltage.

The switching of the internal step-up circuit can

create some noise that could disturb the current

control loop. In order to minimize the interference

between the step-up circuit and the linear control

loop of the output current is suggested to choose

an LBOOST of 220µH with an equivalent series

resistor minimum of 2Ω.

Another way to decoupling the noise effects of the

step-up from the linear control loop is taking care

in the PC BOARD design about the GROUND

path.

The charging current of the inductor, for the inter-

nal step-up converter, flowing through the pin

LBOOST (43) is coming out from the device at

GND pin 42.

The RC value of the compensating network must

be choosen to have for high frequencies a flat

gain of about 20dB so that the double pole of the

motor makes the Bode diagram change its slope

and decrease with 40dB/decade stabilizing the

whole system cutting the bandwidth. An empiric

way to find good RC value for compensation net-

work can be the follow:

A good solution is to keep separate in the PC

BOARD the GND track connectionof this pin (42)

from the other GND pins (6,7,8,40,41).

1)set a great value of C in order to not interfere

at high frequencies

Pin 37 of the device is the input of the internal

sense amplifier (see Fig. 4).

2)give, with motor completely stopped, an exci-

tation as voltage step and act on R in order to

get an acceptable current overshoot

3)decrease the value of C until to have a good

gain at low frequencies.

The voltage at this pin provides the feedback sig-

nal which is internally used to regulate the mo-

torurrent.

In order to have no differences in regulated cur-

Figure 5.

8/11

L6237

rent level of the three phase currents, is sug-

gested to connect the sense resistor using two

differents tracks: one for the connection of the

sources of the output DMOS (pins 35, 36, 58,

59) and another one for the sense amplifier input

(pin 37).

The typical application of the L6237 is in HDD

systems where there is the need to park the

Read-Write Heads before the motor braking.

At power supply switch-off the BRK input is driven

low (Active Low), so the power output stage is

switched in a high impedance state. The schottky

diode 1N5818 insulates the L6237 from the main

power supply. The spindle motor now, acting as a

three-phase alternator, supplies the Heads voice-

coil motor through integrated diodes that rectifie

the EMFvoltage. After a delay longer than the

parking time, the lower output DMOS can be

switched-on and the spindle motor is braked.

Figure 6: Application Circuits

9/11

L6237

TQFP64 PACKAGE MECHANICAL DATA

inch

TYP.

DIM.

MIN.

TYP.

MAX.

1.85

0.25

1.50

0.28

0.20

12.60

MIN.

MAX.

0.073

0.010

0.059

0.011

0.0079

0.496

1.30

0.18

0.12

1.40

0.23

0.16

0.051

0.007

0.055

0.009

0.0047

0.0063

10.00

7.50

0.50

0.394

0.295

0.0197

12.60

0.496

10.00

7.50

0.50

0.394

0.295

0.40

0.60

1.30

0.0157

0.0197

0.0236

0.052

0°(min.), 5°(max.)

0.10mm

Seating Plane

PQFP64

10/11

L6237

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men-

tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex-

press written approval of SGS-THOMSON Microelectronics.

1994 SGS-THOMSON Microelectronics - All RightsReserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -

Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.

11/11

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