QL901M-6PS680I中文资料_数据手册_规格书

QL901M QuickMIPS™ Data Sheet

QuickMIPS ESP Family

• • • • • •

1.0 Overview

The QuickMIPS™ Embedded Standard Products

(ESPs) family provides an out-of-the box solution

consisting of the QL901M QuickMIPS chip and

the QuickMIPS development environment. The

development environment includes a Reference

Design Kit (RDK) with drivers, real-time

operating systems, and QuickMIPS system

model. With the RDK, software and hardware

engineers can evaluate, debug, and emulate

their system in parallel.

• 16 Kbytes of on-chip, high-speed SRAM for

use by multiple AHB Bus Masters

• 32-bit 66/33 MHz PCI Host and Satellite

(Master/Target) operation with DMA

channels and FIFO for full bandwidth

• Two MAC10/100s with MII ports connect

easily to external transceivers/PHY devices

• One AHB 32-bit master port/one AHB

32-bit slave port to Programmable Fabric

• Global System Configuration and Interrupt

Controller

CPU

Peripheral Bus (AMBA APB)

• High-performance MIPS 4Kc processor runs

up to 133 MHz in .25µ

• 32-bit APB runs at half the CPU clock

(173 Dhrystone MIPS)

frequency (the same as the AHB clock)

• 1.3 Dhrystone MIPS per MHz

• Three APB slave ports in the programmable

• MDU supports MAC instructions for

fabric

DSP functions

• Two serial ports (one with Modem control

• 16 Kbytes of Instruction Cache

signals and one with IRDA-compliant signals)

(4-way set associative)

• Four general-purpose 32-bit timer/counters

• 16 Kbytes of Data Cache (4-way set

on one APB port

associative) with lockout capability per line

16 Kbytes

SRAM

MIPS 4Kc

w/Caches

32-bit PCI

66/33 MHz

Ethernet

Memory

Controller

Interrupt

Controller

10/100 MAC 10/100 MAC

High-Performance Bus (AMBA AHB)

ECI to AHB

AHB to APB

• High-performance 32-bit AMBA AHB bus

standard for high-speed system bus running

at half the CPU clock

32-bit Advanced High-Performance Bus

Two 16550

UARTs

Four 32-bit

Timer/Counters

• High-bandwidth memory controller for

SDRAM, SRAM, and EPROM

32-bit Advanced Peripheral Bus

• SDRAM support for standard SDRAMs up to

256 MBytes with auto refresh, up to 4 banks

non-interleaved

36 RAM Blocks (Configurations 128x18; 256x9; 512x4; or 1024x2)

Configurable

3 APB

Slave

I/F

JTAG

Logic Analyzer

• Support for PC100 type memories with up

Via-Link Programmable Fabric

Monitor (CLAM)

1 AHB

Master I/F

to two chip enables

1 AHB

18 ECU Blocks-- 8x8 Multiply, 16-bit carry/add

• EPROM controller for boot code

Slave I/F

• 8-bit, 16-bit, and 32-bit device width support

Figure 1: Embedded QuickMIPS Block Diagram

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QL901M QuickMIPS^TMData Sheet Rev B

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Programmable Via-Link Fabric

• Embedded memory configurable as RAM or FIFO

• 252 programmable I/Os

• High-speed dynamically configurable ECUs enable hardware implementation of DSP functions with

3-bit instructions

• Fabric I/O standard options: LVTLL, LVCMOS, PCI, GTL+, SSTL, and SSTL3

Table 1: Programmable Fabric Features

Logic Arrays

Columns x Rows

Maximum

Flip-Flops

Maximum System Gates*

536,472

Logic Cells

RAM Blocks** RAM Bits ECU Blocks***

72x28

2,016

4,788

36

82,944

18

** Possible Configurations:

128x18, 256x9, 512x4, or 1024x2

*** 8x8 Multiply,

16-bit carry-add

* 75K ASIC gates

On-Chip Debug Blocks

• On-chip instrumentation blocks for debug and trace capabilities

• Configurable Logic Analysis Module (CLAM) blocks with IP in programmable fabric allow user to look

at selected signals from IP function in fabric

Development and Programming

• Complete QuickLogic software suite of development tools enables rapid implementation of IP

functions for complete SOC solution

• Complete chip simulation of user-defined programmable-logic IP functions with the processor,

caches, memory, and all hardwired functions on-chip

• Synthesis of IP functions into the programmable fabric

• Place-and-Route tool for efficient implementation of IP functions in the programmable fabric

• Extensive timing analysis of IP functions with the rest of the chip to ensure full chip functionality

• Programming and debug support of the entire chip through JTAG port

• Integrated debug support for the MIPS 4Kc processor

• MIPS Language and Debug tool support for the MIPS 4Kc processor from approved third party

MIPS vendors

• ECU support for a variety of DSP algorithms and functions

• QuickLogic library of standard IP functions for plug-and-play implementation of standard IP functions

in the programmable fabric for a complete SOC solution

• QuickMIPS Reference Design Kit (RDK) provides a complete Board Support Package for

chip evaluation

• Programming and debug support

• Device-driver support for standard IP functions

• Boot-up code and diagnostics

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Design Tools Platform Support

• QuickWorks, the complete product suite, supports Windows 95/98/NT/2000. It includes SpDE

(layout including place & route, timing analysis, and back-annotation), Synplify-Lite (synthesis), Turbo

Writer (HDL-enhanced text editor), etc.

• QuickTool supports Solaris. It has only the layout software (SpDE).

• QuickMIPS simulation is enabled through either:

• a SmartModel (VMC-generated model, encrypted RTL, relatively slow). This option supports both

Verilog and VHDL.

• SaiLAhead co-verification platform from Saivision (very fast C model). This option only supports

Verilog (no VHDL) at this time.

Table 2: Design Tools Platform Support

Solaris

Windows NT Windows 2000

Linux

Synthesis

Layout

Synplify-Lite

SpDE

X (in QuickWorks) X (in QuickWorks)

X (in QuickTool) X (in QuickWorks) X (in QuickWorks)

ModelSim/VCS

X

SmartModel

SaiLAhead

Verilog XL/NC

ModelSim

Simulation

X

Verilog XL/NC

SaiLAhead Platform

The “SaiLAhead for QuickMIPS” co-verification platform is tailored for QuickMIPS devices. It enables

simulation of user-defined logic functions that are to be implemented in the QuickMIPS programmable

fabric with the rest of the QuickMIPS fixed system logic functions, which verifies overall QuickMIPS

functionality. Simultaneously, the SaiLAhead platform has a powerful, feature-rich debugger, which

enables QuickMIPS users to develop and debug their application code (C and MIPS assembly). The

SaiLAhead platform accelerates the speed of simulation of the QuickMIPS device in a simulator such as

NC-Verilog by using C models for various fixed system logic functions in the QuickMIPS device. This

platform also provides a standalone C environment offering additional speed-up of simulation of the

entire QuickMIPS design. Please refer to http://www.saivision.com for more information on the

SaiLAhead platform.

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QL901M QuickMIPS™ Data Sheet Rev B

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2.0 Embedded Computational Units (ECUs)

Traditional programmable logic architectures do not implement arithmetic functions efficiently or

effectively. These functions require high logic cell usage while garnering only moderate performance

results. By embedding a dynamically reconfigurable computational unit, the QuickMIPS chip can address

various arithmetic functions efficiently and effectively providing for a robust DSP platform. This

approach offers greater performance than traditional programmable logic implementations. The ECU

block is ideal for complex DSP, filtering, and algorithmic functions. The QuickMIPS architecture allows

functionality above and beyond that achievable using DSP processors or programmable logic devices.

The embedded block is implemented at the transistor level with the following block diagram in Figure 2.

16

8

Abus

Xbus

Ybus

8

Multiply

Add

Register

3

2

1

I bus

Sign

17

Rbus

Sequencer

Memory

Logic Cell

Figure 2: Embedded Computational Unit (ECU) Block Diagram

Table 3: ECU Comparisons

Slowest Speed

Function

Description

Fastest Speed Grade

Grade

16 bit

32 bit

64 bit

8 x 8

8 ns

2.5 ns

5.6 ns

Adder

10 ns

12 ns

6.7 ns

10 ns

4.3 ns

Multiplier

16 x 16

12ns

6.7 ns

System Clock

200 MHz

400 MHz

Implementation of the equivalent ECU block as HDL in a programmable logic architecture requires 205

logic cells with a 10 ns delay in a -4 speed grade. There are a maximum of 18 ECU blocks and a

minimum of 10 ECU blocks in the QuickMIPS chip. The ECU blocks are placed next to the RAM

circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations.

Eighteen 8-bit Multiply Accumulate functions can be implemented per cycle for a total of 2.6 billion

MACs/s when clocked at 144 MHz. Further Multiply Accumulate functions also can be implemented in

the programmable logic.

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The ECU block can be configured for eight arithmetic functions via an instruction as shown in Table 4.

The modes for the ECU block are dynamically reprogrammable through the Instruction Set Sequencer.

Table 4: ECU Mode Select Criteria

Instruction Set

Operation

Multiply

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Multiply - Add

Accumulate

Add

Multiply (registered)

Multiply - Add (registered)

Multiple - Accumulate

Add (registered)

The Sequencer can be a variety of logic operators, such as a FIFO loaded with various algorithms, an

external software driven algorithm, or an internal state machine. This flexibility allows the designer to

reconfigure the ECU for algorithmic intensive applications in which functions change on the next clock

cycle, such as adaptive filtering.

3.0 Design Flow

The QuickMIPS design flow, similar to ASIC design flow, is shown in Figure 3.

MIPS Programming System Configuration Customer IP Design in FPGA

Compiler,

Assembler, Linker

Global Register

Configuration

QuickIP Models

Synthesis Lib

RTL

Debugger

Synthesis

EJTAG

Place & Route

Timing Analysis

QuickMIPS

System

Model

Timing Lib

Board-level

Support Package

Final Netlist

& Timing

QuickIP Netlist

Full-System

Functional Co-simulation

with Timing

Chip Programming

Figure 3: QuickMIPS Hardware/Software Co-Development Flow

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QL901M QuickMIPS™ Data Sheet Rev B

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A typical design process goes through the flow shown above. After passing postlayout simulation,

QuickMIPS devices can be programmed for testing on the hardware testbench. Because QuickLogic

devices are One-Time-Programmable (OTP), it is recommended that these devices are programmed only

after they pass postlayout simulation to minimize development cost and reduce bench debugging time.

The QuickMIPS design flow is supported by QuickLogic's QuickWorks™ (for Microsoft Windows) and

QuickTool™ (for UNIX) design software suites version 9.2 and up. Many third-party synthesis and

simulation tools are also supported. The QuickWorks software suite can be downloaded from

QuickLogic's Web site (www.quicklogic.com). Please contact a QuickLogic sales representative to

obtain a license or get QuickTool software.

Both Verilog and VHDL design methodologies are fully supported. The flow described below assumes

that the QuickWorks or QuickTool 9.2 software has been installed.

3.1 Simulation

QuickLogic provides the system simulation environment. This environment includes the QuickMIPS

VMC model, ROM and RAM models, reset and clock generation, boot code, and sample programs (read

and write to memory). This environment allows customers to focus on their RTL code and not have to

worry about bringing up the system simulation environment.

The simulation behavior of the QuickMIPS ESP core is provided by the VMC model. VMC (Verilog

Model Compiler) is a tool from Synopsys that compiles Verilog RTL (Register-Transfer-Level) code into

binary code. A VMC model (the binary code) implements the same logic functions as the RTL code while

providing IP protection. In simulation, it communicates to the simulator via PLI (Programmable

Language Interface) for Verilog or FLI (Foreign Language Interface) for VHDL.

Because of the VMC model, the Silos III Verilog simulator and Active-HDL VHDL simulator bundled in

QuickWorks are not supported in QuickMIPS simulation flow. A third-party simulator must be used. The

currently supported simulators include:

• Verilog simulators: Verilog-XL, NC Verilog, VCS, ModelSim

• VHDL simulators: VSS, ModelSim

3.2 Synthesis

Synthesis is the process of turning the HDL code describing the fabric behavior into gates. Three third-

party synthesis tools are supported:

• Synplify-Lite from Synplicity (bundled in QuickWorks)

• Exemplar Leonardo Spectrum

• Synopsys Design Compiler

Refer to the corresponding QuickNotes on the QuickLogic support Web site for further information.

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3.3 Layout

Layout is performed in SpDE, which is the QuickLogic layout environment in both QuickWorks and

QuickTool. The input to the layout is a netlist from synthesis. SpDE can accept netlists in both the

QuickLogic format (.qdf) and industry standard EDIF.

3.4 Programming

Once it has been determined that the design is functionally correct and meets the desired timing

constraints, run the sequencer and save the <design>.chp file. You can either import the design into

QuickPro if you want to program it yourself, or submit the file to QuickLogic's WebASIC service to obtain

programmed devices overnight at the following URL: www.quicklogic.com/webasic.

QuickPro is the software to program a .chp file into QuickLogic devices. It is freeware and does not

require a license. You can download it from the QuickLogic Web site. It runs only on Microsoft Windows-

based PCs. To program your device, you also need a programmer called DeskFab and a programming

adapter for the package you are using. Please contact a QuickLogic sales representative when you are

handling the programming.

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QL901M QuickMIPS™ Data Sheet Rev B

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4.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=0.74)

The AC Specifications, Logic Cell diagrams, and waveforms are provided below.

Figure 4: QuickMIPS Logic Cell

Table 5: Logic Cells

Symbol

Parameter

Propagation

delay (ns)

Logic Cells

tPD

Combinatorial delay: time taken by the combinatorial circuit to output

0.257

0.22

Setup time: the amount of time the synchronous input of the flip flop must be stable before

the active clock edge

tSU

Hold time: the amount of time the synchronous input of the flip flop must be stable after the

active clock edge

thl

0

Clock to out delay: the amount of time the synchronous input of the flip flop must be stable

after the active clock edge

tCLK

0.255

tCWHI

Clock High Time: the length of time that the clock stays high

Clock Low Time: the length of time that the clock stays low

0.46

tCWLO

Set Delay: amount of time between when the flip flop is “set” (high)

and when Q is consequent “set” (high)

tSET

tRESET

tSW

0.18

0.09

0.3

Reset Delay: amount of time between when the flip flop is “reset” (low) and when Q is

consequent “reset” (low)

Set Width: length of time that the SET signal remains high

(low if active low)

Reset Width: length of time that the RESET signal remains high

(low if active low)

tRW

0.3

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SET

D

Q

CLK

RESET

Figure 5: Logic Cell Flip Flop

CLK

tCWI (min)

tCWLO (min)

SET

RESET

Q

tRESET

tRW

tSET

tSW

Figure 6: Logic Cell Flip Flop Timings - First Waveform

CLK

D

Q

tHL

tSU

tCLK

Figure 7: Logic Cell Flip Flop Timings - Second Waveform

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QL901M QuickMIPS™ Data Sheet Rev B

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Figure 8: QuickMIPS Global Clock Structure

Table 6: QuickMIPS Clock Performance

Clock Performance

Global

Dedicated

1.51 ns

2.06 ns

0.55 ns

1.59 ns

1.73 ns

0.14 ns

Macro

I/O

Skew

Table 7: QuickMIPS Input Register Cell

Symbol

Input Register Cell Only

tGCKP

Parameter

Propagation delay (ns)

Global clock pin delay to quad net

1.34

0.56

GCKB

Global clock buffer delay (quad net to flip flop)

Global Clock Buffer

Programmable Clock

Hardware Clock

Global Clock

tPGCK

tBGCK

Figure 9: Global Clock Structure Schematic

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[9:0]

WA

RE

RCLK

[17:0]

WD

WE

[9:0]

RA

RD

[17:0]

WCLK

MODE

[1:0]

ASYNCRD

QuickRAM Module

Figure 10: RAM Module

Table 8: RAM Cell Synchronous Write Timing

Symbol

RAM Cell Synchronous Write Timing

Parameter

Propagation

delay (ns)

WA setup time to WCLK: the amount of time the WRITE ADDRESS must be

stable before the active edge of the WRITE CLOCK

tSWA

tHWA

tSWD

tHWD

tSWE

tHWE

tWCRD

0.675

0

WA hold time to WCLK: the amount of time the WRITE ADDRESS must be

stable after the active edge of the WRITE CLOCK

WD setup time to WCLK: the amount of time the WRITE DATA must be stable

before the active edge of the WRITE CLOCK

0.654

0

WD hold time to WCLK: the amount of time the WRITE DATA must be stable

after the active edge of the WRITE CLOCK

WE setup time to WCLK: the amount of time the WRITE ENABLE must be

stable before the active edge of the WRITE CLOCK

0.623

0

WE hold time to WCLK: the amount of time the WRITE ENABLE must be stable

after the active edge of the WRITE CLOCK

WCLK to RD (WA=RA): the amount of time between the active WRITE CLOCK

edge and the time when the data is available at RD

4.38

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QL901M QuickMIPS™ Data Sheet Rev B

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WCLK

WA

tSWA

tSWD

tHWA

tHWD

tHWE

WD

WE

RD

tSWE

old data

new data

tWCRD

Figure 11: RAM Cell Synchronous Write Timing

Table 9: RAM Cell Synchronous & Asynchronous Read Timing

Symbol

Parameter

Propagation

delay (ns)

RAM Cell Synchronous Read Timing

RA setup time to RCLK: the amount of time the READ ADDRESS must

be stable before the active edge of the READ CLOCK

tSRA

tHRA

tSRE

0.686

0

RA hold time to RCLK: the amount of time the READ ADDRESS must

be stable after the active edge of the READ CLOCK

RE setup time to WCLK: the amount of time the READ ENABLE must be

stable before the active edge of the READ CLOCK

0.243

0

RE hold time to WCLK: the amount of time the READ ENABLE must be

stable after the active edge of the READ CLOCK

tHRE

tRCRD

RCLK to RD: the amount of time between the active READ CLOCK edge

and the time when the data is available at RD

4.38

RAM Cell Asynchronous Read Timing

RA to RD: amount of time between when the READ ADDRESS is input

and when the DATA is output

rPDRD

2.06

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RCLK

RA

tSRA

tHRA

tHRE

RE

RD

tSRE

old data

new data

tRCRD

rPDRD

Figure 12: RAM Cell Synchronous & Asynchronous Read Timing

+

-

INPUT

Q

E

D

REGISTER

R

PAD

Q

OUTPUT

D

REGISTER

R

E

R

Q

OUTPUT ENABLE

REGISTER

D

Figure 13: QuickMIPS Cell I/O

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QL901M QuickMIPS™ Data Sheet Rev B

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tICLK

tIN, tINI

tISU

+

-

tSID

Q E

R

D

PAD

Figure 14: QuickMIPS Input Register Cell

Table 10: Input Register Cell

Symbol

Input Register Cell Only

Parameter

Propagation

delay (ns)

Input register setup time: the amount of time the synchronous input of

the flip flop must be stable before the active clock edge

tISU

tIH

3.12

0

Input register hold time: the amount of time the synchronous input of the

flip flop must be stable after the active clock edge

Input register clock to Q: the amount of time taken by the flip flop to

output after the active clock edge

tICLK

tIRST

tIESU

tIEH

1.08

0.99

0.37

0

Input register reset delay: amount of time between when the flip flop is

“reset”(low) and when Q is consequently “reset” (low)

Input register clock enable setup time: the amount of time “enable” must

be stable before the active clock edge

Input register clock enable time: the amount of time “enable” must be

stable after the active clock edge

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Table 11: Standard Input Delays

Symbol

Parameter

Propagation

delay (ns)

Standard

Input Delays

To get the total input delay and this delay to tISU

tSID (LVTTL)

LVTTL input delay: Low Voltage TTL for 3.3V applications

0.34

0.42

LVCMOS2 input delay: Low Voltage CMOS for 2.5V and lower

applications

tSID (LVCMOS2)

tSID (GTL+)

tSID (SSTL3)

tSID (SSTL2)

GTL+ input delay: Gunning Transceiver Logic

0.68

0.55

SSTL3 input delay: Stub Series Terminated Logic for 3.3V

SSTL2 input delay: Stub Series Terminated Logic for 2.5V

0.607

R

CLK

D

Q

tISU

tIHL

tICLK

tIRST

E

tIESU

tIEH

Figure 15: QuickMIPS Input Register Cell Timing

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QL901M QuickMIPS™ Data Sheet Rev B

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PAD

OUTPUT

REGISTER

Figure 16: QuickMIPS Output Register Cell

Table 12: QuickMIPS Output Register Cell

Symbol

Output Register Cell Only

Parameter

Propagation

delay (ns)

tOUTLH

tOUTHL

tPZH

Output Delay low to high (10% of H)

0.40

0.55

2.94

2.34

3.07

2.53

Output Delay high to low (90% of H)

Output Delay 3-state to high (10% of Z)

Output Delay 3-state to low (90% of Z)

Output Delay high to 3-state

tPZL

tPHZ

tPLZ

Output Delay low to 3-state

3.15 (fast slew)

10.2(slow slew)

tCO

Clock to out delay

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tOUTHL

H

L

tOUTLH

H

tPZL

Z

L

Z

L

tPZH

tPHZ

H

Z

L

Z

L

tPLZ

Figure 17: QuickMIPS Output Register Cell Timing

Table 13: VCCIO = 3.3 V

Fast Slew

Slow Slew

2.8 V/ns

1.0 V/ns

Rising Edge

Falling Edge

2.86 V/ns

Table 14: VCCIO = 2.5 V

Fast Slew

Slow Slew

Rising Edge

Falling Edge

1.7 V/ns

1.9 V/ns

0.6 V/ns

Table 15: ESP PLL Timing Parameters

Standby

Current (

Minimum Lock

Frequency

Duty

Cycle

Crystal

Accuracy

Jitter

Frequency Range

Lock Time

µ

a)

<200ps

157

µ

a

40-66.6 MHz

25 MHz

60/40

200 PPM

10 µs

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QL901M QuickMIPS™ Data Sheet Rev B

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PCI_CLK

Tval

PCI_AD(output)[31:0]

PCI_C_BE_n(output)[3:0]

PCI_PAR(output)

PCI_FRAME_n(output)

PCI_IRDY_n(output)

PCI_TRDY_n(output)

PCI_STOP_n(output)

PCI_DEVSEL_n(output)

PCI_SERR_n

PCI_PERR_n(output)

Tval(ptp)

Th

PCI_REQ_n

Tsu

PCI_AD(input)[31:0]

PCI_C_BE_n(input)[3:0]

PCI_PAR(input)

PCI_FRAME_n(input)

PCI_IRDY_n(input)

PCI_TRDY_n(input)

PCI_STOP_n(input)

PCI_DEVSEL_n(input)

PCI_IDSEL

PCI_PERR_n(input)

PCI_LOCK_n

Tsu(ptp)

PCI_GNT_n

Figure 18: PCI Waveforms

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Table 16: PCI AC Timing

66 MHz

33 MHz

Parameter^a

Units

Min

15

6

Max

Min

30

11

1

Max

Tcyc

Thigh

Tlow

–

PCI_CLK Cycle Time

PCI_CLK High Time

ns

PCI_CLK Low Time

6

ns

PCI_CLK Slew Rate

1.5

2

4

6

4

V/ns

ns

Tval

PCI_CLK to Signal Valid Delay

2

11

PCI_CLK to Signal Valid Delay

point-to-point signals^b

Tval (ptp)

2

6

2

12

28

ns

Ton

Toff

Float to Active Delay

Active to Float Delay

ns

14

Input Setup Time to PCI_CLK

bused signals

Tsu

3

5

7

ns

Input Setup Time to PCI_CLK

point-to-point

Tsu (ptp)

10, 12

Th

Trst

Input Hold Time from PCI_CLK

0

1

0

1

ns

Reset Active Time after power stable

Reset Active Time after PCI_CLK stable

Reset Active to output float delay

ms

Trst-clk

Trst-off^c

Trhfa

100

µs

40

ns

PCI_RST_n high to first configuration access

PCI_RST_n high to first PCI_FRAME_n assertion

2

5

2

5

clocks

Trhff

a. All PCI pins are synchronous to the PCI clock except for PCI_RST_n and PCI_INTA_n.

b. Point-to-point signals include PCI_REQ_n and PCI_GNT_n.

c. All output drivers must be 3-stated when PCI_RST_n is active.

TXCLK(in)

TXEN(out)

t_{en_c2q}

TXD[3:0](out)

t_{data_h}

t_{data_v}

Figure 19: Ethernet MAC Transmit Interface Waveforms

Table 17: Ethernet MAC Transmit Interface AC Timing

Parameter

Min

Max

Units

Time from the rising clock edge of TXCLK to

the change in TXEN

t_{en_c2q}

t_{data_v}

t_{data_h}

8.0

ns

Time from the rising clock edge of TXCLK to all

data signals having valid stable values

9.0

ns

Time in which the output data is still valid after

the rising clock edge of TXCLK

0.0

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QL901M QuickMIPS™ Data Sheet Rev B

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RXCLK(in)

RXDV(in)

t_{dv_s}

t_{er_s}

t_{data_h}

t_{dv_h}

t_{er_h}

t_{data_s}

RXER(in)

RXD[3:0](in)

Figure 20: Ethernet MAC Receive Interface Waveforms

Table 18: Ethernet MAC Receive Interface AC Timing

Parameter

Min

2.0

Max

Units

ns

t_{dv_s}

RXDV (receive data valid) to RXCLK setup time

RXDV (receive data valid) from RXCLK hold time

RXER (receive data error) to RXCLK setup time

RXER (receive data error) from RXCLK hold time

RXD (receive data) to RXCLK setup time

RXD (receive data) from RXCLK hold time

t_{dv_h}

t_{er_s}

ns

t_{er_h}

ns

t_{data_s}

t_{data_h}

ns

The timing of the MII Management Interface listed below depends on the system clock frequency. The

numbers displayed are correct for a processor clock frequency of 100 MHz and an AMBA bus system

clock frequency of 50 MHz. Note that for a system clock of 133 MHz, the mandatory MDC minimum

clock cycle of 400ns for some PHY devices will not be met.

•

20

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t_{mdc_cyc}

t_{mdc_l}

t_{mdc_h}

MDC(out)

MDIO(out)

t_mdovh

t_mdozv

t_mdovz

t_mdovs

Figure 21: MII Management Interface Waveforms (1 of 2)

Table 19: MII Management Interface AC Timing (1 of 2)

Parameter

Min

520

260

40

Max

Units

ns

t_{mdc_cyc}

t_{mdc_h}

t_{mdc_l}

MDC cycle time

MDC high time

MDC low time

ns

t_mdozv

t_mdovz

t_mdos

MDIO output high impedance to valid time from rising edge of MDC

MDIO output valid to high impedance time from rising edge of MDC

MDIO output valid before MDC rising edge

ns

40

ns

440

40

ns

t_mdovh

MDIO output valid from MDC rising edge

ns

MDC(out)

MDIO(in)

t_mdis

t_mdih

Figure 22: MII Management Interface Waveforms (2 of 2)

Table 20: MII Management Interface AC Timing (2 of 2)

Parameter

Min

25

0

Max

Units

ns

t_mdis

t_mdih

MDIO setup time to MDC

MDIO hold time to MDC

ns

•

QL901M QuickMIPS™ Data Sheet Rev B

21

SD_CLKIN

Tco_sdram

ADDR[23:0]

SD_CS_n[3:0]

SD_CKE[3:0]

SD_DQM[3:0]

SD_RAS_n

SD_CAS_n

SD_WE_n

DATA(output)[31:0]

Tsu_sdram

Th_sdram

DATA(input[31:0]

Figure 23: SDRAM Waveforms

Table 21: SDRAM AC Timing

Parameter^a

Min

Max

Units

DATA, ADDR, SD_RAS_n, SD_CAS_n, SD_CS_n[3:0],

SD_DQM[3:0], SD_WE_n, SD_CKE[3:0]

Tco

2

8

ns

Tsu

Th

DATA

12

2

ns

a. All timing is measured with respect to the rising edge of SD_CLKIN. All measurements are based on I/Os with 35 pF

load except for SD_CLKOUT, which has a load of 15 pF.

Internal_AHB_Clock

CS_n

ADDR[31:0]

BLS_n[3:0]

OEN_n

addr

byte lane select

WEN_n

D0

D1

DATA[31:0]

read data

Figure 24: SRAM Read Waveforms

•

22

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Internal_AHB_Clock

CS_n

ADDR[31:0]

BLS_n[3:0]

OEN_n

addr

byte lane select

D0

D1

WEN_n

DATA[31:0]

write data

Figure 25: SRAM Write Waveforms

Table 22 and Table 23 below list the synchronous and asynchronous timing for the QuickMIPS Fabric

interface port. Note the following with regards to the fabric timing:

1

2

3

fb_int is asynchronous and is synchronized inside the core.

fb_bigendian is a static signal and reflects the value on the CPU_BIGENDIAN pin.

pm_* and si_* signals are synchronous to the internal MIPS clock which is twice the hclk frequency. Because this internal

clock is not brought to the outside, these signals are considered asynchronous.

All AF_PCI_* signals are static.

4

Table 22: QuickMIPS Interface Port Synchronous Timing (to hclk)

Setup Time (Tsu)

Hold Time (Thold)

Clock-to-out Time (Tco)

hresetn

x^a

x

5.11

Fabric AHB Slave Ports

ahbs_hsel

X

0

10.73

10.56

11.35

8.32

9.50

9.12

9.66

13.07

X

ahbs_haddr

ahbs_htrans

X

ahbs_hwrite

X

ahbs_hsize

X

ahbs_hburst

X

ahbs_hprot

X

ahbs_hwdata

ahbs_hrdata

X

5.94

9.55

10.39

ahbs_hready_out

ahbs_hresp

0

X

0

X

Fabric AHB Master Ports

ahbm_haddr

11.94

11.33

10.39

10.58

0

X

ahbm_htrans

ahbm_hwrite

ahbm_hsize

(Sheet 1 of 2)

•

QL901M QuickMIPS™ Data Sheet Rev B

23

Table 22: QuickMIPS Interface Port Synchronous Timing (to hclk) (Continued)

Setup Time (Tsu)

Hold Time (Thold)

Clock-to-out Time (Tco)

ahbm_hburst

ahbm_hprot^b

ahbm_hwdata

ahbm_hrdata

ahb_hready_in

ahbm_hresp

10.79

0

–

X

–

10.39

X

0

X

0

16.28

11.82

9.02

X

ahbm_hbusreq

ahbm_hgrant

Fabric APB Slave Ports

apbs_paddr

7.40

X

16.64

X

0

4.52

4.66

2.87

4.13

3.80

3.43

3.25

X

apbs_pwdata

apbs_penable

apbs_pwrite

X

apbs_psel0

X

apbs_psel1

X

apbs_psel2

X

apbs_prdata0

apbs_prdata1

apbs_prdata2

Timer Ports

tm_fbenable

7.44

6.79

6.97

0

X

0

X

0.23

X

0

X

tm_overflow2

tm_overflow3

tm_overflow4

4.35

4.48

5.00

X

(Sheet 2 of 2)

a. “x” indicates that this timing delay does not apply to the signal.

b. The ahbm_hprot signal is NOT used by any slave within the standard cell part of the chip. None of the mas-

ters besides the processor-AHB-bridge generates this signal. Therefore there is no setup or hold timing for

ahbm_hprot.

•

24

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Table 23: QuickMIPS Interface Port Asynchronous Timing

Start Port

End Port

ahbs_haddr

ahbs_hsel

Propagation Delay (Tprop)

ahbm_haddr

ahbm_htrans

ahbm_hwrite

ahbm_hsize

8.39

7.71

6.48

6.21

6.04

5.70

7.07

8.15

5.78

5.03

4.98

10.14

10.50

8.28

7.51

7.57

ahbs_htrans

ahbs_hwrite

ahbs_hsize

ahbm_hburst

ahbm_hprot

ahbs_hburst

ahbs_hprot

ahbm_hwdata

ahbs_hrdata

ahbs_hready_out

ahbs_hresp

ahbs_hwdata

ahbm_hrdata

ahb_hready_in

ahbm_hresp

ahbm_hgrant

ahbm_hrdata

ahbm_hbusreq

ahbs_hresp

apbs_prdata0

apbs_prdata1

apbs_prdata2

•

QL901M QuickMIPS™ Data Sheet Rev B

25

5.0 DC Characteristics

The DC specifications are provided in Table 24 through Table 26.

Table 24: Absolute Maximum Ratings

V_CCVoltage

V_CCIOVoltage

-0.5 to 3.6V

-0.5 to 4.6V

2.7V

DC Input Current

ESD Pad Protection

Storage Temperature

20 mA

2000V

-65°C to +150°C

V_REFVoltage

-0.5V to V_CCIO+0.5V

100 mA

Input Voltage

Latch-up Immunity

Maximum Lead

Temperature

300°C

Table 25: Operating Range

Symbol

Parameter

Industrial

Min Max

Commercial

Unit

Min

2.3

0

Max

VCC

VCCIO

TA

Supply Voltage

2.3

2.7

3.6

70

V

2.3

-40

3.6

85

V

I/O Input Tolerance Voltage

Ambient Temperature

Case Temperature

°C

TC

-4 Speed Grade

0.43

2.16

1.80

1.26

1.14

0.47

0.46

2.11

1.76

1.23

1.11

n/a

-5 Speed Grade

-6 Speed Grade

-7 Speed Grade

K

Delay Factor

Table 26: DC Input and Output Levels

V_ILV_IH

V_MAX

V_REF

V_MINV_MAXV_MIN

V_OL

V_OH

I_OL

I_OH

V_MIN

2.0

V_MAX

0.4

V_MIN

24.

mA mA

LVTTL

LVCMOS2

GTL+

n/a

-0.3

0.8

V_CCIO-0.3

V_CCIO-0.5

V_CCIO+0.3

2.0

40

1.5

7.6

9

-2.0

n/a

0.7

1.7

0.7

1.7

0.88

n/a

1.12

n/a

V

_REF-0.2

V_REF+0.2

0.5xV_CC

V_REF+0.18

V_REF+0.2

0.6

n/a

PCI

0.3xV_CC

0.1xV_CC

0.74

1.10

0.9xV_C

1.76

1.90

-0.5

-7.6

-8

SSTL2

SSTL3

1.15

1.3

1.35

1.7

V

_REF-0.18

V_REF-0.2

•

26

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6.0 Pin Descriptions

Table 27 defines the QuickMIPS chip pins.

Table 27: Pin Descriptions

Function

I/O

PCI Signals

PCI Address and Data. PCI_AD[31:0] contain the multiplexed address and data. A bus transaction

consists of a single address phase (or two address phases for 64-bit addresses) followed by one or

more data phases. The QuickMIPS chip supports both read and write bursts.

The address phase occurs in the first clock cycle when PCI_FRAME_n is asserted. During the address

phase, PCI_AD[31:0] contain a 32-bit physical address. For I/O, this is a byte address; for configuration

and memory, it is a DWORD (32-bit) address. During data phases, PCI_AD[7:0] contain the least-

significant byte, and PCI_AD[31:24] contain the most-significant byte.

PCI_AD[31:0]

I/O

Write data is stable and valid when PCI_IRDY_n is asserted; read data is stable and valid when

PCI_TRDY_n is asserted. Data is transferred when both PCI_IRDY_n and PCI_TRDY_n are asserted.

Bus Command and Byte Enables. Bus commands and byte enables are multiplexed on

PCI_C_BE_n[3:0]. During the address phase of a transaction (PCI_FRAME_n is asserted),

PCI_C_BE_n[3:0] define the bus command as shown in the following table (only valid combinations are

shown).

PCI_C_BE_n[3:0]

0000

Bus Command

Interrupt Acknowledge

0001

0010

0011

0110

0111

1010

1011

1100

1101

1110

1111

Special Cycle

I/O Read

I/O Write

Memory Read

PCI_C_BE_n[3:0]

I/O

Memory Write

Configuration Read

Configuration Write

Memory Read Multiple

Dual Address Cycle

Memory Read Line

Memory Write and Invalidate

During each data phase, PCI_C_BE_n[3:0] are byte enables. The byte enables are valid for the entire

data phase and determine which byte lanes contain meaningful data. PCI_C_BE_n[0] applies to byte

0 (PCI_AD[7:0]) and PCI_C_BE_n[3] applies to byte 3 (PCI_AD[31:24]).

PCI Device Select. When asserted low, PCI_DEVSEL_n indicates the driving device has decoded its

address as the target of the current access. As an input, PCI_DEVSEL_n indicates whether any device

on the bus has responded.

PCI_DEVSEL_n

PCI_FRAME_n

I/O

PCI Cycle Frame. The current master asserts PCI_FRAME_n to indicate the beginning and duration of

a bus transaction. While PCI_FRAME_n is asserted, data transfers continue. When PCI_FRAME_n is

deasserted, the transaction is in the final data phase or has completed.

(Sheet 1 of 6)

•

QL901M QuickMIPS™ Data Sheet Rev B

27

Table 27: Pin Descriptions (Continued)

I/O

Function

PCI Grant. A low assertion of PCI_GNT_n indicates to the agent that access to the bus has been

granted. PCI_GNT_n is ignored while PCI_RST_n is asserted.

PCI_GNT_n

PCI_IDSEL

I

PCI Initialization Device Select. PCI_IDSEL is used as a chip select during configuration read and write

transactions (PCI_C_BE_n[3:0] = 1010 or 1011).

I

PCI Interrupt Acknowledge. PCI_INTA_n is a level-sensitive interrupt driven by the QuickMIPS chip.

PCI_INTA_n is asserted and deasserted asynchronously to the PCI_CLK. This interrupt remains

asserted until the interrupt is cleared.

PCI_INTA_n

PCI_IRDY_n

O

Because the PCI interrupt controller is not built into the QuickMIPS ESP core, this pin is output only.

However, such an interrupt controller can be built into the fabric.

PCI Initiator Ready. PCI_IRDY_n is used in conjunction with PCI_TRDY_n. The bus master (initiator)

asserts PCI_IRDY_n to indicate when there is valid data on PCI_AD[31:0] during a write, or that it is

ready to accept data on PCI_AD[31:0] during a read.

I/O

A data phase is completed when both PCI_IRDY_n and PCI_TRDY_n are asserted. During a write, a

low assertion of PCI_IRDY_n indicates that valid data is present on PCI_AD[31:0]. During a read, a low

assertion of PCI_IRDY_n indicates the master is prepared to accept data. Wait cycles are inserted until

both PCI_IRDY_n and PCI_TRDY_n are asserted together.

PCI Lock. A low assertion on PCI_LOCK_n indicates an atomic operation to a bridge that might take

multiple transactions to complete. When PCI_LOCK_n is asserted, non-exclusive transactions can

proceed to a bridge that is not currently locked. Control of PCI_LOCK_n is obtained under its own

protocol in conjunction with PCI_GNT_n. It is possible for different agents to use PCI while a single

master retains ownership of PCI_LOCK_n. Locked transactions can be initiated only by host bridges,

PCI-to-PCI bridges, and expansion bus bridges.

PCI_LOCK_n

PCI_PAR

I

PCI Parity. Parity is driven high or low to create even parity across PCI_AD[31:0] and

PCI_C_BE_n[3:0]. The master drives PCI_PAR for address and write data phases; the target drives

PCI_PAR for read data phases.

I/O

PCI Parity Error. PCI_PERR_n indicates the occurrence of a data parity error during all PCI

transactions except a Special Cycle. The QuickMIPS chip drives PCI_PERR_n low two clocks following

the data when a data parity error is detected. The minimum duration of the deassertion of PCI_PERR_n

is one clock for each data phase that a data parity error is detected. (If sequential data phases each

have a data parity error, the PCI_PERR_n signal is asserted for more than a single clock.)

PCI_PERR_n is driven high for one clock before being 3-stated as with all sustained 3-state signals.

PCI_PERR_n

PCI Request. Assertion of PCI_REQ_n indicates to the arbiter that this agent desires use of the bus.

PCI_REQ_n is 3-stated while PCI_RST_n is asserted.

PCI_REQ_n

PCI_RST_n

O

I

PCI Reset. Asserting PCI_RST_n low resets the internal state of the QuickMIPS PCI block. When

PCI_RST_n is asserted, all PCI output signals are asynchronously 3-stated. PCI_REQ_n and

PCI_GNT_n must both be 3-stated (they cannot be driven low or high during reset).

The assertion/deassertion of PCI_RST_n can be asynchronous to PCI_CLK.

PCI System Error. The QuickMIPS chip asserts PCI_SERR_n to indicate an address parity error, a data

parity error on the Special Cycle command, or any other system error where the result is catastrophic.

PCI_SERR_n is open drain and is actively driven for a single PCI clock. The assertion of PCI_SERR_n

is synchronous to the clock and meets the setup and hold times of all bused signals. However, the

restoring of PCI_SERR_n to the deasserted state is accomplished by a weak pull-up (same value as

used for s/t/s), which is provided by the central resource not by the signaling agent. This pull-up can

take two to three clock periods to fully restore PCI_SERR_n.

PCI_SERR_n

PCI_STOP_n

O

PCI Stop. PCI_STOP_n is asserted low to indicate the current target is requesting the master to stop

the current transaction.

I/O

(Sheet 2 of 6)

•

28

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Table 27: Pin Descriptions (Continued)

I/O

Function

PCI Target Ready. PCI_TRDY_n is used in conjunction with PCI_IRDY_n. The current bus slave

(target) asserts PCI_TRDY_n to indicate when there is valid data on PCI_AD[31:0] during a read, or

that it is ready to accept data on PCI_AD[31:0] during a write.

PCI_TRDY_n

I/O

A data phase is completed when both PCI_TRDY_n and PCI_IRDY_n are asserted. During a read, a

low assertion of PCI_TRDY_n indicates that valid data is present on PCI_AD[31:0]. During a write, a

low assertion indicates the target is prepared to accept data. Wait cycles are inserted until both

PCI_IRDY_n and PCI_TRDY_n are asserted together.

PCI Clock. All PCI signals (except PCI_RST_n and PCI_INTA_n) are sampled on the rising edge of

PCI_CLK. PCI_CLK operates at speeds up to either 33 MHz or 66 MHz.

PCI_CLK

I

Ethernet MAC Signals

Ethernet Collision Detected. The external Ethernet PHY Controller chip asserts COL high upon

detection of a collision on the medium. COL remains asserted while the collision condition persists.

M1_COL/M2_COL

The transitions on the COL signal are not synchronous to either the TXCLK or the RXCLK.

The QuickMIPS MAC core ignores the COL signal when operating in the full-duplex mode.

Ethernet Carrier Sense. The external Ethernet PHY Controller chip asserts CRS high when either

transmit or receive medium is non-idle. The PHY deasserts CRS low when both the transmit and

receive medium are idle. The PHY must ensure that CRS remains asserted throughout the duration of

a collision condition.

M1_CRS/M2_CRS

M1_MDC/M2_MDC

I

The transitions on the CRS signal are not synchronous to either the TXCLK or the RXCLK.

Ethernet Management Data Clock. MDC is sourced by the MAC110 core to the Ethernet PHY

Controller as the timing reference for transfer of information on the MDIO signals. MDC is an aperiodic

signal that has no maximum high or low times. The minimum high and low times for MDC are 160 ns

each, and the minimum period for MDC is 400 ns, regardless of the nominal period of TXCLK and

RXCLK.

O

Ethernet Management Data In/Out. When used as an input, MDIO is the data input signal from the

Ethernet PHY Controller. The PHY drives the Read Data synchronously with respect to the MDC clock

during the read cycles.

M1_MDIO/M2_MDIO

I/O

When used as an output, MDIO is the data output signal from the MAC110 core that drives the control

information during the Read/Write cycles to the External PHY Controller. The MAC110 core drives the

MDIO signal synchronously with respect to the MDC.

Ethernet Receive Clock. RXCLK is a continuous clock that provides the timing reference for the transfer

of the RXDV and RXD[3:0] signals from the Ethernet PHY Controller to the MAC110 core. The Ethernet

PHY Controller chip sources RXCLK. RXCLK has a frequency equal to 25% of the data rate of the

received signal on the Ethernet cable.

M1_RXCLK/M2_RXCLK

I

Ethernet Receive Data. RXD[3:0] transition synchronously with respect to RXCLK. The Ethernet PHY

Controller chip drives RXD[3:0]. For each RXCLK period in which RXDV is asserted, RXD[3:0] transfer

four bits of recovered data from the PHY to the MAC110 core. RXD0 is the least-significant bit. While

RXDV is deasserted low, RXD[3:0] has no effect on the MAC110 core.

M1_RXD[3:0]/M2_RXD[3:0]

Ethernet Receive Data Valid. The Ethernet PHY Controller asserts RXDV high to indicate to the

MAC110 core that it is presenting the recovered and decoded data bits on RXD[3:0] and that the data

on RXD[3:0] is synchronous to RXCLK. RXDV transitions synchronously with respect to RXCLK. RXDV

remains asserted continuously from the first recovered nibble of the frame through the final recovered

nibble, and is deasserted low prior to the first RXCLK that follows the final nibble.

M1_RXDV/M2_RXDV

M1_RXER/M2_RXER

I

Ethernet Receive Error. The Ethernet PHY Controller chip asserts RXER high for one or more RXCLK

periods to indicate to the MAC110 core that an error (a coding error or any error that the PHY is capable

of detecting that is otherwise undetectable by the MAC) was detected somewhere in the frame

presently being transferred from the PHY to the MAC110 core. RXER transitions synchronously with

respect to RXCLK. While RXDV is deasserted low, RXER has no effect on the MAC110 core.

(Sheet 3 of 6)

•

QL901M QuickMIPS™ Data Sheet Rev B

29

Table 27: Pin Descriptions (Continued)

I/O

Function

Ethernet Transmit Clock. TXCLK is a continuous clock that provides a timing reference for the transfer

of the TXEN and TXD signals from the MAC110 core to the Ethernet PHY Controller. The Ethernet PHY

Controller chip sources TXCLK. The operating frequency of TXCLK is 25 MHz when operating at

100 Mbps and 2.5 MHz when operating at 10 Mbps.

M1_TXCLK/M2_TXCLK

I

Ethernet Transmit Data. The QuickMIPS MAC110 core drives TXD[3:0]. TXD[3:0] transition

synchronously with respect to TXCLK. For each TXCLK period in which TXEN is asserted, TXD[3:0]

have the data to be accepted by the Ethernet PHY Controller chip. TXD0 is the least-significant bit.

While TXEN is deasserted, ignore the data presented on TXD[3:0].

M1_TXD[3:0]/M2_TXD[3:0]

M1_TXEN/M2_TXEN

O

Ethernet Transmit Enable. A high assertion on TXEN indicates that the MAC110 core is presenting

nibbles on the MII for transmission. The QuickMIPS MAC110 core asserts TXEN with the first nibble of

the preamble and holds TXEN asserted while all nibbles to be transmitted are presented to the MII.

TXEN is deasserted low prior to the first TXCLK following the final nibble of the frame. TXEN is

transitions synchronously with respect to TXCLK.

Memory Controller Interface Signals

BLS_n[3:0]

O

Byte Enables. These signals determine the validity of the bytes on the DATA bus.

CS_n[7:0]

ADDR[23:0]

DATA[31:0]

OEN_n

Chip Selects. These signals are the active-low chip selects for the SRAM.

Memory Address. This 24-bit address contains the memory address.

Memory Data. This 32-bit bus contains the memory data.

O

I/O

O

SRAM Output Enable. OEN_n is the active-low output enable to the external SRAM.

SDRAM Column Address Strobe. SD_CAS_n is the active-low column address strobe for the external

SDRAM.

SD_CAS_n

O

SD_CKE[3:0]

SD_CLKIN

O

I

SDRAM Output Clock Enables. SD_CKE[3:0] determine whether the next clock is valid or not.

SDRAM Input Clock. SD_CLKIN is the external SDRAM clock.

SD_CLKOUT

SD_CS_n[3:0]

SD_DQM[3:0]

O

SDRAM Output Clock. SD_CLKOUT is the clock from the QuickMIPS chip to the external SDRAMs.

SDRAM Output Chip Select. SD_CS_n[3:0] are the active-low chip selects for the external SDRAMs.

SDRAM Data Mask. SD_DQM[3:0] are the data masks for DATA[31:0]

SDRAM Row Address Strobe. SD_RAS_n is the active-low row address strobe for the external

SDRAM.

SD_RAS_n

SD_WE_n

WEN_n

O

SDRAM Write Enable. SD_WE_n is the active-low write enable to the SDRAMs.

SRAM Transfer Direction. WEN_n indicates whether transactions between the QuickMIPS chip and the

external SRAM are reads (WEN_n is high) or writes (WEN_n is low).

UART Interface Signals

U1_CTS_n

U1_DCD_n

I

UART1 Clear To Send. A low on this signal indicates the external device is ready to transfer data.

UART1 Data Carrier Detect. A low on this signal indicates the data carrier has been detected.

UART1 Data Set Ready. A low on this signal indicates the modem or data set is ready to establish the

link to the QuickMIPS UART.

U1_DSR_n

I

UART1 Data Terminal Ready. The QuickMIPS chip asserts this output low to indicate it is ready to

establish the external communication link.

U1_DTR_n

U1_RI_n

O

I

UART1 Ring Indicator. This input is an active-low ring indicator.

UART1 Request To Send. The QuickMIPS chip asserts this signal low to inform the external device that

the UART is ready to send data.

U1_RTS_n

O

UART1 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the

UART or the IrDA block.

U1_RXD_SIRIN

I

(Sheet 4 of 6)

•

30

www.quicklogic.com

Table 27: Pin Descriptions (Continued)

I/O

Function

UART1 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from

either the UART or the IrDA block.

U1_TXD_SIROUT_n

O

UART2 Received Serial Data/SIR Received Serial Data. This input receives serial data for either the

UART or the IrDA block.

U2_RXD_SIRIN

I

UART2 Transmitted Serial Data/SIR Transmitted Serial Data. This output transmits serial data from

either the UART or the IrDA block.

U2_TXD_SIROUT_n

O

Test Interface Signals

EJTAG Test Clock. This clock controls the updates to the TAP controller and the shifts through the

Instruction register or selected data registers. Both the rising and falling edges of EJTAG_TCK are

used.

EJTAG_TCK

I

EJTAG Test Data In. Serial test data is input on this pin and is shifted into the Instruction or data register.

This input is sampled on the rising edge of EJTAG_TCK.

EJTAG_TDI

I

O

I

EJTAG Test Data Out. The QuickMIPS chip outputs serial test data on this pin from the Instruction or

data register. This signal changes on the falling edge of EJTAG_TCK.

EJTAG_TDO

EJTAG_TMS

EJTAG_TRST

EJTAG_DEBUGM

EJTAG Test Mode Select. This input is the control signal for the TAP controller. It is sampled on the

rising edge of EJTAG_TCK.

EJTAG Test Reset. This signal is asserted high asynchronously to reset the TAP controller, Instruction

register, and EJTAGBOOT indication.

I

Debug Mode. This bit is asserted high when the MIPS 4Kc core is in Debug Mode. This output can be

used to bring the chip out of low power mode.

O

Debug Exception Request. Assertion high of this input indicates a debug exception request is pending.

The request is cleared when debug mode is entered. Requests that occur while the chip is in debug

mode are ignored.

EJTAG_DINT

I

Fabric Interface Signals

I/O<A>53:0

I/O

I

Programmable Input/Output/3-State/Bidirectional pin in Bank A.

Programmable Input/Output/3-State/Bidirectional pin in Bank B.

Programmable Input/Output/3-State/Bidirectional pin in Bank C.

Programmable Input/Output/3-State/Bidirectional pin in Bank D.

Programmable Global Clock Pin. Tie to VCC or GND if unused.

Differential I/O Reference Voltage. Connect to GND when using TTL, PCI or LVCMOS.

Low Skew I/O Control Pins. Tie to GND if unused.

JTAG Clock. Tie to GND if unused.

I/O71:0

I/O<C>71:0

I/O<D>53:0

CLK<8:0>

INREF<A:D>

IOCTRL<A:D>

TCLK

TDI

I

JTAG Data In. Tie to VCC if unused.

TDO

O

JTAG Data Out. Leave unconnected if unused.

TMS

O

JTAG Test Mode Select. Tie to VCC if unused.

TRSTB

I

JTAG Reset. Tie to GND if unused.

Timer Interface Signals

TM_OVERFLOW

TM_ENABLE

O

I

Timer Overflow. This output is asserted high when an internal timer overflows.

Timer Enable. This signal is asserted high to enable the internal timer.

Miscellaneous Signals

BOOT<1:0>

I

Boot chip size. 00 = 8 bit, 01 = 16 bit, 10 = 32 bit, and 11 = reserved.

(Sheet 5 of 6)

•

QL901M QuickMIPS™ Data Sheet Rev B

31

Table 27: Pin Descriptions (Continued)

CPU_BIGENDIAN

CPU_EXTINT_n<6:0>

PL_BYPASS

I/O

Function

Endian Setting. A High on this input indicates big-endian byte ordering; a Low on this input indicates

little-endian byte ordering.

I

CPU Interrupts. Asserting Low any of these inputs causes an interrupt to the QuickMIPS chip.

PLL Bypass. When High, the 2X multiplication of the input clock is not performed and the output clocks

are half their normal frequencies.

PL_CLKOUT

PL_CLOCKIN

O

I

Output Clock from PLL.

Input Clock to PLL.

PLL Enable. A High assertion of this signal powers down the PLL when it is not being used to reduce

overall device power and puts the QuickMIPS chip into a quiescent current testing mode. When

PL_ENABLE is Low, the PLL is not functional, but the clock outputs can be used if the PL_BYPASS

input is High.

PL_ENABLE

I

PLL Lock. The lock output indicates when the PLL is locked to the input clock and is producing valid

output clocks.

PL_LOCK

O

PL_RESET_n

PL_WARMRESET_n

STM

I

PLL Reset.

PLL Warm Reset.

QuickLogic Reserved pin. Tie to GND on the PCB.

Power and Ground Signals

GND

I

Ground pin. Tie to GND on the PCB.

Ground for the PLL.

GNDPLL

VCCIO

Supply pin for I/O. Set to 2.5V for 2.5V I/O, 3.3V for 3.3V compliant I/O, or refer to the I/O Standards

table.

I

VCCIO<A:D>

VCCPLL

VCC

I

VCCIO port for each of the four I/O banks.

Supply for the PLL.

Supply pin. Tie to 2.5V supply.

(Sheet 6 of 6)

QL 901M- 6 PS680 C

QuickLogic device

Operating Range

C = Commercial

I = Industrial

QuickMIPS device part

number

Package Code

PS680 = 680-pin BGA (1.0mm)

Speed Grade

6 = Faster

Figure 26: Ordering Information

•

32

www.quicklogic.com

7.0 680 PBGA Pinout Diagram

Top

Pin A1

Corner

QuickMIPS

QL901M

Figure 27: 680-Pin PBGA Package Marking (Top View)

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Pin A1

Corner

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

Figure 28: 680-Pin PBGA Package Marking (Bottom View)

•

QL901M QuickMIPS™ Data Sheet Rev B

33

8.0 680 PBGA Pinout Table

Table 28: 680 PBGA Pinout Table

680

PBGA

680

PBGA

680

PBGA

680

PBGA

680

PBGA

680

PBGA

Function

A1

A2

GND

B26

B27

B28

B29

B30

B31

B32

B33

B34

C1

INREF

I/O

GND

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

E1

I/O<C>

I/O

GND

F32

F33

F34

G1

GND

I/O

I/O<D>

I/O<C>

VCC

M31

M32

M33

M34

N1

I/O<A>

IOCTRL<A>

I/O<A>

INREF<A>

I/O<D>

VCC

R30

R31

R32

R33

R34

T1

VCC

I/O<A>

I/O<D>

VCCIO<D>

GND

A3

I/O<C>

INREF<C>

I/O<C>

GND

A4

A5

G2

A6

G3

N2

A7

G4

N3

T2

A8

G5

N4

T3

A9

GND

G30

G31

G32

G33

G34

H1

VCC

N5

T4

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

B1

GND

N13

N14

N15

N16

N17

N18

N19

N20

N21

N22

N30

N31

N32

N33

N34

P1

GND

T5

C2

I/O<C>

GND

I/O

I/O<D>

I/O<C>

VCCIO<D>

VCCIO<A>

I/O

I/O<A>

I/O<D>

I/O

I/O<A>

I/O<D>

I/O<A>

I/O<D>

I/O<A>

IOCTRL<D>

INREF<D>

IOCTRL<D>

I/O<D>

I/O<A>

VCCIO<C>

VCCIO

GND

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T30

T31

T32

T33

T34

U1

C3

C4

I/O<C>

IOCTRL<C>

I/O<C>

TMS

GND

C5

GND

C6

H2

GND

C7

I/O

VCC

H3

GND

C8

H4

GND

C9

H5

GND

CLK<5>

I/O

IOCTRL

I/O

GND

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

D1

H30

H31

H32

H33

H34

J1

GND

E2

I/O<C>

VCC

VCCIO<A>

I/O<A>

GND

E3

IOCTRL<A>

I/O<A>

I/O<D>

VCCIO<D>

GND

E4

E5

E6

E7

VCC

J2

E8

VCCIO<C>

I/O<C>

VCC

J3

P2

CLK<6>

I/O

IOCTRL

I/O

GND

E9

J4

P3

U2

I/O<D>

VCCIO<D>

GND

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

F1

J5

P4

U3

J30

J31

J32

J33

J34

K1

P5

U4

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P30

P31

P32

P33

P34

R1

U5

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U30

U31

U32

U33

U34

V1

VCCIO<C>

VCC

GND

I/O<C>

I/O

VCC

GND

K2

GND

B2

GND

K3

GND

B3

I/O<C>

IOCTRL<C>

I/O<C>

CLK<8>

CLK<7>

I/O

K4

GND

B4

K5

GND

B5

VCCIO

VCC

K30

K31

K32

K33

K34

L1

VCCIO<A>

I/O<A>

I/O<D>

VCC

GND

B6

VCCIO<A>

I/O<A>

GND

B7

I/O

VCCIO

VCC

B8

I/O

GND

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

D2

GND

L2

D3

I/O<C>

L3

R2

GND

D4

VCC

L4

R3

V2

I/O<D>

VCCIO

GND

D5

I/O

VCC

L5

R4

V3

D6

L30

L31

L32

L33

L34

M1

M2

M3

M4

M5

M30

R5

V4

D7

R13

R14

R15

R16

R17

R18

R19

R20

R21

R22

VCCIO<D>

GND

V5

D8

VCC

V13

V14

V15

V16

V17

V18

V19

V20

V21

D9

GND

D10

D11

D12

D13

D14

D15

D16

I/O<C>

VCC

GND

F2

GND

F3

GND

F4

I/O<C>

VCC

GND

F5

GND

F30

F31

VCC

GND

I/O

VCCIO<A>

GND

(Sheet 1 of 2)

•

34

www.quicklogic.com

Table 28: 680 PBGA Pinout Table (Continued)

680

PBGA

680

PBGA

680

PBGA

680

PBGA

680

PBGA

680

PBGA

Function

V22

V30

V31

VCCIO

I/O<A>

AA17

AA18

AA19

GND

AE5

AE30

AE31

M2_RXDV

ADDR<2>

OEN_n

AK10

AK11

AK12

PCI_AD<17>

PCI_FRAME_n

PCI_PAR

AL31

AL32

AL33

GND

AN18

AN19

AN20

CPU_EXTINT_n<6>

CPU_EXTINT_n<2>

U1_RTS_n

ADDR<23>

ADDR<20>

U1_TXD

_SIROUT_n

V32

I/O<A>

AA20

GND

AE32

BLS_n<0>

AK13

VCC

AL34

ADDR<15>

AN21

V33

V34

W1

I/O<A>

GND

AA21

AA22

AA30

GND

AE33

AE34

AF1

CS_n<6>

CS_n<3>

M2_TXEN

AK14

AK15

AK16

VCCIO

AM1

AM2

AM3

M1_RXDV

NC

AN22

AN23

AN24

SD_CKE<2>

SD_CAS_n

VCCIO

EJTAG_TRST

EJTAG_TDO

I/O<D>

GND

SD_CS_n<2>

CPU_EXTINT

_n<1>

W2

W3

I/O<D>

AA31

AA32

EJTAG_DEBUGM

CLK<3>

AF2

AF3

M2_TXD<1>

M2_RXER

AK17

AK18

AM4

AM5

M1_RXD<1>

AN25

AN26

SD_DQM<1>

DATA<30>

CPU_

BIGENDIAN

TM_OVERFLOW

W4

W5

I/O<D>

GNDPLL

VCCIO

GND

AA33

AA34

AB1

I/O<A>

TCK

AF4

AF5

M2_RXD<2>

M2_RXD<0>

ADDR<7>

AK19

AK20

AK21

AK22

U1_RI_n

U1_DCD_n

VCCIO

AM6

AM7

AM8

AM9

PCI_GNT_n

PCI_AD<30>

PCI_AD<26>

PCI_AD<21>

AN27

AN28

AN29

AN30

DATA<23>

DATA<21>

DATA<17>

DATA<12>

W13

W14

AF30

AF31

AB2

TDI

ADDR<4>

VCC

PCI_C_BE

_n<3>

W15

GND

AB3

GND

AF32

ADDR<0>

AK23

SD_CLKIN

AM10

AN31

DATA<8>

W16

W17

W18

W19

W20

W21

W22

GND

VCCIO

AB4

AB5

STM

VCC

AF33

AF34

AG1

AG2

AG3

AG4

AG5

BLS_n<1>

WEN_n

AK24

AK25

AK26

AK27

AK28

AK29

AK30

DATA<28>

DATA<24>

DATA<16>

VCCIO

AM11

AM12

AM13

AM14

AM15

AM16

AM17

PCI_DEVSEL_n

PCI_SERR_n

PCI_AD<15>

PCI_AD<11>

PCI_AD<5>

PCI_AD<1>

EJTAG_TDI

AN32

AN33

AN34

AP1

DATA<4>

GND

AB13

AB14

AB15

AB16

AB17

GND

M2_MDC

M2_TXCLK

M2_RXD<1>

M2_CRS

VCCIO

GND

VCCIO

GND

VCC

AP2

GND

DATA<2>

DATA<1>

AP3

PCI_INTA_n

PCI_AD<29>

AP4

CPU_EXTINT

_n<5>

W30

W31

I/O<A>

AB18

AB19

VCCIO

AG30

AG31

VCCIO

AK31

AK32

ADDR<22>

ADDR<18>

AM18

AM19

AP5

AP6

PCI_AD<27>

PCI_AD<24>

CPU_EXTINT_n

<0>

ADDR<12>

W32

W33

W34

Y1

I/O<A>

I/O<D>

PL_CLOCKIN

VCCIO

GND

AB20

AB21

AB22

AB30

AB31

AB32

AB33

AB34

AC1

VCCIO

GND

AG32

AG33

AG34

AH1

ADDR<5>

ADDR<1>

BLS_n<3>

M2_RXD<3>

M2_RXCLK

M1_MDIO

M1_MDC

VCC

AK33

AK34

AL1

AL2

AL3

AL4

AL5

AL6

AL7

AL8

AL9

AL10

ADDR<14>

ADDR<11>

M1_TXD<0>

M1_RXCLK

M1_CRS

AM20

AM21

AM22

AM23

AM24

AM25

AM26

AM27

AM28

AM29

AM30

AM31

U1_DTR_n

SD_CKE<3>

SD_CKE<0>

SD_CS_n<3>

SD_DQM<2>

SD_CLKOUT

DATA<26>

AP7

AP8

PCI_AD<22>

PCI_AD<18>

PCI_IRDY_n

PCI_LOCK_n

PCI_C_BE_n<1>

PCI_AD<13>

PCI_AD<10>

PCI_AD<6>

PCI_AD<2>

GND

AP9

VCC

AP10

AP11

AP12

AP13

AP14

AP15

AP16

AP17

AP18

Y2

CS_n<0>

GND

AH2

Y3

AH3

GND

Y4

TRSTB

CLK<2>

VCC

AH4

M1_RXD<2>

PCI_RST_n

M1_RXD<0>

PCI_IDSEL

PCI_CLK

Y5

AH5

DATA<20>

Y13

Y14

Y15

Y16

AH30

AH31

AH32

AH33

VCC

DATA<15>

AC2

TDO

ADDR<16>

ADDR<9>

ADDR<6>

DATA<13>

GND

AC3

PL_CLKOUT

PL_BYPASS

DATA<9>

GND

AC4

PCI_AD<20>

DATA<5>

GND

PCI_C_BE

_n<2>

Y17

Y18

GND

AC5

BOOT<0>

CS_n<5>

AH34

AJ1

ADDR<3>

M2_COL

AL11

AL12

AM32

AM33

GND

AP19

AP20

CPU_EXTINT_n<3>

U2_TXD

_SIROUT_n

AC30

PCI_STOP_n

DATA<0>

Y19

Y20

Y21

Y22

Y30

GND

AC31

AC32

AC33

AC34

AD1

CS_n<2>

NC

AJ2

AJ3

AJ4

M1_TXEN

M1_TXD<1>

M1_TXCLK

M1_COL

AL13

AL14

AL15

AL16

AL17

PCI_AD<14>

PCI_AD<8>

PCI_AD<7>

PCI_AD<3>

EJTAG_TMS

AM34

AN1

AN2

AN3

AN4

ADDR<19>

GND

AP21

AP22

AP23

AP24

AP25

U1_DSR_n

U1_RXD_SIRIN

SD_CKE<1>

SD_RAS_n

GND

EJTAG_DINT

VCC

GND

VCCIO

CLK<4>

AJ5

AJ30

TM_ENABLE

PCI_REQ_n

PL_LOCK

ADDR<21>

SD_CS_n<0>

CPU_EXTINT

_n<4>

Y31

I/O<A>

AD2

PL_ENABLE

AJ31

ADDR<17>

AL18

AN5

PCI_AD<31>

AP26

SD_DQM<0>

Y32

Y33

I/O<A>

I/O<D>

CLK<0>

CLK<1>

VCCIO

VCCPLL

VCCIO

GND

AD3

AD4

PL_WARMRESET_n

M2_MDIO

AJ32

AJ33

AJ34

AK1

AK2

AK3

AK4

AK5

AK6

AK7

AK8

AK9

ADDR<13>

ADDR<10>

ADDR<8>

M1_TXD<3>

M1_TXD<2>

M1_RXER

M1_RXD<3>

NC

AL19

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AL29

AL30

U2_RXD_SIRIN

U1_CTS_n

SD_WE_n

SD_CS_n<1>

SD_DQM<3>

DATA<31>

DATA<25>

DATA<19>

DATA<11>

DATA<6>

AN6

AN7

PCI_AD<28>

PCI_AD<25>

PCI_AD<19>

PCI_AD<16>

PCI_TRDY_n

PCI_PERR_n

PCI_C_BE_n<0>

PCI_AD<12>

PCI_AD<9>

AP27

AP28

AP29

AP30

AP31

AP32

AP33

AP34

DATA<29>

DATA<27>

DATA<22>

DATA<18>

DATA<14>

DATA<10>

GND

Y34

AD5

M2_TXD<2>

BLS_n<2>

CS_n<7>

AN8

AA1

AA2

AA3

AA4

AA5

AA13

AA14

AA15

AA16

AD30

AD31

AD32

AD33

AD34

AE1

AN9

AN10

AN11

AN12

AN13

AN14

AN15

AN16

AN17

CS_n<4>

CS_n<1>

NC

GND

PL_RESET_n

BOOT<1>

GND

AE2

VCC

PCI_AD<4>

GND

AE3

M2_TXD<3>

M2_TXD<0>

VCCIO

DATA<7>

PCI_AD<0>

GND

AE4

PCI_AD<23>

DATA<3>

EJTAG_TCK

(Sheet 2 of 2)

•

QL901M QuickMIPS™ Data Sheet Rev B

35

9.0 Mechanical Drawings

Figure 29 provides the mechanical dimensions of the 680-pin Plastic Ball Grid Array (PBGA) package.

Figure 29: 680-pin PBGA Package Mechanical Drawing

•

36

www.quicklogic.com

10.0 Revision History

Table 29: Revision History

Comments

Revision

Date

A

B

Dec 2001

First release.

Dec 19 2001

PLL information re-evaluated

The information contained in this product brief, and the accompanying software programs are protected by

copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make

periodic modifications of this product without obligation to notify any person or entity of such revision. Copying,

duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an

authorized representative of QuickLogic is prohibited.

QuickLogic, pASIC, and ViaLink are registered trademarks, and QuickMIPS, SpDE and QuickWorks are

trademarks of QuickLogic Corporation.

Verilog is a registered trademark of Cadence Design Systems, Inc.

SaiLAhead^TMis a registered trademark of Saivision.

•

QL901M QuickMIPS™ Data Sheet Rev B

37

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QL901M-6PS680I

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