概述
数据手册06XS3517 概述
Smart High Side Switch Module 智能高侧开关模块
06XS3517 数据手册
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PDF下载Document Number: MC06XS3517
Rev. 2.0, 2/2012
Freescale Semiconductor
Advance Information
Smart High Side Switch Module
(Triple 6.0 m and Dual 17 m)
06XS3517
The 06XS3517 device is a five channel 12 V high side switch
module with integrated control and a high number of protective and
diagnostic functions. It is designed for automotive lighting and
industrial applications. The low RDS(ON) channels (three 6.0 m, two
17 m) can control different types of lighting applications; bulbs,
Xenon-HID lights, and LEDs. Control, device configuration, and
diagnostics are performed through a 16-bit SPI interface (3.3 V or
5.0 V). When communication with the external microcontroller or VDD
is lost, the device enters a fail-safe operation mode, but remains
operational, controllable, and protected.
HIGH SIDE SWITCH
The channels are controlled by an external clock signal and allow
staggered switch-on delay, to improve EMC performances.
Programmable output voltage slew rates (individually programmable)
further helps improve EMC performance. To avoid shutting off the
device upon inrush current while still being able to closely track the
load current, a dynamic over-current threshold profile is featured. Load
current in each channel can be sensed. The duty cycle of the channels
can be controlled independently and the switching frequency of each
of them can be doubled. The 06XS3517 is housed in a non-leaded
Power QFN package with an exposed pad.
Bottom View
FKSUFFIX
98ART10511D
24-PIN PQFN
PB FREE
Features
ORDERING INFORMATION
Temperature
• Three 6.0 m and Two 17 m protected high side switches
• Optional sixth channel with an external SMART MOSFET
• 16-bit SPI communication interface with daisy chain capability
• Accurate temperature & current sensing
Device
Package
Range (T )
A
MC06XS3517AFK
-40°C to 125°C
24 PQFN
• Fail-safe mode including autorestart
• PWM module with programmable switch-on delay and frequency prescaler
• Over-voltage, under-voltage, over-current, over-temperature, and reverse battery protections
• Dedicated bulb over-current protection with inrush current handling
• Sleep mode with low current consumption
• Normal operating range 7.0 V to 20 V, extended operating range 6.0 V - 28 V
12 V
12 V
5.0 V
06XS3517
VCC
VBAT
CP
LIMP
Watchdog
FLASHER
IGN
OUT1
OUT2
OUT3
OUT4
OUT5
FETIN
FETOUT
RSTB
CLOCK
CSB
MCU
FOG
SO
SI
Smart
Switch
SCLK
CSNS
GND
Figure 1. 06XS3517 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2012. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VCC
VBAT
CP
Charge
Pump
OV/UV/POR
detections
Vcc failure
detection
Internal
Regulator
RUP
CSB
SO
SI
Gate Drive
drain/gate clamp
SCLK
Logic
LED Control
RDWN
OUT1
(* Park)
Over-current
Detection
CLOCK
LIMP
FOG
Open Load
Detection
FLASHER
IGN
Over-temperature
Detection
RSTB
OUT1
OUT2
(* LBeam)
OUT2
OUT3
RDWN
OUT3
(* HBeam)
Over-temperature
Prewarning
OUT4
(* Fog)
OUT4
OUT5
OUT5
(* Flash)
Shared Output Current
sensing pin (Analog MUX)
FETIN
(* Sense In)
CSNS
Current Recopy
Synchronization
Temperature
Feedback
VCC
Driver for an External
SMART MOSFET
FETOUT
(* Logic Level)
GND
* See 06XS3517 Typical Application
Figure 2. 06XS3517 Simplified Internal Block Diagram
06XS3517
Analog Integrated Circuit Device Data
2
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
Transparent
Top View
13 12 11 10
9
8
7
6
5
4
3
2
1
16
17
24
CP
CSNS
GND
23
GND
14
GND
OUT5
18
22
OUT1
15
VBAT
19
20
21
OUT2
OUT4
OUT3
Figure 3. 06XS3517 Pin Connections
Table 1. 06XS3517 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on Page 17.
Pin
Number
Pin Name Pin Function
Formal Name
Definition
This pin receives the current sense signal of the external SMART MOSFET.
1
2
FETIN
IGN
Input
Input
External FET Input
This input wakes the device. It also controls the Outputs 1 and 2 in case of Fail
mode activation. This pin has an internal pull-down resistor.
Ignition Input
(Active High)
This input wakes the device. It is also used to initialize the device configuration
and fault registers through SPI. This digital pin has a passive internal pull-down.
3
4
5
RSTB
FLASHER
CLOCK
Input
Input
Reset
This input wakes the device and allows control over channel 5. (FLASHER) This
pin has an internal pull-down resistor.
Flasher Input
(Active High)
This pin state depends on RSTB logic level.
Input/Output
Clock Input
As long as RSTB input pin is set to logic [0], this pin is pulled up to report wake
events. Otherwise, the PWM frequency and timing are generated from this
digital clock input by the PWM module.
This pin has a passive internal pull-down.
The Fail mode can be activated by this digital input. This pin has a passive
internal pull-down.
6
7
8
LIMP
FOG
CSB
Input
Input
Input
Limp Home Input
(Active High)
This input wakes the device. This pin has a passive internal pull-down.
FOG Input (Active
high)
When this digital signal is high, SPI signals are ignored. Asserting this pin low
starts a SPI transaction. The transaction is signaled as completed when this
signal returns high. This pin has a passive internal pull-up resistance.
Chip Select
(Active Low)
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 06XS3517 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on Page 17.
Pin
Number
Pin Name Pin Function
Formal Name
Definition
This digital input pin is connected to the master microcontroller providing the
required bit shift clock for SPI communication. This pin has a passive internal
pull-down resistance.
9
SCLK
SI
Input
Input
SPI Clock Input
This data input is sampled on the positive edge of the SCLK. This pin has a
passive internal pull-down resistance.
10
Master-Out Slave-
In
SPI logic power supply.
11
12
VCC
SO
Power
Output
Logic Supply
SPI data is sent to the MCU by this pin. This data output changes on the
negative edge of SCLK and when CSB is high, this pin is high-impedance.
Master-In Slave-
Out
This pin outputs a logic level that can be used to control an external SMART
MOSFET. This output is also called OUT6.
13
FETOUT
Output
External FET Gate
If OUT6 is not used in the application, this output pin is set to logic high when
the current sense output becomes valid when CSNS sync SPI bit is set to logic
[1].
This pin is the ground for the logic and analog circuitry of the device.
Power supply pin.
14,17,23
15
GND
VBAT
CP
Ground
Power
Output
Output
Ground
Battery Input
Charge Pump
This pin is the connection for an external tank capacitor (for internal use only).
Protected 17 m high side switch output terminals.
16
22
18
OUT1
OUT5
Output 1
Output 5
Protected 6.0 mhigh side switch output terminals
21
20
19
OUT2
OUT3
OUT4
Output
Output
Output 2
Output 3
Output 4
This pin is outputs the current sense signal of OUT1:OUT5, FETIN current, and
it is used externally to generate a ground-referenced voltage for the
microcontroller to monitor output current. If desired, this pin can also report a
voltage proportional to the temperature on the GND flag.
24
CSNS
Current Sense
Output
OUT1:OUT5, FETin current sensing and temperature sensing are activated
through the SPI interface.
Notes
1. The pins 14, 17, and 23 must be shorted on the board.
06XS3517
Analog Integrated Circuit Device Data
4
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or
permanent device damage.
Parameter
Symbol
Value
Unit
ELECTRICAL RATINGS
Over-voltage Test Range (all OUT[1:5] ON with nominal DC current)
Maximum operating voltage
V
V
V
BAT
BAT
28
40
Load dump (400 ms) @ 25 °C
Reverse Polarity Voltage Range (all OUT[1:5] ON with nominal DC current)
2.0 Min @ 25°C
V
-18
VCC Supply Voltage
V
-0.3 to 5.5
V
V
CC
OUT[1:5] Voltage
Positive
V
OUT
40
Negative (ground disconnected)
-16
Digital Current in Clamping Mode (SI, SCLK, CSB, RSTB, IGN, FLASHER, LIMP,
and FOG)
I
±1.0
mA
mA
IN
FETIN Input Current
I
+10
-1.0
FETIN
VSO
SO, FETOUT, CLOCK, and CSNS Outputs Voltage
-0.3 to V +0.3
CC
V
Outputs Clamp Energy Using Single Pulse Method (L = 2.0 mH; R = 0.0 ;
V
BAT = 14 V @150 °C initial)
mJ
OUT[1,5]
E1,5
30
OUT[2:4]
E2,3,4
100
ESD Voltage(2)
V
V
ESD
Human Body Model (HBM)
±2000
±8000
Human Body Model (HBM) OUT [1:5], VPWR, and GND
Charge Device Model (CDM)
Corner Pins (1, 13, 19, 21)
All Other Pins (2-12, 14-18, 20, 22-24)
750
500
Notes
2. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device
Model.
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground, unless mentioned otherwise. Exceeding these ratings may cause malfunction or
permanent device damage.
Parameter
Symbol
Value
Unit
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
Junction
Peak Package Reflow Temperature During Reflow(3)
Storage Temperature
TPPRT
TSTG
260
°C
-55 to 150
C
THERMAL RESISTANCE
Thermal Resistance, Junction to Case(4)
RJC
1.0
K/W
Notes
3. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
4. Typical value guaranteed per design.
06XS3517
Analog Integrated Circuit Device Data
6
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
POWER INPUTS (VBAT, VCC)
Symbol
Min
Typ
Max
Unit
Battery Supply Voltage Range
Full performance & short-circuit
V
V
BAT
7.0
6.0
–
–
20.0
28.0
Extended voltage range(5)
Battery Supply Under-voltage (UV flag is set ON)
Battery Supply Over-voltage (OV flag is set ON)
Battery Voltage Clamp(6)
V
5.0
27.5
40
5.5
30
–
6.0
32.5
48
V
V
V
V
BATUV
V
BATOV
V
BATCLAMP
Battery Supply Power on Reset
If VBAT < 5.5 V, VBAT = VCC
If VBAT < 5.5 V, VCC = 0
V
2.0
2.0
–
–
3.0
4.0
BATPOR1
BATPOR2
V
VBAT Supply Current @ 25 °C and V
= 12 V and V = 5.0 V
CC
BAT
Sleep state current, outputs opened
Sleep state current, outputs grounded
IBATSLEEP1
IBATSLEEP2
IBAT
–
–
–
0.5
0.5
5.0
5.0
A
A
Normal mode, IGN = 5.0 V, RSTB = 5.0 V, outputs open
10.0
20.0
mA
Digital Supply Voltage Range, Full Performance
Digital Supply Under-voltage (VCC Failure)
V
3.0
2.2
–
5.5
2.8
V
V
CC
V
2.5
CCUV
Sleep Current Consumption on V
Output OFF
@ 25 °C and V
= 12 V
BAT
A
I
CC
CCSLEEP
–
0.2
5.0
Supply Current Consumption on V
No SPI
and V
= 12 V
BAT
mA
I
CC
CC
–
–
–
–
2.6
5.0
3.0 MHz SPI communication
LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, FOG)
Input High Logic Level(7)
V
2.0
–
–
–
–
–
V
V
V
V
IH
Input Low Logic Level(7)
V
0.8
2.2
IL
IGNTH
Voltage Threshold for Wake-up (IGN, FLASHER, FOG, RST)
V
1.0
Input Clamp Voltage (IGN, FLASHER, LIMP, FOG, CS, SCLK, SI, RST)
I = 1.0 mA
V
CL_POS
7.5
–
13
Input Forward Voltage (IGN, FLASHER, LIMP, FOG, CS, SCLK, SI, RST)
I = -1.0 mA
V
V
CL_NEG
-2.0
100
100
–
-0.3
400
400
Input Passive Pull-up Resistance on CS Input(8)
R
200
200
k
k
UP
Input Passive Pull-down Resistance on SI, SCLK, FLASHER, IGN, FOG,
CLOCK, LIMP, RST pins(8)
R
DWN
Notes
5. In extended mode, the functionality is guaranteed but not the electrical parameters.
6. Outputs shorted to ground, I = + 500 mA and I = OCHI (guaranteed by design).
OUT
OUT
7. Valid for RST, SI, SCLK, CS, CLOCK, IGN, FLASHER, FOG, and LIMP pins.
8. Valid for the following input voltage range: -0.3 V to VCC +0.3 V.
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LOGIC INPUT/OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, FOG) (CONTINUED)
SO High-state Output Voltage
IOH = 1.0 mA
VSOH
VCC
0.8
–
0.95
0.2
–
SO Low-state Output Voltage
IOL = -1.6 mA
VSOL
V
0.4
CLOCK Output Voltage Reporting Wake-up Event (ICLOCK=1.0mA)
SO and CSNS Tri-state Leakage Current
VCLOCKH
ISOLEAK
0.8
0.95
0.0
–
VCC
A
V
-1.0
1.0
Current Sense Output Clamp Voltage
V
CSNS
CSNS open and I
= IFSR
5.0
6.0
–
7.0
OUT[1:5]
OUTPUTS (OUT 1-5)
Output Negative Clamp Voltage
= - 500 mA, Outputs OFF
V
V
OUT
I
-22.0
-16.0
OUT
Output Leakage Current in OFF State
Sleep mode, outputs grounded, TA = 25 °C
Sleep mode, outputs grounded, TA = 125 °C
Normal mode, outputs grounded
ILEAK(OFF)
µA
–
–
–
0.0
0.0
20
2.0
3.0
25
Current Sense Error(9) over the Full Voltage and Temperature Range
I /I
%
CS CS
%Full Scale Range (FSR), LED Control bit = 0, Channels 1,5 (17 m)
-14
-15
-17
-25
-40
0.0
0.0
0.0
0.0
0.0
14
15
17
25
40
point @ 0.75 FSR
point @ 0.50 FSR
point @ 0.25 FSR
point @ 0.1 FS
point @ 0.05FSR
% Full-Scale Range (FSR), LED Control bit =0, Channels 2,3,4 (6.0 m)
-14
-15
-17
-34
0.0
0.0
0.0
0.0
14
15
17
34
point @ 0.75 FSR
point @ 0.50 FSR
point @ 0.25 FSR
point @ 0.1 FSR
Current Sense error with one calibration point (50% FSR, VBAT = 13.5 at
25 °C(10)
-6.0
-6.0
–
–
6.0
6.0
%
%
Current Sense error with one calibration point (50% FSRLED, VBAT = 13.5 at
25 °C(10)
Temperature Drift of Current Sense Output(11)
I /T
ppm/°C
CS
V
= 13.5 V, I
= 2.8 A, I
= 5.5 A, reference taken at
OUT2-4
–
±280
175
±400
195
BAT
OUT1,5
T =25 °C
A
Over-temperature Shutdown
Notes
T
155
°C
OTS
9. 10 V < VBAT < 16 V. I /I
(measured I
targeted I )/ targeted I with targeted I = 5.0 mA. Test conditions of accuracy
CS - CS CS CS
CS CS =
measurement of point I(HS[1]) @ 0.05*FSR: I(HS[5]) = 0, I(HS[2]) = I(HS[3]) = I(HS[4]) =8.0 A
10. Based on statistical analysis covering 99.74% of parts, except 10% of FSR. Refer to Current Sense section for more details.
11. Based on statistical data. Not production tested. I /T=[(measured I at T - measured I at T ) / measured I at room] / (T -T )
CS
CS
1
CS
2
CS
1
2
06XS3517
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS (OUT 1-5) (CONTINUED)
Thermal Prewarning(12)
T
110
125
0.5
140
°C
OTSWARN
Output Voltage Threshold
V
0.475
0.525
VBAT
OUT_TH
CHANNEL 1 - PARKING LIGHT (17 m CHANNEL)
Output Drain-to-Source ON Resistance (I
= 2.8 A, T = 25 °C)
R
m
OUT
A
DS(ON)25
V
V
= 13.5 V
= 7.0 V
–
–
–
–
17
BAT
BAT
26.7
Output Drain-to-Source ON Resistance (I
= 150 °C)(12)
= 2.8 A, V
= 13.5 V,
BAT
R
m
m
OUT
DS(ON)150
T
A
–
–
–
–
28.9
34
Reverse Output ON Resistance (IOUT = -2.8 A, TA = 25 C)(13)
= -12 V
R
SD(ON)
V
BAT
High Over-current Shutdown Threshold 1, V
High Over-current Shutdown Threshold 2
Low Over-current Shutdown Threshold
= 16 V
I
I
48
56.2
25.8
11.5
0.3
72
30.5
14
A
A
BAT
OCHI1
OCHI2
21.0
9.0
I
A
OCLO
Open Load-current Threshold in ON State(14)
Open Load-current Threshold in ON State with LED(15)
= V - 0.8 V
I
0.08
0.77
A
OL
I
mA
OLLED
V
4.0
10.0
20.0
OUT
BAT
Current Sense Full-scale Range(16)
I
–
9.5
–
–
–
A
CS FSR
Severe Short-circuit Impedance Range(17)
R
R
225
m
SC1(OUT1)
CHANNEL 2 - LOW BEAM (6.0 m CHANNEL)
Output Drain-to-Source ON Resistance (I
= 5.5 A, T = 25 °C)
R
m
OUT
OUT
A
DS(ON)25
V
V
= 13.5 V
= 7.0 V
–
–
–
–
6.0
9.0
BAT
BAT
Output Drain-to-Source ON Resistance (I
= 150 °C)(17)
= 5.5 A, V
= 13.5 V,
BAT
m
m
DS(ON)150
–
–
10.2
T
A
Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C)(18)
= -12 V
R
SD(ON)
V
–
–
12.0
BAT
High Over-current Shutdown Threshold 1, V
High Over-current Shutdown Threshold 2
Notes
= 16 V
I
I
96
40
123
150
61
A
A
BAT
OCHI1
OCHI2
50.5
12. Parameter guaranteed by design, however, it is not production tested.
13. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
.
BAT
14. OLLED1, bit D0 in SI data is set to [0].
15. OLLED1, bit D0 in SI data is set to [1].
16. For typical value of ICS FSR, ICSNS = 5.0 mA.
17. Parameter guaranteed by design; however, it is not production tested.
18. Source-to-Drain ON resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
.
BAT
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CHANNEL 2 - LOW BEAM (6.0 m CHANNEL) (CONTINUED)
Low Over-current Shutdown Threshold
Optional Xenon lamp
I
A
OCLO
28
17
35
42
28
Optional H7 bulb
22.5
Open Load Current Threshold in ON State(19)
I
0.15
0.62
1.55
A
OL
Open Load Current Threshold in ON State with LED(20)
I
mA
OLLED
V
= V
- 0.8 V
BAT
4.0
10.0
20.0
OL
Current Sense Full-scale Range(21)
Optional Xenon bulb
I
A
CS FSR
–
–
30
19
–
–
Optional H7 bulb
Severe Short-circuit Impedance Range(22)
SC1(OUT2)
R
65
–
–
m
m
CHANNEL 3- HIGH BEAM (6.0 m CHANNEL)
Output Drain-to-Source ON Resistance (I
= 5.5 A, T = 25 °C)
R
DS(ON)25
OUT
A
–
–
–
–
6.0
9.0
V
V
= 13.5 V
= 7.0 V
BAT
BAT
Output Drain-to-Source ON Resistance (I
= 150 °C)(22)
= 5.5 A, V
= 13.5 V,
R
m
m
OUT
BAT
DS(ON)150
–
–
–
–
10.2
12
T
A
Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C)(23)
= -12 V
R
SD(ON)25
V
BAT
High Over-current Shutdown Threshold 1, V
High Over-current Shutdown Threshold 2
= 16 V
I
96
40
123
150
61
A
A
A
BAT
OCHI1
I
50.5
OCHI2
Low Over-current Shutdown Threshold
H7 Bulb
I
OCLO
17
22.5
0.62
28
Open Load Current Threshold in ON State(24)
Open Load Current Threshold in ON State with LED(25)
= V - 0.8 V
OL
I
0.15
1.55
A
I
mA
OLLED
4.0
10.0
20.0
V
OL
BAT
Current Sense Full-scale Range (21)
CS FSR
SC1(OUT3)
I
–
19
–
–
–
A
Severe Short-circuit Impedance Range(22)
R
65
m
Notes
19. OLLED2, bit D1 in SI data is set to [0].
20. OLLED2, bit D1 in SI data is set to [1].
21. For typical value of I
CS FSR, ICSNS = 5.0mA.
22. Parameter guaranteed by design; however, it is not production tested.
23. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
.
BAT
24. OLLED3, bit D2 in SI data is set to [0].
25. OLLED3, bit D2 in SI data is set to [1].
06XS3517
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CHANNEL 4 - FOG LIGHT(6.0 m CHANNEL)
Output Drain-to-Source ON Resistance (I
= 5.5 A, T = 25 °C)
R
m
OUT
A
DS(ON)25
–
–
–
–
6.0
9.0
V
V
= 13.5 V
= 7.0 V
BAT
BAT
Output Drain-to-Source ON Resistance (I
= 150 °C)(26)
= 5.5 A, V
= 13.5 V,
R
m
m
OUT
BAT
DS(ON)150
–
–
–
–
10.2
12
T
A
Reverse Source-to-Drain ON Resistance (IOUT = -5.5 A, TA = 25 C)(27)
= -12 V
R
SD(ON)25
V
BAT
High Over-current Shutdown Threshold 1, V
High Over-current Shutdown Threshold 2
= 16 V
I
96
40
123
150
61
A
A
A
BAT
OCHI1
I
50.5
OCHI2
Low Over-current Shutdown Threshold
H7 Bulb
I
OCLO
17
22.5
0.62
28
Open Load Current Threshold in ON State(28)
Open Load Current Threshold in ON State with LED(29)
= V - 0.8 V
OL
I
0.15
1.5
A
I
mA
OLLED
4.0
10.0
20.0
V
OL
BAT
Current Sense Full Scale Range(30)
CS FSR
SC1(OUT4)
I
–
19
–
–
–
A
Severe Short-circuit Impedance Range(26)
R
65
m
CHANNEL 5 - FLASHER (17 m CHANNEL)
Output Drain-to-Source ON Resistance (I
= 2.8 A, T = 25 °C)
R
m
OUT
A
DS(ON)25
–
–
–
–
17
V
V
= 13.5 V
= 7.0 V
BAT
BAT
26.7
Output Drain-to-Source ON Resistance (I
= 150 °C)(31)
= 2.8 A, V
= 13.5 V,
R
m
m
OUT
BAT
DS(ON)150
–
–
–
–
18.9
34
T
A
Reverse Source-to-Drain ON Resistance (IOUT = -2.8A, TJ = 25C)(32)
= -12V
R
SD(ON)25
V
BAT
High Over-current Shutdown Threshold 1,
High Over-current Shutdown Threshold 2
Low Over-current Shutdown Threshold
I
I
48
21.0
9.0
56.2
25.8
11.5
72
30.5
14
A
A
A
OCHI1
OCHI2
I
OCLO
Notes
26. Parameter guaranteed by design; however, it is not production tested.
27. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
.
BAT
BAT
28. OLLED4, bit D3 in SI data is set to [0].
29. OLLED4, bit D3 in SI data is set to [1].
30. For typical value of ICS FSR, ICSNS = 5.0 mA.
31. Parameter guaranteed by design; however, it is not production tested.
32. Source-to-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V
.
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CHANNEL 5 - FLASHER (17 m CHANNEL) (CONTINUED)
Open Load Current Threshold in ON State(33)
OL
I
0.08
4.0
0.3
0.77
20.0
A
Open Load Current Threshold in ON State with LED(34)
OLLED
I
mA
10.0
V
= V
- 0.8 V
BAT
OL
Current Sense Full Scale Range(35)
CS FSR
I
–
8.8
–
–
–
A
Severe Short-circuit Impedance Range(36)
SC1(OUT5)
R
225
m
SPARE FETOUT(OUT6) / FETIN (OUT1)
FETOUT Output High Level @ I = 1.0 mA
FETOUT Output Low Level @ I = -1.0 mA
FETIN Input Full Scale Range Current
FETIN Input Clamp Voltage
V
0.8
–
–
–
0.4
–
V
CC
H MAX
V
0.2
5.0
V
mA
V
H MIN
I
–
FETIN
V
CLIN
I
= 5.0 mA, CSNS open
5.3
0.0
–
–
–
13
0.4
6.0
FET IN
Drop Voltage on FETIN (FETIN - CSNS)
= 5.0 mA, 5.5 V > CSNS > 3.0 V
V
V
DRIN
I
FETIN
FETIN Leakage Current When External Current Switch Sense Is Enabled
5.5 V > V > 0.0 V, CSNS open
IFETINLEAK
A
-1.0
FETIN
TEMPERATURE OF GND FLAG
Analog Temperature Feedback Range
-40
925
10.9
–
150
1075
11.7
°C
mV
T
V
FEED_RANGE
Analog Temperature Feedback at TA = 25 °C with 5.0 k > RCSNS > 500
V
1000
11.3
T_FEED
Analog Temperature Feedback Derating with 5.0 k > RCSNS > 500 (36)
DT_FEED
V
mV/°C
Analog Temperature Feedback Precision (36)
DT_ACC
DT_ACC_CAL
V
-15
–
–
15
°C
°C
Analog Temperature Feedback Precision with calibration point at 25 °C (36)
-5.0
5.0
Notes
33. OLLED5, bit D4 in SI data is set to [0].
34. OLLED5, bit D4 in SI data is set to [1].
35. For typical value of ICS FSR, ICSNS = 5.0 mA.
36. Parameter guaranteed by design; however, it is not production tested.
06XS3517
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS TIMING (OUT1 TO OUT5)
Current Sense Valid Time (valid for resistive loads only),(37)
s
tCSNS(VAL)
0
0
100
50
200
100
SR bit = 0
SR bit = 1
Current Sense Settling Time on Resistive Load Only(37)
s
tCSNS(SET)
tSYNC(val)
–
10
30
Current Sense Synchronization signal - typical validation time
SR bit = 0
SR bit = 1
0
0
90
45
180
90
SR
R
V/s
Driver Output Positive Slew Rate (30% to 70% @ V
SR bit = 0
= 14 V)
BAT
0.14
0.2
0.4
0.4
0.8
0.8
I
I
= 2.8 A for OUT1 and OUT5
OUT
OUT
= 5.5 A for OUT2, OUT3, and OUT4
SR bit = 1
0.28
0.4
0.8
0.8
1.6
1.6
I
I
=0.7 A for OUT1 and OUT5
OUT
OUT
= 1.4 A for OUT2, OUT3, and OUT4
SR
F
V/s
Driver Output Negative Slew Rate (70% to 30% @ V
SR bit = 0
= 14 V)
BAT
0.14
0.2
0.4
0.4
0.8
0.8
I
I
= 2.8 A for OUT1 and OUT5
OUT
OUT
= 5.5 A for OUT2, OUT3, and OUT4
SR bit = 1
0.28
0.4
0.8
0.8
1.6
1.6
I
I
= 0.7 A for OUT1 and OUT5
OUT
OUT
= 1.4 A for OUT2, OUT3, and OUT4
SR
Driver Output Matching Slew Rate (SR /SR ) (70% to 30% @ V = 14 V
BAT
R
F
@25 °C)
SR bit = 0: I
= 2.8 A for OUT1 and OUT5 and I
= 0.7 A for OUT1 and OUT5 and I
= 5.5 A for OUT2/3/4
= 1.4 A for OUT2/3/4
0.8
0.8
1.0
1.0
1.2
1.2
OUT
OUT
OUT
OUT
SR bit = 1: I
s
s
tDLYON
Driver Output Turn-ON Delay (SPI ON Command [No PWM, CS Positive
Edge] to Output = 50% V @ V = 14 V) (see Figure 6)
BAT
BAT
SR bit = 0: I
SR bit = 1: I
= 2.8 A for OUT1 and OUT5 and I
= 0.7 A for OUT1 and OUT5 and I
= 5.5 A for OUT2/3/4
= 1.4 A for OUT2/3/4
65
35
–
–
300
120
OUT
OUT
OUT
OUT
tDLYOFF
Driver Output Turn-OFF Delay (SPI OFF command [CS Positive Edge] to
Output = 50% V @ V = 14 V) (see Figure 6)
BAT
BAT
SR bit = 0: I
SR bit = 1: I
= 2.8 A for OUT1 and OUT5 and I
= 0.7 A for OUT1 and OUT5 and I
= 5.5 A for OUT2/3/4
= 1.4 A for OUT2/3/4
40
15
–
–
110
80
OUT
OUT
OUT
OUT
Notes
37. Not production tested. See Figure 7, Current Sensing Time Delays.
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUTS TIMING (OUT1 TO OUT5) (CONTINUED)
Driver Output Matching Time (tDLY(ON) - tDLY(OFF)) @ Output = 50% V
s
tRF
BAT
with V
= 14 V, f
= 240 Hz,
= 50%, @25 °C
PWM
BAT
PWM
10
–
–
200
70
SR bit = 0: I
SR bit = 1: I
= 2.8 A for OUT1 and OUT5 and I
= 0.7 A for OUT1 and OUT5 and I
= 5.5 A for OUT2/3/4
= 1.4 A for OUT2/3/4
OUT
OUT
OUT
5.0
OUT
PWM MODULE
f
60.0
7.68
4.0
–
–
–
400
51.2
96
Hz
kHz
%
PWM Frequency Range
PWM
f
Clock Input Frequency Range
CLK
PWM_MAX
Output PWM Duty Cycle maximum range for 11 V<VBAT<18 V(38), (39)
PWM_LIN
Output PWM Duty Cycle linear range for 11 V<VBAT<18 V(40)
5.5
–
96
%
WATCHDOG TIMING
t
50
75
100
ms
Watchdog Timeout (SPI Failure)
WDTO
I/O PLAUSIBILITY CHECK TIMING
s
tSD
Fault Shutdown Delay Time (from Over-temperature or OCHI1 or OCHI2 or
OCLO or UV Fault Detection to Output = 50%V
without round shaping
–
7.0
30
BAT
feature for turn off)
ms
ms
ms
ms
t1
High Over-current Threshold Time 1
for OUT1 and OUT5
7.0
14
10
20
13.5
26
for OUT2, OUT3, and OUT4
t2
High Over-current Threshold Time 2
for OUT1 and OUT5
52.5
105
75
97.5
195
150
for OUT2, OUT3, and OUT4
tAUTORST
Autorestart Period
52.5
105
75
97.5
195
for OUT1 and OUT5
for OUT2, OUT3, and OUT4
150
tOCHI_AUTO
Autorestart Over-current Shutdown Delay Time
for OUT1 and OUT5
3.5
7.0
5.0
6.5
10.0
13.0
for OUT2, OUT3, and OUT4
t
7.0
10.0
150
13.0
195
ms
ms
Limp Home Input pin Deglicher Time
LIMP
Cyclic Open Load Detection Timing with LED(41)
Flasher Toggle Timeout
Fog Toggle Timeout
105
tOLLED
t
1.4
1.4
2.3
2.3
3.0
3.0
s
s
FLASHER
t
FOG
Notes
38. Not production tested. See Figure 7, Current Sensing Time Delays.
39. The PWM ratio is measured at VOUT = 50% of VBAT in nominal range of PWM frequency (from 60 Hz to 400 Hz). It is possible to put the
device fully on (PWM duty cycle = 100%) and fully off (PWM duty cycle = 0%). Between 4%-96%, OCHI1,2, OCLO and open load are
available in ON state. See Figure 6, Output Slew Rate and Time Delays.
40. Linear range is defined by output duty cycle to SPI duty cycle configuration +/-1 LSB. For values outside linear duty cycle range, a
calibration curve is available.
41. IOLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 8, Serial Input Address
and Configuration Bit Map, page 25.
06XS3517
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0 V VCC 5.5 V, 7.0 V VBAT 20 V, -40 C TA 125 C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
I/O PLAUSIBILITY CHECK TIMING (CONTINUED)
t
1.4
1.0
100
2.3
2.0
200
3.0
4.0
400
s
Ignition Toggle Timeout
IGNITION
LCLK DET
HCLK DET
f
f
kHz
kHz
Clock Input Low Frequency Detection Range
Clock Input High Frequency Detection Range
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
fSPI
tCSB
–
–
–
–
–
–
–
–
–
–
3.0
1.0
500
167
167
167
83
MHz
us
Rising Edge of CSB to Falling Edge of CSB (Required Setup Time)(42)
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)(42)
Required High State Duration of SCLK (Required Setup Time)(42)
Required Low State Duration of SCLK (Required Setup Time)(42)
Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)(42)
SI to Falling Edge of SCLK (Required Setup Time)(43)
Falling Edge of SCLK to SI (Required Setup Time)(43)
tLEAD
–
ns
tWSCLKH
tWSCLKL
tLAG
–
ns
–
ns
50
25
25
ns
tSI(SU
tSIHOLD
tRSO
ns
83
ns
SO Rise Time
CL = 80 pF
ns
–
25
50
SO Fall Time
CL = 80 pF
tFSO
ns
–
25
50
SI, CSB, SCLK Incoming Signal Rise Time(43)
SI, CSB, SCLK Incoming Signal Fall Time(43)
Time from Falling Edge of SCLK to SO Low-impedance(44)
Time from Rising Edge of SCLK to SO High-impedance(45)
Notes
tRSI
tFSI
tSO(EN)
tSO(DIS)
–
–
–
–
–
–
50
50
ns
ns
ns
ns
–
145
145
65
42. Maximum setup time required for the 06XS3517 is the minimum guaranteed time needed from the microcontroller.
43. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
44. Time required for output status data to be available for use at SO. 1.0 kon pull-up on CSB.
45. Time required for output status data to be terminated at SO. 1.0 kon pull-up on CSB.
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
VIL
t
t
CSB
ENBL
VIH
90% V
CC
CSB
10%V
CC
VIL
t
RSI
I
t
WSCLKH
t
LEAD
t
LAG
VIH
90% VCC
SCLKB
10% VCC
VIL
t
SI(SU)
t
WSCLKL
t
FSI
t
SI(HOLD)
VIH
90%V
CC
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SIB
10%VCC
VIL
Figure 4. Input Timing Switching Characteristics
t
t
FSI
RSI
VOH
2.0 V
50%
SCLKB
0.8 V
VOL
tSO(EN)
VOH
90% V
CC
SOB
10%VCC
VOL
Low to High
tRSO
tVALID
tFSO
SOB
VOH
90% V
CC
High to Low
10% VCC
VOL
tSO(DIS)
Figure 5. SCLK Waveform and Valid SO Data Delay Time
06XS3517
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
CSB
High logic level
Low logic level
Time
VOUT[1:5]
V
PWR
R
PWM
50%V
PWR
Time
tDLY(OFF)
tDLY(ON)
VOUT[1:5]
70% V
PWR
SRF
SRR
30% V
PWR
Time
Figure 6. Output Slew Rate and Time Delays
CSB
High logic level
Low logic level
Time
Time
IOUT[1:5]
I
MAX
tDLY(OFF)
tDLY(ON)
tCSNS(VAL)
tCSNS(SET)
ICSNS
Time
VFETOUT
tSYNC(VAL)
High logic level
only available with CSNS sync bit = 1
Low logic level
Time
Figure 7. Current Sensing Time Delays
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 06XS3517 is designed for low-voltage automotive and
industrial lighting applications. Its five low RDS(ON) MOSFETs
(three 6.0 mandtwo 16 m) can control the high sides of
five separate resistive loads (bulbs). Programming, control,
and diagnostics are accomplished using a 16-bit SPI
interface.
FUNCTIONAL PIN DESCRIPTION
SUPPLY VOLTAGE (VBAT)
The VBAT pin of the 06XS3517 is the power supply of the
device. In addition to its supply function, this tab contributes
to the thermal behavior of the device by conducting the heat
from the switching MOSFETs to the printed circuit board.
SUPPLY VOLTAGE (VCC)
This is an external voltage input pin used to supply the
digital portion of the circuit and the gate driver of the external
SMART MOSFET.
GROUND (GND)
This pin is the ground of the device.
CLOCK INPUT / WAKE-UP OUTPUT (CLOCK)
When the part is in Normal mode (RST=1), the PWM
frequency and timing are generated from the rising edge of
clock input by the PWM module. The clock input frequency is
the selectable factor 27 = 128 or 28 = 256 of the PWM
frequency per output, depending PR bit value.
The OUT1:6 can be controlled in the range of 4% to 96%
with a resolution of 7 bits of the duty cycle (bits D[6:0]).
The synchronization of the switching phases between
different IC is provided by an SPI command in combination
with the CSB input. The bit in the SPI is called PWM sync
(initialization register).
Figure 5 describes the PWM resolution.
Table 5. PWM Resolution
On/Off Duty cycle (7 bits
Output state
In Normal mode, no PWM feature (100% duty cycle) is
provided in the following instances:
(Bit D7)
resolution)
X
0
OFF
• With the following SPI configuration: D7:D0=FF.
• In case of clock input signal failure (out of fPWM), the
outputs state depends of D7 bit value (D7=1=ON) in
Normal mode.
1
0000000
PWM (1/128 duty cycle)
PWM (2/128 duty cycle)
PWM (3/128 duty cycle)
fully ON
1
1
1
0000001
0000010
1111111
In Fail mode, the ouputs state depend on IGN, FLASHER,
and FOG pins.
If RSTB=0, this pin reports the wake-up event for wake=1
when VBAT and VCC are in operational voltage range.
The timing includes four programmable PWM switching
phases (0°, 90°, 180°, and 270°) to improve overall EMC
behavior of the light module.
LIMP HOME INPUT (LIMP)
As an example: When the load currents have equal
amplitude, the amplitude of the input current is divided by
four, while the ripple frequency is 4 times the original. The two
following pictures illustrate this behavior.
The Fail mode of the component can be activated by this
digital input port. The signal is “high active”, meaning the Fail
mode can be activated by a logic high signal at the input.
mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
IGNITION INPUT (IGN)
The ignition input wakes the device. It also controls the Fail
06XS3517
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
FLASHER INPUT (FLASHER)
FETOUT OUTPUT (FETOUT)
The flasher input wakes the device. It also controls the Fail
Mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
This output pin can be used to control an external SMART
MOSFET (OUT6) at a logic level (1=ON, 0=OFF).
The high level of the FETOUT Output is VCC, if VBAT and
VCC are available, in case FETOUT is a controlled ON.
FOG INPUT (FOG)
FETOUT is not protected if there is a short-circuit or under-
voltage on VBAT.
The fog input wakes the device. It also controls the Fail
Mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
In case of a reverse battery, OUT6 is OFF.
FETIN INPUT (FETIN)
RESET INPUT (RSTB)
This input pin receives the current recopy from an external
SMART MOSFET. It can be routed on CSNS output by a SPI
command.
This input wakes the device when the RSTB pin is at
logic [1]. It is also used to initialize the device configuration
and the SPI faults registers when the signal is low. All SI/SO
registers described Table 8 and Table are reset. The fault
management is not affected by RSTB (see Figure 2).
SPI PROTOCOL DESCRIPTION
The SPI interface has a full-duplex, three-wire,
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CSB).
CURRENT SENSE OUTPUT (CSNS)
The current sense output pin is an analog current output or
a voltage proportional to the temperature on the GND flag.
The routing to the external resistor is SPI programmable.
The SI/SO pins of the 06XS3517 device follow a first-in,
first-out (D15 to D0) protocol, with both input and output
words transferring the most significant bit (MSB) first. All
inputs are compatible with 3.3 V and 5.0 V CMOS logic
This current sense monitoring may be synchronized in
case of the OUT6 is not used. The CSNS output is valid after
a rising edge on the FETOUT pin (after tsync(val) s.) if the
CSNS sync SPI bit was set to logic [0] and remains valid till a
falling edge is generated. Connection of the FETOUT pin to
a MCU input pin allows the MCU to sample the CSNS pin
during a valid time slot. Since this falling edge is generated at
the end of this time slot, upon a switch-off command, this
feature may be used to implement maximum current control.
levels, supplied by VCC
.
The SPI lines perform the following functions:
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the
06XS3517 device. The SI pin accepts data into the input shift
register on the falling edge of the SCLK signal, while the SO
pin shifts data information out of the SO line driver on the
rising edge of the SCLK signal. It is important that the SCLK
pin be in a logic low state whenever CSB makes any
transition. For this reason, it is recommended the SCLK pin
be in a logic [0] whenever the device is not accessed (CSB
logic [1] state). SCLK has a passive pull-down, RDWN. When
CSB is logic [1], signals at the SCLK and SI pins are ignored,
and SO is tri-stated (high-impedance) (see Figure 8).
CHARGE PUMP (CP)
An external capacitor must be connected between the CP
and the VBAT pin. It is used as a tank for the internal charge
pump. Its value is 100 nF ±20%, 25 V maximum.
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CS
SCLK
SI
D15
D14
D13
D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Notes
1. D15:D0 relate to the most recent ordered entry of data into the device.
2. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.
Figure 8. Single 16-Bit Word SPI Communication
SERIAL INPUT (SI)
CHIP SELECT (CS)
The SI pin is a serial interface command data input pin.
Each SI bit is read on the falling edge of SCLK. A 16-bit
stream of serial data is required on the SI pin, starting with
The CSB pin enables communication with the master
device. When this pin is in a logic [0] state, the device is
capable of transferring information to, and receiving
D15 to D0. SI has a passive pull-down, RDOWN
.
information from, the master device. The 06XS3517 device
latches in data from the Input Shift registers to the addressed
registers on the rising edge of CSB. The device transfers
status information from the power output to the Shift register
on the falling edge of CSB. The SO output driver is enabled
when CSB is logic [0]. CSB should transition from a logic [1]
to a logic [0] state only when SCLK is a logic [0]. CSB has a
SERIAL OUTPUT (SO)
The SO data pin is a tri-stateable output from the shift
register. The SO pin remains in a high-impedance state until
the CSB pin is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO pin
changes state on the rising edge of SCLK and reads out on
the falling edge of SCLK.
passive pull-up, RUP
.
06XS3517
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION MODES
FUNCTIONAL DEVICE OPERATION
OPERATION MODES
SLEEP MODE
D7 bit
The Sleep mode is the default mode of the 06XS3517.
This is the state of the device after first applying battery
voltage (VBAT) and prior to any I/O transitions. This is also the
state of the device when IGN, FOG, FLASHER, and RSTB
are logic [0] (wake=0). In the Sleep mode, the outputs and all
internal circuitry are OFF to minimize current draw. In
addition, all SPI-configurable features of the device are reset.
The 06XS3517 will transit to two modes (Normal and Fail)
depending on wake and fail signals (see Fig13).
D0-D6 bits
Output
Over-current
FAIL MODE
The transition to the other modes is according following
signals:
The 06XS3517 is in Fail mode when:
• Wake = IGN or IGN_ON or FLASHER or
FLASHER_ON or RSTB or FOG or FOG_ON
• Fail = VCC fail or SPI fail or External limp
• Wake = 1
• Fail = 1.
In Fail mode:
• The outputs are under control of external pins (see
Table 6)
NORMAL MODE
The 06XS3517 is in Normal mode when:
• The outputs are fully protected in case of an overload,
over-temperature and under-voltage (on VBAT or on
VCC).
• Wake = 1
• Fail = 0
• The SPI reports continuously the content of address 11
(Initialization register), regardless previously requested
output data word.
• Analog current sense is not available.
• Output 2 is configured in Xenon mode.
• In case of an overload (OCHI2 or OCLO) conditions or
under-voltage on VBAT, the outputs are under control
of autorestart feature.
In Normal operating mode the power outputs are under full
control of the SPI as follows:
• The outputs 1 to 6, including multiphase timing and
selectable slew-rate, are controlled by the
programmable PWM module.
• The outputs 1 to 5 are switched OFF in case of an
under-voltage on VBAT.
• The outputs 1 to 5 are protected by the selectable over-
current double window and over-temperature shutdown
circuit.
• The digital diagnosis feature transfers status of the
smart outputs via SPI.
• In case of serious overload condition (OCHI1 or OT) the
corresponding output is latched OFF until a new wake-
up event (wake=0 then 1).
IGN_ON
• The analog current sense output (current recopy
feature) can be routed by SPI.
• The outputs 1 and 5 can be configured to control LED
loads.
1.4 sec min
IGN (external)
OUT[1,2]
• The SPI reports NM=1 in this mode.
The figure below describes the PWM, outputs and over-
current behavior in Normal mode.
Over-current
Table 6. Output States During Limp Home
Output 1
Parking Light
Output 2
Low Beam
Output 3
High Beam
Output 4
Fog Light
Output 5
Flasher
External Switch
Spare
IGN Pin
IGN Pin
OFF
FOG Pin
FLASHER Pin
OFF
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
OPERATION MODES
The Autorestart is not limited in time.
AUTORESTART STRATEGY
The autorestart circuitry is used to supervise the outputs
and reactivate high side switches in cases of overload or
under-voltage failure conditions, to provide a high availability
of the outputs.
TRANSITION FAIL TO NORMAL MODE
To leave Fail mode, the fail condition must be removed
(fail=0). The microcontroller has to toggle the SPI D10 bit (0
to 1) to reset the watchdog bit (WD); the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode.
Autorestart feature is available in Fail mode (after loss of
SPI communication). Autorestart is activated in case of
overload condition (OCHI2 or OCLO) or under-voltage
condition on VBAT (see Figure 12).
TRANSITION NORMAL TO FAIL MODE
The autorestart periodically switches ON the outputs.
During ON state of the switch OCHI1 window is enabled for
tochi_Auto, then after the output is protected by OCLO.
To leave the Normal mode, a fail condition must occur
(fail=1). The previous latched faults are reset by the transition
into Fail mode.
Output current
If the SI is shorted to VDD, the device transmits to Fail
Safe mode until the WD bit toggles through the SPI (from [0]
to [1]).
OCHI1
All settings are according to predefined values (all bits set
to logic [0]).
OCLO or UV fault
START-UP SEQUENCE
The 06XS3517 enters in Normal mode after start-up if
following sequence is provided:
OCLO
• VBAT and VCC power supplies must be above their
under-voltage thresholds (Sleep mode).
• generate wake up event (wake=1) from 0 to 1 on RSTB.
The device switches to Normal mode.
• apply PWM clock after maximum 200 s (min 50 s).
• send SPI command to the Device status register to clear
the clock fail flag to enable the PWM module to start.
tochi_auto
time
Auto period
Figure 9. Over-current window in case of Autorestart
In case of OCHI1 or OT, the channel is latched OFF until
wake-up (wake=0 then 1).
Figure 10 describes the wake-up block diagram.
In case of OCLO or under-voltage, the output is switched
OFF and turned On again automatically after the autorestart
period (150 ms for 6.0 mOhm channels or 75 ms for
17 mOhm channels).
POWER OFF MODE
The 06XS3517 is in Power OFF mode when the battery
voltage is below VBATPOR[1,2] thresholds. For more details,
refer to Loss of VBAT.
In case of an under-voltage in Fail mode, the outputs 1 to
5 will be latched off. The corresponding output is switched on
only after the autorestart period (tAUTORST-T1 or tAUTORST-T2).
06XS3517
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATION MODES
(fail=0) and (wake=1)
Sleep
(wake=0)
(wake=1) and (fail=1) *
(wake=0)
VBAT < VBATPOR[1,2]
VBAT > VBATPOR[1,2]
VBAT < VBATPOR[1,2]
Power OFF
VBAT < VBATPOR[1,2]
Normal
Fail
(fail=0) and (wake=1)
(fail=1) and (wake=1)
Notes:
* only available in case of a Vcc fail condition
wake = (RSTB = 1) OR (IGN_ON = 1) OR (Flasher_ON = 1) OR (FOG_ON = 1)
fail = (VCC_fail = 1) OR (SPI_fail = 1) OR (ext_limp = 1)
Figure 10. Operating Modes State Machine
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATION MODES
VBAT
wake
Wake-up bar
VBAT
VCC
Internal
regulator
IGN_ON
IGN
Watchdog
Dig2.5V
Flasher_ON
FLASHER
Watchdog
Oscillator
Fog_ON
Fault
management
PWM freq
detector
FOG
Watchdog
SPI registers
PWM module
VCC fail
SPI fail
RSTB
OR
Fail
External
Limp
reset
VCC
OR
UVF
CLOCK
1.4 sec min
external
external_ON
external: IGN, FLASHER, FOG
external_ON: IGN_ON, FLASHER_ON, FOG_ON
Figure 11. Wake-up Block Diagram
06XS3517
Analog Integrated Circuit Device Data
24
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
SERIAL INPUT COMMUNICATION
SPI communication compliant to 3.3 V and 5.0 V is
accomplished using 16-bit messages. A message is
transmitted by the master starting with the MSB, D15, and
ending with the LSB, D0. Each incoming command message
on the SI pin can be interpreted using the bit assignment
described in Table 7. The 5 bits D15:D11, called register
address bits, are used to select the command register. Bit
D10 is the watchdog bit. The remaining 10 bits, D9:D0, are
used to configure and control the output and its protection
features. Multiple messages can be transmitted in
Table 7. SI Message Bit Assignment
Message Bit Description
Register address bits.
Bit Sig
MSB
SI Msg Bit
D15:D11
Watchdog in: toggled to satisfy watchdog
requirements.
D10
Used to configure inputs, outputs, device
protection features, and SO status content.
LSB
D9:D0
succession to accommodate those applications where daisy
chaining is desirable or to confirm transmitted data as long as
the messages are all multiples of 16 bits. Any attempt made
to latch in a message that is not 16 bits will be ignored.
DEVICE REGISTER ADDRESSING
The register addresses (D15:D11) and the impact of the
serial input registers on device operation are described in this
section. Table 8 summarizes the SI registers.
All SPI registers are reset (all bit equal 0) in case of RSTB
equal 0 or fail mode (Fail=1).
Table 8. Serial Input Address and Configuration Bit Map
SI Address
SI Data
SI Register
D1 D1 D1 D1 D1
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
5
4
3
2
1
0
0
0
0
0
WD
0
0
FOGen PWM
sync
Xenon MUX2
MUX1
MUX0
SOA1
SOA0
Initialization
Config OL
0
0
0
0
0
0
0
1
1
0
WD
WD
05
0
0
0
0
0
0
OLLED5 OLLED4 OLLED3 OLLED2 OLLED1
Config
Prescaler
PR1
PR2
PR3
0
0
0
0
PR4
SR4
PR5
SR5
PR6
0
Config SR
0
0
0
0
0
0
1
1
0
1
WD
1
SR1
0
SR2
0
SR3
0
0
0
WD CSNS
sync
NO_OC NO_OC NO_OC NO_OC NO_OC
HI5 HI4 HI3 HI2 HI1
Config CSNS
Control
OUT1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
WD Phase2 Phase1 ONoff PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
Control
OUT2
Control
OUT3
Control
OUT4
Control
OUT5
Control
External
Switch
RESET
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Note: testmode address used only by FSL is D[15:11]=01111 with RSTB pin voltage higher than 8.0 V typ.
X = Don’t care and 0 = need to rewrite logic “0”
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The watchdog timeout is specified by tWDTO parameter. As
long as the WD bit (D10) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally. If an internal
watchdog timeout occurs before the WD bit is toggled, the
device will revert to Fail mode. All registers are cleared. To
exit the Fail mode, send valid SPI communication with
WD bit = 1.
ADDRESS 00000—INITIALIZATION
The Initialization register is used to read the various
statuses, choose one of the six outputs current recopy, load
the H7 bulbs profile for OUT2 only, enable the FOG pin and
synchronize the switching phases between different devices.
The register bits D1 and D0 determine the content of the 16
bits of the next SO data. (Refer Serial Output Communication
(Device Status Return Data)) Table describes the register of
initialization.
Table 9. Initialization Register
SI Address
SI Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
WD
0
0
FOGen PWM Xenon MUX2 MUX1 MUX0 SOA1 SOA0
sync
D6 (PWM sync) = 0, No synchronization
D4, D3, D2 (MUX2, MUX1, MUX0) = 000, No current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 001, OUT1 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 010, OUT2 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 011, OUT3 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 100, OUT4 current sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 101, OUT5 current sense
D6 (PWM sync) = 1, Synchronization on CSB positive edge
D5 (Xenon) = 0, Xenon
D5 (Xenon) = 1, H7 Bulb
D7 (FOGen) = 0, FOG pin does not control the output 4
D7 (FOGen) = 1, FOG input controls the output 4
D4, D3, D2 (MUX2, MUX1, MUX0) = 110, External Switch current
sense
D4, D3, D2 (MUX2, MUX1, MUX0) = 111, Temperature analog feedback
ADDRESS 00001—CONFIGURATION OL
ADDRESS 00011—CONFIGURATION CSNS
The Configuration OL register is used to enable the open
load detection for LEDs in Normal mode (OLLEDn in Table 8)
and to active the LED Control.
The Configuration Current Sense register is used to
disable the high over-current shutdown phase (OCHI1 and
OCHI2 dynamic levels) in order to activate immediately the
current sense analog feedback.
When bit D0 is set to logic [1], the open load detection
circuit for LED is activated for output 1. When bit D0 is set to
logic [0], open load detection circuit for standard bulbs is
activated for output 1.
When bit D9 is set to logic [1], the current sense
synchronization signal is reported on FETOUT output pin.
When the corresponding NO_OCHI bit is set to logic [1],
the output is only protected with OCLO level. The current
sense is immediately available if it is selected through SPI, as
described in Figures 13. The NO_OCHI bit per output is
automatically reset at each corresponding ON/OFF bit
transition from logic [1] to [0], and in case of over-temperature
or over-current fault. All NO_OCHI bits are also reset in case
of under-voltage fault detection.
When bit D5 is set to logic [1], the LED Control is activated
for output 1.
ADDRESS 00010—CONFIGURATION PRESCALER
AND SR
Two configuration registers are available at this address.
The Configuration Prescaler when D9 bit is set to logic [0] and
Configuration SR when D9 bit is set to logic [1].
ADDRESS 01001—CONTROL OUT1
The Configuration Prescaler register is used to enable the
PWM clock prescaler per output. When the corresponding
PR bit is set to logic [1], the clock prescaler (reference clock
divided by 2) is activated for the dedicated output.
Bits D9 and D8 control the switching phases as shown in
Table 10.
Table 10. Switching Phases
The SR Prescaler register is used to increase the output
slew rate by a factor of 2. When the corresponding SR bit is
set to logic [1], the output switching time is divided by 2 for the
dedicated output.
D9:D8
00
PWM Phase
0°
01
90°
10
180°
270°
11
06XS3517
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Bit D7 at logic [1] turns ON OUT1. OUT1 is turned OFF
with bit D7 at logic [0]. This register allows the master to
control the duty cycle and the switching phases of OUT1. The
duty cycle resolution is given by bits D6:D0.
new message data is clocked into the SI pin. The first 16 bits
of data clocking out of the SO, and following a CSB transition,
is dependant upon the previously written SPI word (SOA1
and SOA0 defined in the last SPI initialization word).
D7 = 0, D6:D0 = XX output OFF.
Any bits clocked out of the SO pin after the first 16 will be
representative of the initial message bits clocked into the SI
pin since the CSB pin first transitioned to a logic [0]. This
feature is useful for daisy chaining devices.
D7 = 1, D6:D0 = 00 output ON during 1/128.
D7 = 1, D6:D0 = 1A output ON during 27/128 on PWM
period.
A valid message length is determined following a CSB
transition of logic [0] to logic [1]. If the message length is
valid, the data is latched into the appropriate registers. A valid
message length is a multiple of 16 bits. At this time, the SO
pin is tri-stated and the fault status register is now able to
accept new fault status information.
D7 = 1, D6:D0 = 7F output continuous ON (no PWM).
ADDRESS 01010—CONTROL OUT2
Same description as OUT1.
ADDRESS 01011—CONTROL OUT3
The output status register correctly reflects the status of
the Initialization-selected register data at the time that the
CSB is pulled to a logic [0] during SPI communication and/or
for the period of time since the last valid SPI communication,
with the following exceptions:
Same description as OUT1.
ADDRESS 01100—CONTROL OUT4
Same description as OUT1.
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V, resulting in an under-
voltage shutdown of the outputs, may result in incorrect
data loaded into the status register.
ADDRESS 01101—CONTROL OUT5
Same description as OUT1.
ADDRESS 01110—CONTROL EXTERNAL SWITCH
Same description as OUT1.
SERIAL OUTPUT BIT ASSIGNMENT
ADDRESS 01111 —TEST MODE
The contents of bits OD15:OD0 depend on bits D1:D0
from the most recent initialization command SOA[1:0] (refer
to Table 8), and as explained in the paragraphs that follow.
This register is reserved for test and is not available with
SPI during normal operation.
The register bits are reset by a read operation and also if
the fault is removed.
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN
DATA)
Table 11 summarizes the SO register content. Bit OD10
reflects Normal mode (NM).
When the CSB pin is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB first as the
Table 11. Serial Output Bit Map Description
Previous
SO Data
SI Data
Status/
Mode
SO SO OD1 OD1
OD1
0
OD13 OD12 OD11
OD9 OD8 OD7 OD6 OD5 OD4 OD3
OD2
OD1 OD0
A1 A0
5
4
Fault
Status
0
0
1
1
X
0
1
0
1
X
0
0
UVF OTW OTS NM
OL5 OVL5 OL4 OVL4 OL3 OVL OL2
3
OVL2
OL1 OVL1
Overloa
d Status
0
1
1
0
1
0
1
0
UVF OTW OTS NM OC5 OTS5 OC4 OTS4 OC3 OTS OC2
3
OTS2 OC1 OTS1
Device
Status
UVF OTW OTS
NM
0
0
1
OV
X
0
0
X
0
0
X
0
0
RC
FOG FLASHE IGN CLOCK
pin R pin pin fail
Output
Status
UVF OTW OTS NM
0
OUT OUT4
5
OUT3 OUT OUT1
2
Reset
0
0
0
0
0
0
0
0
0
0
X = Don’t care
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
PREVIOUS ADDRESS SOA[1:0]=00
If the previous two LSBs are 00, bits OD15:OD0 reflect the
fault status (Table 11).
Table 12. Fault Status
OD15 OD14 OD13 OD12 OD11 OD10
UVF OTW OTS NM
OD13 (UVF) = Under-voltage Flag on VBAT
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
0
OL5
OVL5
OL4
OVL4
OL3
OVL3
OL2
OVL2
OL1
OVL1
OD9, OD7, OD5, OD3, OD1 (OL5, OL4, OL3, OL2, OL1) = Open Load
Flag at Outputs 5 through 1, respectively.
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD8, OD6, OD4, OD2, OD0 (OVL5, OVL4, OVL3, OVL2, OVL1) =
Overload Flag for Outputs 5 through 1, respectively.This corresponds
to OCHI or OCLO faults.
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OVL=OCHI1+OCHI2+OCLO
PREVIOUS ADDRESS SOA[1:0]=01
If the previous two LSBs are 01, bits OD15:OD0 reflect the temperature status (Table 13).
Table 13. Overload Status
OD15 OD14 OD13 OD12 OD11 OD10
UVF OTW OTS NM
OD13 (UVF) = Under-voltage Flag on VBAT
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
0
1
OC5
OTS5
OC4
OTS4
OC3
OTS3
OC2
OTS2
OC1
OTS1
OD9, OD7, OD5, OD3, OD1 (OC5, OC4, OC3, OC2, OC1) = High
Over-current Shutdown Flag for Outputs 5 through 1, respectively
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD8, OD6, OD4, OD2, OD0 (OTS5, OTS4, OTS3, OTS2, OTS1) =
Over-temperature Flag for Outputs 5 through 1, respectively
Note
A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0].
OC=OCHI1+OCHI2
PREVIOUS ADDRESS SOA[1:0]=10
If the previous two LSBs are 10, bits OD15:OD0 reflect the status of the 06XS3517 (Table 14).
Table 14. Device Status
OD15 OD14 OD13 OD12 OD11 OD10
UVF OTW OTS NM
OD9
OD8
OD7
OD6
OD5
OD4
OD3
FOG FLASHER IGN pin CLOCK
pin pin fail
OD2
OD1
OD0
1
0
0
0V
X
X
X
RC
OD13 (UVF) = Under-voltage Flag on VBAT
OD4 (RC) = Logic [0] indicates a Front Penta Device. Logic [1] indicates
a Rear Penta Device
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
OD3 (FOG pin) = indicates the FOG pin state
OD2 (FLASHER pin) = Indicates the FLASHER pin state in real time
OD1 (IGN pin) = Indicates the IGN pin state in real time
OD8 (Overvoltage) = Over-voltage Flag on VBAT in real time
OD0 (CLOCK fail) = Logic [1], which indicates a clock failure. The
content of this bit is reset by read operation.
06XS3517
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
PREVIOUS ADDRESS SOA[1:0]=11
If the previous two LSBs are 11, bits OD15:OD0 reflect the
status of the 06XS3517 (Table 14).
Table 15. Output Status
OD15 OD14 OD13 OD12 OD11 OD10
UVF OTW OTS NM
OD13 (UVF) = Under-voltage Flag on VBAT
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
1
0
0
0
0
0
0
OUT5 OUT4
OUT3
OUT2 OUT1
OD3 (OUT4) = Logic [0] indicates the OUT4 voltage is lower than
OUT_TH. Logic [1] indicates the OUT4 voltage is higher than VOUT_TH
OD2 (OUT3) = Logic [0] indicates the OUT3 voltage is lower than
OUT_TH. Logic [1] indicates the OUT3 voltage is higher than VOUT_TH
OD1 (OUT2) = Logic [0] indicates the OUT2 voltage is lower than
OUT_TH. Logic [1] indicates the OUT2 voltage is higher than VOUT_TH
OD0 (OUT1) = Logic [0] indicates the OUT5 voltage is lower than
OUT_TH. Logic [1] indicates the OUT1 voltage is higher than VOUT_TH
V
OD12 (OTW) = Over-temperature Prewarning Flag
OD11 (OTS) = Over-temperature Flag for all outputs
OD10 (NM) = Normal mode
V
OD4 (OUT5) = Logic [0] indicates the OUT5 voltage is lower than
OUT_TH. Logic [1] indicates the OUT5 voltage is higher than
VOUT_TH
V
V
V
PROTECTION AND DIAGNOSIS FEATURES
OUTPUT PROTECTION FEATURES
Output current
The 06XS3517 provides the following protection features:
• Protection against transients on VBAT supply line (per
ISO 7637)
OCHI1
• Active clamp, including protection against negative
transients on output line
• Over-temperature
• Severe and resistive over-current
• Open Load during ON state
OCHI2
OCLO
These protections are provided for each output (OUT1:5).
Over-temperature Detection
t1
The 06XS3517 provides over-temperature shutdown for
each output (OUT1:OUT5). It can occur when the output pin
is in the ON or OFF state. An over-temperature fault condition
results in turning OFF the corresponding output. The fault is
latched and reported via SPI. To delatch the fault and be able
to turn ON again the outputs, the failure condition must be
removed (T< 175 °C, typically) and:
time
t2
Figure 12. Two-segment Over-current Window in
Normal Mode
OCHI (IOCHI1 and then IOCHI2) is only activated after
toggling D7 bit of the corresponding Control Out registers in
Normal Mode. During switch-on, a severe short-circuit
condition at the output is reported as an OCHI fault. In Fail
Mode, the control of OCHI window is provided by the toggles:
IGN_ON, Flasher_ON, and FOG_ON. The current thresholds
(IOCHI1, IOCHI2 and IOCLO) and the time (t1 and t2) are fixed
numbers for each channel. After t2, the OCLO current
threshold is activated to protect in steady state. t1 and t2 times
are compared to “on” state duration (tON) of the output. In
case of the output is controlled in PWM mode during the
inrush period, the tON corresponds to the sum of each “on”
state duration in order to only account for times the channel
was actually in the ON state.
• if the device was in Normal mode, the output
corresponding register (bit D7) must be rewritten.
Application of complete OCHI window (OCHI1+OCHI2
during t2) depends on toggling or not toggling the D7 bit.
• if the device was in Fail mode, the corresponding output is
locked until restart of the device: wake-up from Sleep
mode or VBATPOR1
.
The corresponding SPI fault report (OTS bit) is removed
after a read operation.
Over-current Detections
The 06XS3517 provides a dynamic over-current shutdown
protection (see Figure 12) in order to protect the internal
power transistors and the harness in the event of overload
(fuse characteristic).
OUT2 is default loaded with the Xenon profile. The use of
H7 bulbs at this output requires SPI programming (Xenon
bit).
In case of overload (OCHI1 or OCHI2 or OCLO detection),
the corresponding output is disabled immediately. The fault is
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
latched and the status is reported via SPI. To delatch the
fault, the failure condition must be removed and:
feature resets OCHI2 or OCLO fault after corresponding
Autorestart period.
For OCHI1:
The SPI fault reports are removed together after a read
operation:
• if the device was in Normal mode: the channel’s
associated on/off bit (bit D7) must be rewritten D7=1.
Application of complete OCHI window depends on
toggling or not toggling D7 bit.
- OC bit=(OCHI1) or (OCHI2) fault
- OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault
• if the device was in Fail mode, the failure is locked until
restart of the device: wake-up from Sleep mode or
Over-voltage detection and active clamp
The 06XS3517 possesses an active gate clamp circuit in
order to limit the maximum drain to source voltage.
V
.
BATPOR1
For OCHI2 and OCLO:
In case of overload on an output the corresponding switch
(OUT[1 to 5]) is turned off which leads to high-voltage at
VBAT with an inductive VBAT line. The maximum VBAT
voltage is limited at VBATCLAMP by automatically turning on
the channel. In case of open load condition, the positive
transient pulses (ISO 7637 pulse 2 and inductive battery line)
shall also be handled by the application.
• if the device was in Normal mode: channel’s associated
on/off bit (bit D7) must be rewritten D7=1. Application of
complete OCHI window depends on toggling or not
toggling D7 bit.
• if the device was in Fail mode, Autorestart is activated. The
device Autorestart feature opens a fixed window width and
restarts at a fixed period with OCHI1 window. Autorestart
Figures 13 and 14 describe the faults management in
Normal mode and Fail mode.
Note: t1 and t2 refer to Figure 12.
(OCHI2=1) or (OT=1) or (UV=1) or (D7=0)
(OCHI1=1) or (OT=1) or (UV=1) or (D7=0)
t1<tON<t2 and (NO_OCHI=0) without fault
D7=0 then 1 without fault
and (NO_OCHI=0)
tON=t1 without fault
tON=t2 without fault
OCHI2
OFF
(rewrite D7=1) and (tON<t1)
without fault and
(NO_OCHI=0)
(NO_OCHI=1) without fault
OCHI1
(NO_OCHI=1) without fault
OCLO
tON<t1 and (NO_OCHI=0) without fault
t
ON>t1 without fault and (rewrite D7=1) and (NO_OCHI=0)
(tON>t2) and (rewrite D7=1) without fault
D7=0 then 1 without fault and (NO_OCHI=1)
(OCLO=1) or (OT=1) or (UV=1) or (D7=0)
Figure 13. Faults Management in Normal Mode (for OUT[1:5] Only)
06XS3517
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
(OT=1) or
(OCHI1=1)
(external_ON=0)
OFF-latched State
(OT=1)
(external_ON=0)
(external_ON=1)
(OT=1)
(t>tOCHI2) and (autorestart=0)
(t>tOCHI1) and (autorestart=0)
OFF
out: OFF
autorestart=0
OCHI2
out: external
OCHI1
out: external
OCLO
out: external
(UV=1) and
(external_on=1)
(t>tOCHI1_AUTO) and (autorestart=1)
(t>tAUTORESTART
and (UV*=0)
)
(UV=1)
(UV=1) or (OCHI2=1)
(OCLO=1) or
(UV=1)
OFF Autorestart
out: OFF
autorestart=1
(external_ON=0)
(external_ON=0)
1.4 sec min
external
external_ON
external: IGN, FLASHER, FOG
external_ON: IGN_ON, Flasher_ON, FOG_ON
Note: * See Autorestart strategy chapter.
Figure 14. Faults Management in Fail Mode (for OUT[1:5] Only)
external resistor. The CSNS resistance value is defined in
function to VCC voltage value. It is recommended to use
resistor 500 < RCSNS < 5.0 k. Typical value is 1.0 k for
5.0 V application. The channel the current of which is sensed
is addressed through bits MUX[4,2] bits of the Initialization
register.
DIAGNOSTIC Functions
Open Load
The 06XS3517 provides open load detection for each
output (OUT1:OUT5) when the output pin is in the ON state.
Open load detection levels can be chosen by SPI to detect a
standard bulb, a Xenon bulb for OUT2 only, or LEDs (OLLED
bit). Open load for LEDs only is detected during each regular
switch-off state or periodically each tOLLED (fully-on,
D[6:0]=7F). To detect OLLED in fully on state, the output must
be on at least tOLLED. When an open load has been detected,
the output stays ON.
The current recopy feature for OUT1:5 is disabled during
a high over-current shutdown phase (t2) and is only enabled
during low over-current shutdown thresholds. The current
recopy output delivers current only during ON time of the
output switch without overshoot (aperiodic settling).
The current recopy is not active in Fail mode.
To delatch the fault bit, the condition should be removed
and the SPI read operation is needed (OL bit). In case of a
Power on Reset on VBAT, the fault will be reset.
With a calibration strategy, the output current sensing
precision can be improved significantly. One calibration point
at 25 °C for 50% of FSR allows removing part to part
contribution. So, the calibrated part precision goes down to
6.0% over [20% - 75%] output current FSR, over-voltage
range (10 V to 16 V) and temperature range (-40 to 125 °C).
Current Sense
The 06XS3517 diagnosis for load current (OUT1:6) is
done using the current sense (CSNS) pin connected to an
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
Board Temperature Feedback
TEMPERATURE PREWARNING
The 06XS3517 provides a temperature prewarning
reported via the SPI (OTW bit) in Normal mode. The
information is latched. To delatch, a read SPI command is
needed. In case of a Power on Reset, the fault will be reset.
The 06XS3517 provides a voltage proportional to the
temperature on the GND flag, often representative for the
temperature of the underlaying PCB land. This voltage is
available at the CSNS output pin when the associated
UX[2,0] bits are set to “111”. Figure 15 shows the output
voltage over temperature.
EXTERNAL PIN STATUS
.
The 06XS3517 provides the status of the FLASHER, FOG,
and IGN pins via the SPI in real time and in Normal mode.
typ
2.5
min
FAILURE HANDLING STRATEGY
max
A highly sophisticated fault handling strategy allows
guaranteeing the various lighting functions even in case of
failures inside the component or the light module.
Components are protected against:
2
1.5
1
•
•
•
Reverse Polarity
Loss of Supply Lines
Fatal Mistreatment of Logic I/O Pins
0.5
0
REVERSE POLARITY PROTECTION ON VBAT
-40
-20
0
20
40
60
80
100
120
140
160
180
Board temperature (°C)
In case of a permanently reverse voltage operation, the
channels are turned ON (RSD Ohm) in order to prevent
thermal overloads. No protections are available.
Figure 15. Temperature sensing voltage
The board temperature feedback is not active in Fail
mode.
An external diode on VCC is necessary in order to protect
the 06XS3517 in cases from reverse polarity.
In case of negative transients on the VBAT line (per
ISO 7637), the VCC supplied functions are still available
operating, while the VBAT line is negative. Without loads on
OUT1:5 pin, an external clamp between VBAT and GND is
mandatory to avoid exceeding maximum ratings. The
maximum external clamp voltage shall be between the
reverse battery condition and -20 V.
With a calibration strategy, the temperature monitoring
precision can be improved. So, one calibration point at 25 °C
allows removing part to part contribution, as presented in
Figure 16.
typ
2.5
Therefore, the device is protected against latch-up with or
without load on OUT outputs.
min
max
2
1.5
1
LOSS OF SUPPLY LINES
The 06XS3517 is protected against the loss of any supply
line. The detection of the supply line failure is provided inside
the device itself.
0.5
0
LOSS OF VBAT
During an under-voltage of VBAT (VBATPOR1
<
-40
-20
0
20
40
60
80
100
120
140
160
180
VBAT < VBATUV), the outputs [1-5] are switched off
immediately. No current path from VBAT to VCC exists. The
external MOSFET (OUT6) can be controlled in Normal mode
by the SPI if VCC is above VCCUV. The fault is reported to the
UVF bit (OD13). To delatch the fault, the under-voltage
condition should be removed and:
Board temperature (°C)
Figure 16. Analog Temperature Precision with
Calibration Strategy
Output Voltage Status
• To turn-on the output, the corresponding D7 bit must be
rewritten to logic [1] in Normal mode. Application of the
OCHI window depends on toggling or not toggling the
D7 bit.
• If the device was in Fail mode, the fault will be delatched
by the Autorestart feature periodically.
The 06XS3517 provides the state of OUT1:OUT5 outputs
in real time through SPI. The OUT bit is set to logic [1] when
the corresponding output voltage is higher or equal then half
of the supply voltage. This bit allows synchronizing current
sense and diagnosing short-circuit between OUT and VBAT
terminals.
06XS3517
Analog Integrated Circuit Device Data
32
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
In case of VBAT < VBATPOR1 (Power OFF mode), the
behavior depends on VCC
• all latched faults are reset if VCC < VCCUV
LOSS OF GROUND (GND)
:
During loss of ground, the 06XS3517 cannot drive the
loads (the outputs (1:5) are switched OFF), but is not
destroyed by the operating condition. Current limit resistors in
the digital input lines protect the digital supply against
excessive current (1.0 kOhm typical). The state of the
external smart power switch controlled by FETOUT is not
guaranteed, and the state of external smart MOS is defined
with an external termination resistor.
,
• all latched faults are maintained under VCC in nominal
conditions. In case VBAT is disconnected, OUT[1:5]
outputs are OFF. OUT6 output state depends on the
previous SPI configuration. The SPI configuration,
reporting, and daisy-chain features are provided for
RST is set to logic [1]. The SPI pull-up and pull-down
current resistors are available. This fault condition can
be diagnosed with UVF fault in OD13 reporting bit. The
previous device configuration is maintained. No current
FATAL MISTREATMENT OF LOGIC I/O PINS
The digital I/Os are protected against fatal mistreatment
by signal plausibility check according to Table 16.
is conducted from VCC to VBAT
.
LOSS OF V (DIGITAL LOGIC SUPPLY LINE)
Table 16. Logic I/O Plausibility Check
CC
During loss of VCC (VCC < VCCUV) and with wake=1, the
06XS3517 is switched automatically into Fail mode. The
external SMART MOSFET is turned OFF. All SPI registers
are reset and must be reprogrammed when VCC goes above
Input/Output
LIMP
Signal Check Strategy
Debounce for 10 ms
(PWM) CLOCK
SPI (MOSI, SCLK, CS)
Frequency range (bandpass filter)
WD, D10 bit internal toggle
V
CCUV. The device will transit in OFF mode if VBAT
<
VBATPOR2
.
In case the LIMP input is set to logic [1] for a delay longer
than 10 ms typical, the 06XS3517 is switched into Fail mode.
In case of a (PWM) Clock failure, no PWM feature is provided
and the bit D7 defines the outputs state. In case of SPI failure,
the 06XS3517 is switched into Fail mode (see Figure 17)
LOSS OF V AND VBAT
CC
If the external VBAT and VCC supplies are disconnected (or
not within specification: (VCC and VBAT) < VBATPOR1), all SPI
register contents are reset with default values corresponding
to all SPI bits are set to logic [0] and all latched faults are also
reset.
1
0
0
WD Bit D10
timeout
D10 is toggled after
the window watchdog
75 ms window watchdog
75 ms window watchdog
Fail Mode activation
Figure 17. Watchdog window
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 18 gives the architecture of a vehicle lighting
system, including fog lights, battery redundancy concept,
light substitution mode, and Fail mode.
MOSI, MISO, SCLK
CP
CP
CS
CLOCK
CS
100nF
100nF
06XS3517
06XS3517
CLOCK
VBAT
VCC
RST
IGN
RST
VBAT
VCC
CornerLight
Switch
(Front Left)
CornerLight
Switch
(Front Right)
IGN
LIMP
LIMP
FLASHER
FLASHER
FOG
FOG
CSNS
CSNS
100nF
100nF
VBAT
VCC
CP
CP
CS
CS
35XS3500
35XS3500
CLOCK
CLOCK
VBAT
VCC
RST
IGN
RST
IGN
CornerLight
Switch
(Rear Right)
CornerLight
Switch
(Rear Left)
LIMP
LIMP
FLASHER
FLASHER
STOP
CSNS
STOP
CSNS
Microcontroller
Watchdog
VCC
WD
(5.0V)
(5.0V)
Flasher
VBAT
Ignition
Stop Light
VBAT
Figure 18. 06XS3517 Typical Application
EMC PERFORMANCES
The 06XS3517 will be compliant to CISPR25 Class5 in the
Standby mode with 22 nF decoupling capacitor on OUT[1:5].
06XS3517
Analog Integrated Circuit Device Data
34
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
06XS3517
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
PACKAGING
PACKAGING DIMENSIONS
FK SUFFIX
24-PIN PQFN
98ART10511D
ISSUE 0
06XS3517
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
PACKAGING
PACKAGING DIMENSIONS
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
REVISION HISTORY
REVISION HISTORY
REVISION
1.0
DATE
2/2012
2/2012
DESCRIPTION OF CHANGES
•
Initial release
•
•
Corrected ordering information from MC06XS3517FK to MC06XS3517AFK
Updated 98A package drawing
2.0
06XS3517
Analog Integrated Circuit Device Data
Freescale Semiconductor
40
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MC06XS3517
Rev. 2.0
2/2012
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