概述
数据手册ICS8512061I 概述
SINGLE CHANNEL 0.7V DIFFERENTIALTO-LVTTL TRANSCEIVER 单通道0.7V DIFFERENTIALTO ， LVTTL收发器
ICS8512061I 数据手册
通过下载ICS8512061I数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载SINGLE CHANNEL 0.7V DIFFERENTIAL-
TO-LVTTL TRANSCEIVER
ICS8512061I
General Description
Features
The ICS8512061I is a transceiver which can
interchange data across multipoint data bus
structures.
• One HCSL output pair and one LVCMOS/LVTTL output
• One single-ended LVCMOS/LVTTL signal input
• LVTTL I/O signal: up to 250MHz
S
IC
HiPerClockS™
The device has an LVTTL driver and one HCSL
receiver driver. It translates between LVTTL signals
and HCSL signals.
• HCSL interface pins in high impedance state when the device is
powered down
• Power-up and power-down glitch-free
• Additive Phase Jitter, RMS: 0.23ps (typical)
• Full 3.3V operating supply
Applications
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Backplane Transmission
Telecommunication System
Data Communications
ATCA Clock Distribution
Block Diagram
Pin Assignment
GND
QB
QA
1
2
3
4
8
7
6
5
nQA
VDD
IREF
DIR_SEL
IN
ICS8512061I
8 Lead TSSOP
QB
4.40mm x 3.0mm x 0.925mm package body
G Package
IREF
HCSL
Interface
Top View
QA
Pullup
IN
nQA
Pulldown
DIR_SEL
IDT™ / ICS™ TRANSCEIVER
1
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
2
GND
Power
Output
Power supply ground.
Single-ended output. LVCMOS/LVTTL interface levels.
QB
HCSL receiver and driver direction select pin. When HIGH, selects the
3
DIR_SEL
Input
Pulldown IN-to-QA/nQA path. When LOW, selects the QA/nQA-to-QB path.
LVCMOS/LVTTL interface levels.
4
5
IN
Input
Input
Pullup
Single-ended signal input. LVCMOS/LVTTL interface levels.
An external fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode QA/nQA outputs.
IREF
6
VDD
Power
Output
Power supply pin.
7, 8
Differential transceiver pair. HCSL interface levels.
nQA, QA
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Power Dissipation
Input Pullup Resistor
4
CPD
VDD = 3.6V
8
pF
RPULLUP
51
51
20
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance QB
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
129.5°C/W (0 mps)
-65°C to 150°C
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V 0.3V, TA = -40°C to 85°C
Symbol Parameter
VDD Core Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
V
3.0
3.3
3.6
20
mA
IDT™ / ICS™ TRANSCEIVER
2
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
2
VDD + 0.3
Input Low Voltage
-0.3
0.8
5
V
IN
VDD = VIN = 3.6V
µA
µA
µA
µA
IIH
Input High Current
DIR_SEL
IN
VDD = VIN = 3.6V
150
V
DD = 3.6V, VIN = 0V
-150
-5
IIL
Input Low Current
DIR_SEL
VDD = 3.6V, VIN = 0V
VDD = 3.6V
Output High Voltage;
NOTE 1
VOH
VOL
QB
QB
2.6
V
V
Output Low Voltage;
NOTE 1
VDD = 3.6V
0.5
NOTE: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section, Output Load Test Circuit diagram.
Table 3C. Differential DC Characteristics, VDD = 3.3V 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
DIR_SEL = 0
DIR_SEL = 0
Minimum
0.15
Typical
Maximum
1.3
Units
VPP
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
V
V
VCMR
GND + 0.5
VDD – 0.85
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
AC Electrical Characteristics
Table 4A. LVTTL (QB) Output Mode, Receiver AC Characteristics, VDD = 3.3V 0.3V, TA = -40°C to 85°C
Symbol Parameter
FMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
250
Units
MHz
ns
Propagation Delay, NOTE 1
QA/nQA to QB
1.7
2.5
100MHz, Integration Range: 12kHz
– 20MHz
tjit
Buffer Additive Phase Jitter, RMS
0.23
ps
tR/tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% - 80%
200
40
700
60
ps
%
NOTE 1: Measured from VDD/2 input cross point to the output at VDD/2.
IDT™ / ICS™ TRANSCEIVER
3
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Table 4B. HCSL (QA/nQA) AC Characteristics, VDD = 3.3V 0.3V, TA = -40°C to 85°C
Parameter
Symbol
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
250
MHz
100MHz, Integration Range:
12kHz – 20MHz
tjit
Buffer Additive Phase Jitter, RMS
Propagation Delay, NOTE 1
Rising Edge Rate; NOTE 2, 3
0.29
ps
tPD
IN to QA/nQA
1.1
0.6
1.7
4.0
ns
Rise
Edge Rate
V/ns
Fall
Edge Rate
Falling Edge Rate; NOTE 2, 3
Ringback Voltage; NOTE 2, 4
0.6
4.0
100
V/ns
V
Vrb
-100
Absolute Max Output Voltage;
NOTE 5, 6
VMAX
1150
mV
Absolute Min Output Voltage;
NOTE 5, 7
VMIN
-300
250
mV
mV
Absolute Crossing Voltage;
NOTE 5, 8, 9
VCROSS
550
Total Variation of VCROSS over all
edges; NOTE 5, 8, 10
∆VCROSS
140
55
mV
%
odc
Output Duty Cycle; NOTE 11
45
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from VDD/2 input cross point to the differential output crossing point.
NOTE 2: Measurement taken from differential waveform.
NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from QA minus nQA). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero
crossing.
NOTE 4: TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it
is allowed to drop back into the VRB 100 differential range. See Parameter Measurement Information Section.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of QA equals the Falling edge of nQA.
See Parameter Measurement Information Section
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all
crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the total variation of all crossing voltage of Rising QA and Falling nQA. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 11: Input duty cycle must be 50%.
IDT™ / ICS™ TRANSCEIVER
4
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Additive Phase Jitter (HCSL)
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.29ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™ TRANSCEIVER
5
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Additive Phase Jitter (LVCMOS)
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.23ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™ TRANSCEIVER
6
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Parameter Measurement Information
3.3V 0.3V
1.65V 0.15V
50Ω
50Ω
V
33Ω
33Ω
DD
Qx
SCOPE
V
DD
49.9Ω
49.9Ω
2pF
nQx
HCSL
Qx
IREF
LVCMOS
GND
GND
0V
2pF
475Ω
-1.65V 0.15V
3.3V HCSL Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
nQA
QA
VDD
2
IN
VDD
nQA
2
t
QB
PD
QA
tPD
Differential Propagation Delay
LVCMOS Propagation Delay
T
STABLE
V
RB
Rise Edge Rate
Fall Edge Rate
+150mV
RB = +100mV
V
+150mV
0.0V
0.0V
RB = -100mV
-150mV
V
-150mV
Q - nQ
Q - nQ
V
RB
T
STABLE
Differential Measurement Points for Rise/Fall Time
Differential Measurement Points for Ringback
IDT™ / ICS™ TRANSCEIVER
7
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Parameter Measurement Information, continued
Clock Period (Differential)
nQ
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
VCROSS_DELTA = 140mV
0.0V
Q
Q/nQ
Single-ended Measurement Points for Delta Cross Point
Differential Measurement Points for Duty Cycle/Period
VMAX = 1.15V
nQ
VCROSS_MAX = 550mV
V
CROSS_MIN = 250mV
Q
V
MIN = -0.30V
Single-ended Measurement Points for Absolute Cross
Point/Swing
IDT™ / ICS™ TRANSCEIVER
8
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
Differential Outputs
All control pins has internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOSOutput
All unused LVCMOS output can be left floating. There should be no
trace attached.
IDT™ / ICS™ TRANSCEIVER
9
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Recommended Termination
Figure 1A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
Figure 1A. Recommended Termination
Figure 1B is the recommended termination for applications which
require a point to point connection and contain the driver and
receiver on the same PCB. All traces should all be 50Ω impedance.
Figure 1B. Recommended Termination
IDT™ / ICS™ TRANSCEIVER
10
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Power Considerations (HCSL Outputs)
This section provides information on power dissipation and junction temperature for the ICS8512061I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8512061I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *20mA = 72mW
Power (outputs)MAX = 46.8mW/Loaded Output pair
Total Power_MAX = 72mW + 46.8mW = 118.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5°C/W per Table 5A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.119W * 129.5°C/W = 100.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 5A. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5
123.5
IDT™ / ICS™ TRANSCEIVER
11
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 2.
VDD
IOUT = 17mA
VOUT
RREF
=
475Ω 1%
RL
50Ω
IC
Figure 2. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power
dissipation, use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD MAX.
_
Power = (VDD_MAX – VOUT) * IOUT, since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.6V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 46.8mW
IDT™ / ICS™ TRANSCEIVER
12
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Power Considerations (LVCMOS Outputs)
This section provides information on power dissipation and junction temperature for the ICS8512061I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8512061I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *20mA = 72mW
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50Ω + ROUT)] = 3.6V / [2 * (50Ω + 20Ω)] = 25.7mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (25.7mA)2 = 13.2mW per output
Dynamic Power Dissipation at 250MHz
Power (250MHz) = CPD * Frequency * (VDD)2 = 8pF * 250MHz * (3.6V)2 = 25.9mW per output
Total Power
= Power (core)MAX + Power (ROUT) + Power (250MHz)
= 72mW + 13.2mW + 25.9mW
= 111.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5°C/W per Table 5B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.111W *129.5°C/W = 99.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 5B. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5
123.5
IDT™ / ICS™ TRANSCEIVER
13
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Reliability Information
Table 6. θJA vs. Air Flow Table for a 8 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5
123.5
Transistor Count
The transistor count for ICS8512061I is: 294
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP
Table 7. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
8
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.5
0.80
0.19
0.09
2.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ TRANSCEIVER
14
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Ordering Information
Table 8. Ordering Information
Part/Order Number
8512061AGILF
8512061AGILFT
Marking
61AIL
61AIL
Package
“Lead-Free” 8 Lead TSSOP
“Lead-Free” 8 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ TRANSCEIVER
15
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
B
T3C
3
Added Differential DC Characteristics Table.
11/19/08
IDT™ / ICS™ TRANSCEIVER
16
ICS8512061AGI REV. B NOVEMBER 19, 2008
ICS8512061I
SINGLE CHANNEL 0.7V DIFFERENTIAL-TO-LVTTL TRANSCEIVER
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
ICS8512061I 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ICS8516 | ICSI | LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP | 获取价格 |
|
| ICS8516EY | IDT | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 | 获取价格 |
|
| ICS8516EY-T | IDT | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 | 获取价格 |
|
| ICS8516EYLF | IDT | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 | 获取价格 |
|
| ICS8516EYLF-T | IDT | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 | 获取价格 |
|
| ICS8516FY | ICSI | LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP | 获取价格 |
|
| ICS8516FY-01 | IDT | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 | 获取价格 |
|
| ICS8516FY-01LFT | IDT | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 | 获取价格 |
|
| ICS8516FY-01T | IDT | Low Skew Clock Driver, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48 | 获取价格 |
|
| ICS8516FYI | ICSI | LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP | 获取价格 |
|
ICS8512061I 相关文章
探秘赋能未来互联世界的 Nordic 无线科技
- 2025-05-14
- 6
3000 亿芯片巨头海光信息：手握 “CPU+DCU” 挑战英伟达
- 2025-05-14
- 17
PCIE 全揭秘：芯片公司竞相追逐的关键技术
- 2025-05-13
- 35
四位数码管：12 个引脚的合理分配策略
- 2025-05-13
- 16
