1EDN8511B
更新时间：2024-12-03 14:08:56
品牌：INFINEON
描述：Buffer/Inverter Based MOSFET Driver, PDSO6, SOT-23, 6 PIN
概述
规格参数
数据手册1EDN8511B 概述
Buffer/Inverter Based MOSFET Driver, PDSO6, SOT-23, 6 PIN MOSFET 驱动器
1EDN8511B 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Active |
| 包装说明： | SOT-23, 6 PIN | Reach Compliance Code： | compliant |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| Factory Lead Time： | 1 week | 风险等级： | 5.75 |
| 高边驱动器： | NO | 接口集成电路类型： | BUFFER OR INVERTER BASED MOSFET DRIVER |
| JESD-30 代码： | R-PDSO-G6 | 长度： | 2.9 mm |
| 功能数量： | 1 | 端子数量： | 6 |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | LSSOP |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, LOW PROFILE, SHRINK PITCH |
| 峰值回流温度（摄氏度）： | NOT SPECIFIED | 座面最大高度： | 1.45 mm |
| 最大供电电压： | 20 V | 最小供电电压： | 4.5 V |
| 标称供电电压： | 12 V | 表面贴装： | YES |
| 端子形式： | GULL WING | 端子节距： | 0.95 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 断开时间： | 0.025 µs | 接通时间： | 0.025 µs |
| 宽度： | 1.6 mm | Base Number Matches： | 1 |
1EDN8511B 数据手册
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PDF下载EiceDRIVER™
1EDN751x/1EDN851x
Features
Fast, Precise, Strong and Compatible
•
•
•
5 ns slew rate to support high speed Superjunction MOSFET (like CoolMos™ C7) or GaN devices
19 ns propagation delay precision for fast MOSFET and GaN switching
8 A sink and 4 A source driver capability enables fast switching for very high efficiency applications and
powers low ohmic MOSFET
•
Industry standard packages and pinout ease system-design upgrades
The New Reference in Ruggedness
•
•
•
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET protection under abnormal
conditions
-10 V input voltage capability delivers robustness and crucial safety margin when device is driven from pulse-
transformers
5 A reverse current robustness eliminates the need for output protection circuitry
Applications
•
•
•
•
•
•
•
Server SMPS (Switch Mode Power Supplies)
TeleCom SMPS
DC-to-DC Converter
Bricks
Power Tools
Industrial SMPS
Motor Control
Example Topologies
•
•
•
Synchronous Rectification
Power Factor Correction PFC (DCM, CCM)
LLC, ZVS in combination with pulse transformer for isolation
Description
The 1EDN7x/1EDN8x is an advanced single-channel driver. It is suited to drive logic and normal level MOSFETs
and supports OptiMOSTM, CoolMOSTM, Standard Level MOSFETs, Superjunction MOSFETs, as well as IGBTs and
GaN Power devices.
Data Sheet
www.infineon.com/1EDN
Please read the Important Notice and Warnings at the end of this document
Rev. 2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Description
The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to +20 V.
-10 V input pin robustness protects the driver against latch-up or electrical overstress which can be induced by
parasitic ground inductances. This greatly enhances system stability.
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET and GaN protection under abnormal
conditions. Under such circumstances, this UVLO mechanism provides crucial independence from whether and
when other supervisors circuitries detect abnormal conditions.
The output is able to sink 8 A and source 4 A currents utilizing a true rail-to-rail stage. This ensures very low on-
resistance of 0.85 Ω up to the positive and 0.35 Ω down to the negative rail respectively. Industry-leading reverse
current robustness eliminates the need for Schottky diodes at the outputs and reduces the bill-of-material.
The pinout of the 1EDN family is compatible with the industry standard. Three package variants, SOT23 6-pin, 5-
pin and WSON 6-pin, allow optimization of PCB board space usage and thermal characteristics.
VDD
Load
1EDN751x/
1EDN851x
IN+
VDD
OUT_SRC
OUT_SNK
Rg1
M1
IN-
GND
Rg2
CVDD
Figure 1
Typical application
Data Sheet
2
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
1.1
1.2
Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Undervoltage Lockout Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
3
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Driver Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
4.3
4.4
4.5
5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
5.2
5.3
5.4
6
7
8
9
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data Sheet
3
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Product Versions
1
Product Versions
The 1EDN751x/1EDN851x is available in 2 different Undervoltage Lockout and 3 package versions.
Table 1
Product Versions
Package
Type. UVLO
Part Number
IC Topside
Marking Code
PG-SOT23-6-2
4.2 V
8 V
1EDN7511B
1EDN8511B
71
81
PG-SOT23-5-1
4.2 V
1EDN7512B
72
PG-WSON-6-1
4.2 V
1EDN7512G
1N7512
AG_XXX
HYYWW
1.1
Undervoltage Lockout Versions
The 2 Undervoltage Lockout versions are indicated by the variable x in the product version 1EDNz:
•
•
z=7: lower voltage for logic level MOSFETs (typ. 4.2 V)
z=8: higher voltage for standard and superjunction MOSFETs (typ. 8.0 V)
Please refer to the functional description section for more details in Chapter 4.5
Data Sheet
4
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Product Versions
1.2
Package Versions
Following versions regarding UVLO and output configuration are available.
•
•
•
a standard SOT-23; 6 pin (1EDN7511B and 1EDN8511B)
a standard SOT-23; 5 pin (1EDN7512B)
a leadless WSON-6; 6 pin (1EDN7512G)
Data Sheet
5
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Pin Configuration and Description
2
Pin Configuration and Description
The pin configuration for the PG-SOT23-6-2 package is shown in Figure 2. Pin description is given below in
Table 2. For functional details, please read Chapter 4.
1
2
3
VDD
IN+
IN-
6
5
4
OUT_SRC
OUT_SNK
GND
Figure 2
Pin Configuration PG-SOT23-6-2 (top side view)
Table 2
Symbol
IN+
Pin Configuration
Description
Non-inverting Input
Logic Input; if IN+ is low or left open causes OUT low
IN-
Inverting Input
Logic Input; if IN- is high or left open, causes OUT low
GND
VDD
Ground
Positive Supply Voltage
Operating range 4.5 V to 20 V
OUT_SNK
OUT_SRC
Driver Output Sink
Low-impedance output with sink capability
Driver Output Source
Low-impedance output with source capability
Note:
The pin configuration in the PG-SOT23-6-2 features separated source and sink outputs.
Data Sheet
6
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Pin Configuration and Description
The pin configuration for the PG-SOT23-5-1 package is shown in Figure 3. Pin description is given below in
Table 3. For functional details, please read Chapter 4.
1
2
3
VDD
GND
IN+
OUT
IN-
5
4
Figure 3
Pin Configuration PG-SOT23-5-1 (top side view)
Table 3
Symbol
IN+
Pin Configuration
Description
Non-inverting Input
Logic Input; if IN+ is low or left open causes OUT low
IN-
Inverting Input
Logic Input; if IN- is high or left open, causes OUT low
GND
VDD
Ground
Positive Supply Voltage
Operating range 4.5 V to 20 V
OUT
Driver Output
Low-impedance output and sink capability
Note:
Package PG-SOT23-5-1 features a shorted source sink output.
Data Sheet
7
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Pin Configuration and Description
The pin configuration for the PG-WSON-6-1 package is shown in Figure 4. Pin description is given below in
Table 4. For functional details, please read Chapter 4.
IN+
1
2
6
5
IN-
GND
GND
VDD
3
4
OUT
Figure 4
Pin Configuration PG-WSON-6-1 (top side view)
Table 4
Symbol
IN+
Pin Configuration
Description
Non-inverting Input
Logic Input; if IN+ is low or left open causes OUT low
IN-
Inverting Input
Logic Input; if IN- is high or left open, causes OUT low
GND
VDD
Ground
Positive Supply Voltage
Operating range 4.5 V to 20 V
OUT
Driver Output
Low-impedance output with source and sink capability
Note:
1. Package PG-WSON-6-1 has a combined source sink output.
2. Exposed pad of PG-WSON-6-1 package has to be connected to GND pin.
Data Sheet
8
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Block Diagram
3
Block Diagram
A simplified functional block diagram for the PG-SOT23-6-2 is given in Figure 5. This version has separated source
and sink outputs.
VCC
UVLO
active
filter
IN+
OUT_SRC
Logic
GND
VCC
active
filter
IN-
OUT_SNK
GND
Figure 5
Block Diagram 1EDN7511B and 1EDN8511B
A simplified functional block diagram for PG-WSON-6-1 is depicted in Figure 6. This version has one common
output.
VCC
UVLO
active
filter
IN+
Logic
GND
VCC
OUT
active
filter
IN-
GND
Figure 6
Block Diagram 1EDN7512B 1EDN7512G
Data Sheet
9
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Functional Description
4
Functional Description
4.1
Introduction
The 1EDN751x/1EDN851x is a fast single-channel driver for low-side switches. Rail-to-rail output stages with very
low output impedance and high current capability are chosen to ensure highest flexibility and cover a high variety
of applications.
The focus on robustness at the input and output side gives this device an additional safety margin in critical
abnormal situations. An extended negative voltage range protects input pins against ground shifts. No current
flows over the ESD structure in the IC during a negative input level. Output is robust against reverse current. The
interaction with the power MOSFET, even reverse reflected power will be handled by the strong internal output
stage.
Inputs are compatible with LV-TTL signal levels. The threshold voltages with a typical hysteresis of 1.1 V are kept
constant over the supply voltage range.
Since the 1EDN751x/1EDN851x aims particularly at fast-switching applications, signal delays and rise/fall times
have been minimized to support low switching losses in the MOSFET.
4.2
Supply Voltage
The maximum supply voltage is 20 V. This high voltage can be valuable in order to exploit the full current
capability of 1EDN751x/1EDN851x when driving very large MOSFETs. The minimum operating supply voltage is
set by the undervoltage lockout function to a typical default value of 4.2 V or of 8 V. This lockout function protects
power MOSFETs from running into linear mode with subsequent high power dissipation.
4.3
Driver Inputs
The non-inverting input is internally pulled down to a logic low voltage. The inverting input is internally pulled up
to a logic high voltage. This prevents a switch-on event during power-up and a not-driven input condition.
All inputs are compatible with LV-TTL levels and provide a hysteresis of typically 1.1 V. This hysteresis is
independent of the supply voltage.
All input pins have a negative extended voltage range. This prevents cross-current over signal wires during GND
shifts between signal source (controller) and driver input.
4.4
Driver Outputs
The rail-to-rail output stage realized with complementary MOS transistors is able to provide a typical 4 A of
sourcing and 8 A sinking current. This asymmetrical push-pull stage enables a perfect “brake before make” (turn
off ist faster than turn on) condition, which is needed in half-bridge power MOSFET stages.
This driver output stage has a shoot-through protection and current limiting behavior.
The output impedance is very low with a typical value below 0.85 Ω for the sourcing p-channel MOS and 0.35 Ω
for the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for achieving true
rail-to-rail behavior and avoiding a source follower’s voltage drop.
The gate drive output is held low actively in case of floating inputs or during startup or power down once UVLO is
not exceeded. Under any situation, startup, UVLO or shutdown, the output is held under defined conditions.
Data Sheet
10
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Functional Description
4.5
Undervoltage Lockout (UVLO)
The Undervoltage Lockout function ensures that the output can be switched to its high level only if the supply
voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the switch transistor is not switched
on if the driving voltage is too low to completely switch it on, thereby avoiding excessive power dissipation.
The UVLO level is set to a typical value of 4.2 V / 8 V (with hysteresis). UVLO of 4.2 V is normally used for logic level
based MOSFETs. For higher level, like standard and high voltage superjunction MOSFETS, an UVLO voltage of
typically 8 V is available.
Data Sheet
11
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Characteristics
5
Characteristics
The absolute maximum ratings are listed in Table 5. Stresses beyond these values may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
5.1
Absolute Maximum Ratings
Table 5
Absolute Maximum Ratings
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
-0.3
-10
Max.
22
Positive supply voltage
Voltage at pins IN+, IN-
VVDD
VIN
V
V
22
Voltage at pins OUT, OUT_SRC, VOUT
-0.3
VVDD+0.3
V
Note1)
OUT_SNK
Reverse current peak at pins
OUT, OUT_SRC/OUT_SNK
ISNK_rev
ISRC_rev
TJ
-5
5
Apk
< 500 ns
Junction temperature
Storage temperature
ESD capability
-40
-55
150
150
1.5
°C
°C
kV
TS
VESD
Charged Device Mode
(CDM) 2)
ESD capability
VESD
2.5
kV
Human Body Model
(HBM) 3)
1) Voltage spikes resulting from reverse current peaks are allowed.
2) According to JESD22-C101
3) According to JESD22-A114
5.2
Thermal Characteristics
Table 6
Thermal Characteristics
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
Max.
PG-SOT23-6-2, Tamb=25°C
Thermal resistance junction-
ambient 1)
RthJA25
RthJC25
RthJB25
ΨthJC25
ΨthJB25
170
81
K/W
K/W
K/W
K/W
K/W
Thermal resistance junction-
case (top) 2)
Thermal resistance junction-
board 3)
52
Characterization parameter
junction-case (top)4)
14
Characterization parameter
junction-board 5)
51
Data Sheet
12
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Characteristics
Table 6
Thermal Characteristics (continued)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
PG-SOT23-5-1, Tamb=25°C
Thermal resistance junction-
ambient 1)
RthJA25
RthJC25
RthJB25
RthJB25
ΨthJB25
ΨthJB25
180
76
60
16
14
52
K/W
K/W
K/W
K/W
K/W
K/W
Thermal resistance junction-
case (top) 2)
Thermal resistance junction-
board 3)
Thermal resistance junction-
bottom (heat sink)6)
Characterization parameter
junction-case (top) 4)
Characterization parameter
junction-board 5)
PG-WSON-6-1, Tamb=25°C
Thermal resistance junction-
ambient 1)
RthJA25
RthJP25
RthJB25
RthJB25
ΨthJC25
ΨthJB25
63
83
16
16
9
K/W
K/W
K/W
K/W
K/W
K/W
Thermal resistance junction-
case (top) 2)
Thermal resistance junction-
board 3)
Thermal resistance junction-
bottom (heat sink) 6)
Characterization parameter
junction-top 4)
Characterization parameter
15
junction-board 5)
1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,
high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to
control the PCB temperature, as described in JESD51-8.
4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
6) The junction-to-bottom thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No
specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Data Sheet
13
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Characteristics
5.3
Operating Range
Table 7
Operating Range
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
4.5
-5
Max.
20
Supply voltage
VVDD
VIN
TJ
V
Min defined by UVLO
Logic input voltage
20
V
1)
Junction temperature
-40
150
°C
1) Continuous operation above 125 °C may reduce life time.
5.4
Electrical Characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They are
valid within the full operating range. The supply voltage is VVDD= 12 V. Typical values are given at TJ=25°C.
Table 8
Power Supply
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
VDD quiescent current
VDD quiescent current
IVDDqu1
IVDDqu2
0.4
mA
mA
OUT = high, VVDD= 12 V
OUT = low, VVDD= 12 V
0.37
Table 9
Undervoltage Lockout for Logic Level MOSFET
Symbol Values
Parameter
Unit Note or Test Condition
Min.
Typ.
Max.
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
3.9
4.2
4.5
V
V
V
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
3.6
3.9
0.3
4.2
UVLO threshold hysteresis
UVLOhys
Table 10 Undervoltage Lockout for Standard and Superjunction MOSFET Version
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Undervoltage Lockout (UVLO) UVLOon
turn on threshold
7.4
8.0
7.0
1.0
8.6
V
V
V
Undervoltage Lockout (UVLO) UVLOoff
turn off threshold
6.5
—
7.5
—
UVLO threshold hysteresis
UVLOhys
Data Sheet
14
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Characteristics
Table 11 Logic Inputs IN+, IN-
Parameter
Symbol
VINH
VINL
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input voltage threshold for
transition LH
1.9
2.1
2.3
V
V
Input voltage threshold for
transition HL
0.8
1.0
1.2
Input pull up resistor1)
Input pull down resistor2)
RIN H
RIN L
400
100
kΩ
kΩ
1) Inputs with initial high logic level
2) Inputs with initial low logic level
Table 12 Static Output Caracteristics
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
Typ.
Max.
High Level (Sourcing) Output Ron_SRC
Resistance
0.42
0.85
1.46
Ω
A
ISRC = 50 mA
1)
High Level (Sourcing) Output ISRC_peak
4.0
Current
Low Level (Sinking) Output
Resistance
Ron_SNK
0.18
0.35
-8.0
0.64
Ω
A
ISNK = 50 mA
2)
Low Level (Sinking) Output
Current
ISNK_Peak
1) Active limited by design at approx. 5.2 Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
2) Active limited by design at approx. -10.4 Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
Table 13 Dynamic Characteristics (see Figure 7, Figure 8, Figure 9)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input to output propagation
delay
TPDON
15
19
25
ns
ns
CLOAD= 1.8 nF, VVDD= 12 V
CLOAD= 1.8 nF, VVDD= 12 V
Input to output propagation
delay
TPDOFF
15
19
25
Rise Time
Fall Time
TRISE
TFAll
TPW
—
—
—
6.5
4.5
6
111)
91)
ns
ns
ns
CLOAD= 1.8 nF, VVDD= 12 V
CLOAD= 1.8 nF, VVDD= 12 V
CLOAD= 1.8 nF, VVDD= 12 V
Minimum input pulse width
that changes output state
10
1) Parameter verified by design, not 100% tested in production.
Data Sheet
15
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Timing Diagrams
6
Timing Diagrams
Figure 7 shows the definition of rise, fall and delay times for the inputs. This is also valid for the inverted control.
VIN H
VIN L
IN-
Lo w Lo gic Level
VIN H
VIN L
IN+
90%
10%
90%
10%
TPDON
OUT
ENx
TRIS E
TFAL L
TPDOF F
Figure 7
Propagation Delay, Rise and Fall Time, Non-inverted
Figure 8 illustrates the undervoltage lockout function.
UVLOon
UVLOoff
VDD
OUT
Figure 8
UVLO Behaviour, Input INx Drives OUT Normally High.
Figure 9 illustrates the minimum input pulse width that changes output state.
( static low level)
IN-
VINH
VINL
IN+
TPW
90%
OUT
Figure 9
TPW, minimum input pulse width that changes output state.
Data Sheet
16
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Typical Characteristics
7
Typical Characteristics
UVLO ON/OFF
vs
TEMPERATURE
UVLO HYSTERESIS
vs
TEMPERATURE
0.6
0.4
0.2
0
4.5
4.3
4.1
3.9
3.7
on value
off value
IN+ high, IN- low
Indication Outx
IN+ high, IN- low
Indication Outx
-50
0
50
T junction [°C]
100
150
-50
0
50
100
150
T junction [°C]
Figure 10 Undervoltage Lockout 1EDN7x (4.2 V)
UVLO ON/OFF
vs
TEMPERATURE
UVLO HYSTERESIS
vs
TEMPERATURE
8.8
on value
1.1
0.9
0.7
0.5
off value
8.4
8
7.6
7.2
6.8
6.4
IN+ high, IN- low
Indication Outx
IN+ high, IN-
100 150
-50
0
50
100
150
-50
0
50
T junction [°C]
T junction [°C]
Figure 11 Undervoltage Lockout 1EDN8x (8 V)
Data Sheet
17
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Typical Characteristics
VINL / VINH to OUTx
INx HYSTERESIS
vs
vs
TEMPERATURE
TEMPERATURE
1.2
1.1
1
typ ON threshold
typ OFF threshold
2.7
2.3
1.9
1.5
1.1
0.7
VDD=12V
VDD=12V
100 150
0.9
-50
0
50
100
150
-50
0
50
T junction [°C]
T junction [°C]
Figure 12 Input (INx) Characteristic
VINx to OUT PROPAGATIONDELAY
VINx to OUT PROPAGATIONDELAY
vs
vs
TEMPERATURE
TEMPERATURE
25
22.5
20
25
22.5
20
typ turn-off
typ turn-on
typ turn-off
typ turn-on
17.5
15
17.5
15
VDD=12V
Input 5V
VDD=12V
Input 3.3V
-50
0
50
100
150
-50
0
50
100
150
T junction [°C]
T junction [°C]
Figure 13 Propagation Delay (INx) on Different Input Logic Levels (See Figure 7)
Data Sheet
18
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Typical Characteristics
OUTx RISE/FALLTIME 10%- 90%
vs
TEMPERATURE
8
7
6
5
4
3
typ turn-on
typ turn-off
VDD=12V
OUTx with 1.8nF load
-50
0
50
100
150
T junction [°C]
Figure 14 Rise / Fall Times with Load on Output
Data Sheet
19
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Typical Characteristics
CURRENT CONSUMPTION
CURRENT CONSUMPTION
vs
OPERATING SUPPLYVDD
vs
TEMPERATURE
0.45
0.43
0.41
0.39
0.37
0.35
0.6
0.5
0.4
0.3
0.2
0.1
OUT High
OUT Low
OUT High
OUT Low
VDD=12V
IN+ to 12V
IN- to GND
Tj=25°C
-50
0
50
T junction [°C]
100
150
0
10
VDD [V]
20
CURRENT CONSUMPTION
vs
FREQUENCY
50
40
30
20
10
0
Tamb 25°C
Input 50%@3.3V
Device self-heating
Load 1.8nF serial
VDD 4,5V
VDD 12V
VDD 20V
0
250
500
750
1000
Frequency [kHz]
Figure 15 Power Consumption Related to Temperature, Voltage Supply and Frequency
Data Sheet
20
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Typical Characteristics
REVERSECURRENT @OUT
with OUT HIGH
vs REVERSEVOLTAGE
REVERSECURRENT @OUTx
with OUT LOW
vs REVERSEVOLTAGE
8.0
6.5
5.0
3.5
2.0
0.5
-1.5
-3.0
-4.5
-6.0
-7.5
Test Conditions:
Tj = 25°C,
1µs positive Pulse
fsw = 1kHz
10 W
2.5 W
5 W
7.5 W
7.5 W
5 W
Test Conditions:
Tj = 25°C,
1µs negative Pulse
fsw = 1kHz
10 W
2.5 W
0.75
1.00
1.25
1.50
1.75
-1.75
-1.50
-1.25
VOUT [V]
-1.00
-0.75
VOUT [V]
Figure 16 Output OUTx with reverse current and resulting power dissipation
Data Sheet
21
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Outline Dimensions
8
Outline Dimensions
Figure 17 PG-SOT23-6-2 Outline Dimensions
Figure 18 PG-SOT23-6-2 Footprint Dimensions
Data Sheet
22
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Outline Dimensions
Figure 19 PG-SOT23-6-2 Packaging Dimensions
Figure 20 PG-SOT23-5-1 Outline Dimensions
Data Sheet
23
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Outline Dimensions
Figure 21 PG-SOT23-5-1 Footprint Dimensions
Figure 22 PG-SOT23-5-1 Packaging Dimensions
Data Sheet
24
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Outline Dimensions
Figure 23 PG-WSON-6-1 Outline Dimensions
Figure 24 PG-WSON-6-1 Footprint Dimensions
Data Sheet
25
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Outline Dimensions
Figure 25 PG-WSON-6-1 Packaging Dimensions
Notes
1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”:
http://www.infineon.com/cms/en/product/technology/packages/.
2. Pin description and orientation is located in Chapter 2.
Data Sheet
26
Rev.2.0
2016-10-28
EiceDRIVER™
1EDN751x/1EDN851x
Revision History
9
Revision History
Rev. 2.0, 2016-10-28
Page/ Item Subjects (major changes since previous revision)
updated from version 1.0
Responsible Date
15
15
16
23
Symbols correction Ron_SRC, Ron_SNK, ISRC_peak, ISNK_Peak : Table 12
Adding max. and min. values of Ron_SRC, Ron_SNK: Table 12
Insert pulse timing diagram: Figure 9
Restructured dimensional tolerances in drawing: Figure 20
Tobias Gerber 2016/10/28
Data Sheet
27
Rev.2.0
2016-10-28
Please read the Important Notice and Warnings at the end of this document
Trademarks of Infineon Technologies AG
µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
The information given in this document shall in no For further information on technology, delivery terms
Edition 2016-10-28
Published by
Infineon Technologies AG
81726 Munich, Germany
event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest
characteristics ("Beschaffenheitsgarantie").
Infineon Technologies Office (www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
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In addition, any information given in this document is
subject to customer's compliance with its obligations
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© 2016 Infineon Technologies AG.
All Rights Reserved.
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