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28F800C3

更新时间：2025-06-29 01:40:02
品牌：INTEL
描述：3 Volt Intel Advanced+ Boot Block Flash Memory

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28F800C3 概述

3 Volt Intel Advanced+ Boot Block Flash Memory 3伏特英特尔高级+引导块闪存 闪存

28F800C3 规格参数

生命周期：TransferredReach Compliance Code：unknown
ECCN代码：3A991.B.1.AHTS代码：8542.32.00.51
风险等级：5.73Is Samacsys：N
内存密度：134217728 bit内存集成电路类型：FLASH
内存宽度：8功能数量：1
字数：16777216 words字数代码：16000000
组织：16MX8编程电压：3 V
认证状态：Not Qualified最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
技术：CMOS类型：NOR TYPE
Base Number Matches：1

28F800C3 数据手册

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3 Volt Intel® Advanced+ Boot  
Block Flash Memory  
28F800C3, 28F160C3, 28F320C3, 28F640C3  
Specification Update  
November 2002  
Notice: The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors  
known as errata which may cause the product to deviate from published specifications. Current  
characterized errata are documented in this specification update.  
Order Number: 297938-014  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY  
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN  
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS  
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES  
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER  
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.  
Intel may make changes to specifications and product descriptions at any time, without notice.  
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for  
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.  
The 28F800C3, 28F160C3, 28F320C3, 28F640C3 may contain design defects or errors known as errata which may cause the product to deviate from  
published specifications. Current characterized errata are available on request.  
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.  
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-  
548-4725 or by visiting Intel's website at http://www.intel.com.  
Copyright © Intel Corporation, 2002.  
*Other names and brands may be claimed as the property of others.  
2
28F800C3, 28F160C3, 28F320C3, 28F640C3, 28F640C3 Specification Update  
Contents  
Revision History ......................................................................................... 5  
Preface....................................................................................................... 6  
Summary Table of Changes....................................................................... 7  
Identification Information............................................................................ 9  
Errata ....................................................................................................... 10  
Specification Changes ............................................................................. 15  
Specification Clarifications ....................................................................... 17  
Documentation Changes ......................................................................... 17  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
3
4
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
Revision History  
Date  
Version  
Description  
05/13/98  
-001  
Document includes all known specifications to date (original version).  
Changed Ordering Information for 32-Mbit densities to 95 ns and 115 ns available  
access speed only  
06/02/98  
-002  
Added µBGA* package mark clarification  
Added test condition clarification for I  
PPD  
07/08/98  
08/12/98  
09/09/98  
-003  
-004  
-005  
Added specification change for µBGA* package pinout  
Added Errata for Maximum I Change  
CCD  
Added Specification Change for Byte-Wide Protection Register Addressing  
Added CFI Primary-Vendor Specific Extended Query Change  
Added Block Locking Command Sequence Change  
VIH Maximum Specification Change  
Removed 48-Lead TSOP Package Pinout Change (fixed in 290645-002)  
Removed Protection Register Addressing Change (fixed in 290645-002)  
Removed CFI Query Structure Output Table Change (fixed in 290645-002)  
Removed Ordering Information Change (fixed in 290645-002)  
Removed µBGA* Package Pinout Change (fixed in 290645-002)  
Removed Protection Register Addressing Clarification (fixed in 290645-002)  
Removed µBGA* Package Mark Clarification (fixed in 290645-002)  
09/24/98  
-006  
Removed Byte-Wide Protection Register Addressing Change (fixed in 290645-  
003)  
Removed V Maximum Change (fixed in 290645-003)  
10/02/98  
-007  
IH  
Removed I  
Test Condition Clarification (fixed in 290645-003)  
PPD  
Name changed from 3 Volt Advanced+ Boot Block Flash Memory Family  
Added Specification Change #1, Maximum I Change  
CCD  
Added Specification Change #2, CFI Primary-Vendor Specific Extended Query  
Change  
05/04/99  
10/05/00  
-008  
-009  
Added Specification Change #3, Block Locking Command Sequence Change  
Added Specification Change #4, 32-Mb Maximum V Change  
CC  
Updated CFI feature identification bit definition  
Renamed Specification Change #4, 32-Mb Maximum V Change, to 0.25µm  
32-Mb Maximum V Change, and modified it to indicate that the affected product  
is the 32-Mbproduct on the 0.25µm process  
CC  
CC  
Revised Erratum #1, Maximum I  
when V =12 V  
PP  
CCE  
05/03/01  
07/23/01  
11/05/01  
3/05/02  
-010  
-011  
-012  
-013  
Added Erratum #2, 28F320C3xC Reset Failure  
Updated Erratum #2, 28F320C3xC Reset Failure, added 3.3v Vcc max  
Added Erratum #3, 28F640C3xC for Maximum I  
/ I  
Change  
CCD CCS  
Added Erratum #4, 28F160C3xC Erase Resume Issue  
Added Erratum #5, 28F160C3xC and 28F640C3xC Lock/Unlock/Lock-Down  
Operation  
11/21/02  
-014  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
5
Preface  
Preface  
This document is an update to the specifications contained in the Affected Documents/Related  
Documents table below. This document is a compilation of device and documentation errata,  
specification clarifications and changes. It is intended for hardware system manufacturers and  
software developers of applications, operating systems, or tools.  
Information types defined in Nomenclature are consolidated into the specification update and are  
no longer published in other documents.  
This document may also contain information that was not previously published.  
Affected Documents/Related Documents  
Title  
Order  
®
3 Volt Intel Advanced+ Boot Block Flash Memory, 28F800C3, 28F160C3, 28F320C3,  
28F640C3 (x16) Datasheet  
290645-014  
Nomenclature  
Errata are design defects or errors. These may cause the behavior of the 28F800C3, 28F160C3,  
28F320C3, 28F640C3 to deviate from published specifications. Hardware and software designed  
to be used with any given stepping must assume that all errata documented for that stepping are  
present on all devices.  
Specification Changes are modifications to the current published specifications. These changes  
will be incorporated in any new release of the specification.  
Specification Clarifications describe a specification in greater detail or further highlight a  
specification’s impact to a complex design situation. These clarifications will be incorporated in  
any new release of the specification.  
Documentation Changes include typos, errors, or omissions from the current published  
specifications. These will be incorporated in any new release of the specification.  
Note: Errata remain in the specification update throughout the product’s life cycle, or until a particular  
stepping is no longer commercially available. Under these circumstances, errata removed from the  
specification update are archived and available upon request. Specification changes, specification  
clarifications, and documentation changes are removed from the specification update when the  
appropriate changes are made to the appropriate product specification or user documentation  
(datasheets, manuals, etc.).  
6
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
Summary Table of Changes  
Summary Table of Changes  
The following table indicates the errata, specification changes, specification clarifications, or  
documentation changes which apply to the 28F800C3, 28F160C3, 28F320C3, 28F640C3 product.  
Intel may fix some of the errata in a future stepping of the component, and account for the other  
outstanding issues through documentation or specification changes as noted. This table uses the  
following notations:  
Codes Used in Summary Table  
Stepping  
X:  
This erratum exists in the stepping indicated. Specification Change or  
Clarification that applies to this stepping.  
(No mark) or (Blank box): This erratum is fixed in listed stepping, or specification change does not  
apply to listed stepping.  
Page  
(Page):  
Page location of item in this document.  
Status  
Doc:  
Document change or update will be implemented.  
This erratum may be fixed in a future stepping of the product.  
This erratum has been previously fixed.  
Plan Fix:  
Fixed:  
NoFix:  
There are no plans to fix this erratum.  
Row  
Change bar to left of table row indicates this erratum is either new or  
modified from the previous version of the document.  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Udpate  
7
Summary Table of Changes  
Errata  
Number  
Page  
Status  
Errata  
1
2
3
4
5
10  
10  
11  
12  
14  
Plan Fix  
Plan Fix  
Plan Fix  
Plan Fix  
Plan Fix  
“28F320C3xC Maximum ICCE when Vpp=12V”  
“28F320C3xC Reset Failure”  
“28F640C3xC Maximum ICCS and ICCD Change”  
“28F160C3xC Erase Resume Issue”  
“28F160C3xC and 28F640C3xC Lock/Unlock/Lock-Down Operation”  
Specification Changes  
8 Mb and 16Mb - 28F160C3 and 28F800C3  
Number  
Page  
Specification Changes  
1
2
3
15  
15  
15  
Maximum I  
Change  
CCD  
CFI Primary-Vendor Specific Extended Query Change  
Block Locking Command Sequence Change  
32Mb - 28F320C3  
Number  
Page  
Specification Changes  
1
2
3
4
15  
15  
15  
16  
Maximum I  
Change  
CCD  
CFI Primary-Vendor Specific Extended Query Change  
Block Locking Command Sequence Change  
0.25µm 32-MbMaximum V  
Change  
CC  
Specification Clarifications  
Number  
Page  
Specification Clarifications  
None in this Specification Update revision  
N/A  
17  
Documentation Changes  
Number  
Document Revision  
Page  
Documentation Changes  
None in this Specification Update revision  
N/A  
17  
8
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
Identification Information  
Identification Information  
Markings  
The Finished Processing Order (FPO) number correlates to a specific device stepping as illustrated  
in the table below:  
(1)  
Stepping  
A Stepping  
Identifier  
Ninth digit on topside FPO mark (third line) = anything  
Note: Device steppings are based on continuous improvements made in manufacturing and testing of the device and  
represent the current material shipped.  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Udpate  
9
Errata  
Errata  
1.  
28F320C3xC Maximum ICCE when Vpp=12V  
Problem:  
When VPP=12V, ICCE Max on 28F320C3xC devices on the 0.18µm deviates from the published  
specification and increases from 15mA to 25mA. The following is the revised specification for  
these products.  
V
11.4 V –12.6 V  
2.7 V –3.6 V  
PP  
V
/
CC  
Sym  
Parameter  
Unit  
Test Conditions  
V
CCQ  
Typ  
Max  
V
= V  
(12V), Erase in  
PP  
PP2  
I
V
Erase Current  
8
25  
mA  
CCE  
CC  
Progress  
Implication:  
Status:  
The increased current requirements may result in increased power drawn from the power supply  
during limited 12 V production programming. 3 V programming is unaffected.  
32-Mb devices on the 0.18mm process are affected.  
2.  
28F320C3xC Reset Failure  
Problem:  
The 0.18µm 28F320C3xC devices can unintentionally reset under certain conditions where VPP  
toggles.  
Implication:  
When the reset occurs, any command being executed is interrupted and the flash switches to read  
array mode.  
Workaround: There are four workarounds for this erratum:  
1) Tie VPP to VCC  
;
2) If the third and forth digits on the top side FPO mark (third line) is equal or greater than “23”,  
then VCC may be set from 2.7v to 3.3v. VCC must not exceed 3.3v  
3) Set VPP to a static high or static low level as shown here; and  
Hold VPP Static  
No restrictions on  
other waveforms  
VPP  
CE#  
WE#  
10  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
Errata  
4) Wait 2 ms after a VPP transition to access the flash device, as shown here.  
2 ms  
2 ms  
VPP  
CE#  
WE#  
Status:  
This erratum affects all 0.18µm 28F320C3 devices. Root cause has been identified and this erratum  
may be fixed in a future stepping of the product.  
3.  
28F640C3xC Maximum ICCS and ICCD Change  
Problem:  
On the 0.18µm 28F640C3xC devices, the maximum ICCS and ICCD deviates from the published  
specification and increases from 15 µA to 20 µA. The following table shows the revised ICCS and  
ICCD specifications.  
V
2.7 V –3.6 V  
2.7 V –3.6 V  
CC  
Sym  
Parameter  
V
Unit  
Test Conditions  
CCQ  
Note  
Type  
Max  
V
CC = VCCMax  
CE# = RP# = VCCQ  
or during Program/ Erase  
Suspend  
ICCS  
VCC Standby Current  
1,7  
7
20  
µA  
µA  
WP# = VCCQ or GND  
VCC = VCCMax  
VCC Deep Power-Down  
Current  
VCCQ = VCCQMax  
VIN = VCCQ or GND  
RP# = GND 0.2 V  
ICCD  
1,7  
7
20  
NOTE:  
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 °C.  
2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or  
VCCQ voltage listed at the top of each column.  
Implication:  
The increased current requirements may result in a nominal increase in power drawn from the  
power supply.  
Workaround: None  
Status: This erratum affects all 0.18µm 28F640C3xC devices. Root cause has been identified and this  
erratum may be fixed in a future stepping of the product.  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Udpate  
11  
Errata  
4.  
28F160C3xC Erase Resume Issue  
Problem:  
On the 0.18µm 28F160C3xC devices, a design anomaly was discovered. During an Erase-Suspend  
operation, if the Program (40H/10H) sequence is executed, under limited conditions the proceeding  
Erase Resume command (D0H) may not actually resume the device. No customers have reported  
failures in product applications. Customers who use any version of FDI (Intel Flash Data  
Integrator) software will not see this issue. If the Read Array command is issued prior to the Erase  
Resume command, users will not see the issue (typical in XIP applications).  
Implication:  
The Resume Command (D0H) may be ignored by the device and will not correctly resume. The  
device will appear to remain in suspend (via status register). After a reset of the flash device the  
status register will clear. This failure has been recreated in a lab environment only.  
Workaround: There are 2 workarounds for this erratum.  
1. If FDI (Intel Flash Data Integrator) software is used, users will not see the issue.  
2. During an Erase-Suspend (B0H), user must issue any of the following commands after issuing  
the Program (40H/10H) and data sequence but before issuing the Erase-Resume (D0H)  
command.  
First Bus Cycle  
Addr  
Second Bus Cycle  
Addr  
Command  
Oper  
Data  
Oper  
Data  
Read Array  
Write  
Write  
Write  
Write  
Write  
Write  
Write  
X
X
X
X
X
X
X
FFH  
Read Configuration  
Read Query  
90H  
Read  
Read  
Read  
IA  
QA  
X
ID  
98H  
QD  
Read Status Register  
Clear Status Register  
Program/Erase Suspend  
Unlock Block  
70H  
50H  
SRD  
B0H  
60H  
Write  
BA  
D0H  
PA: Program Address  
IA: Identifier Address  
QA: Query Addr  
BA: Block Address  
QD: Query Data  
ID: Identifier Data  
SRD: Status Register Data  
12  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
Errata  
Figure 1. Workaround Placement  
Erase Suspend/Resume Flow chart  
Standard Sequence  
Pass Sequence  
start  
start  
Erase Suspend  
(B0H)  
Erase Suspend  
(B0H)  
Any Valid  
Operation(s)  
Program  
(40H/10H)  
andData  
Program  
(40H/10H)  
andData  
ISSUEHERE  
Workaround  
commands:  
FFH  
EraseResume  
(D0H)  
50H  
60H +D0H  
70H  
90H  
98H  
B0H  
Erasemay not  
Resume  
EraseResume  
(D0H)  
EraseResumed  
Status:  
Root cause has been identified. New material will be available in August 2002.  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Udpate  
13  
Errata  
5.  
28F160C3xC and 28F640C3xC Lock/Unlock/Lock-Down Operation  
Problem:  
On the 16Mb and 64Mb 0.18µm devices, if CE# is deasserted after any block lock operation and  
before the next write sequence, the part may perform the same operation on additional blocks. (See  
waveform below.)  
CE#  
0x60  
0x2F  
WE#  
Implication:  
When CE# is deasserted after performing a block lock operation to a specific block and prior to the  
next write sequence, other blocks may perform the same operation.  
Workaround: Depending on software implementation, systems may already be effectively managing this  
erratum. There is currently a workaround for this erratum:  
Immediately after performing a block lock, unlock, or lock-down operation, perform a valid write  
sequence before chip enable (CE#) is deasserted.  
For example, one possible solution is shown below:  
1) Assert CE# and toggle WE# to write the block lock setup command (0x60).  
2) Toggle WE# a second time to write the confirm command (lock = 0x01; unlock = 0xD0; lock-  
down = 0x2F).  
3) Toggle WE# a third time (ex: 0xFF- Read Array) before CE# is deasserted. (See waveform  
below.) Any other valid write sequence will also work (i.e., 0x90 - Read Configuration, 0x40 -  
Program, 0x20 - Erase).  
CE#  
WE#  
0x60  
0x2F  
(0xFF)  
Status:  
16Mb and 64Mb devices on the 0.18µm process are affected. Root cause has been identified and  
this erratum may be fixed in a future stepping of the product.  
14  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
Specification Changes  
Specification Changes  
1.  
Maximum I  
Change  
CCD  
Issue:  
The maximum ICCD increases from 20 µA to 25 µA on 0.25µm 8-Mb, 16-Mb and 32-Mb versions  
only. The following table shows the revised ICCD specification.  
V
2.7 V –3.6 V  
2.7 V –3.6 V  
CC  
Sym  
Parameter  
V
Unit  
Test Conditions  
CCQ  
Note  
Type  
Max  
V
CC = VCCMax  
VCC Deep Power-Down  
Current  
VCCQ = VCCQMax  
VIN = VCCQ or GND  
RP# = GND 0.2 V  
ICCD  
1,7  
7
25  
µA  
NOTE:  
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 °C.  
2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or  
VCCQ voltage listed at the top of each column.  
2.  
CFI Primary-Vendor Specific Extended Query Change  
Issue:  
The value for address 3A in the CFI Primary-Vendor Specific Extended Query Table (Optional  
Feature and Command Support) has been changed from 0Eh to 66h.  
8-Mbit,  
16-Mbit,  
32-Mbit  
Length  
(bytes)  
Offset(1)  
Description  
(P+5)h  
04h  
Optional Feature & Command Support  
3A: 66  
3B: 00  
3C: 00  
3D: 00  
bit 0 Chip Erase Supported  
(1=yes, 0=no)  
(1=yes, 0=no)  
(1=yes, 0=no)  
(1=yes, 0=no)  
(1=yes, 0=no)  
(1=yes, 0=no)  
(1=yes, 0=no)  
(1=yes, 0=no)  
(1=yes, 0=no)  
bit 1 Suspend Erase Supported  
bit 2 Suspend Program Supported  
bit 3 Legacy Lock/Unlock Supported)  
bit 4 Queued Erase Supported  
bit 5 IBL Supported (2)  
bit 6 OTP Bits Supported (3)  
bit 7 Page Mode Reads Supported  
bit 8 Synchronous Burst Supported  
bits 9–31 reserved for future use; undefined bits are “0”  
NOTES:  
1. The variable P is a pointer that is defined at offset 15H Table D5  
2. IIBL refers to “Instant, Individual Block Locking.”  
3. OTP refers to “One Time Programmab le.”  
CFI templates that support the Advanced+ Boot Block features will recognize block locking and  
unlocking support on affected devices. The CFI Primary-Vendor Specific Extended Query Table  
will be corrected on future steppings.  
3.  
Block Locking Command Sequence Change  
Issue:  
A Read Status Register command must be issued following an Unlock Block command to a block  
that is in the Lockdown or Locked-Lockdown state. WP# must be held valid for all three bus  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Udpate  
15  
Specification Changes  
cycles. See the 3 Volt Advanced+ Boot Block Flash Memory datasheet for a description of the  
Lockdown and Locked-Lockdown states.  
First Bus Cycle  
Second Buss Cycle  
Third Bus Cycle  
Command  
Notes  
Oper  
Addr  
Data  
Oper  
Write  
Addr  
Data  
D0H  
Oper  
Write  
Addr  
Data  
70H  
Unlock  
Block  
4
Write  
X
60H  
BA  
X
Customers may need to modify their software. Note: If the Locking Operations Flowchart (Figure  
16 in the datasheet) is implemented for locking operations with WP# held valid through the Read  
Status Register command, software modifications are not necessary. Future steppings will require  
WP# valid only through the Write Lock, Unlock, or Lockdown commands.  
4.  
0.25µm 32-Mb Maximum V Change  
CC  
Issue:  
The maximum VCC decreases from 3.6 V to 3.3 V on 0.25µm 32-Mb versions only. The following  
table shows the revised VCC specification.  
Symbol  
VCC  
Parameter  
VCC Supply Voltage  
Notes  
Min  
Max  
Units  
1
2.7  
3.3  
Volts  
Other implied specification changes, as a result of the VCC change, are described in the following  
table:  
Symbol  
VCC1  
Parameter  
VCC Supply Voltage  
Notes  
Min  
Max  
Units  
1
1
1
1
2.7  
3.0  
3.3  
3.3  
3.3  
3.3  
Volts  
Volts  
Volts  
Volts  
VCC2  
VCCQ1  
VPP1  
VCC Supply Voltage  
I/O Supply Voltage  
Supply Voltage  
2.7  
1.65  
NOTE: 1. VCC and VCCQ must share the same the same supply when they are in the VCC1 range.  
The maximum VCC has changed on the 0.25µm 32-Mb devices. The maximum VCC specification  
has not changed on the 16-Mb, 8-Mb. This may become an issue if the system voltage regulator  
used has a VCC range tolerance that is outside the new specification, which may cause the device to  
operate in a condition which is outside the specifications of the current datasheet.  
16  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  
Specification Clarifications  
Specification Clarifications  
There are no specification clarifications in this Specification Update revision.  
Documentation Changes  
There are no documentation changes in this Specification Update revision.  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Udpate  
17  
Documentation Changes  
18  
28F800C3, 28F160C3, 28F320C3, 28F640C3 Specification Update  

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型号 制造商 描述 价格 文档
28F800CE-T/B ETC Boot Flash 获取价格
28F800CV-T/B ETC 8-MBIT (512K X 16. 1024K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY 获取价格
28F800F3 INTEL FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT 获取价格
28FE-BT-VK-N ETC 1.25mm pitch Connectors for FFC 获取价格
28FE-ST-VK-N ETC 1.25mm pitch Connectors for FFC 获取价格
28FHA-SM1-GAN-ETB(HF) JST 此FHA连接器是当前FHJ连接器的更新产品。这是Non-ZIF型连接器，用于0.3mm厚的FPC，封装高度为1.1mm，体积小，节省空间。 获取价格
28FHSY-RSM1-GAN-TB JST 这种ZIF型“翻转锁”FPC连接器实现了0.9mm封装高度的低型面特征，尽管FPC的厚度为0.3mm。 获取价格
28FHT-SM1-GAN-TF(HF) JST 采用Non-ZIF型（一次对配）低型面并节省空间无卤素 获取价格
28FHT-SMR-GAN-TF(HF) JST 采用Non-ZIF型（一次对配）低型面并节省空间无卤素 获取价格
28FHY-RSM1-GAN-TF JST 该连接器适用于0.3mm厚的FPC，封装高度为1.3mm。通过采用凸缘式 FPC，可防止 FPC 未接插、错误接插，提高连接可靠性。 获取价格

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