25AA1024-I/MFG中文资料_数据手册_规格书

25AA1024/25LC1024

™

1 Mbit SPI Bus Serial Flash

Device Selection Table

Part Number

VCC Range

Page Size

Temp. Ranges

Packages

25LC1024

25AA1024

2.5-5.5V

1.8-5.5V

256 Byte

I,E

I

P, SM, MF

Features

Description

• Max. clock 20 MHz

The Microchip Technology Inc. 25AA1024/25LC1024

*

(25XX1024 ) is a 1024 Kbit serial reprogrammable

• Flash and byte-level serial EEPROM operation

• Low-power CMOS technology

Flash memory with both Flash and byte-level serial

EEPROM functions. The memory is accessed via a

simple Serial Peripheral Interface™ (SPI™) compatible

serial bus. The bus signals required are a clock input

(SCK) plus separate data in (SI) and data out (SO) lines.

Access to the device is controlled by a Chip Select (CS)

input.

- Max. Write Current: 5 mA at 5.5V, 20 MHz

- Read Current: 10 mA at 5.5V, 20 MHz

- Standby Current: 1µA at 5.5V (Deep power-

down)

• 131,072 x 8-bit organization

• Byte and Page (256 byte page) Write Operations

(5 ms max.)

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

Chip Select, allowing the host to service higher priority

interrupts.

• Electronic Signature for device ID

• Self-timed ERASE and WRITE cycles

- Sector Erase (1 second/sector typical)

- Bulk Erase (2 seconds typical)

• Sector write protection (32K byte/sector)

The 25XX1024 is available in standard packages

including 8-lead PDIP and SOIC, and advanced 8-lead

DFN package. Pb-free (Pure Sn) finish is also

available.

- Protect none, 1/4, 1/2 or all of array

• Built-in write protection

- Power-on/off data protection circuitry

- Write enable latch

- Write-protect pin

Package Types (not to scale)

• High reliability

- Endurance: 100,000 erase/write cycles

DFN

PDIP/SOIC

• Temperature ranges supported;

(MF)

(P, SM)

- Industrial (I):

- Automotive (E):

-40°C to +85°C

-40°C to +125°C

1

2

3

4

CS

SO

8

7

6

5

VCC

HOLD

SCK

SI

CS

SO

WP

VCC

1

2

3

4

8

7

6

5

HOLD

SCK

SI

• Standard and Pb-free packages available

WP

VSS

Pin Function Table

VSS

Name

Function

CS

SO

Chip Select Input

Serial Data Output

Write-Protect

SPI is a registered trademark of Motorola Semiconductor.

WP

V^SS

SI

Ground

Serial Data Input

Serial Clock Input

Hold Input

SCK

HOLD

V^CC

*25XX1024 is used in this document as a generic part number

for the 25AA1024, 25LC1024 devices.

Supply Voltage

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 1

25AA1024/25LC1024

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V^SS......................................................................................................... -0.6V to VCC +1.0V

Storage temperature .................................................................................................................................-65°C to 150°C

Ambient temperature under bias...............................................................................................................-40°C to 125°C

ESD protection on all pins..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an

extended period of time may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Industrial (I):

T^A= -40°C to +85°C

T^A= -40°C to +125°C

VCC = 1.8V to 5.5V

VCC = 2.5V to 5.5V

DC CHARACTERISTICS

Automotive (E):

Param.

Sym.

Characteristic

Min.

Max.

Units

Test Conditions

No.

D001

V^IH1

High-level input

voltage

.7 VCC

VCC +1

V

D002

D003

D004

D005

D006

V^IL1

V^IL2

V^OL

V^OH

Low-level input

voltage

-0.3

0.3 VCC

0.2 VCC

0.4

V

VCC ≥ 2.7V

VCC < 2.7V

Low-level output

voltage

—

IOL = 2.1 mA

—

0.2

IOL = 1.0 mA, VCC < 2.5V

IOH = -400 µA

High-level output

voltage

VCC -0.5

—

D007

D008

I^LI

Input leakage current

1

µA

CS = VCC, VIN = VSS TO VCC

CS = VCC, VOUT = VSS TO VCC

ILO

Output leakage

current

D009

D010

CINT

Internal capacitance

(all inputs and

outputs)

—

7

pF

TA = 25°C, CLK = 1.0 MHz,

V^CC= 5.0V (Note)

I^CCRead

—

10

5

mA

VCC = 5.5V; FCLK = 20.0 MHz;

SO = Open

Operating current

VCC = 2.5V; FCLK = 10.0 MHz;

SO = Open

D011

D012

I^CCWrite

—

5

3

mA

VCC = 5.5V

V^CC= 2.5V

I^CCS

—

20

10

µA

CS = VCC = 5.5V, Inputs tied to VCC or

V^SS, 125°C

Standby current

CS = VCC = 5.5V, Inputs tied to VCC or

V^SS, 85°C

D13

I^CCSPD

Deep power-down

current

—

1

µA

CS = VCC = 5.5V, Inputs tied to VCC or

V^SS

Note:

This parameter is periodically sampled and not 100% tested.

DS21836A-page 2

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

TABLE 1-2:

AC CHARACTERISTICS

Industrial (I):

T^A= -40°C to +85°C

T^A= -40°C to +125°C

VCC = 1.8V TO 5.5V

VCC = 2.5V to 5.5V

AC CHARACTERISTICS

Automotive (E):

Param.

Sym

No.

Characteristic

Clock frequency

Min

Max

Units

Conditions

1

2

3

F^CLK

T^CSS

T^CSH

—

20

10

2

MHz 4.5 ≤ V^CC≤ 5.5

MHz 2.5 ≤ V^CC< 4.5

MHz 1.8 ≤ V^CC< 2.5

CS setup time

25

50

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

250

CS hold time

50

—

ns

4.5 ≤ V^CC≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

(Note 3)

100

500

4

5

T^CSD

Tsu

CS disable time

Data setup time

50

—

ns

5

—

ns

4.5 ≤ V^CC≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

10

50

6

T^HD

Data hold time

10

20

—

ns

4.5 ≤ V^CC≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

100

7

8

9

T^R

T^F

CLK rise time

CLK fall time

Clock high time

—

20

ns

(Note 1)

T^HI

25

50

—

ns

4.5 ≤ V^CC≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

250

10

T^LO

Clock low time

25

50

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

250

11

12

13

T^CLD

T^CLE

T^V

Clock delay time

Clock enable time

50

—

ns

Output valid from clock

low

—

25

50

ns

4.5 ≤ V^CC≤ 5.5

2.8 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

250

14

15

T^HO

T^DIS

Output hold time

0

—

ns

(Note 1)

Output disable time

—

25

50

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

(Note 1)

250

16

17

T^HS

HOLD setup time

10

20

—

ns

4.5 ≤ V^CC≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

100

T^HH

HOLD hold time

10

20

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

100

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance estimates

in a specific application, please consult the Total Endurance™ Model which can be obtained from our web

site.

3: Includes T^HItime.

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 3

25AA1024/25LC1024

TABLE 1-2:

(CONTINUED) AC CHARACTERISTICS

Industrial (I):

T^A= -40°C to +85°C

T^A= -40°C to +125°C

VCC = 1.8V TO 5.5V

VCC = 2.5V to 5.5V

AC CHARACTERISTICS

Automotive (E):

Param.

Sym

No.

Characteristic

Min

Max

Units

Conditions

18

Thz

HOLD low to output

High-Z

15

30

—

ns

4.5 ≤ V^CC≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

(Note 1)

150

19

Thv

HOLD high to output valid

15

30

—

ns

4.5 ≤ VCC ≤ 5.5

2.5 ≤ V^CC< 4.5

1.8 ≤ V^CC< 2.5

150

20

21

Trel

Tpd

CS High to Standby mode

—

1.6

µs

VCC = 1.8V to 5.5V

CS High to Deep power-

down

22

23

24

25

Tce

Tse

Twc

—

Chip erase cycle time

Sector erase cycle time

Internal write cycle time

Endurance

—

4

2

s

V^CC= 1.8V to 5.5V

Byte or Page mode

—

5

ms

100K

—

E/W (Note 2)

Cycles

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but established by characterization and qualification. For endurance estimates

in a specific application, please consult the Total Endurance™ Model which can be obtained from our web

site.

3: Includes T^HItime.

TABLE 1-3:

AC TEST CONDITIONS

AC Waveform:

V^LO= 0.2V

—

V^HI= VCC - 0.2V

(Note 1)

(Note 2)

—

V^HI= 4.0V

C^L= 100 pF

Timing Measurement Reference Level

Input

0.5 V^CC

Output

0.5 VCC

Note 1: For VCC ≤ 4.0V

2: For V^CC> 4.0V

DS21836A-page 4

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

FIGURE 1-1: HOLD TIMING

CS

17

16

SCK

18

19

high-impedance

n

SO

n+2

n+1

n

n-1

5

don’t care

n

n+2

n+1

n

n-1

SI

HOLD

FIGURE 1-2: SERIAL INPUT TIMING

4

CS

12

11

2

7

3

8

Mode 1,1

Mode 0,0

SCK

5

6

SI

MSB in

LSB in

high-impedance

SO

FIGURE 1-3: SERIAL OUTPUT TIMING

CS

3

9

10

Mode 1,1

Mode 0,0

SCK

13

15

14

MSB out

LSB out

SO

don’t care

SI

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 5

25AA1024/25LC1024

2.0

FUNCTIONAL DESCRIPTION

2.1

Principles of Operation

2.3

Write Sequence

The 25XX1024 is a 131,072 byte Serial Flash designed

to interface directly with the Serial Peripheral Interface

(SPI) port of many of today’s popular microcontroller

Prior to any attempt to write data to the 25XX1024, the

write enable latch must be set by issuing the WREN

instruction (Figure 2-4). This is done by setting CS low

and then clocking out the proper instruction into the

25XX1024. After all eight bits of the instruction are

transmitted, the CS must be brought high to set the

write enable latch. If the write operation is initiated

immediately after the WREN instruction without CS

being brought high, the data will not be written to the

array because the write enable latch will not have been

properly set.

®

families, including Microchip’s PICMicro microcontrol-

lers. It may also interface with microcontrollers that do

not have a built-in SPI port by using discrete I/O lines

programmed properly in firmware to match the SPI

protocol.

The 25XX1024 contains an 8-bit instruction register.

The device is accessed via the SI pin, with data being

clocked in on the rising edge of SCK. The CS pin must

be low and the HOLD pin must be high for the entire

operation.

Once the write enable latch is set, the user may

proceed by setting the CS low, issuing a WRITEinstruc-

tion, followed by the 24-bit address, with seven MSBs

of the address being don’t care bits, and then the data

to be written. Up to 256 bytes of data can be sent to the

device before a write cycle is necessary. The only

restriction is that all of the bytes must reside in the

same page.

Table 2-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSB first, LSB

last.

Data (SI) is sampled on the first rising edge of SCK

after CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25XX1024 in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

Note:

Page write operations are limited to writing

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size (or

‘page size’), and end at addresses that are

integer multiples of page size - 1. If a Page

Write command attempts to write across a

physical page boundary, the result is that

the data wraps around to the beginning of

the current page (overwriting data

previously stored there), instead of being

written to the next page as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

2.2

Read Sequence

The device is selected by pulling CS low. The 8-bit read

instruction is transmitted to the 25XX1024 followed by

the 24-bit address, with seven MSBs of the address

being don’t care bits. After the correct read instruction

and address are sent, the data stored in the memory at

the selected address is shifted out on the SO pin. The

data stored in the memory at the next address can be

read sequentially by continuing to provide clock pulses.

The internal address pointer is automatically incre-

mented to the next higher address after each byte of

data is shifted out. When the highest address is

reached (1FFFFh), the address counter rolls over to

address 00000h allowing the read cycle to be contin-

ued indefinitely. The read operation is terminated by

raising the CS pin (Figure 2-1).

For the data to be actually written to the array, the CS

must be brought high after the Least Significant bit (D0)

th

of the n data byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 2-2 and Figure 2-3

for more detailed illustrations on the byte write

sequence and the page write sequence respectively.

While the write is in progress, the Status Register may

be read to check the status of the WPEN, WIP, WEL,

BP1 and BP0 bits (Figure 2-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enable latch is reset.

DS21836A-page 6

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

BLOCK DIAGRAM

Status

HV Generator

Register

EEPROM

Array

Memory

Control

Logic

X

I/O Control

Logic

Dec

Page Latches

SI

SO

Y Decoder

CS

SCK

Sense Amp.

R/W Control

HOLD

WP

VCC

VSS

TABLE 2-1:

INSTRUCTION SET

Instruction Name

Instruction Format

Description

READ

WRITE

WREN

WRDI

RDSR

WRSR

PE

0000 0011

0000 0010

0000 0110

0000 0100

0000 0101

0000 0001

0100 0010

1101 1000

1100 0111

1010 1011

1011 1001

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Set the write enable latch (enable write operations)

Reset the write enable latch (disable write operations)

Read Status Register

Write Status Register

Page Erase - erase one page in memory array

Sector Erase - erase one sector in memory array

Chip Erase - erase all sectors in memory array

Release from Deep power-down and read electronic signature

Deep Power-down mode

SE

CE

RDID

DPD

FIGURE 2-1:

READ SEQUENCE

CS

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31 32 33 34 35 36 37 38 39

SCK

instruction

24 Bit Address

23 22 21 20

0

1

2

1

0

SI

Data Out

high-impedance

7

6

5

4

3

2

1

0

SO

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 7

25AA1024/25LC1024

FIGURE 2-2:

BYTE WRITE SEQUENCE

CS

Twc

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31 32 33 34 35 36 37 38 39

SCK

instruction

24-bit address

23 22 21 20

data byte

0

1

0

2

1

0

7

6

5

4

3

2

1

0

SI

high-impedance

SO

FIGURE 2-3:

PAGE WRITE SEQUENCE

CS

0

1

2

3

4

5

6

7

8

9

10 11

29 30 31 32 33 34 35 36 37 38 39

SCK

instruction

24-bit address

data byte 1

0

1

0 23 22 21 20

2

1

0

7

6

5

4

3

2

1

0

SI

CS

40 41 42 43 44 45 46 47

49 50 51 52 53 54 55

48

SCK

data byte 2

data byte 3

data byte n (256 max)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

SI

DS21836A-page 8

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

The following is a list of conditions under which the

write enable latch will be reset:

2.4

Write Enable (WREN) and Write

Disable (WRDI)

• Power-up

The 25XX1024 contains a write enable latch. See

Table 2-4 for the Write-Protect Functionality Matrix.

This latch must be set before any write operation will be

completed internally. The WRENinstruction will set the

latch, and the WRDIwill reset the latch.

• WRDIinstruction successfully executed

• WRSRinstruction successfully executed

• WRITEinstruction successfully executed

FIGURE 2-4:

WRITE ENABLE SEQUENCE (WREN)

CS

SCK

SI

0

1

2

3

4

5

6

7

0

1

0

high-impedance

SO

FIGURE 2-5:

WRITE DISABLE SEQUENCE (WRDI)

CS

0

1

2

3

4

5

6

7

SCK

0

1

0

1

0

SI

high-impedance

SO

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 9

25AA1024/25LC1024

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch and is read-only. When set to

a ‘1’, the latch allows writes to the array, when set to a

‘0’, the latch prohibits writes to the array. The state of

this bit can always be updated via the WREN or WRDI

commands regardless of the state of write protection

on the Status Register. These commands are shown in

Figure 2-4 and Figure 2-5.

2.5

Read Status Register Instruction

(RDSR)

The Read Status Register instruction (RDSR) provides

access to the Status Register. The Status Register may

be read at any time, even during a write cycle. The

Status Register is formatted as follows:

TABLE 2-2:

STATUS REGISTER

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write-protected. These bits

are set by the user issuing the WRSRinstruction. These

bits are nonvolatile, and are shown in Table 2-3.

7

6

–

X

5

–

X

4

–

X

3

2

1

0

W/R

W/R W/R

R

WPEN

BP1 BP0 WEL WIP

See Figure 2-6 for the RDSRtiming sequence.

W/R = writable/readable. R = read-only.

The Write-In-Process (WIP) bit indicates whether the

25XX1024 is busy with a write operation. When set to

a ‘1’, a write is in progress, when set to a ‘0’, no write

is in progress. This bit is read-only.

FIGURE 2-6:

READ STATUS REGISTER TIMING SEQUENCE (RDSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

instruction

0

1

0

1

SI

Data from Status Register

high-impedance

7

6

5

4

3

2

1

0

SO

DS21836A-page 10

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP pin. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the Status Register control the

programmable hardware write-protect feature. Hard-

ware write protection is enabled when WP pin is low

and the WPEN bit is high. Hardware write protection is

disabled when either the WP pin is high or the WPEN

bit is low. When the chip is hardware write-protected,

only writes to nonvolatile bits in the Status Register are

disabled. See Table 2-4 for a matrix of functionality on

the WPEN bit.

2.6

Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to write to the nonvolatile bits in the Status

Register as shown in Table 2-2. The user is able to

select one of four levels of protection for the array by

writing to the appropriate bits in the Status Register.

The array is divided up into four segments. The user

has the ability to write-protect none, one, two or all four

of the segments of the array. The partitioning is

controlled as shown in Table 2-3.

See Figure 2-7 for the WRSR timing sequence.

TABLE 2-3:

ARRAY PROTECTION

Array Addresses

Unprotected

BP1

BP0

Write-Protected

none

All (Sectors 0, 1, 2 & 3)

(00000h - 1FFFFh)

0

Upper 1/4 (Sector 3)

(18000h - 1FFFFh)

Lower 3/4 (Sectors 0, 1 & 2)

(00000h - 17FFFh)

0

1

Upper 1/2 (Sectors 2 & 3)

(10000h - 1FFFFh)

Lower 1/2 (Sectors 0 & 1)

(00000h - 0FFFFh)

0

1

All (Sectors 0, 1, 2 & 3)

(00000h - 1FFFFh)

none

FIGURE 2-7:

WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)

CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

SCK

instruction

0

data to Status Register

7

6

5

4

3

2

1

0

1

SI

high-impedance

SO

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 11

25AA1024/25LC1024

2.7

Data Protection

2.8

Power-On State

The following protection has been implemented to

prevent inadvertent writes to the array:

The 25XX1024 powers on in the following state:

• The device is in low-power Standby mode

(CS = 1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or Status Register

write, the write enable latch is reset

• CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

TABLE 2-4:

WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

WPEN

WP

Protected Blocks

Unprotected Blocks

Status Register

(SR bit 1)

(SR bit 7)

(pin 3)

Protected

Writable

Protected

Writable

Protected

Writable

0

x

0

1

x

1

x

1

0 (low)

1 (high)

1

x = don’t care

DS21836A-page 12

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

2.9

PAGE ERASE

The Page Erase function will erase all bits (FFh) inside

the given page. A Write Enable (WREN) instruction

must be given prior to attempting a Page Erase. This

is done by setting CS low and then clocking out the

proper instruction into the 25XX1024. After all eight

bits of the instruction are transmitted, the CS must be

brought high to set the write enable latch.

CS must then be driven high after the last bit if the

address or the Page Erase will not execute. Once the

CS is driven high the self-timed Page Erase cycle is

started. The WIP bit in the Status Register can be read

to determine when the Page Erase cycle is complete.

If a Page Erase function is given to an address that

has been protected by the Block Protect bits (BP0,

BP1) then the sequence will be aborted and no erase

will occur.

The Page Erase function is entered by driving CS low,

followed by the instruction code Figure 2-8, and three

address bytes. Any address inside the page to be

erased is a valid address.

FIGURE 2-8:

PAGE ERASE SEQUENCE

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31

instruction

24-bit address

23 22 21 20

0

1

0

1

0

2

1

0

high-impedance

SO

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 13

25AA1024/25LC1024

2.10 SECTOR ERASE

The Sector Erase function will erase all bits (FFh)

inside the given sector. A Write Enable (WREN) instruc-

tion must be given prior to attempting a Sector Erase.

This is done by setting CS low and then clocking out

the proper instruction into the 25XX1024. After all

eight bits of the instruction are transmitted, the CS

must be brought high to set the write enable latch.

CS must then be driven high after the last bit if the

address or the Sector Erase will not execute. Once the

CS is driven high the self-timed Sector Erase cycle is

started. The WIP bit in the Status Register can be read

to determine when the Sector Erase cycle is complete.

If a Sector Erase instruction is given to an address that

has been protected by the Block Protect bits (BP0,

BP1) then the sequence will be aborted and no erase

will occur.

The Sector Erase function is entered by driving CS

low, followed by the instruction code Figure 2-9, and

three address bytes. Any address inside the sector to

be erased is a valid address.

See Table 2-3 for Sector Addressing.

FIGURE 2-9:

SECTOR ERASE SEQUENCE

CS

SCK

SI

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31

instruction

24-bit address

23 22 21 20

1

0

1

0

2

1

0

high-impedance

SO

DS21836A-page 14

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

2.11 CHIP ERASE

The Chip Erase function will erase all bits (FFh) in the

array. A Write Enable (WREN) instruction must be given

prior to executing a Chip Erase. This is done by setting

CS low and then clocking out the proper instruction

into the 25XX1024. After all eight bits of the instruction

are transmitted, the CS must be brought high to set

the write enable latch.

The CS pin must be driven high after the eighth bit of

the instruction code has been given or the Chip Erase

function will not be executed. Once the CS pin is

driven high the self-timed Chip Erase function begins.

While the device is executing the Chip Erase function

the WIP bit in the Status Register can be read to

determine when the Chip Erase function is complete.

The Chip Erase function is entered by driving the CS

low, followed by the instruction code (Figure 2-10)

onto the SI line.

The Chip Erase function is ignored if either of the

Block Protect bits (BP0, BP1) are not 0, meaning ¼,

½, or all of the array is protected.

FIGURE 2-10:

CHIP ERASE SEQUENCE

CS

0

1

2

3

4

5

6

7

SCK

1

0

1

SI

high-impedance

SO

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 15

25AA1024/25LC1024

2.12 DEEP POWER-DOWN MODE

Deep Power-down Mode of the 25XX1024 is its lowest

power consumption state. The device will not respond

to any of the read or write commands while in Deep

Power-down mode, and therefore it can be used as an

additional software write protection feature.

All instructions given during Deep Power-down mode

are ignored except the Read Electronic Signature

Command (RDID). The RDID command will release

the device from Deep power-down and outputs the

electronic signature on the SO pin, and then returns

the device to Standby mode after delay (T

)

REL

The Deep Power-down mode is entered by driving CS

low, followed by the instruction code (Figure 2-11) onto

the SI line, followed by driving CS high.

Deep Power-down mode automatically releases at

device power-down. Once power is restored to the

device it will power-up in the Standby mode.

If the CS pin is not driven high after the eighth bit of

the instruction code has been given, the device will not

execute Deep power-down. Once the CS line is driven

high there is a delay (T ) before the current settles to

DP

its lowest consumption.

FIGURE 2-11:

DEEP POWER-DOWN SEQUENCE

CS

0

1

2

3

4

5

6

7

SCK

1

0

1

0

1

SI

high-impedance

SO

DS21836A-page 16

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

Release from Deep Power-down mode and Read

Electronic Signature is entered by driving CS low,

followed by the RDID instruction code (Figure 2-12)

and then a dummy address of 24 bits (A23-A0). After

the last bit of the dummy address is clock in, the 8-bit

Electronic signature is clocked out on the SO pin.

2.13 RELEASE FROM DEEP POWER-

DOWN AND READ ELECTRONIC

SIGNATURE

Once the device has entered Deep Power-down mode

all instructions are ignored except the Release from

Deep Power-down and Read Electronic Signature

command. This command can also be used when the

device is not in Deep Power-down to read the

electronic signature out on the SO pin unless another

command is being executed such as Erase, Program

or Write Status Register.

After the signature has been read out at least once,

the sequence can be terminated by driving CS high.

The device will then return to Standby mode and will

wait to be selected so it can be given new instructions.

If additional clock cycles are sent after the electronic

signature has been read once, it will continue to output

the signature on the SO line until the sequence is

terminated.

FIGURE 2-12:

RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

0

1

2

3

4

5

6

7

8

9 10 11

29 30 31 32 33 34 35 36 37 38 39

SCK

instruction

24-bit address

23 22 21 20

1

0

1

0

1

0

1

2

1

0

SI

Electronic Signature Out

high-impedance

7

6

5

4

3

2

1

0

SO

0

1

0

1

0

1

Manufacturers ID 0x29

Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure

the device will be taken out of Deep Power-down mode. However, there is a delay T that occurs before the device

REL

returns to Standby mode (I

), as shown in Figure 2-13.

CCS

FIGURE 2-13:

RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE

CS

T

REL

0

1

2

3

4

5

6

7

SCK

instruction

1

0

1

0

1

0

1

SI

high-impedance

SO

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 17

25AA1024/25LC1024

The WP pin function is blocked when the WPEN bit in

the Status Register is low. This allows the user to install

the 25XX1024 in a system with WP pin grounded and

still be able to write to the Status Register. The WP pin

functions will be enabled when the WPEN bit is set

high.

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Name

Pin Number

Function

3.4

Serial Input (SI)

CS

SO

1

2

3

4

5

6

7

8

Chip Select Input

Serial Data Output

Write-Protect Pin

Ground

The SI pin is used to transfer data into the device. It

receives instructions, addresses and data. Data is

latched on the rising edge of the serial clock.

WP

V^SS

SI

3.5

Serial Clock (SCK)

Serial Data Input

Serial Clock Input

Hold Input

The SCK is used to synchronize the communication

between a master and the 25XX1024. Instructions,

addresses or data present on the SI pin are latched on

the rising edge of the clock input, while data on the SO

pin is updated after the falling edge of the clock input.

SCK

HOLD

V^CC

Supply Voltage

3.1

Chip Select (CS)

3.6

Hold (HOLD)

A low level on this pin selects the device. A high level

deselects the device and forces it into Standby mode.

However, a programming cycle which is already

initiated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a

program cycle, the device will go into Standby mode as

soon as the programming cycle is complete. When the

device is deselected, SO goes to the high-impedance

state, allowing multiple parts to share the same SPI

bus. A low-to-high transition on CS after a valid write

sequence initiates an internal write cycle. After power-

up, a low level on CS is required prior to any sequence

being initiated.

The HOLD pin is used to suspend transmission to the

25XX1024 while in the middle of a serial sequence

without having to retransmit the entire sequence again.

It must be held high any time this function is not being

used. Once the device is selected and a serial

sequence is underway, the HOLD pin may be pulled

low to pause further serial communication without

resetting the serial sequence. The HOLD pin must be

brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high-to-

low transition. The 25XX1024 must remain selected

during this sequence. The SI, SCK and SO pins are in

a high-impedance state during the time the device is

paused and transitions on these pins will be ignored. To

resume serial communication, HOLD must be brought

high while the SCK pin is low, otherwise serial

communication will not resume. Pulling the HOLD line

low at any time will tri-state the SO line.

3.2

Serial Output (SO)

The SO pin is used to transfer data out of the

25XX1024. During a read cycle, data is shifted out on

this pin after the falling edge of the serial clock.

3.3

Write-Protect (WP)

This pin is used in conjunction with the WPEN bit in the

Status Register to prohibit writes to the nonvolatile bits

in the Status Register. When WP is low and WPEN is

high, writing to the nonvolatile bits in the Status

Register is disabled. All other operations function

normally. When WP is high, all functions, including

writes to the nonvolatile bits in the Status Register,

operate normally. If the WPEN bit is set, WP low during

a Status Register write sequence will disable writing to

the Status Register. If an internal write cycle has

already begun, WP going low will have no effect on the

write.

DS21836A-page 18

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

4.0

PACKAGING INFORMATION

Package Marking Information

8-Lead DFN

4.1

Example:

XXXXXXX

T/XXXXX

YYWW

5LC1024

I/MF

0328

NNN

1L7

Example:

8-Lead PDIP

25AA1024

I/P 1L7

XXXXXXXX

T/XXXNNN

0328

YYWW

Example:

8-Lead SOIC

25LC1024

I/SN 0328

XXXXXXXX

T/XXYYWW

1L7

NNN

Legend: XX...X Part number

T

Temperature (I,E)

Blank Commercial

YY

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

WW

NNN

Note: Custom marking available.

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 19

25AA1024/25LC1024

8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S)

E

p

B

E1

n

L

R

D1

D

D2

PIN 1

EXPOSED

METAL

PADS

ID

1

2

E2

BOTTOM VIEW

TOP VIEW

α

A2

A3

A

A1

Units

Dimension Limits

INCHES

MILLIMETERS*

MIN

NOM

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.050 BSC

1.27 BSC

0.85

Overall Height

A

A2

A1

A3

E

.033

.039

1.00

Molded Package Thickness

Standoff

.026

.0004

.031

.002

0.65

0.80

0.05

.000

0.00

0.01

0.20 REF.

Base Thickness

Overall Length

.008 REF.

.194 BSC

.184 BSC

.158

4.92 BSC

4.67 BSC

Molded Package Length

Exposed Pad Length

Overall Width

E1

E2

D

.152

.163

3.85

4.00

4.15

.236 BSC

.226 BSC

.091

5.99 BSC

5.74 BSC

Molded Package Width

Exposed Pad Width

Lead Width

D1

D2

B

.085

.014

.020

.097

.019

.030

2.16

0.35

0.50

2.31

2.46

0.47

0.75

.016

0.40

0.60

.356

Lead Length

L

.024

Tie Bar Width

R

.014

α

Mold Draft Angle Top

12

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC equivalent: pending

Drawing No. C04-113

DS21836A-page 20

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

Top to Seating Plane

8

.100

.155

.130

2.54

A

.140

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 21

25AA1024/25LC1024

8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)

E

E1

p

D

2

n

1

B

α

c

A2

A

φ

A1

L

β

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.050

.075

.074

.005

.313

.208

.205

.025

4

1.27

Overall Height

A

.070

.080

1.78

1.75

1.97

1.88

0.13

7.95

5.28

5.21

0.64

4

2.03

Molded Package Thickness

Standoff

A2

A1

E

.069

.002

.300

.078

.010

.325

.212

.210

.030

8

1.98

0.25

8.26

5.38

5.33

0.76

8

§

0.05

7.62

5.11

5.13

0.51

0

Overall Width

Molded Package Width

Overall Length

E1

D

.201

.202

.020

0

Foot Length

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.014

0

.009

.017

12

.010

.020

15

0.20

0.36

0

0.23

0.43

12

0.25

0.51

15

B

α

Mold Draft Angle Top

Mold Draft Angle Bottom

β

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

Drawing No. C04-056

DS21836A-page 22

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

ON-LINE SUPPORT

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

Microchip provides on-line support on the Microchip

World Wide Web site.

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can receive the most current upgrade kits.The Hot Line

Numbers are:

The web site is used by Microchip as a means to make

files and information easily available to customers. To

view the site, the user must have access to the Internet

®

and a web browser, such as Netscape or Microsoft

®

Internet Explorer. Files are also available for FTP

download from our FTP site.

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

Connecting to the Microchip Internet

Web Site

042003

The Microchip web site is available at the following

URL:

www.microchip.com

The file transfer site is available by using an FTP

service to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A

variety of Microchip specific business information is

also available, including listings of Microchip sales

offices, distributors and factory representatives. Other

data available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Conferences for products, Development Systems,

technical information and more

• Listing of seminars and events

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 23

25AA1024/25LC1024

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

25AA1024/25LC1024

DS21836A

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21836A-page 24

Preliminary

 2003 Microchip Technology Inc.

25AA1024/25LC1024

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

X

–

Examples:

25AA1024-I/SMG = 1 Mbit, 1.8V Serial Flash,

Tape & Reel

Package

Lead

Temp Range

a)

b)

c)

d)

e)

f)

Industrial temp., SOIC package, Pb-free

Finish

25AA1024T-I/SM = 1 Mbit, 1.8V Serial Flash,

Industrial temp., Tape & Reel, SOIC package

25AA1024T-I/MF = 1 Mbit, 1.8V Serial Flash,

Industrial temp., Tape & Reel, DFN package

Device

25AA1024 1 Mbit, 1.8V, 256-Byte Page SPI Serial Flash

25LC1024 1 Mbit, 2.5V, 256-Byte Page SPI Serial Flash

25LC1024-I/SMG = 1 Mbit, 2.5V Serial Flash,

Industrial temp., SOIC package, Pb-free

Tape & Reel

Blank

T

=

Standard packaging (tube)

Tape & Reel

25LC1024-I/P = 1 Mbit, 2.5V Serial Flash,

Industrial temp., P-DIP package

Temperature Range

I

=

-40°C to+85°C

-40°C to+125°C

E

25LC1024T-E/MF = 1 Mbit, 2.5V Serial Flash,

Extended temp., Tape & Reel, DFN package

Package

MF

P

=

Micro Lead Frame (6 x 5 mm body), 8-lead

Plastic DIP (300 mil body), 8-lead

SM

Plastic SOIC (207 mil body), 8-lead

Lead Finish

Blank

G

=

Standard 63% / 37% Sn/Pb

Matte Tin (Pure Sn)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 25

25AA1024/25LC1024

NOTES:

DS21836A-page 26

Preliminary

 2003 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, K^EELOQ, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE and PowerSmart are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,

SEEVAL and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,

SmartSensor, SmartShunt, SmartTel and Total Endurance are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip’s quality system for the

design and manufacture of development

systems is ISO 9001 certified.

 2003 Microchip Technology Inc.

Preliminary

DS21836A-page 27

WORLDWIDE SALES AND SERVICE

Korea

AMERICAS

ASIA/PACIFIC

168-1, Youngbo Bldg. 3 Floor

Corporate Office

Australia

Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Suite 22, 41 Rawson Street

Epping 2121, NSW

Australia

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or

82-2-558-5934

Fax: 480-792-7277

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Singapore

Technical Support: 480-792-7627

Web Address: http://www.microchip.com

200 Middle Road

China - Beijing

#07-02 Prime Centre

Singapore, 188980

Unit 915

Atlanta

Bei Hai Wan Tai Bldg.

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100

Fax: 86-10-85282104

3780 Mansell Road, Suite 130

Alpharetta, GA 30022

Tel: 770-640-0034

Fax: 770-640-0307

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Kaohsiung Branch

30F - 1 No. 8

Boston

Min Chuan 2nd Road

Kaohsiung 806, Taiwan

Tel: 886-7-536-4818

Fax: 886-7-536-4803

China - Chengdu

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978-692-3848

Fax: 978-692-3821

Rm. 2401-2402, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Taiwan

Chengdu 610016, China

Tel: 86-28-86766200

Taiwan Branch

Chicago

11F-3, No. 207

333 Pierce Road, Suite 180

Itasca, IL 60143

Fax: 86-28-86766599

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

China - Fuzhou

Tel: 630-285-0071

Fax: 630-285-0075

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Dallas

Fuzhou 350001, China

Tel: 86-591-7503506

Fax: 86-591-7503521

EUROPE

4570 Westgrove Drive, Suite 160

Addison, TX 75001

Tel: 972-818-7423

Fax: 972-818-2924

Austria

Durisolstrasse 2

China - Hong Kong SAR

A-4600 Wels

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Austria

Detroit

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250

Fax: 852-2401-3431

Regus Business Centre

Lautrup hoj 1-3

China - Shanghai

Room 701, Bldg. B

Fax: 248-538-2260

Ballerup DK-2750 Denmark

Tel: 45-4420-9895 Fax: 45-4420-9910

Far East International Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Kokomo

France

2767 S. Albright Road

Kokomo, IN 46902

Tel: 765-864-8360

Fax: 765-864-8387

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Tel: 86-21-6275-5700

Fax: 86-21-6275-5060

China - Shenzhen

Los Angeles

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Tel: 86-755-82901380

18201 Von Karman, Suite 1090

Irvine, CA 92612

Germany

Tel: 949-263-1888

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Fax: 949-263-1338

Fax: 86-755-8295-1393

Phoenix

China - Shunde

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7966

Fax: 480-792-4338

Room 401, Hongjian Building

No. 2 Fengxiangnan Road, Ronggui Town

Shunde City, Guangdong 528303, China

Tel: 86-765-8395507 Fax: 86-765-8395571

Italy

Via Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

China - Qingdao

San Jose

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-436-7950

Rm. B505A, Fullhope Plaza,

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Fax: 408-436-7955

Tel: 86-532-5027355 Fax: 86-532-5027205

P. A. De Biesbosch 14

NL-5152 SC Drunen, Netherlands

Tel: 31-416-690399

India

Toronto

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

6285 Northam Drive, Suite 108

Mississauga, Ontario L4V 1X5, Canada

Tel: 905-673-0699

Fax: 31-416-690340

United Kingdom

505 Eskdale Road

Fax: 905-673-6509

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

07/28/03

DS21836A-page 28

Preliminary

 2003 Microchip Technology Inc.

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	DFN
包装说明：	HVSON, SOLCC8,.25	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.54
最大时钟频率 (fCLK)：	20 MHz	耐久性：	100000 Write/Erase Cycles
JESD-30 代码：	R-PDSO-N8	JESD-609代码：	e3
长度：	5.99 mm	内存密度：	1048576 bit
内存集成电路类型：	FLASH	内存宽度：	8
湿度敏感等级：	1	功能数量：	1
端子数量：	8	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVSON	封装等效代码：	SOLCC8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	260
电源：	2/5 V	编程电压：	1.8 V
认证状态：	Not Qualified	座面最大高度：	1 mm
串行总线类型：	SPI	最大待机电流：	0.000001 A
子类别：	Flash Memories	最大压摆率：	0.01 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	1.8 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	类型：	NOR TYPE
宽度：	4.92 mm	最长写入周期时间 (tWC)：	5 ms
写保护：	HARDWARE/SOFTWARE	Base Number Matches：	1

型号	制造商	描述	价格	文档
25AA1024-I/P	MICROCHIP	1 Mbit SPI Bus Serial EEPROM	获取价格
25AA1024-I/PG	MICROCHIP	128K X 8 SPI BUS SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, DIP-8	获取价格
25AA1024-I/S16K	MICROCHIP	1024k, 128K X 8 , 1.8V SER EE, DIE in WAFFLE PK, -40C to +85C, Die-Waffle, WPAC	获取价格
25AA1024-I/SM	MICROCHIP	1 Mbit SPI Bus Serial EEPROM	获取价格
25AA1024-I/SM16KVAO	MICROCHIP	EEPROM, 1MX1, Serial, CMOS, PDSO8	获取价格
25AA1024-I/W16K	MICROCHIP	1024k, 128K X 8 , 1.8V SER EE, WAFER, -40C to +85C, Uncut Wafer, WJAR	获取价格
25AA1024I/MF	MICROCHIP	1M X 8 SPI BUS SERIAL EEPROM, PDSO8, 6 X 5 MM, ROHS COMPLIANT, PLASTIC, DFN-8	获取价格
25AA1024I/P	MICROCHIP	1M X 8 SPI BUS SERIAL EEPROM, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8	获取价格
25AA1024I/SM	MICROCHIP	1M X 8 SPI BUS SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, DSM-8	获取价格
25AA1024T-E/MF	MICROCHIP	1 Mbit SPI Bus Serial EEPROM	获取价格

25AA1024-I/MFG

25AA1024-I/MFG 概述

25AA1024-I/MFG 规格参数

25AA1024-I/MFG 数据手册

25AA1024-I/MFG 相关器件

25AA1024-I/MFG 相关文章

热门型号