25LC1024-I/SMG

更新时间:2024-12-04 13:02:59
品牌:MICROCHIP
描述:128K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.208 INCH, PLASTIC, SOIC-8

25LC1024-I/SMG 概述

128K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.208 INCH, PLASTIC, SOIC-8 闪存

25LC1024-I/SMG 规格参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.3针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.5
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:586807Samacsys Pin Count:8
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:8 Lead SM SOIJSamacsys Released Date:2017-01-11 17:13:05
Is Samacsys:N最大时钟频率 (fCLK):20 MHz
耐久性:100000 Write/Erase CyclesJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:5.28 mm
内存密度:1048576 bit内存集成电路类型:FLASH
内存宽度:8湿度敏感等级:1
功能数量:1端子数量:8
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:3/5 V
编程电压:2.7 V认证状态:Not Qualified
座面最大高度:2.03 mm串行总线类型:SPI
最大待机电流:0.000001 A子类别:Flash Memories
最大压摆率:0.01 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
类型:NOR TYPE宽度:5.21 mm
最长写入周期时间 (tWC):5 ms写保护:HARDWARE/SOFTWARE
Base Number Matches:1

25LC1024-I/SMG 数据手册

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25LC1024  
1 Mbit SPI Bus Serial EEPROM  
Device Selection Table  
Part Number  
VCC Range  
Page Size  
Temp. Ranges  
Packages  
25LC1024  
2.5-5.5V  
256 Byte  
I,E  
P, SM, MF  
Features:  
Description:  
• 20 MHz max. Clock Speed  
• Byte and Page-level Write Operations:  
- 256 byte page  
The Microchip Technology Inc. 25LC1024 is a 1024  
Kbit serial EEPROM memory with byte-level and page-  
level serial EEPROM functions. It also features Page,  
Sector and Chip erase functions typically associated  
with Flash-based products. These functions are not  
required for byte or page write operations. The memory  
is accessed via a simple Serial Peripheral Interface  
(SPI) compatible serial bus. The bus signals required  
are a clock input (SCK) plus separate data in (SI) and  
data out (SO) lines. Access to the device is controlled  
by a Chip Select (CS) input.  
- 6 ms max. write cycle time  
- No page or sector erase required  
• Low-Power CMOS Technology:  
- Max. Write current: 5 mA at 5.5V, 20 MHz  
- Read current: 7 mA at 5.5V, 20 MHz  
- Standby current: 1A at 2.5V  
(Deep power-down)  
• Electronic Signature for Device ID  
• Self-Timed Erase and Write Cycles:  
- Page Erase (6 ms max.)  
Communication to the device can be paused via the  
hold pin (HOLD). While the device is paused, transi-  
tions on its inputs will be ignored, with the exception of  
Chip Select, allowing the host to service higher priority  
interrupts.  
- Sector Erase (10 ms max.)  
- Chip Erase (10 ms max.)  
• Sector Write Protection (32K byte/sector):  
- Protect none, 1/4, 1/2 or all of array  
The 25LC1024 is available in standard packages  
including 8-lead PDIP and SOIJ, and advanced 8-lead  
DFN package. All devices are Pb-free.  
• Built-In Write Protection:  
- Power-on/off data protection circuitry  
- Write enable latch  
- Write-protect pin  
• High Reliability:  
Package Types (not to scale)  
- Endurance: 1M erase/write cycles  
DFN  
PDIP/SOIJ  
(P, SM)  
- Data Retention: >200 years  
- ESD Protection: >4000V  
(MF)  
1
2
3
4
CS  
SO  
8
7
6
5
VCC  
HOLD  
SCK  
SI  
CS  
SO  
WP  
VCC  
1
2
3
4
8
7
6
5
Temperature Ranges Supported:  
HOLD  
SCK  
SI  
- Industrial (I):  
- Automotive (E):  
-40C to +85C  
-40°C to +125°C  
WP  
VSS  
VSS  
• Pb-Free and RoHS Compliant  
2010 Microchip Technology Inc.  
DS22064D-page 1  
25LC1024  
1.0  
ELECTRICAL CHARACTERISTICS  
(†)  
Absolute Maximum Ratings  
VCC.............................................................................................................................................................................6.5V  
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V  
Storage temperature .................................................................................................................................-65°C to 150°C  
Ambient temperature under bias...............................................................................................................-40°C to 125°C  
ESD protection on all pins..........................................................................................................................................4 kV  
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at those or any other conditions above those  
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an  
extended period of time may affect device reliability.  
TABLE 1-1:  
DC CHARACTERISTICS  
Industrial (I):  
Automotive (E):  
TA = -40°C to +85°C  
TA = -40°C to +125°C  
VCC = 2.5V to 5.5V  
VCC = 2.5V to 5.5V  
DC CHARACTERISTICS  
Param.  
No.  
Sym.  
Characteristic  
Min.  
Max.  
VCC +1  
Units  
Test Conditions  
D001  
VIH1  
High-level input  
voltage  
.7 VCC  
V
D002  
D003  
D004  
VIL1  
VIL2  
VOL  
Low-level input  
voltage  
-0.3  
-0.3  
0.3 VCC  
0.2 VCC  
0.4  
V
V
V
VCC2.7V  
VCC < 2.7V  
Low-level output  
voltage  
IOL = 2.1 mA  
D005  
VOH  
High-level output  
voltage  
VCC -0.2  
V
IOH = -400 A  
D006  
D007  
ILI  
Input leakage current  
±1  
±1  
A  
A  
CS = VCC, VIN = VSS or VCC  
CS = VCC, VOUT = VSS or VCC  
ILO  
Output leakage  
current  
D008  
D009  
CINT  
Internal capacitance  
(all inputs and  
outputs)  
7
pF  
TA = 25°C, CLK = 1.0 MHz,  
VCC = 5.0V (Note)  
ICC Read  
10  
5
mA  
mA  
VCC = 5.5V; FCLK = 20.0 MHz;  
SO = Open  
VCC = 2.5V; FCLK = 10.0 MHz;  
SO = Open  
Operating current  
D010  
D011  
ICC Write  
ICCS  
7
5
mA  
mA  
VCC = 5.5V  
VCC = 2.5V  
20  
A  
CS = VCC = 5.5V, Inputs tied to VCC or  
VSS, 125°C  
Standby current  
12  
A  
CS = VCC = 5.5V, Inputs tied to VCC or  
VSS, 85°C  
D012  
ICCSPD  
Deep power-down  
current  
1
2
A  
A  
CS = VCC = 2.5V, Inputs tied to VCC or  
VSS, 85°C  
CS = VCC = 2.5V, Inputs tied to VCC or  
VSS, 125°C  
Note:  
This parameter is periodically sampled and not 100% tested.  
DS22064D-page 2  
2010 Microchip Technology Inc.  
25LC1024  
TABLE 1-2:  
AC CHARACTERISTICS  
Industrial (I):  
Automotive (E):  
TA = -40°C to +85°C  
TA = -40°C to +125°C  
VCC = 2.5V to 5.5V  
VCC = 2.5V to 5.5V  
AC CHARACTERISTICS  
Param.  
Sym.  
No.  
Characteristic  
Clock frequency  
Min.  
Max.  
Units  
Conditions  
1
2
3
FCLK  
TCSS  
TCSH  
20  
10  
MHz 4.5V VCC 5.5V (I)  
MHz 2.5V VCC 5.5V (I, E)  
CS setup time  
CS hold time  
25  
50  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
50  
100  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
4
5
TCSD  
Tsu  
CS disable time  
Data setup time  
50  
ns  
5
10  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
6
THD  
Data hold time  
10  
20  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
7
8
9
TR  
TF  
CLK rise time  
CLK fall time  
Clock high time  
20  
20  
ns  
ns  
(Note 1)  
(Note 1)  
THI  
25  
50  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
10  
TLO  
Clock low time  
25  
50  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
11  
12  
13  
TCLD  
TCLE  
TV  
Clock delay time  
50  
50  
ns  
ns  
Clock enable time  
Output valid from clock low  
25  
50  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
14  
15  
THO  
TDIS  
Output hold time  
0
ns  
(Note 1)  
Output disable time  
25  
50  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
16  
17  
18  
THS  
THH  
THZ  
HOLD setup time  
HOLD hold time  
10  
20  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
10  
20  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
HOLD low to output  
High-Z  
15  
30  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
(Note 1)  
19  
THV  
HOLD high to output valid  
15  
30  
ns  
ns  
4.5V VCC 5.5V (I)  
2.5V VCC 5.5V (I, E)  
20  
21  
TREL  
TPD  
CS High to Standby mode  
100  
100  
s  
s  
CS High to Deep power-  
down  
22  
23  
24  
TCE  
TSE  
TWC  
Chip erase cycle time  
Sector erase cycle time  
Internal write cycle time  
10  
10  
6
ms  
ms  
ms  
Byte or Page mode and Page  
Erase  
Note 1: This parameter is periodically sampled and not 100% tested.  
2: This parameter is not tested but established by characterization and qualification. For endurance  
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained  
from Microchip’s web site at www.microchip.com.  
2010 Microchip Technology Inc.  
DS22064D-page 3  
25LC1024  
TABLE 1-2:  
AC CHARACTERISTICS (CONTINUED)  
Industrial (I):  
Automotive (E):  
TA = -40°C to +85°C  
TA = -40°C to +125°C  
VCC = 2.5V to 5.5V  
VCC = 2.5V to 5.5V  
AC CHARACTERISTICS  
Param.  
Sym.  
No.  
Characteristic  
Endurance  
Min.  
Max.  
Units  
Conditions  
25  
1M  
E/W Page mode, 25°C, 5.5V (Note 2)  
Cycles  
Note 1: This parameter is periodically sampled and not 100% tested.  
2: This parameter is not tested but established by characterization and qualification. For endurance  
estimates in a specific application, please consult the Total Endurance™ Model which can be obtained  
from Microchip’s web site at www.microchip.com.  
TABLE 1-3:  
AC TEST CONDITIONS  
AC Waveform:  
VLO = 0.2V  
VHI = VCC - 0.2V  
(Note 1)  
(Note 2)  
VHI = 4.0V  
CL = 30 pF  
Timing Measurement Reference Level  
Input  
0.5 VCC  
0.5 VCC  
Output  
Note 1: For VCC 4.0V  
2: For VCC > 4.0V  
DS22064D-page 4  
2010 Microchip Technology Inc.  
25LC1024  
FIGURE 1-1: HOLD TIMING  
CS  
17  
17  
16  
16  
SCK  
18  
19  
High-Impedance  
Don’t Care  
n
SO  
n + 2  
n + 2  
n + 1  
n
n - 1  
5
n
n + 1  
n
n - 1  
SI  
HOLD  
FIGURE 1-2: SERIAL INPUT TIMING  
4
CS  
12  
11  
2
7
3
8
Mode 1,1  
Mode 0,0  
SCK  
SI  
5
6
MSB in  
LSB in  
High-Impedance  
SO  
FIGURE 1-3: SERIAL OUTPUT TIMING  
CS  
3
9
10  
Mode 1,1  
SCK  
Mode 0,0  
13  
15  
14  
MSB out  
LSB out  
SO  
SI  
Don’t Care  
2010 Microchip Technology Inc.  
DS22064D-page 5  
25LC1024  
2.0  
2.1  
FUNCTIONAL DESCRIPTION  
BLOCK DIAGRAM  
STATUS  
Register  
HV Generator  
Principles of Operation  
The 25LC1024 is a 131,072 byte Serial EEPROM  
designed to interface directly with the Serial Peripheral  
Interface (SPI) port of many of today’s popular  
microcontroller families, including Microchip’s PIC®  
microcontrollers. It may also interface with microcon-  
trollers that do not have a built-in SPI port by using  
discrete I/O lines programmed properly in firmware to  
match the SPI protocol.  
EEPROM  
Array  
Memory  
Control  
Logic  
X
I/O Control  
Logic  
Dec  
Page Latches  
Y Decoder  
The 25LC1024 contains an 8-bit instruction register.  
The device is accessed via the SI pin, with data being  
clocked in on the rising edge of SCK. The CS pin must  
be low and the HOLD pin must be high for the entire  
operation.  
SI  
SO  
CS  
SCK  
Table 2-1 contains a list of the possible instruction  
bytes and format for device operation. All instructions,  
addresses and data are transferred MSB first, LSB last.  
Sense Amp.  
R/W Control  
HOLD  
WP  
VCC  
VSS  
Data (SI) is sampled on the first rising edge of SCK  
after CS goes low. If the clock line is shared with other  
peripheral devices on the SPI bus, the user can assert  
the HOLD input and place the 25LC1024 in ‘HOLD’  
mode. After releasing the HOLD pin, operation will  
resume from the point when the HOLD was asserted.  
TABLE 2-1:  
INSTRUCTION SET  
Instruction Name  
Instruction Format  
Description  
READ  
WRITE  
WREN  
WRDI  
RDSR  
WRSR  
PE  
0000 0011  
0000 0010  
0000 0110  
0000 0100  
0000 0101  
0000 0001  
0100 0010  
1101 1000  
1100 0111  
1010 1011  
1011 1001  
Read data from memory array beginning at selected address  
Write data to memory array beginning at selected address  
Set the write enable latch (enable write operations)  
Reset the write enable latch (disable write operations)  
Read STATUS register  
Write STATUS register  
Page Erase – erase one page in memory array  
Sector Erase – erase one sector in memory array  
Chip Erase – erase all sectors in memory array  
Release from Deep power-down and read electronic signature  
Deep Power-Down mode  
SE  
CE  
RDID  
DPD  
DS22064D-page 6  
2010 Microchip Technology Inc.  
25LC1024  
The data stored in the memory at the next address can  
be read sequentially by continuing to provide clock  
pulses. The internal Address Pointer is automatically  
incremented to the next higher address after each byte  
of data is shifted out. When the highest address is  
reached (1FFFFh), the address counter rolls over to  
address, 00000h, allowing the read cycle to be contin-  
ued indefinitely. The read operation is terminated by  
raising the CS pin (Figure 2-1).  
Read Sequence  
The device is selected by pulling CS low. The 8-bit  
READ instruction is transmitted to the 25LC1024  
followed by the 24-bit address, with seven MSBs of the  
address being “don’t care” bits. After the correct READ  
instruction and address are sent, the data stored in the  
memory at the selected address is shifted out on the  
SO pin.  
FIGURE 2-1:  
READ SEQUENCE  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
Instruction  
24-bit Address  
23 22 21 20  
0
0
0
0
0
0
1
1
2
1
0
SI  
Data Out  
High-Impedance  
7
6
5
4
3
2
1
0
SO  
2010 Microchip Technology Inc.  
DS22064D-page 7  
25LC1024  
2.2  
Write Sequence  
Note:  
Page write operations are limited to writing  
bytes within a single physical page,  
regardless of the number of bytes  
actually being written. Physical page  
boundaries start at addresses that are  
integer multiples of the page buffer size (or  
‘page size’), and end at addresses that are  
integer multiples of page size – 1. If a  
Page Write command attempts to write  
across a physical page boundary, the  
result is that the data wraps around to the  
beginning of the current page (overwriting  
data previously stored there), instead of  
being written to the next page as might be  
expected. It is therefore necessary for the  
application software to prevent page write  
operations that would attempt to cross a  
page boundary.  
Prior to any attempt to write data to the 25LC1024, the  
write enable latch must be set by issuing the WREN  
instruction (Figure 2-4). This is done by setting CS low  
and then clocking out the proper instruction into the  
25LC1024. After all eight bits of the instruction are  
transmitted, the CS must be brought high to set the  
write enable latch. If the write operation is initiated  
immediately after the WREN instruction without CS  
being brought high, the data will not be written to the  
array because the write enable latch will not have been  
properly set.  
A write sequence includes an automatic, self timed  
erase cycle. It is not required to erase any portion of the  
memory prior to issuing a Write command.  
Once the write enable latch is set, the user may  
proceed by setting the CS low, issuing a WRITEinstruc-  
tion, followed by the 24-bit address, with seven MSBs  
of the address being “don’t care” bits, and then the data  
to be written. Up to 256 bytes of data can be sent to the  
device before a write cycle is necessary. The only  
restriction is that all of the bytes must reside in the  
same page.  
For the data to be actually written to the array, the CS  
must be brought high after the Least Significant bit (D0)  
of the nth data byte has been clocked in. If CS is  
brought high at any other time, the write operation will  
not be completed. Refer to Figure 2-2 and Figure 2-3  
for more detailed illustrations on the byte write  
sequence and the page write sequence, respectively.  
While the write is in progress, the STATUS register may  
be read to check the status of the WPEN, WIP, WEL,  
BP1 and BP0 bits (Figure 2-6). A read attempt of a  
memory array location will not be possible during a  
write cycle. When the write cycle is completed, the  
write enable latch is reset.  
Note:  
When doing a write of less than 256 bytes  
the data in the rest of the page is refreshed  
along with the data bytes being written.  
This will force the entire page to endure a  
write cycle, for this reason endurance is  
specified per page.  
FIGURE 2-2:  
BYTE WRITE SEQUENCE  
CS  
Twc  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
SI  
Instruction  
24-bit Address  
23 22 21 20  
Data Byte  
0
0
0
0
0
0
1
0
2
1
0
7
6
5
4
3
2
1
0
High-Impedance  
SO  
DS22064D-page 8  
2010 Microchip Technology Inc.  
25LC1024  
FIGURE 2-3:  
PAGE WRITE SEQUENCE  
CS  
0
1
2
3
4
5
6
7
8
9
10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
Instruction  
24-bit Address  
Data Byte 1  
0
0
0
0
0
0
1
0 23 22 21 20  
2
1
0
7
6
5
4
3
2
1
0
SI  
CS  
40 41 42 43 44 45 46 47  
Data Byte 2  
49 50 51 52 53 54 55  
Data Byte 3  
48  
7
SCK  
SI  
Data Byte n (256 max)  
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2010 Microchip Technology Inc.  
DS22064D-page 9  
25LC1024  
The following is a list of conditions under which the  
write enable latch will be reset:  
2.3  
Write Enable (WREN) and Write  
Disable (WRDI)  
• Power-up  
The 25LC1024 contains a write enable latch. See  
Table 2-4 for the Write-Protect Functionality Matrix.  
This latch must be set before any write operation will be  
completed internally. The WRENinstruction will set the  
latch, and the WRDIwill reset the latch.  
WRDIinstruction successfully executed  
WRSRinstruction successfully executed  
WRITEinstruction successfully executed  
PEinstruction successfully executed  
SEinstruction successfully executed  
CEinstruction successfully executed  
FIGURE 2-4:  
WRITE ENABLE SEQUENCE (WREN)  
CS  
SCK  
SI  
0
1
2
3
4
5
6
7
0
0
0
0
0
1
1
0
High-Impedance  
SO  
FIGURE 2-5:  
WRITE DISABLE SEQUENCE (WRDI)  
CS  
0
1
2
3
4
5
6
7
SCK  
0
0
0
0
0
0
1
0
SI  
High-Impedance  
SO  
DS22064D-page 10  
2010 Microchip Technology Inc.  
25LC1024  
The Write Enable Latch (WEL) bit indicates the status  
of the write enable latch and is read-only. When set to  
a ‘1’, the latch allows writes to the array, when set to a  
0’, the latch prohibits writes to the array. The state of  
this bit can always be updated via the WREN or WRDI  
commands regardless of the state of write protection  
on the STATUS register. These commands are shown  
in Figure 2-4 and Figure 2-5.  
2.4  
Read Status Register Instruction  
(RDSR)  
The Read Status Register instruction (RDSR) provides  
access to the STATUS register. The STATUS register  
may be read at any time, even during a write cycle. The  
STATUS register is formatted as follows:  
TABLE 2-2:  
STATUS REGISTER  
The Block Protection (BP0 and BP1) bits indicate  
which blocks are currently write-protected. These bits  
are set by the user issuing the WRSRinstruction. These  
bits are nonvolatile and are shown in Table 2-3.  
7
6
X
5
X
4
X
3
2
1
0
W/R  
W/R W/R  
R
R
WPEN  
BP1 BP0 WEL WIP  
See Figure 2-6 for the RDSRtiming sequence.  
W/R = writable/readable. R = read-only.  
The Write-In-Process (WIP) bit indicates whether the  
25LC1024 is busy with a write operation. When set to  
a ‘1’, a write is in progress, when set to a ‘0’, no write  
is in progress. This bit is read-only.  
FIGURE 2-6:  
READ STATUS REGISTER TIMING SEQUENCE (RDSR)  
CS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
SCK  
SI  
Instruction  
0
0
0
0
0
1
0
1
Data from STATUS register  
High-Impedance  
7
6
5
4
3
2
1
0
SO  
2010 Microchip Technology Inc.  
DS22064D-page 11  
25LC1024  
The Write-Protect Enable (WPEN) bit is a nonvolatile  
bit that is available as an enable bit for the WP pin. The  
Write-Protect (WP) pin and the Write-Protect Enable  
(WPEN) bit in the STATUS register control the  
programmable hardware write-protect feature. Hard-  
ware write protection is enabled when WP pin is low  
and the WPEN bit is high. Hardware write protection is  
disabled when either the WP pin is high or the WPEN  
bit is low. When the chip is hardware write-protected,  
only writes to nonvolatile bits in the STATUS register  
are disabled. See Table 2-4 for a matrix of functionality  
on the WPEN bit.  
2.5  
Write Status Register Instruction  
(WRSR)  
The Write Status Register instruction (WRSR) allows the  
user to write to the nonvolatile bits in the STATUS  
register as shown in Table 2-2. The user is able to  
select one of four levels of protection for the array by  
writing to the appropriate bits in the STATUS register.  
The array is divided up into four segments. The user  
has the ability to write-protect none, one, two, or all four  
of the segments of the array. The partitioning is  
controlled as shown in Table 2-3.  
See Figure 2-7 for the WRSR timing sequence.  
TABLE 2-3:  
ARRAY PROTECTION  
Array Addresses  
Write-Protected  
Array Addresses  
Unprotected  
BP1  
BP0  
none  
All (Sectors 0, 1, 2 & 3)  
(00000h-1FFFFh)  
0
0
Upper 1/4 (Sector 3)  
(18000h-1FFFFh)  
Lower 3/4 (Sectors 0, 1 & 2)  
(00000h-17FFFh)  
0
1
1
1
Upper 1/2 (Sectors 2 & 3)  
(10000h-1FFFFh)  
Lower 1/2 (Sectors 0 & 1)  
(00000h-0FFFFh)  
0
1
All (Sectors 0, 1, 2 & 3)  
(00000h-1FFFFh)  
none  
FIGURE 2-7:  
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)  
CS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
1
15  
0
SCK  
SI  
Instruction  
Data to STATUS register  
7
6
5
4
3
2
0
0
0
0
0
0
0
1
High-Impedance  
SO  
DS22064D-page 12  
2010 Microchip Technology Inc.  
25LC1024  
2.6  
Data Protection  
2.7  
Power-On State  
The following protection has been implemented to  
prevent inadvertent writes to the array:  
The 25LC1024 powers on in the following state:  
• The device is in low-power Standby mode  
(CS= 1)  
• The write enable latch is reset  
• SO is in high-impedance state  
• A high-to-low-level transition on CS is required to  
enter active state  
• The write enable latch is reset on power-up  
• A write enable instruction must be issued to set  
the write enable latch  
• After a byte write, page write or STATUS register  
write, the write enable latch is reset  
• CS must be set high after the proper number of  
clock cycles to start an internal write cycle  
• Access to the array during an internal write cycle  
is ignored and programming is continued  
TABLE 2-4:  
WRITE-PROTECT FUNCTIONALITY MATRIX  
WEL  
(SR bit 1)  
WPEN  
(SR bit 7)  
WP  
(pin 3)  
Protected Blocks  
Unprotected Blocks  
STATUS Register  
Protected  
Protected  
Protected  
Protected  
Protected  
Writable  
Writable  
Writable  
Protected  
Writable  
Protected  
Writable  
0
x
0
1
1
x
1
x
1
0 (low)  
1 (high)  
1
x = don’t care  
2010 Microchip Technology Inc.  
DS22064D-page 13  
25LC1024  
2.8  
PAGE ERASE  
The Page Erase function will erase all bits (FFh) inside  
the given page. A Write Enable (WREN) instruction  
must be given prior to attempting a Page Erase. This  
is done by setting CS low and then clocking out the  
proper instruction into the 25LC1024. After all eight  
bits of the instruction are transmitted, the CS must be  
brought high to set the write enable latch.  
CS must then be driven high after the last bit if the  
address or the Page Erase will not execute. Once the  
CS is driven high, the self-timed Page Erase cycle is  
started. The WIP bit in the STATUS register can be  
read to determine when the Page Erase cycle is  
complete.  
If a Page Erase function is given to an address that  
has been protected by the Block Protect bits (BP0,  
BP1) then the sequence will be aborted and no erase  
will occur.  
The Page Erase function is entered by driving CS low,  
followed by the instruction code (Figure 2-8), and  
three address bytes. Any address inside the page to  
be erased is a valid address.  
FIGURE 2-8:  
PAGE ERASE SEQUENCE  
CS  
SCK  
SI  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31  
Instruction  
24-bit Address  
23 22 21 20  
0
1
0
0
0
0
1
0
2
1
0
High-Impedance  
SO  
DS22064D-page 14  
2010 Microchip Technology Inc.  
25LC1024  
2.9  
SECTOR ERASE  
The Sector Erase function will erase all bits (FFh)  
inside the given sector. A Write Enable (WREN) instruc-  
tion must be given prior to attempting a Sector Erase.  
This is done by setting CS low and then clocking out  
the proper instruction into the 25LC1024. After all eight  
bits of the instruction are transmitted, the CS must be  
brought high to set the write enable latch.  
CS must then be driven high after the last bit if the  
address or the Sector Erase will not execute. Once the  
CS is driven high, the self-timed Sector Erase cycle is  
started. The WIP bit in the STATUS register can be  
read to determine when the Sector Erase cycle is  
complete.  
If a SECTOR ERASEinstruction is given to an address  
that has been protected by the Block Protect bits (BP0,  
BP1) then the sequence will be aborted and no erase  
will occur.  
The Sector Erase function is entered by driving CS  
low, followed by the instruction code (Figure 2-9), and  
three address bytes. Any address inside the sector to  
be erased is a valid address.  
See Table 2-3 for Sector Addressing.  
FIGURE 2-9:  
SECTOR ERASE SEQUENCE  
CS  
SCK  
SI  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31  
Instruction  
24-bit Address  
23 22 21 20  
1
1
0
1
1
0
0
0
2
1
0
High-Impedance  
SO  
2010 Microchip Technology Inc.  
DS22064D-page 15  
25LC1024  
2.10 CHIP ERASE  
The Chip Erase function will erase all bits (FFh) in the  
array. A Write Enable (WREN) instruction must be given  
prior to executing a Chip Erase. This is done by setting  
CS low and then clocking out the proper instruction  
into the 25LC1024. After all eight bits of the instruction  
are transmitted, the CS must be brought high to set  
the write enable latch.  
The CS pin must be driven high after the eighth bit of  
the instruction code has been given or the Chip Erase  
function will not be executed. Once the CS pin is  
driven high, the self-timed Chip Erase function begins.  
While the device is executing the Chip Erase function  
the WIP bit in the STATUS register can be read to  
determine when the Chip Erase function is complete.  
The Chip Erase function is entered by driving the CS  
low, followed by the instruction code (Figure 2-10)  
onto the SI line.  
The Chip Erase function is ignored if either of the  
Block Protect bits (BP0, BP1) are not 0, meaning ¼,  
½, or all of the array is protected.  
FIGURE 2-10:  
CHIP ERASE SEQUENCE  
CS  
0
1
2
3
4
5
6
7
SCK  
1
1
0
0
0
1
1
1
SI  
High-Impedance  
SO  
DS22064D-page 16  
2010 Microchip Technology Inc.  
25LC1024  
2.11 DEEP POWER-DOWN MODE  
Deep Power-Down mode of the 25LC1024 is its lowest  
power consumption state. The device will not respond  
to any of the Read or Write commands while in Deep  
Power-Down mode, and therefore it can be used as an  
additional software write protection feature.  
All instructions given during Deep Power-Down mode  
are ignored except the Read Electronic Signature  
Command (RDID). The RDID command will release  
the device from Deep power-down and outputs the  
electronic signature on the SO pin, and then returns  
the device to Standby mode after delay (TREL  
)
The Deep Power-Down mode is entered by driving CS  
low, followed by the instruction code (Figure 2-11) onto  
the SI line, followed by driving CS high.  
Deep Power-Down mode automatically releases at  
device power-down. Once power is restored to the  
device, it will power-up in the Standby mode.  
If the CS pin is not driven high after the eighth bit of the  
instruction code has been given, the device will not  
execute Deep power-down. Once the CS line is driven  
high, there is a delay (TDP) before the current settles  
to its lowest consumption.  
FIGURE 2-11:  
DEEP POWER-DOWN SEQUENCE  
CS  
0
1
2
3
4
5
6
7
SCK  
1
0
1
1
1
0
0
1
SI  
High-Impedance  
SO  
2010 Microchip Technology Inc.  
DS22064D-page 17  
25LC1024  
Release from Deep Power-Down mode and Read  
Electronic Signature is entered by driving CS low,  
followed by the RDID instruction code (Figure 2-12)  
and then a dummy address of 24 bits (A23-A0). After  
the last bit of the dummy address is clocked in, the  
8-bit Electronic signature is clocked out on the SO  
pin.  
2.12 RELEASE FROM DEEP  
POWER-DOWN AND READ  
ELECTRONIC SIGNATURE  
Once the device has entered Deep Power-Down  
mode all instructions are ignored except the release  
from Deep Power-down and Read Electronic Signa-  
ture command. This command can also be used when  
the device is not in Deep Power-down, to read the  
electronic signature out on the SO pin unless another  
command is being executed such as Erase, Program  
or Write STATUS register.  
After the signature has been read out at least once,  
the sequence can be terminated by driving CS high.  
The device will then return to Standby mode and will  
wait to be selected so it can be given new instructions.  
If additional clock cycles are sent after the electronic  
signature has been read once, it will continue to output  
the signature on the SO line until the sequence is  
terminated.  
FIGURE 2-12:  
RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE  
CS  
0
1
2
3
4
5
6
7
8
9 10 11  
29 30 31 32 33 34 35 36 37 38 39  
SCK  
Instruction  
24-bit Address  
23 22 21 20  
1
0
1
0
1
0
1
1
2
1
0
SI  
Electronic Signature Out  
High-Impedance  
7
6
5
4
3
2
1
0
SO  
0
0
1
0
1
0
0
1
Manufacturers ID 0x29  
Driving CS high after the 8-bit RDID command, but before the Electronic Signature has been transmitted, will still  
ensure the device will be taken out of Deep Power-Down mode. However, there is a delay TREL that occurs before the  
device returns to Standby mode (ICCS), as shown in Figure 2-13.  
FIGURE 2-13:  
RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE  
CS  
TREL  
0
1
2
3
4
5
6
7
SCK  
SI  
Instruction  
1
0
1
0
1
0
1
1
High-Impedance  
SO  
DS22064D-page 18  
2010 Microchip Technology Inc.  
25LC1024  
The WP pin function is blocked when the WPEN bit in  
the STATUS register is low. This allows the user to  
install the 25LC1024 in a system with WP pin grounded  
and still be able to write to the STATUS register. The  
WP pin functions will be enabled when the WPEN bit is  
set high.  
3.0  
PIN DESCRIPTIONS  
The descriptions of the pins are listed in Table 3-1.  
TABLE 3-1:  
Name  
PIN FUNCTION TABLE  
Pin Number  
Function  
3.4  
Serial Input (SI)  
CS  
SO  
1
2
3
4
5
6
7
8
Chip Select Input  
Serial Data Output  
Write-Protect Pin  
Ground  
The SI pin is used to transfer data into the device. It  
receives instructions, addresses and data. Data is  
latched on the rising edge of the serial clock.  
WP  
VSS  
SI  
3.5  
Serial Clock (SCK)  
Serial Data Input  
Serial Clock Input  
Hold Input  
The SCK is used to synchronize the communication  
between a master and the 25LC1024. Instructions,  
addresses or data present on the SI pin are latched on  
the rising edge of the clock input, while data on the SO  
pin is updated after the falling edge of the clock input.  
SCK  
HOLD  
VCC  
Supply Voltage  
3.1  
Chip Select (CS)  
3.6  
Hold (HOLD)  
A low level on this pin selects the device. A high level  
deselects the device and forces it into Standby mode.  
However, a programming cycle which is already  
initiated or in progress will be completed, regardless of  
the CS input signal. If CS is brought high during a  
program cycle, the device will go into Standby mode as  
soon as the programming cycle is complete. When the  
device is deselected, SO goes to the high-impedance  
state, allowing multiple parts to share the same SPI  
bus. A low-to-high transition on CS after a valid write  
sequence initiates an internal write cycle. After power-  
up, a low level on CS is required prior to any sequence  
being initiated.  
The HOLD pin is used to suspend transmission to the  
25LC1024 while in the middle of a serial sequence  
without having to retransmit the entire sequence again.  
It must be held high any time this function is not being  
used. Once the device is selected and a serial  
sequence is underway, the HOLD pin may be pulled  
low to pause further serial communication without  
resetting the serial sequence. The HOLD pin must be  
brought low while SCK is low, otherwise the HOLD  
function will not be invoked until the next SCK high-to-  
low transition. The 25LC1024 must remain selected  
during this sequence. The SI, SCK and SO pins are in  
a high-impedance state during the time the device is  
paused and transitions on these pins will be ignored. To  
resume serial communication, HOLD must be brought  
high while the SCK pin is low, otherwise serial  
communication will not resume. Pulling the HOLD line  
low at any time will tri-state the SO line.  
3.2  
Serial Output (SO)  
The SO pin is used to transfer data out of the  
25LC1024. During a read cycle, data is shifted out on  
this pin after the falling edge of the serial clock.  
3.3  
Write-Protect (WP)  
This pin is used in conjunction with the WPEN bit in the  
STATUS register to prohibit writes to the nonvolatile  
bits in the STATUS register. When WP is low and  
WPEN is high, writing to the nonvolatile bits in the  
STATUS register is disabled. All other operations  
function normally. When WP is high, all functions,  
including writes to the nonvolatile bits in the STATUS  
register, operate normally. If the WPEN bit is set, WP  
low during a STATUS register write sequence will  
disable writing to the STATUS register. If an internal  
write cycle has already begun, WP going low will have  
no effect on the write.  
2010 Microchip Technology Inc.  
DS22064D-page 19  
25LC1024  
4.0  
4.1  
PACKAGING INFORMATION  
Package Marking Information  
8-Lead DFN  
Example:  
XXXXXXX  
T/XXXXX  
YYWW  
5LC1024  
e
3
I/MF  
0328  
NNN  
1L7  
Example:  
25LC1024  
8-Lead PDIP  
XXXXXXXX  
T/XXXNNN  
I/P  
1L7  
e
3
0328  
YYWW  
Example:  
8-Lead SOIJ  
25LC1024  
I/SM  
XXXXXXXX  
T/XXXXXX  
YYWWNNN  
e
3
07281L7  
Legend: XX...X Part number or part number code  
T
Temperature (I, E)  
Y
Year code (last digit of calendar year)  
YY  
WW  
NNN  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code (2 characters for small packages)  
Pb-free JEDEC designator for Matte Tin (Sn)  
e
3
Note:  
For very small packages with no room for the Pb-free JEDEC designator  
, the marking will only appear on the outer carton or reel label.  
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
DS22064D-page 20  
2010 Microchip Technology Inc.  
25LC1024  
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ꢎꢂ ꢃꢆꢌ+ꢆꢏꢈꢀ'ꢆꢊꢀꢍꢆ ꢈꢀꢋꢅꢈꢀꢋꢉꢀ'ꢋꢉꢈꢀꢈ$ꢐꢋ!ꢈ#ꢀ&ꢄꢈꢀ)ꢆꢉ!ꢀꢆ&ꢀꢈꢅ#!ꢂ  
,ꢂ ꢃꢆꢌ+ꢆꢏꢈꢀꢄ!ꢀ!ꢆ*ꢀ!ꢄꢅꢏ"ꢇꢆ&ꢈ#ꢂ  
ꢑꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢏꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢏꢀꢐꢈꢉꢀꢓꢔꢕ-ꢀ.ꢁꢑꢂ/ꢕꢂ  
0ꢔ12 0ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢖꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ  
ꢗ-32 ꢗꢈ%ꢈꢉꢈꢅꢌꢈꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅ(ꢀ"!"ꢆꢇꢇꢊꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ(ꢀ%ꢋꢉꢀꢄꢅ%ꢋꢉ'ꢆ&ꢄꢋꢅꢀꢐ"ꢉꢐꢋ!ꢈ!ꢀꢋꢅꢇꢊꢂ  
ꢕꢄꢌꢉꢋꢌꢍꢄꢐ ꢌꢍꢅꢋꢇꢋꢏꢊ ꢒꢉꢆ*ꢄꢅꢏ 1ꢚꢑꢝꢁꢎꢎ0  
2010 Microchip Technology Inc.  
DS22064D-page 21  
25LC1024  
ꢑꢒꢊꢃ$ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢐꢆꢌ+ꢆꢏꢈꢀ#ꢉꢆ*ꢄꢅꢏ!(ꢀꢐꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢕꢄꢌꢉꢋꢌꢍꢄꢐꢀꢃꢆꢌ+ꢆꢏꢄꢅꢏꢀꢔꢐꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ  
ꢍ&&ꢐ244***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢐꢂꢌꢋ'4ꢐꢆꢌ+ꢆꢏꢄꢅꢏ  
DS22064D-page 22  
2010 Microchip Technology Inc.  
25LC1024  
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ%&ꢁꢂꢋ&ꢃꢆꢕꢇꢗꢆMꢆ'((ꢆꢛꢋꢈꢆꢜꢒꢅ ꢆ!ꢇꢍ%ꢇ#  
ꢑꢒꢊꢃ$ 3ꢋꢉꢀ&ꢍꢈꢀ'ꢋ!&ꢀꢌ"ꢉꢉꢈꢅ&ꢀꢐꢆꢌ+ꢆꢏꢈꢀ#ꢉꢆ*ꢄꢅꢏ!(ꢀꢐꢇꢈꢆ!ꢈꢀ!ꢈꢈꢀ&ꢍꢈꢀꢕꢄꢌꢉꢋꢌꢍꢄꢐꢀꢃꢆꢌ+ꢆꢏꢄꢅꢏꢀꢔꢐꢈꢌꢄ%ꢄꢌꢆ&ꢄꢋꢅꢀꢇꢋꢌꢆ&ꢈ#ꢀꢆ&ꢀ  
ꢍ&&ꢐ244***ꢂ'ꢄꢌꢉꢋꢌꢍꢄꢐꢂꢌꢋ'4ꢐꢆꢌ+ꢆꢏꢄꢅꢏ  
N
NOTE 1  
E1  
3
1
2
D
E
A2  
A
L
A1  
c
e
eB  
b1  
b
5ꢅꢄ&!  
ꢘ71;-ꢔ  
ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢀ6ꢄ'ꢄ&!  
ꢕꢘ7  
78ꢕ  
:
ꢂꢁꢚꢚꢀ0ꢔ1  
M
ꢂꢁ,ꢚ  
M
ꢂ,ꢁꢚ  
ꢂꢎ/ꢚ  
ꢂ,ꢛ/  
ꢂꢁ,ꢚ  
ꢂꢚꢁꢚ  
ꢂꢚꢛꢚ  
ꢂꢚꢁ:  
M
ꢕꢓ9  
7"')ꢈꢉꢀꢋ%ꢀꢃꢄꢅ!  
ꢃꢄ&ꢌꢍ  
ꢐꢀ&ꢋꢀꢔꢈꢆ&ꢄꢅꢏꢀꢃꢇꢆꢅꢈ  
ꢕꢋꢇ#ꢈ#ꢀꢃꢆꢌ+ꢆꢏꢈꢀꢖꢍꢄꢌ+ꢅꢈ!!  
0ꢆ!ꢈꢀ&ꢋꢀꢔꢈꢆ&ꢄꢅꢏꢀꢃꢇꢆꢅꢈ  
ꢔꢍꢋ"ꢇ#ꢈꢉꢀ&ꢋꢀꢔꢍꢋ"ꢇ#ꢈꢉꢀ<ꢄ#&ꢍ  
ꢕꢋꢇ#ꢈ#ꢀꢃꢆꢌ+ꢆꢏꢈꢀ<ꢄ#&ꢍ  
8 ꢈꢉꢆꢇꢇꢀ6ꢈꢅꢏ&ꢍ  
7
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ꢓꢁ  
-
-ꢁ  
6
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ꢈ0  
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ꢂꢎꢁꢚ  
ꢂꢁꢜ/  
M
ꢂꢁꢁ/  
ꢂꢚꢁ/  
ꢂꢎꢜꢚ  
ꢂꢎꢑꢚ  
ꢂ,ꢑ:  
ꢂꢁꢁ/  
ꢂꢚꢚ:  
ꢂꢚꢑꢚ  
ꢂꢚꢁꢑ  
M
ꢂ,ꢎ/  
ꢂꢎ:ꢚ  
ꢂꢑꢚꢚ  
ꢂꢁ/ꢚ  
ꢂꢚꢁ/  
ꢂꢚꢙꢚ  
ꢂꢚꢎꢎ  
ꢂꢑ,ꢚ  
ꢖꢄꢐꢀ&ꢋꢀꢔꢈꢆ&ꢄꢅꢏꢀꢃꢇꢆꢅꢈ  
6ꢈꢆ#ꢀꢖꢍꢄꢌ+ꢅꢈ!!  
5ꢐꢐꢈꢉꢀ6ꢈꢆ#ꢀ<ꢄ#&ꢍ  
6ꢋ*ꢈꢉꢀ6ꢈꢆ#ꢀ<ꢄ#&ꢍ  
8 ꢈꢉꢆꢇꢇꢀꢗꢋ*ꢀꢔꢐꢆꢌꢄꢅꢏꢀꢀꢞ  
ꢑꢒꢊꢃꢉ$  
ꢁꢂ ꢃꢄꢅꢀꢁꢀ ꢄ!"ꢆꢇꢀꢄꢅ#ꢈ$ꢀ%ꢈꢆ&"ꢉꢈꢀ'ꢆꢊꢀ ꢆꢉꢊ(ꢀ)"&ꢀ'"!&ꢀ)ꢈꢀꢇꢋꢌꢆ&ꢈ#ꢀ*ꢄ&ꢍꢀ&ꢍꢈꢀꢍꢆ&ꢌꢍꢈ#ꢀꢆꢉꢈꢆꢂ  
ꢎꢂ ꢞꢀꢔꢄꢏꢅꢄ%ꢄꢌꢆꢅ&ꢀ1ꢍꢆꢉꢆꢌ&ꢈꢉꢄ!&ꢄꢌꢂ  
,ꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅ!ꢀꢒꢀꢆꢅ#ꢀ-ꢁꢀ#ꢋꢀꢅꢋ&ꢀꢄꢅꢌꢇ"#ꢈꢀ'ꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢐꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢂꢀꢕꢋꢇ#ꢀ%ꢇꢆ!ꢍꢀꢋꢉꢀꢐꢉꢋ&ꢉ"!ꢄꢋꢅ!ꢀ!ꢍꢆꢇꢇꢀꢅꢋ&ꢀꢈ$ꢌꢈꢈ#ꢀꢂꢚꢁꢚ@ꢀꢐꢈꢉꢀ!ꢄ#ꢈꢂ  
ꢑꢂ ꢒꢄ'ꢈꢅ!ꢄꢋꢅꢄꢅꢏꢀꢆꢅ#ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢄꢅꢏꢀꢐꢈꢉꢀꢓꢔꢕ-ꢀ.ꢁꢑꢂ/ꢕꢂ  
0ꢔ12ꢀ0ꢆ!ꢄꢌꢀꢒꢄ'ꢈꢅ!ꢄꢋꢅꢂꢀꢖꢍꢈꢋꢉꢈ&ꢄꢌꢆꢇꢇꢊꢀꢈ$ꢆꢌ&ꢀ ꢆꢇ"ꢈꢀ!ꢍꢋ*ꢅꢀ*ꢄ&ꢍꢋ"&ꢀ&ꢋꢇꢈꢉꢆꢅꢌꢈ!ꢂ  
ꢕꢄꢌꢉꢋꢌꢍꢄꢐ ꢌꢍꢅꢋꢇꢋꢏꢊ ꢒꢉꢆ*ꢄꢅꢏ 1ꢚꢑꢝꢚꢁ:0  
2010 Microchip Technology Inc.  
DS22064D-page 23  
25LC1024  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22064D-page 24  
2010 Microchip Technology Inc.  
25LC1024  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
2010 Microchip Technology Inc.  
DS22064D-page 25  
25LC1024  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
DS22064D-page 26  
2010 Microchip Technology Inc.  
25LC1024  
APPENDIX A:  
REVISION HISTORY  
Revision A (10/2007)  
Original release.  
Revision B (5/2008)  
Modified parameter D006 in Table 1-1; Revised  
Package Marking Information; Replaced Package  
Drawings.  
Revision C (10/08)  
Updated Package Drawings.  
Revision D (05/10)  
Revised Table 1-2, Param. No. 25 Conditions; Revised  
Section 2.2, added note; Updated SOIJ package  
drawings.  
2010 Microchip Technology Inc.  
DS22064D-page 27  
25LC1024  
NOTES:  
DS22064D-page 28  
2010 Microchip Technology Inc.  
25LC1024  
THE MICROCHIP WEB SITE  
CUSTOMER SUPPORT  
Microchip provides online support via our WWW site at  
www.microchip.com. This web site is used as a means  
to make files and information easily available to  
customers. Accessible by using your favorite Internet  
browser, the web site contains the following  
information:  
Users of Microchip products can receive assistance  
through several channels:  
• Distributor or Representative  
• Local Sales Office  
• Field Application Engineer (FAE)  
Technical Support  
Product Support – Data sheets and errata,  
application notes and sample programs, design  
resources, user’s guides and hardware support  
documents, latest software releases and archived  
software  
• Development Systems Information Line  
Customers  
should  
contact  
their  
distributor,  
representative or field application engineer (FAE) for  
support. Local sales offices are also available to help  
customers. A listing of sales offices and locations is  
included in the back of this document.  
General Technical Support – Frequently Asked  
Questions (FAQ), technical support requests,  
online discussion groups, Microchip consultant  
program member listing  
Technical support is available through the web site  
at: http://support.microchip.com  
Business of Microchip – Product selector and  
ordering guides, latest Microchip press releases,  
listing of seminars and events, listings of  
Microchip sales offices, distributors and factory  
representatives  
CUSTOMER CHANGE NOTIFICATION  
SERVICE  
Microchip’s customer notification service helps keep  
customers current on Microchip products. Subscribers  
will receive e-mail notification whenever there are  
changes, updates, revisions or errata related to a  
specified product family or development tool of interest.  
To register, access the Microchip web site at  
www.microchip.com, click on Customer Change  
Notification and follow the registration instructions.  
2010 Microchip Technology Inc.  
DS22064D-page 29  
25LC1024  
READER RESPONSE  
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-  
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation  
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.  
Please list the following information, and use this outline to provide us with your comments about this document.  
To:  
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RE:  
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Name  
Company  
Address  
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Telephone: (_______) _________ - _________  
FAX: (______) _________ - _________  
Application (optional):  
Would you like a reply?  
Y
N
25LC1024  
DS22064D  
Literature Number:  
Device:  
Questions:  
1. What are the best features of this document?  
2. How does this document meet your hardware and software development needs?  
3. Do you find the organization of this document easy to follow? If not, why?  
4. What additions to the document do you think would enhance the structure and subject?  
5. What deletions from the document could be made without affecting the overall usefulness?  
6. Is there any incorrect or misleading information (what and where)?  
7. How would you improve this document?  
DS22064D-page 30  
2010 Microchip Technology Inc.  
25LC1024  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
PART NO.  
Device  
X
/XX  
X
Examples:  
Tape & Reel  
Package  
Temp Range  
a)  
25LC1024-I/P = 1 Mbit, 2.5V Serial EEPROM,  
Industrial temp., P-DIP package  
b)  
25LC1024T-E/MF  
= 1 Mbit, 2.5V Serial  
EEPROM, Extended temp., Tape & Reel, DFN  
package  
Device:  
25LC1024 1 Mbit, 2.5V, SPI Serial EEPROM  
Tape & Reel:  
Blank  
T
=
=
Standard packaging (tube)  
Tape & Reel  
Temperature  
Range:  
I
E
=
=
-40C to+85C  
-40C to+125C  
Package:  
MF  
P
SM  
=
=
=
Micro Lead Frame (6 x 5 mm body), 8-lead  
Plastic DIP (300 mil body), 8-lead  
Plastic SOIJ (5.28 mm), 8-lead  
2010 Microchip Technology Inc.  
DS22064D-page 31  
25LC1024  
NOTES:  
DS22064D-page 32  
2010 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC,  
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,  
32  
PIC logo, rfPIC and UNI/O are registered trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,  
MXDEV, MXLAB, SEEVAL and The Embedded Control  
Solutions Company are registered trademarks of Microchip  
Technology Incorporated in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, CodeGuard,  
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,  
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial  
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified  
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code  
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,  
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,  
TSHARC, UniWinDriver, WiperLock and ZENA are  
trademarks of Microchip Technology Incorporated in the  
U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2010, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
ISBN: 978-1-60932-228-1  
Microchip received ISO/TS-16949:2002 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
2010 Microchip Technology Inc.  
DS22064D-page 33  
WORLDWIDE SALES AND SERVICE  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
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Tel: 852-2401-1200  
Fax: 852-2401-3431  
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Tel: 91-80-3090-4444  
Fax: 91-80-3090-4123  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://support.microchip.com  
Web Address:  
www.microchip.com  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
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Tel: 91-20-2566-1512  
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Tel: 61-2-9868-6733  
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Tel: 49-89-627-144-0  
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Tel: 86-10-8528-2100  
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Tel: 86-23-8980-9588  
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Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
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Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
Detroit  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Taiwan - Hsin Chu  
Tel: 886-3-6578-300  
Fax: 886-3-6578-370  
Kokomo  
Kokomo, IN  
Tel: 765-864-8360  
Fax: 765-864-8387  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Kaohsiung  
Tel: 886-7-536-4818  
Fax: 886-7-536-4803  
Los Angeles  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Santa Clara  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Xiamen  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
Toronto  
Mississauga, Ontario,  
Canada  
Tel: 905-673-0699  
Fax: 905-673-6509  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
01/05/10  
DS22064D-page 34  
2010 Microchip Technology Inc.  

25LC1024-I/SMG 相关器件

型号 制造商 描述 价格 文档
25LC1024-I/WF16K MICROCHIP 1024k, 128K X 8, 2.5V SER EE IND, WAFER on FR, -40C to +85C, Wafer-Frame, WFRAME 获取价格
25LC1024T-E/MF MICROCHIP 1 Mbit SPI Bus Serial EEPROM 获取价格
25LC1024T-E/MFG MICROCHIP 128K X 8 SPI BUS SERIAL EEPROM, PDSO8, 6 X 5 MM, PLASTIC, DFN-8 获取价格
25LC1024T-E/P MICROCHIP 1 Mbit SPI Bus Serial EEPROM 获取价格
25LC1024T-E/SM MICROCHIP 1 Mbit SPI Bus Serial EEPROM 获取价格
25LC1024T-I/MF MICROCHIP 1 Mbit SPI Bus Serial EEPROM 获取价格
25LC1024T-I/P MICROCHIP 1 Mbit SPI Bus Serial EEPROM 获取价格
25LC1024T-I/SM MICROCHIP 1 Mbit SPI Bus Serial EEPROM 获取价格
25LC1024_08 MICROCHIP 1 Mbit SPI Bus Serial EEPROM 获取价格
25LC12 TOSHIBA RECTIFIER DIODE,800V V(RRM),STR-M6 获取价格

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