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M5M5V4R01J-12

更新时间：2024-09-15 01:49:41

品牌：MITSUBISHI

描述：4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

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M5M5V4R01J-12 概述

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM 4194304 - BIT （ 4194304 - WORD BY 1位） CMOS静态RAM SRAM

M5M5V4R01J-12 规格参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOJ	包装说明：	SOJ, SOJ32,.44
针数：	32	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	Is Samacsys：	N
最长访问时间：	12 ns	I/O 类型：	SEPARATE
JESD-30 代码：	R-PDSO-J32	JESD-609代码：	e0
内存密度：	4194304 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	1	功能数量：	1
端子数量：	32	字数：	4194304 words
字数代码：	4000000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX1	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOJ
封装等效代码：	SOJ32,.44	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	PARALLEL
电源：	3.3 V	认证状态：	Not Qualified
最大待机电流：	0.01 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.16 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.13 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

M5M5V4R01J-12 数据手册

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MITSUBISHI LSIs

M5M5V4R01J-12,-15

1997.11.20 Rev.F

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

DESCRIPTION

The M5M5V4R01J is a family of 4194304-word by 1-bit static

RAMs, fabricated with the high performance CMOS silicon gate

process and designed for high speed application.

PIN CONFIGURATION (TOP VIEW)

32 A21

³¹A20

The M5M5V4R01J is offered in a 32-pin plastic small outline J-

lead package(SOJ).

address

inputs

A19

address

inputs

A¹⁸

A17

A¹⁶

These device operate on a single 3.3V supply, and are directly

TTL compatible. They include a power down feature as well.

VCC

GND

chip select

input

output enable

input

(0V)

FEATURES

GND

VCC

(3.3V)

• Fast access time

M5M5V4R01J-12 •••• 12ns(max)

M5M5V4R01J-15 •••• 15ns(max)

(0V)

(3.3V)

data outputs

data inputs

²³Q

• Low power dissipation

Active •••••••••• 297mW(typ)

Stand by •••••••••• 3.3mW(typ)

A15

write control

input

A¹⁰

A14

A¹³

A12

• Single +3.3V power supply

• Fully static operation : No clocks, No refresh

• Test mode is available

address

inputs

address

inputs

18 A11

• Easy memory expansion by S

byte control

input

• Three-state outputs : OR-tie capability

• OE prevents data contention in the I/O bus

• Directly TTL compatible : All inputs and outputs

B1/B4

Outline 32P0K

APPLICATION

High-speed memory units

PACKAGE

32pin 400mil SOJ

BLOCK DIAGRAM

MEMORY ARRAY

512 ROWS

8192 COLUMNS

A⁵

data

outputs

address

inputs

COLUMN I/O CIRCUITS

data

inputs/

COLUMN ADDRESS

COLUMN

ADDRESS

DECODERS

VCC(3.3V)

GND(0V)

COLUMN INPUT BUFFERS

OE 26

B1/B4 17

15 16 18

29 30 31 32

19 20 21 22 27 28

_{A9 A10 A11 A12 A13 A14 A15 A16 A17 A18}A19 A20 A21

address inputs

MITSUBISHI

ELECTRIC

MITSUBISHI LSIs

M5M5V4R01J-12,-15

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

FUNCTION

The operation mode of the M5M5V4R01J is determined by a

combination of the device control inputs S, W and OE. Each

mode is summarized in the function table.

A write cycle is executed whenever the low level W overlaps

with the low level S. The address must be set-up before the

write cycle and must be stable during the entire cycle.

The data is latched into a cell on the trailing edge of W or S,

whichever occurs first, requiring the set-up and hold time

relative to these edge to be maintained. The output enable

input OE directly controls the output stage. Setting the OE at

a high level, the output stage is in a high impedance state,

and the data bus

A read cycle is excuted by setting W at a high level and OE

at a low level while S are in an active state (S=L).

When setting S at high level, the chip is in a non-selectable

mode in which both reading and writing are disable. In this

mode, the output stage is in a high-impedance state, allowing

OR-tie with other chips and memory expansion by S.

Signal-S controls the power-down feature. When S goes

high, power dissapation is reduced extremely. The access time

from S is equivalent to the address access time.

The RAM works with an organization of 4194304-word by 1

bit,when B1/B4 is low of floating. And an organization of 10485

76-word by 4bit is also obtained for reducing the test time,

when B1/B4 is high.

contention problem in the write cycle is eliminated.

FUNCTION TABLE

Mode

Non selection

Write

High-impedance

Din

Icc

Stand by

High-impedance

Active

Read

High-impedance

Dout

High-impedance

ABSOLUTE MAXIMUM RATINGS

Parameter

Supply voltage

Conditions

With respect to GND

Ta=25 C

Ratings

-2.0^*~ 4.6

Unit

Symbol

Vcc

-2.0^*~ VCC+0.5

Input voltage

V_O

Output voltage

Power dissipation

Operating temperature

Storage temperature(bias)

Storage temperature

1000

Topr

0 ~ 70

Tstg(bias)

-10 ~ 85

-65 ~ 150

stg

*Pulse width ≤ 20ns, In case of DC:-0.5V

(Ta=0 ~ 70 C, Vcc=3.3V ^+10%unless otherwise noted)

DC ELECTRICAL CHARACTERISTICS

-5%

Limits

Condition

Symbol

Parameter

Unit

Typ

Max

Min

V_IH

V_IL

VOH

VOL

I _I

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input current

Vcc+0.3

0.8

2.2

-0.3

2.0

IOH =-4mA

IOL= 8mA

V_I= 0~Vcc

0.4

µA

VI (S)= VIH

VO= 0~Vcc

µA

I _OZ

Output current in off-state

12ns cycle

15ns cycle

160

VI (S)= VIL

other inputs VIH or VIL

Output-open(duty 100%)

Active supply current

(TTL level)

I _CC1

150

100

12ns cycle

15ns cycle

Stand by current

(TTL level)

I _CC2

VI (S)= VIH

VI (S)= Vcc≥0.2V

other inputs V^I≤0.2V

or V^I≥Vcc-0.2V

I _CC3Stand by current

MITSUBISHI

ELECTRIC

MITSUBISHI LSIs

M5M5V4R01J-12,-15

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

^+10%unless otherwise noted)

CAPACITANCE _{(Ta=0 ~ 70 C, Vcc=3.3V}

-5%

Limit

Typ

Unit

Symbol

Parameter

Test Condition

Min

Max

Input capacitance

Output capacitance

V _I=GND, V_I=25mVrms,f=1MHz

V_{O=25mVrms,f=1MHz}

V_O=GND,

Note 1: Direction for current flowing into an IC is positive (no mark).

2: Typical value is Vcc=5V,Ta=25 C

3: CI,CO are periodically sampled and are not 100% tested.

(Ta=0 ~ 70 C, Vcc=3.3V ^+10%unless otherwise noted)

AC ELECTRICAL CHARACTERISTICS

(1)MEASUREMENT CONDITION

-5%

Input pulse levels

_IH=3.0V, V _IL=0.0V

••••••••••••••••••••••••

Input rise and fall time

3ns

••••••••••••••••••••••••••••••••••••••

Input timing reference levels •••••••••••• V _IH=1.5V, V _IL=1.5V

Output timing reference levels =1.5V, V _OL=1.5V

••••••••••

Output loads

Fig1 ,Fig2

••••••••••••••••••••••••••••••••••••••••••

Vcc

Z0=50Ω

OUTPUT

480Ω

5pF

(including

scope and JIG)

255Ω

RL=50Ω

VL=1.5V

Fig.1 Output load

Fig.2 Output load for t en, t dis

MITSUBISHI

ELECTRIC

MITSUBISHI LSIs

M5M5V4R01J-12,-15

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

(2)READ CYCLE

Limits

M5M5V4R01J -12 M5M5V4R01J -15

Unit

Parameter

Symbol

Max

Min

tCR

Read cycle time

Address access time

ta(A)

ta(S)

Chip select access time

(OE)

Output enable access time

Output disable time after S high

Output disable time after OE high

Output enable time after S low

Output enable time after OE low

Data valid time after address change

Power-up time after chip selection

Power-down time after chip selection

tdis(S)

tdis^(OE)

ten(S)

ten(OE)

tv_(A)

tPU

tPD

(3)WRITE CYCLE

Limits

M5M5V4R01J -12 M5M5V4R01J -15

Parameter

Symbol

Unit

Min

Max

Min

t_CW

Write cycle time

tw^(W)

tsu(A)1

tsu(A)2

Write pulse width

Address setup time(W)

Address setup time(S)

(S)

tsu

Chip select setup time

Data setup time

(D)

tsu

th(D)

Data hold time

(W)

trec

Write recovery time

(W)

Output disable time after W low

Output disable time after OE high

Output enable time after W high

tdis

tdis (OE)

ten (W)

ten^(OE)

Output enable time after OE low

Address to W High

(A-WH)

tsu

MITSUBISHI

ELECTRIC

MITSUBISHI LSIs

M5M5V4R01J-12,-15

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

(4)TIMING DIAGRAMS

Read cycle 1

t _CR

VIH

0~21

VIL

(A)

VOH

VOL

PREVIOUS DATA VALID

UNKNOWN

DATA VALID

W=H

S=L

OE=L

Read cycle 2 (Note 4)

t _CR

VIH

VIL

(Note 5)

(S)

tdis

(Note 5)

ten(S)

VOH

UNKNOWN

DATA VALID

VOL

tPU

tPD

ICC1

50%

Icc

ICC2

W=H

OE=L

Note 4. Addresses valid prior to or coincident with S transition low.

5. Transition is measured ±500mv from steady state voltage with specified loading in Figure 2.

Read cycle 3 (Note 6)

t _CR

VIH

VIL

(Note 5)

(OE)

tdis(OE)

(Note 5)

ten(OE)

VOH

VOL

UNKNOWN

DATA VALID

W=H

S=L

Note 6. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))

MITSUBISHI

ELECTRIC

MITSUBISHI LSIs

M5M5V4R01J-12,-15

4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM

Write cycle ( W control mode )

t_CW

VIH

0~21

VIL

(S)

tsu

VIH

VIL

(Note7)

(A-WH)

tsu

VIH

VIL

(A)

tsu

tw(W)

trec(W)

VIH

VIL

(D)

tsu

VIH

VIL

DATA STABLE

(Note 5)

(W)

tdis

(Note 5)

(OE)

ten

(OE)

ten(W)

tdis

VOH

VOL

Hi-Z

Write cycle (S control mode )

t_CW

VIH

0~21

VIL

(S)

tsu

(W)

(A)

trec

tsu

VIH

VIL

(W)

VIH

VIL

(Note7)

(D)

tsu

VIH

VIL

DATA STABLE

(W)

tdis

(S)

ten

(Note5)

VOH

VOL

(Note5)

Hi-Z

(Note8)

Note 7: Hatching indicates the state is don't care.

8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance.

9: ten,tdis are periodically sampled and are not 100% tested.

MITSUBISHI

ELECTRIC

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