概述
数据手册NDS356AP-NB8L005A 概述
-30V P 沟道逻辑电平增强型场效应晶体管
NDS356AP-NB8L005A 数据手册
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NDS356AP
P-Channel Logic Level Enhancement Mode Field Effect Transistor
Features
General Description
-1.1 A, -30 V, RDS(ON) = 0.3 W @ VGS=-4.5 V
RDS(ON) = 0.2 W @ VGS=-10 V.
SuperSOTTM-3
P-Channel logic level enhancement mode
power field effect transistors are produced using ON
Semiconductor's proprietary, high cell density, DMOS
technology. This very high density process is especially
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
Industry standard outline SOT-23 surface mount package
using proprietary SuperSOTTM-3 design for superior
thermal and electrical capabilities.
High density cell design for extremely low RDS(ON)
.
Exceptional on-resistance and maximum DC current
capability.
switching, and low in-line power loss
very small outline surface mount package.
are needed in a
_______________________________________________________________________________
D
S
G
Absolute Maximum Ratings
TA = 25°C unless otherwise noted
Symbol Parameter
NDS356AP
-30
Units
VDSS
VGSS
ID
Drain-Source Voltage
V
V
A
Gate-Source Voltage - Continuous
±20
Maximum Drain Current - Continuous
- Pulsed
(Note 1a)
±1.1
±10
Maximum Power Dissipation
(Note 1a)
(Note 1b)
0.5
W
PD
0.46
Operating and Storage Temperature Range
-55 to 150
°C
TJ,TSTG
THERMAL CHARACTERISTICS
Thermal Resistance, Junction-to-Ambient (Note 1a)
250
75
°C/W
°C/W
R
JA
q
Thermal Resistance, Junction-to-Case
(Note 1)
R
JC
q
Publication Order Number:
© 1997 Semiconductor Components Industries, LLC.
October-2017,Rev 3
NDS356AP/D
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
IDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
VDS = -24 V, VGS = 0 V
-30
V
Zero Gate Voltage Drain Current
-1
µA
-10
100
-100
µA
nA
nA
TJ =55°C
IGSSF
IGSSR
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VGS = 20 V, VDS = 0 V
VGS = -20V, VDS = 0 V
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
-0.8
-0.5
-1.6
-1.3
0.25
-2.5
-2.2
0.3
V
VGS(th)
VDS = VGS, ID = -250 µA
VGS = -4.5 V, ID = -1.1 A
TJ =125°C
TJ =125°C
Static Drain-Source On-Resistance
RDS(ON)
W
0.35
0.14
0.4
0.2
VGS = -10 V, ID = -1.3 A
VGS = -4.5 V, VDS = -5 V
VDS = -5 V, ID = -1.1 A
On-State Drain Current
-3
A
S
ID(ON)
2
gFS
Forward Transconductance
DYNAMIC CHARACTERISTICS
Ciss
Coss
Crss
Input Capacitance
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
280
170
65
pF
pF
pF
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn - On Delay Time
Turn - On Rise Time
Turn - Off Delay Time
Turn - Off Fall Time
Total Gate Charge
8
15
30
90
80
4.4
ns
ns
tD(on)
tr
tD(off)
tf
VDD = -10 V, ID = -1 A,
VGS = -10 V, RGEN = 50 W
17
53
38
3.4
0.7
1.5
ns
ns
nC
nC
nC
Qg
Qgs
VDS = -10 V, ID = -1.1 A,
VGS = -5 V
Gate-Source Charge
Gate-Drain Charge
Qgd
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2
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
Min
Typ
Max
Units
IS
Maximum Continuous Source Current
-0.42
-10
A
A
Maximum Pulsed Drain-Source Diode Forward Current
ISM
VSD
Drain-Source Diode Forward Voltage
-0.8
-1.2
V
VGS = 0 V, IS = -0.42 (Note 2)
Notes:
1. RqJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RqJC is guaranteed by
design while RqCA is determined by the user's board design.
-
-
T
T
R
T
T
J
A
J
A
( )
PD t =
2 ( )
= ID t ´ RDS(ON)@T
( )
t
=
J
( )
t
R
+R
qJA
qJC
qCA
Typical RqJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.
b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.
1b
1a
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
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3
Typical Electrical Characteristics
2
1.8
1.6
1.4
1.2
1
-10
V
= -10V
-7.0
GS
-6.0
V
= -3.5 V
GS
-5.5
-8
-6
-4
-2
0
-5.0
-4.5
-4.0
-4.5
-5.0
-4.0
-5.5
-6.0
0.8
0.6
0.4
-7.0
-8
-3.5
-3.0
-10
0
-2
-4
-6
-10
0
-1
V
-2
-3
-4
-5
I
, DRAIN CURRENT (A)
, DRAIN-SOURCE VOLTAGE (V)
D
DS
Figure 2. On-Resistance Variation
Figure 1. On-Region Characteristics.
with Drain Current and Gate Voltage.
1.6
1.4
1.2
1
2
V
= -4.5V
GS
I
= -1.1A
= -4.5V
1.8
1.6
1.4
1.2
1
D
V
GS
T = 125°C
J
25°C
-55°C
0.8
0.6
0.4
0.8
0.6
-50
-25
0
T
25
50
75
100
125
150
0
-2
-4
, DRAIN CURRENT (A)
-6
-8
, JUNCTION TEMPERATURE (°C)
I
J
D
Figure 3. On-Resistance Variation
Figure 4. On-Resistance Variation
with Temperature.
with Drain Current and Temperature.
1.2
-5
25°C
125°C
T
= -55°C
J
VDS = -10V
VDS = V
GS
I D =- 250µA
1.1
1
-4
-3
-2
-1
0
0.9
0.8
0.7
-50
-25
0
25
50
75
100
125
150
-1
-2
-3
-4
-5
T
, JUNCTION TEMPERATURE (°C)
V
, GATE TO SOURCE VOLTAGE (V)
GS
J
Figure 6. Gate Threshold Variation
Figure 5. Transfer Characteristics.
with Temperature.
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3
Typical Electrical Characteristics (continued)
1.08
5
VGS = 0V
2
1
I
= -250µA
D
1.06
1.04
1.02
1
0.5
T
= 125°C
J
0.1
0.01
25°C
-55°C
0.98
0.96
0.94
0.001
0.0001
-50
-25
0
T
25
50
75
100
125
150
0
0.2
-V
0.4
0.6
0.8
1
1.2
, JUNCTION TEMPERATURE (°C)
J
, BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage Variation with
Source Current and Temperature.
10
600
VDS= -5V
ID = -1.1A
400
300
-10V
8
C
iss
-15V
C
oss
200
6
4
2
0
100
C
rss
f = 1 MHz
VGS = 0 V
50
30
0
1
2
3
4
5
6
7
0.1
0.2
0.5
1
2
5
10
20
Q
, GATE CHARGE (nC)
-V , DRAIN TO SOURCE VOLTAGE (V)
g
DS
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
VDD
ton
toff
td(off)
t d(on)
tr
tf
RL
VIN
90%
90%
D
VOUT
V
OUT
VGS
10%
10%
90%
RGEN
DUT
G
V
50%
50%
IN
S
10%
INVERTED
PULSE WIDTH
Figure 11. Switching Test Circuit.
Figure 12. Switching Waveforms.
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5
Typical Electrical Characteristics (continued)
20
10
5
5
VDS = - 5V
T = -55°C
J
4
3
2
1
0
2
1
25°C
0.5
125°C
VGS = -4.5V
SINGLE PULSE
0.1
0.05
R JA = See Note 1b
q
TA = 25°C
0.01
0.1
0.2
0.5
1
2
5
10
20 30
0
-1
-2
-3
-4
-5
- V , DRAIN-SOURCE VOLTAGE (V)
I
, DRAIN CURRENT (A)
DS
D
Figure 13. Transconductance Variation with Drain
Figure 14. Maximum Safe Operating Area.
Current and Temperature.
1.4
1.3
1.2
1
0.8
0.6
1a
1a
1.1
1b
0.4
1b
1
4.5"x5" FR-4 Board
= 25 o
4.5"x5" FR-4 Board
0.2
T
A
C
TA = 25o
Still Air
C
0.9
0.8
Still Air
GS = -4.5V
V
0
0
0.1
0.2
0.3
2
0.4
0
0.1
0.2
0.3
0.4
2
2oz COPPER MOUNTING PAD AREA (in
)
2oz COPPER MOUNTING PAD AREA (in
)
Figue 15. SuperSOTTM _ 3 Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
Figure 16. Maximum Steady-State Drain
Current versus Copper Mounting Pad Area.
1
D = 0.5
0.5
R
R
(t) = r(t) * R
JA
q
JA
q
0.2
0.1
0.2
0.1
=
See Note 1b
qJA
0.05
0.05
P(pk)
0.02
0.01
0.02
0.01
t
1
t
2
Single Pulse
T - T = P * R
(t)
JA
q
J
A
0.005
Duty Cycle, D = t /t
1
2
0.002
0.001
0.0001
0.001
0.01
0.1
t , TIME (sec)
1
10
100
300
1
Figure 17. Transient Thermal Response Curve.
Note : Characterization performed using the conditions described in note 1b. Transient thermal response will
change depending on the circuit board design.
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6
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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NDS356AP-NB8L005A 相关器件
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| NDS356P | FAIRCHILD | P-Channel Logic Level Enhancement Mode Field Effect Transistor | 获取价格 |
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| NDS356P | TYSEMI | SUPERSOT-3 | 获取价格 |
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| NDS356P/L99Z | TI | 1100mA, 20V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-236AB | 获取价格 |
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