概述
数据手册1337AG 概述
Real-Time Clock With I2C Serial Interface
1337AG 数据手册
通过下载1337AG数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
IDT1337AG
General Description
Features
The IDT1337AG device is a low-power serial real-time clock
(RTC) device with two programmable time-of-day alarms
and a programmable square-wave output. Address and
• Real-Time Clock (RTC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
2
data are transferred serially through an I C bus. The device
• Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC
(surface-mount package with an integrated crystal)
provides seconds, minutes, hours, day, date, month, and
year information. The date at the end of the month is
automatically adjusted for months with fewer than 31 days,
including corrections for leap year. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator.
2
• I C serial interface (Normal and Fast modes)
• Two time-of-day alarms
• Oscillator stop flag
Applications
• Programmable square-wave output defaults to 32kHz on
power-up
• Telecommunication (Routers, Switches, Servers)
• Handhelds (GPS, POS terminals, MP3 players)
• Set-Top Box, Digital Recording,
• Operating voltage of 1.8 to 5.5V
• Industrial temperature range (-40 to +85°C)
• Office (Fax/Printers, Copiers)
• Medical (Glucometer, Medicine Dispensers)
• Other (Thermostats, Vending Machines, Modems, Utility
Meters, Digital Photo Frame devices)
Block Diagram
VCC
Crystal inside package
for 16-pin SOIC ONLY
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz
X1
SQW/INTB
INTA
MUX/
Buffer
32.768 kHz
Oscillator and
Divider
X2
Clock,
Calendar
Counter
Control
Logic
SCL
SDA
I2C
Interface
Alarm
Registers
1 Byte 7 Bytes
Control
Buffer
GND
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
1
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Pin Assignment (8-pin MSOP/SOIC)
X1
X2
8
7
6
5
1
2
3
4
VCC
SQW/INTB
SCL
IDT1337AG
INTA
GND
SDA
Pin Assignment (16-pin SOIC)
16
15
14
13
1
2
3
4
5
6
7
8
SCL
SDA
GND
INTA
NC
SQW/INTB
VCC
NC
IDT1337AG
NC
NC
NC
NC
NC
12
11
10
9
NC
NC
NC
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
2
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Pin Descriptions
Pin Number
Pin
Pin Description/Function
Name
MSOP SOIC
1
2
—
—
X1
X2
Connections for standard 32.768 kHz quartz crystal. The internal oscillator
circuitry is designed for operation with a crystal having a specified load
capacitance (CL) of 7 pF. An external 32.768 kHz oscillator can also drive the
IDT1337AG. In this configuration, the X1 pin is connected to the external
oscillator signal and the X2 pin is left floating.
Interrupt output. When enabled, INTA is asserted low when the time/day/date
matches the values set in the alarm registers. This pin is an open-drain output
and requires an external pull-up resistor (10 k typical).
3
14
INTA
4
5
15
16
GND
SDA
Connect to ground. DC power is provided to the device on these pins.
2
Serial data input/output. SDA is the input/output pin for the I C serial interface.
The SDA pin is an open-drain output and requires an external pull-up resistor
(2 k typical).
6
7
1
2
SCL
Serial clock input. SCL is used to synchronize data movement on the serial
interface. The SCL pin is an open-drain output and requires an external pull-up
resistor (2 k typical).
Square-Wave/Interrupt output. Programmable square-wave or interrupt output
signal. The SQW/INT pin is an open-drain output and requires an external
pull-up resistor (10 k typical). This pin can also function as an additional
interrupt pin under certain conditions (see page 6 for details).
SQW/INTB
8
3
VCC
NC
Primary power supply. DC power is applied to this pin.
—
4 - 13
No connect. These pins are unused and must be connected to ground.
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
3
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Typical Operating Circuit
CRYSTAL
VCC
VCC
VCC
2k
VCC
10k
2k
10k
X1
X2
SCL
SQW/INTB
CPU
IDT1337AG
INTA
SDA
GND
Detailed Description
Communications to and from the IDT1337AG occur serially
over an I C bus. The IDT1337AG operates as a slave device
Effective Load Capacitance
2
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
on the serial bus. Access is obtained by implementing a
START condition and providing a device identification code,
followed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The device
2
is fully accessible through the I C interface whenever VCC
2
is between 5.5 V and 1.8 V. I C operation is not guaranteed
when VCC is below 1.8 V. The IDT1337AG maintains the
time and date when VCC is as low as 1.3 V.
The following sections discuss in detail the Oscillator block,
2
Clock/Calendar Register Block and Serial I C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1337AG RTC are:
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
• Recommended Load Capacitance
• Crystal Effective Series Resistance (ESR)
• Frequency Tolerance
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
4
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Note: IDT1337AGCSRI integrates a standard 32.768 kHz
crystal in the package and contributes an additional
frequency error of 10ppm at nominal VCC (+3.3 V) and
TA=+25°C.
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
ESR (Effective Series Resistance)
PCB Layout
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
Frequency Tolerance
The frequency tolerance for 32 kHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1337AG
typically have a frequency tolerance of +/-20ppm at +25°C.
1337AG
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
Parameter
Nominal Freq.
Symbol Min
Typ Max Units
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32kHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
fO
ESR
CL
32.768
kHz
k
pF
Series Resistance
Load Capacitance
80
7
PCB Design Consideration
• Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
• Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
• Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
• The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
• To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
5
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Address Map
Table 2 (Timekeeper Registers) shows the address map for the IDT1337AG registers. During a multibyte access, when the
2
address pointer reaches the end of the register space (0Fh), it wraps around to location 00h. On an I C START, STOP, or
address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time
information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read
the registers in case of an update of the main registers during a read.
Table 1. Timekeeper Registers
Address
00h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Seconds
Minutes
Range
00 - 59
00 - 59
0
0
10 seconds
10 minutes
AM/PM
Seconds
01h
Minutes
Hour
1 - 12 +
AM/PM
00 - 23
02h
0
12/24
10 hour
0
Hours
10 hour
03h
04h
05h
0
0
0
0
0
0
0
Day
Day
Date
1 - 7
10 date
Date
01 - 31
Century
0
10 month
Month
Month/Century
01 - 12 +
Century
06h
07h
10 year
Year
Year
00 - 99
00 - 59
A1M1
A1M2
10 seconds
Seconds
Alarm 1
Seconds
08h
09h
10 minutes
Minutes
Alarm 1
Minutes
00 - 59
AM/PM
10 hour
1 - 12 +
AM/PM
00 - 23
A1M3
12/24
10 hour
Hour
Alarm 1 Hours
Day,
Date
Alarm 1 Day
Alarm 1 Date
1 - 7
1 - 31
00 - 59
0Ah
0Bh
A1M4
A2M2
DY/DT
10 date
10 minutes
Minutes
Alarm 2
Minutes
AM/PM
10 hour
1 - 12 +
AM/PM
00 - 23
0Ch
0Dh
A2M3
A2M4
12/24
10 hour
Hour
Alarm 2 Hours
Day,
Date
Alarm 2 Day
Alarm 2 Date
Control
1 - 7
DY/DT
10 date
1 - 31
0Eh
0Fh
EOSC
OSF
0
0
0
0
RS2
0
RS1
0
INTCN
A2IE
A2F
A1IE
A1F
0
Status
Note: Unless otherwise specified, the state of the registers are not defined when power is first applied or when VCC falls below the V
min
CCT
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
6
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Clock and Calendar
Alarms
The time and calendar information is obtained by reading
the appropriate register bytes. The RTC registers are
illustrated in Table 1. The time and calendar are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format.
The IDT1337AG contains two time of day/date alarms.
Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm
2 can be set by writing to registers 0Bh to 0Dh. The alarms
can be programmed (by the INTCN bits of the Control
Register) to operate in two different modes—each alarm
can drive its own separate interrupt output or both alarms
can drive a common interrupt output. Bit 7 of each of the
time-of-day/date alarm registers are mask bits (Table 1).
When all of the mask bits for each alarm are logic 0, an
alarm only occurs when the values in the timekeeping
registers 00h–06h match the values stored in the
time-of-day/date alarm registers. The alarms can also be
programmed to repeat every second, minute, hour, day, or
date. Table 2 (Alarm Mask Bits table) shows the possible
settings. Configurations not listed in the table result in
illogical operation
The day-of-week register increments at midnight. Values
that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries result in
undefined operation.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register
pointer rolls over to zero.
The DY/DT bits (bit 6 of the alarm day/date registers) control
whether the alarm value stored in bits 0 to 5 of that register
reflects the day of the week or the date of the month. If
DY/DT is written to a logic 0, the alarm is the result of a
match with date of the month. If DY/DT is written to a logic
1, the alarm is the result of a match with day of the week.
The countdown chain is reset whenever the seconds
register is written. Write transfers occur on the acknowledge
pulse from the device. To avoid rollover issues, once the
countdown chain is reset, the remaining time and date
registers must be written within 1 second. The 1Hz
square-wave output, if enable, transitions high 500ms after
the seconds data transfer, provided the oscillator is already
running.
When the RTC register values match alarm register
settings, the corresponding Alarm Flag (‘A1F’ or ‘A2F’) bit is
set to logic 1. If the corresponding Alarm Interrupt Enable
(‘A1IE’ or ‘A2IE’) is also set to logic 1, the alarm condition
activates one of the interrupt output (INTA or SQW/INTB)
signals. The match is tested on the once-per-second update
of the time and date registers.
The IDT1337AG can be run in either 12-hour or 24-hour
mode. Bit 6 of the hours register is defined as the 12- or
24-hour mode-select bit. When high, the 12-hour mode is
selected. In the 12-hour mode, bit 5 is the AM/PM bit with
logic high being PM. In the 24-hour mode, bit 5 is the second
10-hour bit (20–23 hours). All hours values, including the
alarms, must be reinitialized whenever the 12/24-hour mode
bit is changed. The century bit (bit 7 of the month register)
is toggled when the years register overflows from 99–00.
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
7
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Table 2. Alarm Mask Bits
DY/DT Alarm 1 Register Mask Bits (Bit 7)
Alarm Rate
A1M4
A1M3
A1M2
A1M1
X
X
X
X
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Alarm once per second.
Alarm when seconds match.
Alarm when minutes and seconds match.
Alarm when hours, minutes, and seconds match.
Alarm when date, hours, minutes, and seconds match.
Alarm when day, hours, minutes, and seconds match.
1
DY/DT Alarm 2 Register Mask Bits (Bit 7)
Alarm Rate
A2M4
A2M3
A2M2
X
X
X
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per minute (00 seconds of every minute).
Alarm when minutes match.
Alarm when hours and minutes match.
Alarm when date, hours, and minutes match.
Alarm when day, hours, and minutes match.
1
Special-Purpose Registers
The IDT1337AG has two additional registers (control and status) that control the RTC, alarms, and square-wave output.
Control Register (0Eh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EOSC
0
0
RS2
RS1
INTCN
A2IE
A1IE
Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to
a logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the
square wave has been enabled. Table 3 shows the square-wave frequencies that can be selected with the RS bits.
These bits are both set to logic 1 (32 kHz) when power is first applied.
Table 3. SQW/INT Output
INTCN
RS2
RS1
SQW/INTB Output
1 Hz
A2IE
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
X
X
X
X
1
4.096 kHz
8.192 kHz
32.768 kHz
A2F
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
8
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers
activate the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the
alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to
logic 0, a square wave is output on the SQW/INTB pin.This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the
status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is
set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status
register to assert INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE
bit is disabled (logic 0) when power is first applied.
Table 4. Alarm/Interrupt Table
Bit 2
Bit 1
Bit 0
INTCN
A2IE
A1IE
Alarm 1
None
INTA
Alarm 2
None
None
INTA
INTA
INTB/SQW
SQW
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Hi
Alarm 1
Alarm 2
Alarm 1 or Alarm 2
Hi
SQW
None
INTA
SQW
INTA
SQW
None
INTA
None
None
INTB
Hi
Alarm 1
Hi
Hi
None
INTA
Alarm 2
Alarm 2
INTB
Alarm 1
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
9
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Status Register (0Fh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSF
0
0
0
0
0
A2F
A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped
for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic
1 anytime the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on VCC is insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers.
This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN
bit in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the INTA
pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the SQW/INTB pin
goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1
leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If
the A1IE bit is also a logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
10
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
2
acknowledges with a ninth bit.
I C Serial Data Bus
2
The IDT1337AG supports the I C bus protocol. A device
that sends data onto the bus is defined as a transmitter and
a device receiving data as a receiver. The device that
controls the message is called a master. The devices that
are controlled by the master are referred to as slaves. A
master device that generates the serial clock (SCL),
controls the bus access, and generates the START and
STOP conditions must control the bus. The IDT1337AG
Acknowledge: Each receiving device, when addressed, is
obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
2
operates as a slave on the I C bus. Within the bus
specifications, a standard mode (100 kHz maximum clock
rate) and a fast mode (400 kHz maximum clock rate) are
defined. The IDT1337AG works in both modes.
Connections to the bus are made via the open-drain I/O
lines SDA and SCL.
The following bus protocol has been defined (see the “Data
2
Transfer on I C Serial Bus” figure):
• Data transfer may be initiated only when the bus is not
busy.
• During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpreted as control
signals.
Accordingly, the followingbusconditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line,
from HIGH to LOW, while the clock is HIGH, defines a
START condition.
Stop data transfer: A change in the state of the data line,
from LOW to HIGH, while the clock line is HIGH, defines the
STOP condition.
Data valid: The state of the data line represents valid data
when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on
the line must be changed during the LOW period of the clock
signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions are
not limited, and are determined by the master device. The
information is transferred byte-wise and each receiver
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
11
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
2
Data Transfer on I C Serial Bus
Depending upon the state of the R/W bit, two types of data
transfer are possible:
1101000, followed by the direction bit (R/W), which is 0 for a
write. After receiving and decoding the slave address byte
the device outputs an acknowledge on the SDA line. After
the IDT1337AG acknowledges the slave address + write bit,
the master transmits a register address to the IDT1337AG.
This sets the register pointer on the IDT1337AG. The
master may then transmit zero or more bytes of data, with
the IDT1337AG acknowledging each byte received. The
address pointer increments after each data byte is
transferred. The master generates a STOP condition to
terminate the data write.
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
slave address. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is transmitted by
the master. The slave then returns an acknowledge bit,
followed by the slave transmitting a number of data bytes.
The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received
byte, a “not acknowledge” is returned. The master device
generates all of the serial clock pulses and the START and
STOP conditions. A transfer is ended with a STOP condition
or with a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the bus is not released. Data is transferred with the
most significant bit (MSB) first.
2) Slave Transmitter Mode (Read Mode): The first byte is
received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the
transfer direction is reversed. Serial data is transmitted on
SDA by the IDT1337AG while the serial clock is input on
SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (see the “Data Read–
Slave Transmitter Mode” figure). The slave address byte is
the first byte received after the START condition is
generated by the master. The slave address byte contains
the 7-bit IDT1337AG address, which is 1101000, followed
by the direction bit (R/W), which is 1 for a read. After
receiving and decoding the slave address byte the slave
outputs an acknowledge on the SDA line. The IDT1337AG
then begins to transmit data starting with the register
address pointed to by the register pointer. If the register
pointer is not written to before the initiation of a read mode
the first address that is read is the last one stored in the
register pointer. The IDT1337AG must receive a “not
acknowledge” to end a read.
The IDT1337AG can operate in the following two modes:
1) Slave Receiver Mode (Write Mode): Serial data and
clock are received through SDA and SCL. After each byte is
received an acknowledge bit is transmitted. START and
STOP conditions are recognized as the beginning and end
of a serial transfer. Address recognition is performed by
hardware after reception of the slave address and direction
bit (see the “Data Write–Slave Receiver Mode” figure). The
slave address byte is the first byte received after the START
condition is generated by the master. The slave address
byte contains the 7-bit IDT1337AG address, which is
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
12
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Data Write – Slave Receiver Mode
Data Read (from current Pointer location) – Slave Transmitter Mode
Data Read (Write Pointer, then Read) – Slave Receive and Transmit
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
13
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Handling, PCB Layout, and Assembly
The IDT1337AG package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions
should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning equipment should be avoided to prevent
damage to the crystal.
Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line.
All NC (no connect) pins must be connected to ground.
Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must
be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device
(MSD) classifications.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT1337AG. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Item
Voltage Range (on any pin relative to ground)
Storage Temperature
Rating
-0.3 V to +6.0 V
-55 to +125C
260C
Soldering Temperature
Ambient Operating Temperature (industrial)
-40 to +85°C
Recommended DC Operating Conditions
Parameter
Symbol
Conditions
Full operation
Timekeeping
Min.
1.8
Typ.
Max.
5.5
Units
VCC Supply Voltage
V
3.3
V
V
CC
V
1.3
1.8
CCT
Ambient Operating Temperature (industrial)
Logic 1
T
-40
+85
C
V
A
V
SCL, SDA
0.8VCC
VCC + 0.3
5.5
IH
INTA, SQW/INTB
Logic 0
V
-0.3
+0.3VCC
V
IL
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
14
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
DC Electrical Characteristics
Unless stated otherwise, VCC = 1.8 V to 5.5 V, Ambient Temp. -40 to +85C, Note 1
Parameter
Symbol
Conditions
Min.
-1
Typ.
Max. Units
Input Leakage
I
Note 2
+1
+1
3
µA
µA
LI
I/O Leakage
I
I
Note 3
Note 3
-1
LO
OL
Logic 0 Output
VOL = 0.4 V
mA
Active Supply Current
Standby Current
I
I
Note 4
5
150
1.5
µA
µA
CCA
Notes 5, 6
CCS
DC Electrical Characteristics
Unless stated otherwise, VCC = 1.3 V to 1.8 V, Ambient Temp. -40 to +85C (industrial), Note 1
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Timekeeper Current (Oscillator
Enabled)
I
Notes 5, 7, 8, 9
725
900
nA
CCTOSC
Data-Retention Current (Oscillator
Disabled)
I
Notes 5, 9
300
nA
CCTDDR
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
15
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
AC Electrical Characteristics
Unless stated otherwise, VCC = 1.8 V to 5.5 V, Ambient Temp. -40 to +85C, Note 1
Parameter
Symbol
Conditions
Fast Mode
Min.
100
0
Typ. Max. Units
SCL Clock Frequency
f
400
100
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
SCL
Standard Mode
Fast Mode
Bus Free Time Between a STOP and
START Condition
t
1.3
BUF
Standard Mode
Fast Mode
4.7
Hold Time (Repeated) START
Condition, Note 10
t
0.6
HD:STA
Standard Mode
Fast Mode
4.0
Low Period of SCL Clock
High Period of SCL Clock
t
1.3
LOW
Standard Mode
Fast Mode
4.7
t
0.6
HIGH
Standard Mode
Fast Mode
4.0
Setup Time for a Repeated START
Condition
t
0.6
SU:STA
Standard Mode
Fast Mode
4.7
Data Hold Time, Notes 11, 12
Data Setup Time, Note 13
t
0
0.9
HD:DAT
Standard Mode
Fast Mode
0
t
100
250
20 + 0.1C
SU:DAT
Standard Mode
Fast Mode
Rise Time of Both SDA and SCL
Signals, Note 14
t
300
1000
300
R
B
B
Standard Mode
Fast Mode
Fall Time of Both SDA and SCL Signals,
Note 14
t
20 + 0.1C
F
Standard Mode
Fast Mode
300
Setup Time for STOP Condition
t
0.6
4.0
SU:STO
Standard Mode
Capacitive Load for Each Bus Line,
Note 14
C
400
B
I/O Capacitance (SDA, SCL)
C
Note 15
10
10
pF
I/O
32.768 kHz Clock Accuracy with
External Crystal
TA=25°C
VCC=3.3 V
ppm
32.768 kHz Clock Accuracy with
Internal Crystal
TA=25°C
30
ppm
VCC=3.3 V
(crystal accuracy
20ppm)
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
16
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA, and SQW/INTB.
Note 4: I
—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
CCA
2
Note 5: Specified with the I C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
of
IHMIN
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
need only be met if the device does not stretch the LOW period (t
) of the SCL
LOW
HD:DAT
signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement t
> to 250 ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
+
R(MAX)
t
= 1000 + 250 = 1250 ns before the SCL line is released.
SU:DAT
Note 14: C —total capacitance of one bus line in pF.
B
Note 15: Guaranteed by design. Not production tested.
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
17
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Timing Diagram
Typical Operating Characteristics
Icc vs Vcc
IccA vs Vcc
900
800
700
600
500
400
300
200
10
8
6
INTCN=1
INTCN=0
ICCA
4
2
0
1.3
2.3
3.3
4.3
5.3
1.3
2.3
3.3
4.3
5.3
Vcc (V)
Vcc (V)
Oscillator Frequency vs Vcc
(as measured on one IDT1337C sample)
Icc vs Temperature
32768.4
32768.38
32768.36
32768.34
32768.32
32768.3
800
700
600
500
400
300
200
INTCN=1
INTCN=0
Freq
1.3
2.3
3.3
4.3
5.3
-40
-20
0
20
40
60
80
Vcc(V)
Temperature (C)
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
18
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Thermal Characteristics for 8SOIC
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
Still air
150
140
120
40
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Thermal Characteristics for 8MSOP
Parameter
Symbol
Conditions
Min.
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
Still air
95
C/W
JA
Thermal Resistance Junction to Case
48
C/W
JC
Thermal Characteristics for 16SOIC
Parameter
Symbol
Conditions
Typ. Max. Units
Thermal Resistance Junction to
Ambient
Still air
120
115
105
58
C/W
C/W
C/W
C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
19
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Marking Diagram (8 MSOP)
Marking Diagram (8 SOIC)
8
5
37AI
YYWW$
IDT
1337AG
DCGI
YYWW$
Marking Diagram (16 SOIC)
16
9
1
4
IDT
1337AGC
SRGI
YYWW**$
1
8
Notes:
1. # = product stepping.
2. $ = mark code.
3. ** = sequential lot code.
4. YYWW is the last two digits of the year and week that the part was assembled.
5. “XXX” = traceability (lot code).
6. “G” denotes RoHS compliant package.
7. “I” denotes industrial grade.
8. Bottom marking: country of origin if not USA.
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
20
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches
8
Symbol
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
A
A1
B
C
D
E
e
.0532
.0040
.013
.0075
.1890
.1497
.0688
.0098
.020
.0098
.1968
.1574
E
H
INDEX
AREA
1.27 BASIC
0.050 BASIC
1
2
H
h
L
5.80
0.25
0.40
0
6.20
0.50
1.27
8
.2284
.010
.016
0
.2440
.020
.050
8
D
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
21
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Package Outline and Package Dimensions (8-pin MSOP, 3.00 mm Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches*
8
Symbol
Min
Max
A
A1
A2
b
--
1.10
0.15
0.97
0.38
0.23
--
0.043
0.006
0.038
0.015
0.009
0
0
0.79
0.22
0.08
0.031
0.008
0.003
E1
E
INDEX
AREA
C
D
E
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 Basic
0.118 BASIC
0.193 BASIC
0.118 BASIC
0.0256 Basic
E1
e
1
2
L
0.40
0.80
8
0.016
0.032
8
D
0
0
aaa
-
0.10
-
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
22
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Package Outline and Package Dimensions (16-pin SOIC, 300 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Inches*
Min Max
16
Symbol
Min
--
Max
2.65
--
2.55
0.51
0.32
10.50
10.65
7.60
A
A1
A2
b
--
0.104
--
0.10
2.05
0.33
0.18
10.10
10.00
7.40
0.0040
0.081
0.013
0.007
0.397
0.394
0.291
0.100
0.020
0.013
0.413
0.419
0.299
E1
E
INDEX
AREA
c
D
E
1 2
E1
e
L
1.27 Basic
0.050 Basic
D
0.40
0
1.27
8
0.016
0.050
8
0
aaa
-
0.10
-
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa
C
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
23
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Ordering Information
Part / Order Number
1337AGDVGI
Markings
see page 20
Shipping Packaging
Tubes
Package
8-pin MSOP
8-pin MSOP
16-pin SOIC
16-pin SOIC
8-pin SOIC
8-pin SOIC
Temperature
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
-40 to +85 C
1337AGDVGI8
1337AGCSRGI
1337AGCSRGI8
1337AGDCGI
Tape and Reel
Tubes
Tape and Reel
Tubes
1337AGDCGI8
Tape and Reel
The 1337AGC packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the
integrated crystal (as designated with a “C” before the two-letter package code) may include lead that is exempt under RoHS
requirements. The lead finish is JESD91 category e3.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
24
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Revision History
Rev.
Date
Originator Description of Change
A
B
08/02/13
10/31/13
J. Chao
J. Chao
Initial release
1. Update Alarm/Interrupt table.
2. Update Bit2 and Bit descriptions.
C
D
01/15/14
07/14/17
J. Chao
C. Chen
Removed all references to VFQFPN (16NLG) package.
Updated marking diagram for 8MSOP.
2
IDT® REAL-TIME CLOCK WITH I C SERIAL INTERFACE
25
IDT1337AG
REV D 071417
IDT1337AG
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
('LVFODLPHUꢀRev.1.0 Mar 2020)
Corporate Headquarters
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
Contact Information
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
www.renesas.com
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 202ꢀ Renesas Electronics Corporation. All rights reserved.
1337AG 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 1337B0 | ETC | Peripheral IC | 获取价格 |
|
| 1337B1 | ETC | Peripheral IC | 获取价格 |
|
| 1337B2 | ETC | Peripheral IC | 获取价格 |
|
| 1337C-100K | ABRACON | General Purpose Inductor, 10uH, 10%, 1 Element | 获取价格 |
|
| 1337C-120K | ABRACON | General Purpose Inductor, 12uH, 10%, 1 Element | 获取价格 |
|
| 1337C-151K | ABRACON | General Purpose Inductor, 150uH, 10%, 1 Element | 获取价格 |
|
| 1337C-1R0K | ABRACON | General Purpose Inductor, 1uH, 10%, 1 Element | 获取价格 |
|
| 1337C-1R2K | ABRACON | General Purpose Inductor, 1.2uH, 10%, 1 Element | 获取价格 |
|
| 1337C-1R5K | ABRACON | General Purpose Inductor, 1.5uH, 10%, 1 Element | 获取价格 |
|
| 1337C-1R8K | ABRACON | General Purpose Inductor, 1.8uH, 10%, 1 Element | 获取价格 |
|
1337AG 相关文章
探究驱动器、开关与激光二极管对提升激光雷达性能的作用
- 2025-02-26
- 102
利用数字预失真技术打造超精准信号发生器
- 2025-02-26
- 109
英伟达挑战欧盟反垄断调查：起诉质疑Run:ai收购案的调查
- 2025-02-26
- 79
英特尔18A工艺良率仅20%~30%，下半年量产计划面临挑战
- 2025-02-26
- 79
