概述
数据手册16C26 概述
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 单芯片16位CMOS微机
16C26 数据手册
通过下载16C26数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载M16C/26 Group
REJ09B0176-0100Z
Rev.1.00
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2004.6.10
1. Overview
The M16C/26 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and are packaged in a 48-pin plastic molded QFP. These
single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction
efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction process-
ing capability, makes it suitable for control of various OA, communication, and industrial equipment which
requires high-speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, office/communications/portable/industrial equipment, etc
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.1.00 2004.6.10 page 1 of 37
REJ09B0176-0100Z
M16C/26 Group
1. Overview
1.2 Performance Outline
Table 1.1 lists performance outline of M16C/26 group.
Table 1.1. Performance outline of M16C/26 group
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
50 ns (f(BCLK)= 20MHZ, VCC1= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC1= 2.7V to 5.5V)
(See the product list)
Memory
capacity
I/O port
ROM
RAM
(See the product list)
P15 to P17, P6, P7, P80 to P83, 8bit x 3, 7bit x 1, 4bit x 1, 3bit x 1
P85 to P87, P90 to P93, P10
Multifunction timer
Serial I/O
Timer A:16 bits x 5 channels (TA0, TA1, TA2, TA3, TA4)
Timer B:16 bits x 3 channels (TB0, TB1, TB2)
Three-phase Motor Control Timer
2 channels (UART0, UART1)
UART, clock synchronous
1 channels (UART2)
UART, clock synchronous, I C bus , or IEBus
10 bits x 8 channels
2
1
2
A/D converter
DMAC
Watchdog timer
Interrupt
2 channels (trigger: 20 sources)
15 bits x 1 (with prescaler)
20 internal and 7 external sources, 4 software sources, 7 levels
Clock generation circuit
3 circuits
(These circuits contain a built-in feedback
resistor and external ceramic/quartz oscillator)
• Main clock
• Sub-clock
•
On-chip oscillator(main-clock oscillation stop detect function)
Power supply voltage
VCC=3.0V to 5.5V (f(BCLK)=20MHZ)
VCC=2.7V to 5.5V (f(BCLK)=10MHZ)
VCC=2.7V to 5.5V
Flash memory Program/erase voltage
Number of program/erase
100 times (all area)
3
1000times (program area) /10000 times (data area)
16mA (VCC=3V, f(BCLK)=20MHZ)
25µA (f(BCLK)=f(XCIN)=32kHZ on RAM)
1.8µA (VCC=3V, f(XCIN)=32kHZ, when wait mode)
0.7µA (VCC=3V, when stop mode)
5.0V
Power consumption
I/O
I/O withstand voltage
characteristics Output current
Operating ambient temperature
5mA
-20 to 85°C
-40 to 85°C
3
Device configuration
Package
CMOS high performance silicon gate
48-pin plastic mold QFP
Notes:
1. I2C bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. See Table 1.3 for the number of program/erase and the operating ambient temperatue.
Rev.1.00 2004.6.10 page 2 of 37
REJ09B0176-0100Z
M16C/26 Group
1. Overview
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/26 group.
3
8
8
7
4
8
Port P9
Port P8
Port P7
Port P10
Port P6
Port P1
Internal peripheral functions
Timer (16-bit)
System clock generator
A/D converter
(10 bits
X 8 channels )
X
IN-XOUT
X
CIN-XCOUT
Output (timer A): 5
Input (timer B): 3
On-Chip Oscillator
UART or
clock synchronous serial I/O
(8 bits 3 channels)
Three-phase motor
control circuit
X
Memory
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
R0L
R1L
SB
ROM
(Note 1)
USP
R2
R3
DMAC
(2 channels)
ISP
RAM
(Note 2)
INTB
PC
FLG
A0
A1
FB
Multiplier
Note 1: ROM size depends on microcomputer type.
Note 2: RAM size depends on microcomputer type.
Figure 1.1. Block Diagram
Rev.1.00 2004.6.10 page 3 of 37
REJ09B0176-0100Z
M16C/26 Group
1. Overview
1.4 Product List
Table 1.2 lists the M16C/26 group products, Figure 1.2 shows the type numbers, memory sizes and pack-
ages, Table 1.3 lists the product code, and Figure 1.3 shows the marking.
Table 1.2. Product List
Type No.
As of May 2004
Remarks
ROM capacity
24K + 4K byte
32K + 4K byte
48K + 4K byte
64K + 4K byte
RAM capacity
1K byte
Package type
48P6Q-A
M30262F3GP
M30262F4GP
M30262F6GP
M30262F8GP
1K byte
Flash ROM Version
2K byte
2K byte
Type No.
M 3 0 2 6 2 F 4 GP – D3
Product code:
Refer to Table 1.3
Package type:
GP : Package 48P6Q-A
ROM capacity:
3: (24K + 4K) bytes
4: (32K + 4K) bytes
6: (48K + 4K) bytes
8: (64K + 4K) bytes
Memory type:
F: Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/26 Group
M16C Family
Figure 1.2. Type No., Memory Size, and Package
Rev.1.00 2004.6.10 page 4 of 37
REJ09B0176-0100Z
M16C/26 Group
1. Overview
Table 1.3. Product code
Internal ROM
(Data area)
Internal ROM
(Program area)
Product
Code
Operating Ambient
Package
Temperature
Program and
Erase Endurance
Temperature
Range
Program and
Erase Endurance
Temperature
Range
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
D3
D5
D7
D9
U3
U5
U7
U9
0°C to 60°C
100
10,000
100
100
Lead-included
Lead-free
-40°C to 85°C
-20°C to 85°C
1,000
0°C to 60°C
0°C to 60°C
100
-40°C to 85°C
-20°C to 85°C
1,000
10,000
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
0262F8
A D3
XXXXX
Chip version and product code
A
: Shows chip version.
First version is blank.
Henceforth, whenever it changes a version, it continues with A, B, and C.
D3 : Shows Product code. (See table 1.3 Product Code)
Data code five digits
Figure 1.3. Marking Diagram of Flash Memory versionfor M16C/26 (Top View)
Rev.1.00 2004.6.10 page 5 of 37
REJ09B0176-0100Z
M16C/26 Group
1. Overview
1.5 Pin Configuration
Figures 1.4 showd the pin configurations (top view).
PIN CONFIGURATION (top view)
24
23
P10
P10
P10
7
/AN
/AN
/AN
7
/KI
/KI
/KI
3
P7
P7
1
/TA0in/RXD
2
/SCL(Note 1)
37
2
/CLK2/TA1out/V
6
5
6
5
2
1
38
39
22
21
P73
/CTS
2
/RTS /TA1in/V
2
P10
4
/AN
4
/KI0
P7
4
/TA2out/W
40
20
19
P10
P10
P10
3
2
1
/AN
/AN
/AN
3
2
1
41
42
P7
P7
P7
5
/TA2in/W
/TA3out
/TA3in
6
7
43
18
17
AVss
44
45
P80
/TA4out/U
/TA4in/U
P10
0
/AN
0
16
P81
P82
P83
V
ref
AVcc
P9
46
15
14
/INT
0
/INT
1
47
48
3
13
IVCC (Note 2)
Package: 48P6Q
Note 1. this pin is N channel open-drain output pins.
Note 2. Leave this pin open.
Figure 1.4. Pin Configuration (Top View)
Rev.1.00 2004.6.10 page 6 of 37
REJ09B0176-0100Z
M16C/26 Group
1. Overview
1.6 Pin Description
Table 1.4 and 1.5 describe the available pins.
Table 1.4. Pin Description(1)
Pin name Signal name I/O type
Function
VCC,VSS Power supply
input
Apply 2.7V to 5.5V to the VCC pin, and 0V to the Vss pin.
CNVSS
CNVSS
IVCC
Input
Connect this pin to Vss.
IVCC
Leave this pin open.
____________
RESET Reset input
Input
"L" on this input resets the microcomputer.
XIN
Clock input
Input
These pins are provided for the main clock generating circuit input/output.
Connect a ceramic resonator or crystal between the XIN and the XOUT pins.
To use an externally derived clock, input it to the XIN pin and leave the XOUT
pin open.
XOUT
Clock output
Output
AVCC
AVSS
VREF
Analog power
supply input
Analog power
supply input
Reference
This pin is a power supply input for the A/D converter. Connect this
pin to VCC.
This pin is a power supply input for the A/D converter. Connect this
pin to VSS.
Input
This pin is a reference voltage input for the A/D converter.
Voltage input
P15~P17 I/O port P1
Input/
This is an 3-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
output
entire group of three pins. Additional software selectable secondary
______
functions are: 1) P15 to P17 can be configured as external INT interrupt
pins, and; 2) P15 can input a trigger for the A/D converter.
P60~P67 I/O port P6
P70~P77 I/O port P7
Input/
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output individually.
When used for input, a pull-up resister option can be selected for the
entire group of four pins. Pins in this port also function as UART0 and
UART1 I/O.
output
Input/
This is an 8-bit I/O port equivalent to P6. (P70 and P71 are N channel
open-drain output) P7 can also function as I/O for timer A0 to A3, as
selected by software. Additional programming options are: P70 to P73 can
assume UART2 I/O capabilities, and P72 to P75 can function as output
pins for the three-phase motor control timer.
output
P80~P83, I/O port P8
P85~P87
Input/
P80 to P83 and P85 to P87 are an 7-bit I/O port equivalent to P6.When
used for input, a pull-up resister option can be selected for the entire
group of four pins or three pins. Additional software-selectable secondary
functions are: 1) P80 and P81 can act as either I/O for Timer A4, or as
output pins for the three-phase motor control timer; 2) P82 to P83 can be
output
______
_______ _____
configured as external INT interrupt pins; 3) P85 can be used as NMI/SD.
P85 can not be used as I/O port while the three-phase motor control is
enabled. Apply a stable "H" to P85 after setting the direction register for
P85 to "0" when the three-phase motor control is enabled, and; 4) P86 and
P87 can serve as I/O pins for the sub-clock generation circuit. In this latter
case, a quartzoscillator must be connented between P86 (XCOUT pin) and
P87 (XCIN pin).
Rev.1.00 2004.6.10 page 7 of 37
REJ09B0176-0100Z
M16C/26 Group
1. Overview
Table 1.7. Pin Description(2)
Pin name Signal name
P90~P93 I/O port P9
I/O type
Function
Input/
This is an 4-bit I/O port equivalent to P6. Additional software-selectable
secondary functions are: 1) P90 to P92 can act as Timer B0~B2 input
pins.
output
P100~P107 I/O port P10
Input/
This is an 8-bit I/O port equivalent to P6. This port can also function as
A/D converter input pins, as selected by software. Furthermore, P104 to
P107 can also function as input pins for the key input interrupt function.
output
Rev.1.00 2004.6.10 page 8 of 37
REJ09B0176-0100Z
M16C/26 Group
2. CPU
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H(R0's high bits) R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
Data registers (Note)
R2
R3
A0
A1
FB
Address registers (Note)
Frame base registers (Note)
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
User stack pointer
Interrupt stack pointer
Static base register
ISP
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
IPL
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-
ter relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.1.00 2004.6.10 page 9 of 37
REJ09B0176-0100Z
M16C/26 Group
2. CPU
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.1.00 2004.6.10 page 10 of 37
REJ09B0176-0100Z
M16C/26 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of the M16C/26 group. The address space extends the 1M bytes from address
0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. For example,
a 32-Kbyte internal ROM is allocated to the addresses from F800016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. For example,
a 1-Kbytes internal RAM is allocated to the addresses from 0040016 to 007FF16. In addition to storing data,
the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SRF is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is used
by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software Manual.”
0000016
SFR
FFE0016
0040016
Internal RAM
XXXXX16
0F00016
0FFFF16
Special page
vector table
Reserved area
Internal ROM
Internal ROM
Internal RAM
Size
Address XXXXX16
007FF16
Size
Address YYYYY16
(Note 1)
(Data area)
1K bytes
2K bytes
24K bytes
32K bytes
FA00016
F800016
FFFDC16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
00BFF16
48K bytes
64K bytes
F400016
F000016
Reserved area
YYYYY16
FFFFF16
Watchdog timer
DBC
NMI
Reset
Internal ROM
(Program area)
FFFFF16
Note 1: Shown here is a Block A (2K bytes) and Block B (2K bytes).
Figure 3.1. Memory Map
Rev.1.00 2004.6.10 page 11 of 37
REJ09B0176-0100Z
M16C/26 Group
4. Special Function Register (SFR) MAP
4. Special Function Register (SFR) Map
Address
Register
Symbol
After reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
(Note 2)
PM0
PM1
CM0
CM1
0016
00001000
01001000
00100000
2
2
2
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX00
XX000000
2
2
Oscillation stop detection register
(Note 3)
CM2
0X000000
2
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
XX16
00XXXXXX
0016
0016
X016
2(Note 4)
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1
Voltage detection register 2
(Note 5)
(Note 5)
VCR1
VCR2
00001000
0016
2
Processor mode register 2
Voltage down detection interrupt register
DMA0 source pointer
PM2
D4INT
SAR0
XXX00000
0016
XX16
XX16
XX16
2
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
DAR0
XX16
XX16
XX16
TCR0
XX16
XX16
DM0CON
SAR1
00000X002
XX16
XX16
XX16
DAR1
XX16
XX16
XX16
TCR1
XX16
XX16
DM1CON
00000X002
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 3: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
Note 4: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input
voltage at the VCC1 pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection
circuit enable).
X : Nothing is mapped to this bit
Rev.1.00 2004.6.10 page 12 of 37
REJ09B0176-0100Z
M16C/26 Group
4. Special Function Register (SFR) MAP
Address
004016
004116
004216
004316
004416
Register
Symbol
After reset
XX00X000
INT3 interrupt control register
INT3IC
2
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
INT5 interrupt control register
INT4 interrupt control register
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
INT5IC
INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
XX00X000
XX00X000
2
2
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DMA1 interrupt control register
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
XX00X000
XX00X000
2
2
INT1 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note :The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.00 2004.6.10 page 13 of 37
REJ09B0176-0100Z
M16C/26 Group
4. Special Function Register (SFR) MAP
Address
008016
008116
008216
008316
008416
008516
008616
Register
Symbol
After reset
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
Flash memory control register 4
(Note 2)
(Note 2)
(Note 2)
FMR4
FMR1
FMR0
01000000
0100XX0X
XX000001
2
Flash memory control register 1
Flash memory control register 0
2
2
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Peripheral clock select register
PCLKR
000000112
~
~
~
~
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.
X : Nothing is mapped to this bit
Rev.1.00 2004.6.10 page 14 of 37
REJ09B0176-0100Z
M16C/26 Group
4. Special Function Register (SFR) MAP
Address
Register
Symbol
After reset
034016
034116
034216
Timer A1-1 register
TA11
TA21
TA41
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
XX16
XX16
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Timer A2-1 register
Timer A4-1 register
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
Timer B2 interrupt occurrence frequency set counter
ICTB2
Interrupt cause select register
IFSR
0016
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
0016
000X0X0X
X0000000
X0000000
0016
XX16
XXXXXXXX
XXXXXXXX
00001000
00000010
2
2
2
U2BRG
U2TB
UART2 transmit buffer register
2
2
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
2
2
XXXXXXXX
XXXXXXXX
2
2
Note : The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.00 2004.6.10 page 15 of 37
REJ09B0176-0100Z
M16C/26 Group
4. Special Function Register (SFR) MAP
Address
038016
Register
Symbol
After reset
0016
Count start flag
TABSR
CPSRF
ONSF
TRGSR
UDF
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
0XXXXXXX
0016
2
0016
0016
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00XX0000
00XX0000
00XX0000
2
2
2
Timer B2 special mode register
XXXXXX002
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
XX16
XXXXXXXX
XXXXXXXX
2
2
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
00001000
00000010
2
2
XXXXXXXX
XXXXXXXX
0016
2
2
UART1 transmit/receive mode register
UART1 bit rate generator
UART1 transmit buffer register
U1MR
U1BRG
U1TB
XX16
XXXXXXXX
XXXXXXXX
2
2
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
U1C0
U1C1
U1RB
00001000
00000010
2
2
XXXXXXXX
XXXXXXXX
2
2
UART transmit/receive control register 2
UCON
X00000002
DMA0 request cause select register
DMA1 request cause select register
DM0SL
DM1SL
0016
0016
Note : The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.00 2004.6.10 page 16 of 37
REJ09B0176-0100Z
M16C/26 Group
4. Special Function Register (SFR) MAP
Address
03C016
Register
Symbol
AD0
After reset
A/D register 0
XXXXXXXX
2
2
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
XXXXXXXX
A/D register 1
A/D register 2
A/D register 3
A/D register 4
A/D register 5
A/D register 6
A/D register 7
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A/D control register 2
ADCON2
0016
A/D control register 0
A/D control register 1
ADCON0
ADCON1
00000XXX
2
0016
Port P1 register
P1
XX16
0016
Port P1 direction register
PD1
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
P6
P7
PD6
PD7
P8
XX16
XX16
0016
0016
XX16
XX16
Port P9 register
P9
Port P8 direction register
Port P9 direction register
Port P10 register
PD8
PD9
P10
00X00000
2
0016
XX16
Port P10 direction register
PD10
0016
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
PUR0
PUR1
PUR2
PCR
0016
0016
0016
0016
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.1.00 2004.6.10 page 17 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5. Electrical Characteristics
5.1 Absolute Maximum Ratings
Table 16.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Rated value
Unit
V
V
CC
Supply voltage
V
CC=AVCC
-0.3 to 6.5
-0.3 to 6.5
AVCC
Analog supply voltage
V
CC=AVCC
V
Input
voltage
RESET, CNVSS
,
P1
P8
5
to P1
to P8
7
, P6
, P8
0
to P6
to P8
7
, P7
2
0
to P7
to P9
7
3
,
,
0
3
5
7, P9
-0.3 to VCC+0.3
V
V
I
P100 to P107,
VREF, XIN
P7
0
, P7
1
-0.3 to 6.5
V
V
Output
voltage
P1
P8
5
0
to P1
to P8
7
3
, P6
, P8
0
to P6
to P8
7
, P7
2
to P7
to P93,
7,
5
7, P9
0
-0.3 to VCC+0.3
P100 to P107,
VO
X
OUT
P7
0, P71
V
mW
C
-0.3 to 6.5
300
C
P
d
Power dissipation
Topr=25
Operating ambient temperature
Storage temperature
T
opr
stg
-20 to 85 / -40 to 85
-65 to 150
T
C
Rev.1.00 2004.6.10 page 18 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5.2 Recommended Operating Conditions
Table 1.26.2. Recommended Operating Conditions (Note 1)
Standard
Unit
Symbol
Parameter
Min.
Typ.
Max.
VCC
Supply voltage
2.7
5.5
V
AVcc
Vss
Analog supply voltage
Supply voltage
VCC
V
V
0
0
AVss
Analog supply voltage
HIGH input
V
V
V
RESET, CNVSS, XIN
,
P1
P9
5
to P1
to P9
7
, P6
0
to P6
to P10
7
, P7
7
2
0
to P7
to P7
7
, P8
, P8
0
0
to P8
to P8
3
, P8
, P8
5
5
to P8
to P8
7
,
,
0.8VCC
0.8VCC
0
VCC
voltage
V
IH
IL
0
3, P10
0
6.5
P7
0 , P71
RESET, CNVSS, XIN
,
LOW input
voltage
V
P1
P9
5
0
to P1
to P9
7, P6
0
to P6
to P107
7, P7
7
3
7
0.2VCC
V
3, P10
0
HIGH peak output
current
P1
P8
5
5
to P1
to P8
7
, P6
0
0
to P6
7
, P7
2
to P7
7
, P8
7
0
to P8
to P8
to P8
to P8
3
,
,
,
,
IOH (peak)
IOH (avg)
IOL (peak)
IOL (avg)
mA
mA
mA
mA
-10.0
7, P9
to P9
3
, P10
0
to P10
HIGH average
output current
P1
P8
5
5
to P1
to P8
7, P6
0
0
to P6
7
, P7
, P10
2
to P7
7, P8
0
0
0
3
3
3
-5.0
7, P9
to P9
3
0
to P10
7
LOW peak output
current
P1
P8
5
5
to P1
to P8
7, P6
0
0
to P6
7
, P7
, P10
2
to P7
7, P8
10.0
7, P9
to P9
3
0
to P10
7
LOW average
output current
P1
P8
5
5
to P1
to P8
7, P6
0
0
to P6
7
, P7
, P10
2
to P7
7, P8
5.0
20
7, P9
to P9
3
0
to P10
7
V
CC=3.0 to 5.5V
MHz
MHz
kHz
0
0
Main clock input oscillation frequency
(Note 4)
f (XIN
)
V
CC=2.7 to 3.0V
33.33 X VCC-80
32.768
1
50
f (XCIN
)
Sub-clock oscillation frequency
On-chip oscillation frequency
CPU operation clock
f (Ring)
MHz
MHz
f (BCLK)
0
20
Note 1: Referenced to VCC = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL (peak) for all ports must be 80mA max. The total IOL (peak) for all ports must be -80mA max.
Note 4: Relationship between main clock oscillation frequency and supply voltage.
Main clock input oscillation frequency
33.33 x VCC-80MH
Z
20.0
10.0
0.0
2.7
3.0
5.5
V
CC[V] (main clock: no division)
Rev.1.00 2004.6.10 page 19 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5.3 A/D Conversion Characteristics
Table 16.3. A/D Conversion Characteristics (Note 1)
Standard
Min. Typ. Max.
Symbol
–
Parameter
Measuring condition
Unit
Resolution
V
REF =VCC
10
±3
±5
±2
±3
±5
Bits
LSB
LSB
V
V
V
V
V
V
REF=VCC=5V
AN
AN
0
0
to AN
to AN
7
7
input
input
10 bit
Integral non-linearity
error
INL
–
REF=VCC=3.3V
REF =VCC=3.3V
REF=VCC=5V
LSB
LSB
8 bit
AN
AN
0
0
to AN
to AN
7
7
input
input
10 bit
Absolute
accuracy
LSB
LSB
LSB
LSB
LSB
kΩ
REF=VCC=3.3V
REF =VCC=3.3V
8 bit
±2
±1
±3
±3
Differential non-linearity error
Offset error
DNL
–
–
Gain error
Ladder resistance
10
40
RLADDER
V
V
REF =VCC
Conversion time(10bit), Sample & hold
function available
3.3
µs
t
CONV
REF =VCC=5V, øAD=10MHz
Conversion time(8bit), Sample & hold
function available
2.8
0.3
µs
t
t
V
V
CONV
SAMP
V
REF =VCC=5V, øAD=10MHz
Sampling time
µs
V
REF
IA
Reference voltage
Analog input voltage
2.0
0
V
CC
V
V
REF
Note 1: Referenced to VCC=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise
specified.
Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC is less than 4.2V,
and make ØAD frequency equal to or lower than fAD/2.
Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz or more in addition to a limit of Note 2.
A case with sample & hold function turn ØAD frequency into 1MHz or more in addition to a limit of Note 2.
Rev.1.00 2004.6.10 page 20 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5.4 Flash Memory Version Electrical Characteristics
Table 16.4. Flash Memory Version Electrical Characteristics (Note 1) 100E/W cycle products (D3, D5, U3, U5))
Standard
Typ.
(Note 2)
Symbol
Parameter
Unit
Min.
Max
–
100(Note 4)
cycle
µs
s
Erase/Write cycle (Note 3)
–
–
Word program time (Vcc=5.0V, Topr=25°C)
600
9
75
0.2
0.4
0.7
1.2
2Kbyte block
8Kbyte block
16Kbyte block
32Kbyte block
Block erase time
9
s
9
s
9
s
Time delay from Suspend Request until Erase Suspend
td(SR-ES)
–
8
ms
year
Data retention time (Note 5)
20
Table 16.5. Flash Memory Version Electrical Characteristics (Note 6) 10000 E/W cycle products (D7, D9, U7, U9)
[blockA and block B(Note 7)]
Standard
Typ.
(Note 2)
Symbol
Parameter
Unit
Min.
Max
–
10000(Note 4,10)
cycle
µs
Erase/Write cycle (Note 3, 8, 9)
–
–
Word program time (Vcc=5.0V, Topr=25°C)
100
0.3
Block erase time(Vcc=5.0V, Topr=25°C)
(2Kbyte block)
s
Time delay from Suspend Request until Erase Suspend
td(SR-ES)
8
ms
Note 1: When not otherwise specified, Vcc = 2.7 to5.5V; Topr = 0 to 60 °C.
Note 2: VCC = 5V; TOPR = 25 °C.
Note 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total
number of distinct word addresses - for every block erase. Performing multiple writes to the same address before
an erase operation is prohibited.
Note 4: Maximum number of E/W cycles for which opration is guaranteed.
Note 5: Topr = 55°C.
Note 6: When not otherwise specified, Vcc = 2.7 to 5.5V; Topr = -40 to 85°C (D7, U7) / -20 to 85°C (D9, U9).
Note 7: Table18.5 applies for Block A or B E/W cycles > 1000. Otherwise, use Table 18.4.
Note 8: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different
word addresses (only one time each) as possible. It is important to track the total number of block erases.
Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then clock erase
command at least three times until erase error disappears.
Note 10: When Block A or B E/W cycles exceed 100 (D7, D9, U7, U9), select one wait state per block access. When FMR
17 is set to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait state
insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless of the
setting of FMR17.
Note 11: Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Erase suspend
request
(interrupt request)
FMR46
td(SR-ES)
Table 16.6. Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60oC)
Flash program, erase voltage
Flash read operation voltage
V
CC = 2.7 V to 5.5 V
VCC=2.7 to 5.5 V
Rev.1.00 2004.6.10 page 21 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5.5 Low Voltage Detection Circuit Electrical Charactristics
Table 16.7. Low Voltage Detection Circuit Electrical Characteristics (Note 1, Note 4
)
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
Min.
3.3
Max.
4.4
Voltage down detection voltage (Note 1)
Reset level detection voltage (Notes 1, 2)
Vdet4
Vdet3
3.8
V
V
2.2
2.8
3.6
VCC1=0.8 to 5.5V
V
V
Low voltage reset retention voltage
0.8
2.2
Vdet3s
Vdet3r
2.9
4.0
Low voltage reset release voltage (Note 3)
Note 1: Vdet4 > Vdet3
Note 2: Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the
operation at f(BCLK) ≤ 10MHz is guaranteed.
Note 3: Vdet3r > Vdet3 is not guaranteed.
Note 4: The low voltage detection circuit is designed to use when VCC is set to 5V.
Table 16.8. Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
Measuring condition
Parameter
Unit
ms
Min.
Max.
2
td(P-R)
td(R-S)
td(W-S)
td(M-L)
td(S-R)
td(E-A)
Time for internal power supply stabilization during powering-on
STOP release time
150
150
50
µs
µs
µs
ms
µs
VCC1=2.7 to 5.5V
Low power dissipation mode wait mode release time
Time for internal power supply stabilization when main clock oscillation starts
Hardware reset 2 release wait time
VCC1=Vdet3r to 5.5V
VCC1=2.7 to 5.5V
6 (Note)
20
Low voltage detection circuit operation start time
20
Note : When VCC = 5V
Vdet3r
VCC
td(S-R)
Interrupt for
stop mode
release
CPU clock
td(R-S)
Rev.1.00 2004.6.10 page 22 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5.6 Electrical Charactristics (VCC=5V)
VCC = 5V
Table 16.9. Electrical Characteristics (Note 1
)
Standard
Unit
Symbol
Measuring condition
Parameter
Min.
Typ.
Max.
P1
P8
5
5
to P1
to P8
7
, P6
,P9
0
to P6
7
,P7
2
to P7
7
,P8
0
to P8
3,
HIGH output
voltage
V
V
OH
OH
V
CC-2.0
V
CC
I
I
OH=-5mA
V
V
7
0
to P9
3
, P10
0
to P107
P1
P8
5
5
to P1
to P8
7
, P6
0
to P67,P7
2
to P7 ,P8
7
0
to P8
3,
HIGH output
voltage
V
CC-0.3
V
CC
OH=-200µA
7
,P90
to P93, P10
0
to P10
7
HIGHPOWER
LOWPOWER
I
I
OH=-1mA
V
V
CC-2.0
CC-2.0
V
V
CC
CC
HIGH output voltage
HIGH output voltage
X
OUT
V
V
OH=-0.5mA
V
OH
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
X
COUT
P1
P8
5
5
to P1
to P8
7
, P6
,P9
0
to P6
7
,P7
2
to P7
7
,P80 to P83
7
,
LOW output
voltage
V
V
OL
OL
2.0
V
V
I
I
OL=5mA
7
0
to P9
3
, P10
0
to P10
to P7 ,P8
to P10
P1
P8
5
5
to P1
to P8
7
, P6
,P9
0
to P6
7
,P7
2
7
0
to P8
3
,
LOW output
voltage
0.45
OL=200µA
7
0
to P9
3
, P10
0
7
I
I
OL=1mA
2.0
2.0
HIGHPOWER
LOWPOWER
X
OUT
LOW output voltage
LOW output voltage
V
V
OL=0.5mA
V
OL
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
XCOUT
TA0IN to TA4IN, TB0IN to TB2IN
INT to INT ,INT to INT ,NMI,
ADTRG, SCL, SDA, RxD to RxD
CLK to CLK , TA2OUT to TA4OUT
KI to KI
,
Hysteresis
0
1
3
5
V
V
T+-
T+-
V
V
T-
T-
0.2
0.2
1.0
V
0
2
, CTS
,
0
to CTS2,
0
2
0
3
Hysteresis
RESET
2.5
5.0
V
P1
P8
5
0
to P1
to P8
7
, P6
, P8
0
5
to P6
to P8
7
, P7
, P9
0
0
to P7
to P9
7
,
,
HIGH input
current
3
7
3
I
IH
V
V
I
=5V
=0V
µA
P10
0 to P107,
X
IN, RESET, CNVss
P1
P8
5
0
to P1
to P8
7
, P6
, P8
0
5
to P6
7
, P7
, P9
0
0
to P7
to P9
7
,
,
LOW input
current
3
to P8
7
3
I
I
IL
-5.0
170
µA
kΩ
P10
0 to P107,
X
IN, RESET, CNVss
P1
P8
5
5
to P1
to P8
7
, P6
,P9
0
to P6
7
,P7
2
to P7
7,P80 to P83,
Pull-up
resistance
VI=0V
RPULLUP
30
50
7
0
to P9
3
, P10
0
to P107
R
fXIN
Feedback resistance
Feedback resistance
RAM retention voltage
X
IN
CIN
1.5
15
MΩ
MΩ
V
RfXCIN
X
V
RAM
At stop mode
2.0
Note 1: Referenced to VCC=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
Rev.1.00 2004.6.10 page 23 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
VCC = 5V
Table 16.10. Electrical Characteristics (2) (Note 1
)
Standard
Unit
Symbol
Measuring condition
Parameter
Min.
Typ.
16
Max.
19
f(BCLK)=20MHz,
No division
In single-chip mode, the output
pins are open and other pins are
Mask ROM
mA
mA
mA
VSS
No division, On-chip oscillation
T.B.D
T.B.D
T.B.D
Flash memory
Program
f(BCLK)=10MHz,
V
CC=5.0V
f(BCLK)=10MHz,
CC=5.0V
Flash memory
Erase
mA
µA
V
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3)
Flash memory
25
f(BCLK)=32kHz
Low power dissipation mode,
Flash memory(Note 3)
Power supply current
(VCC=3.0 to 5.5V)
I
CC
420
µA
On-chip oscillation,
Wait mode
µA
µA
T.B.D
7.5
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
Wait mode(Note 2),
Oscillation capacity Low
µA
µA
2.0
0.8
Stop mode,
3.0
T
opr=25°C
Note 1: Referenced to VCC==4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=20MHz unless otherwise specified.
Note 2: With one timer operated using fC32
.
Note 3: This indicates the memory in which the program to be executed exists.
Rev.1.00 2004.6.10 page 24 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
5.7 Timing Requirements (VCC=5V)
VCC = 5V
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 16.11. External Clock Input (XIN input)
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
50
Max.
t
c
ns
ns
ns
ns
ns
t
w(H
)
25
t
w(L)
25
t
r
15
15
t
f
External clock fall time
Rev.1.00 2004.6.10 page 25 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 16.12. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 16.13. Timer A Input (Gating Input in Timer Mode)
Standard
Min. Max.
400
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 16.14. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 16.15. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
t
w(TAH)
ns
ns
100
100
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 16.16. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN
)
t
h(TIN-UP)
400
Table 16.17. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
t
c(TA)
ns
ns
ns
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
t
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
t
Rev.1.00 2004.6.10 page 26 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=5V)
VCC = 5V
Timing Requirements
o
o
(VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 16.18. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 16.19. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 16.20. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 16.21. A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 16.22. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
30
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 16.23. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
Rev.1.00 2004.6.10 page 27 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Timing (VCC=5V)
VCC = 5V
t
c(TA)
tw(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
tw(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN–UP)
t
su(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
t
c(TA)
TAiIN input
t
su(TAIN-TAOUT)
t
su(TAIN-TAOUT)
t
su(TAOUT-TAIN)
TAiOUT input
t
su(TAOUT-TAIN)
t
c(TB)
t
w(TBH)
TBiIN input
t
w(TBL)
t
c(AD)
t
w(ADL)
ADTRG input
Figure 16.1. Timing Diagram (1)
Rev.1.00 2004.6.10 page 28 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Timing (VCC=5V)
VCC = 5V
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
t
w(INL)
INTi input
t
w(INH)
Figure 16.2. Timing Diagram (2)
Rev.1.00 2004.6.10 page 29 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=3V)
VCC = 3V
5.8 Electrical Charactristics (VCC=3V)
Table 16.24. Electrical Characteristics (Note)
Standard
Unit
Measuring condition
Symbol
Parameter
Min.
Typ.
Max.
HIGH output P1
voltage P8
5
0
to P1
to P8
7
, P6
0
5
to P6
7
, P7
, P9
2
0
to P7
to P9
7
,
V
V
OH
OH
V
V
V
CC
I
OH
=
-
1mA
V
CC
-
0.5
3, P8
to P8
7
3, P100 to P107
V
V
CC
CC
HIGHPOWER
LOWPOWER
V
V
CC-
0.5
0.5
I
I
OH=
-
-
0.1mA
X
X
OUT
HIGH output voltage
HIGH output voltage
OH=
50µA
CC-
With no load applied
With no load applied
2.5
1.6
HIGHPOWER
LOWPOWER
COUT
V
V
LOW output
voltage
P1
P8
5
0
to P1
to P8
7, P6
0
5
to P6
7
, P7
, P9
2
0
to P7
to P9
7,
V
V
OL
OL
I
OL=1mA
0.5
3, P8
to P8
7
3, P100 to P107
I
I
OL=0.1mA
0.5
0.5
HIGHPOWER
LOWPOWER
X
X
OUT
LOW output voltage
LOW output voltage
V
V
OL=50µA
With no load applied
With no load applied
0
0
HIGHPOWER
LOWPOWER
COUT
TA0IN to TA4IN, TB0IN to TB2IN
INT to INT ,INT to INT ,NMI,
ADTRG, SCL, SDA, RxD to RxD
CLK to CLK , TA2OUT to TA4OUT
KI to KI
RESET
,
Hysteresis
0
1
3
5
V
V
T+-
T+-
V
V
T-
T-
0
2
, CTS
,
0
to CTS
2,
0.2
0.2
0.8
V
0
2
0
3
Hysteresis
1.8
4.0
V
P1
P8
5
0
to P1
to P8
7
, P6
0
5
to P6
to P8
7
, P7
, P9
0
0
to P7
to P9
7
,
,
HIGH input
current
3, P8
7
3
V
I=3V
I
IH
µA
P10
0 to P107,
X
IN, RESET, CNVss
P1
P8
P10
5
0
to P1
to P8
0 to P107,
7
, P6
0
5
to P6
to P8
7
, P7
, P9
0
0
to P7
to P9
7
,
,
LOW input
current
3, P8
7
3
V
V
I
=0V
=0V
I
IL
µA
kΩ
-
4.0
X
IN, RESET, CNVss
P1
P8
5
5
to P1
to P8
7, P6
0
to P6
7,P7
2
to P7
7,P80 to P83,
Pull-up
resistance
I
R
PULLUP
50
100
500
7,P9
0
to P9
3, P10
0
to P107
R
fXIN
Feedback resistance
Feedback resistance
RAM retention voltage
X
IN
3.0
25
MΩ
MΩ
V
RfXCIN
XCIN
V
RAM
At stop mode
2.0
Note 1 : Referenced to VCC=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Rev.1.00 2004.6.10 page 30 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=3V)
VCC = 3V
Table 16.25. Electrical Characteristics (2) (Note 1)
Standard
Unit
Symbol
Measuring condition
Parameter
Min.
Typ.
8
Max.
13
f(BCLK)=10MHz,
No division
In single-chip mode, the output
pins are open and other pins are
Flash memory
mA
V
SS
No division, On-chip oscillation
T.B.D
T.B.D
mA
mA
mA
Flash memory
Program
f(BCLK)=10MHz,
Vcc
1=3.0V
Flash memory
Erase
f(BCLK)=10MHz,
Vcc1=3.0V
T.B.D
25
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3)
Flash memory
µA
µA
Power supply current
(VCC=2.7 to 3.6V)
I
CC
f(BCLK)=32kHz,
420
Low power dissipation mode,
Flash memory(Note 3)
On-chip oscillation,
Wait mode
µA
µA
T.B.D
6.0
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity High
Flash memory
f(BCLK)=32kHz,
Wait mode (Note 2),
Oscillation capacity Low
µA
µA
1.8
0.7
Stop mode,
3.0
Topr=25°C
Note 1: Referenced to VCC=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.
Note 2: With one timer operated using fC32
.
Note 3: This indicates the memory in which the program to be executed exists.
Rev.1.00 2004.6.10 page 31 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=3V)
VCC = 3V
5.9 Timing Requirements (VCC=3V)
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 16.26. External Clock Input (XIN input)
Standard
Symbol
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
Unit
Min.
100
40
Max.
t
c
ns
ns
ns
ns
ns
t
w(H)
t
w(L)
40
t
r
18
18
t
f
External clock fall time
Rev.1.00 2004.6.10 page 32 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=3V)
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 16.27. Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
Max.
ns
ns
ns
t
t
t
c(TA)
TAiIN input cycle time
60
60
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 16.28. Timer A Input (Gating Input in Timer Mode)
Standard
Min. Max.
Symbol
Parameter
Unit
ns
ns
ns
t
t
t
c(TA)
600
300
300
TAiIN input cycle time
w(TAH)
w(TAL)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 16.29. Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Min. Max.
300
Symbol
Parameter
Unit
ns
ns
ns
t
t
t
c(TA)
TAiIN input cycle time
w(TAH)
w(TAL)
150
150
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
Table 16.30. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 16.31. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
t
t
t
t
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
su(UP-TIN
h(TIN-UP)
)
600
Table 1.6.32. Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min. Max.
t
t
t
c(TA)
µs
ns
ns
2
TAiIN input cycle time
TAiOUT input setup time
TAiIN input setup time
su(TAIN-TAOUT
su(TAOUT-TAIN
)
)
500
500
Rev.1.00 2004.6.10 page 33 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Electrical Characteristics (VCC=3V)
VCC = 3V
Timing Requirements
o
o
(VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)
Table 16.33. Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
60
60
t
t
300
120
120
t
w(TBH)
t
w(TBL)
Table 16.34. Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 16.35. Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 16.36. A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1500
200
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 16.37. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
160
0
50
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 16.38. External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
380
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
Rev.1.00 2004.6.10 page 34 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Timing (VCC=3V)
VCC = 3V
tc(TA)
tw(TAH)
tw(UPH)
TAiIN input
tw(TAL)
tc(UP)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN
)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT
)
tsu(TAIN-TAOUT
)
tsu(TAOUT-TAIN
)
TAiOUT input
tsu(TAOUT-TAIN
)
tc(TB)
tw(TBH)
tw(ADL)
TBiIN input
tw(TBL)
tc(AD)
ADTRG input
Figure 16.3. Timing Diagram (1)
Rev.1.00 2004.6.10 page 35 of 37
REJ09B0176-0100Z
M16C/26 Group
5. Timing (VCC=3V)
VCC = 3V
t
c(CK)
tw(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
th(C–D)
t
w(INL)
INTi input
t
w(INH)
Figure 16.4. Timing Diagram (2)
Rev.1.00 2004.6.10 page 36 of 37
REJ09B0176-0100Z
M16C/26 Group
6. Package
6. Package
Recommended
48P6Q-A
Plastic 48pin 7✕7mm body LQFP
EIAJ Package Code
LQFP48-P-77-0.50
JEDEC Code
–
Weight(g)
–
Lead Material
Cu Alloy
MD
HD
D
48
37
I2
Recommended Mount Pad
1
36
25
F
Dimension in Millimeters
Symbol
Min
–
0
Nom
–
Max
1.7
0.2
–
0.27
0.175
7.1
7.1
–
9.2
9.2
0.65
–
0.75
–
A
A
1
0.1
1.4
0.22
0.125
7.0
7.0
0.5
9.0
9.0
0.5
1.0
0.6
0.25
–
A
2
–
12
b
0.17
0.105
6.9
6.9
–
8.8
8.8
0.35
–
0.45
–
–
–
0°
c
D
E
e
H
H
13
24
A
D
L
1
E
e
L
L1
Lp
A3
x
0.08
0.1
8°
y
y
–
–
L
b
Lp
x
M
Detail F
b2
–
1.0
–
0.225
–
7.4
7.4
–
–
–
–
I
2
M
M
D
E
–
Rev.1.00 2004.6.10 page 37 of 37
REJ09B0176-0100Z
REVISION HISTORY
M16C/26 Hardware Manual
Rev.
Date
Description
Summary
Page
1.00 Jun/10/ 04
-
First edition
C-1
M16C/29 Group
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
16C26 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| 16C2850 | EXAR | DUAL UART WITH 128-byte FIFO’s AND RS-485 HALF DUPLEX CONTROL | 获取价格 |
|
| 16C450 | EXAR | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) | 获取价格 |
|
| 16C505 | MICROCHIP | 14-Pin, 8-Bit CMOS Microcontroller | 获取价格 |
|
| 16C552 | TI | DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO | 获取价格 |
|
| 16C552 | IMP | Dual FIFO UART and Parallel Port | 获取价格 |
|
| 16C554 | MICROCHIP | EPROM-Based 8-Bit CMOS Microcontroller | 获取价格 |
|
| 16C57 | MICROCHIP | EPROM/ROM-Based 8-Bit CMOS Microcontroller Series | 获取价格 |
|
| 16C62P | RENESAS | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER | 获取价格 |
|
| 16C62X | MICROCHIP | EPROM-Based 8-Bit CMOS Microcontroller | 获取价格 |
|
| 16C6KA | RENESAS | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description | 获取价格 |
|
16C26 相关文章
探究驱动器、开关与激光二极管对提升激光雷达性能的作用
- 2025-02-26
- 102
利用数字预失真技术打造超精准信号发生器
- 2025-02-26
- 109
英伟达挑战欧盟反垄断调查：起诉质疑Run:ai收购案的调查
- 2025-02-26
- 79
英特尔18A工艺良率仅20%~30%，下半年量产计划面临挑战
- 2025-02-26
- 79
