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ML5238

更新时间：2025-07-02 05:40:38
品牌：ROHM
描述：电池电压和电流测量短路电流检测内置FET驱动器内置电池均衡开关MCU接口：SPI内置外部微控制器用电源

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免费 PCB/SMT

ML5238 概述

电池电压和电流测量短路电流检测内置FET驱动器内置电池均衡开关MCU接口：SPI内置外部微控制器用电源

ML5238 数据手册

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FEDL5238-10  
Issue date： June. 9, 2023  
ML5238  
16 series Li-ion secondary battery protection, Analog Front End IC  
◼
GENERAL DESCRIPTION  
The ML5238 is analog front end IC for 16 series Lithium Ion secondary battery pack protection system. The  
ML5238 provides the function of cell voltage monitoring, charge/discharge current monitoring function, and it  
can detect over-charge/over-discharge of each battery cell charge/discharge over-current.  
The ML5238 has short current detecting function which can turn off the external charge/discharge MOS-FET  
without external MCU.  
◼
FEATURES  
• 16 cell highly accurate voltage monitoring function: output cell voltage by half from VMON pin  
• built-in cell balancing switches for each cell  
• charge/discharge current monitoring function :  
Select voltage gain of ISP-ISM and output from IMON pin.  
Voltage gain selection: x10 / x50  
• short current detecting function: detecting threshold voltage is selectable,  
ISP-ISM voltage = 0.1V/0.2V/0.3V/0.4V (typ),  
the detecting delay time is set by external capacitor  
• external charge/discharge FET control: NMOS-FET driver built-in  
• MCU interface: SPI serial interface (mode 0)  
• 3.3V regulator for external MCU built-in: output current is 10mA (max)  
• Reference voltage regulator for external ADC: 3.3V(typ), 3.28V(min),3.34V(max) @Ta=-10°C to +60°C  
• Small power consumption  
Normal state  
Power save state  
Power down state  
: 50A (typ), 100A (max)  
: 25A (typ), 50A (max）  
: 0.1A (typ), 1A (max)  
• power supply voltage  
• operating temperature  
• package  
: +7V to +80V  
: -40°C to +85°C  
: 44 pin plastic QFP  
Note: The ML5238 is forbidden to be used for automotive or any equipment, device or system which  
requires an extremely high level of reliability and quality, such as a medical instrument,  
transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or  
other safety device. If whether product is intended to be used for any such special purpose is  
difficult to be decided, please contact a ROHM sales representative before purchasing.  
1/30  
FEDL5238-10  
ML5238  
◼
BLOCK DIAGRAM  
VREG  
VREF  
VDD VDDP  
VDD_SW  
/CS  
SCK  
SDI  
V16  
V15  
Voltage  
Regulator  
MCU I/F  
V14  
V13  
SDO  
Control  
Logic  
/RES  
V12  
V11  
V10  
V9  
/INTO  
/PUPIN  
TEST  
Cell Voltage  
Monitor  
V8  
V7  
V6  
V5  
V4  
V3  
Charger  
Load  
Detector  
PSENSE  
RSENSE  
Reference  
Generator  
C_FET  
D_FET  
FET  
Driver  
V2  
V1  
V0  
Short  
Detector  
Current  
Monitor  
IMON  
GND  
CDLY  
VMON  
ISM ISP  
◼
PIN CONFIGURATION (TOP VIEW)  
VDD  
VDD_SW  
V16  
1
2
3
4
5
6
7
8
9
33 VREF  
32 VMON  
31 IMON  
30 CDLY  
29 NC  
28 PSENSE  
27 RSENSE  
26 NC  
V15  
V14  
V13  
V12  
V11  
V10  
V9 10  
V8 11  
25 C_FET  
24 NC  
23 D_FET  
2/30  
FEDL5238-10  
ML5238  
◼
PIN DESCRIPTION  
Pin No.  
Pin name  
I/O  
Description  
Power supply input pin.  
Connect CR filters for noise rejection.  
−
1
2
3
VDD  
Power supply input pin for battery selection switches and cell balancing  
switched. Connect this pin to VDD via resistor.  
−
VDD_SW  
V16  
Battery cell 16 high voltage input pin  
I
If number of connected cell is 5 to 15, connect this pin to VDD_SW pin.  
Battery cell 16 low voltage input and Battery cell 15 high voltage input pin  
Battery cell 15 low voltage input and Battery cell 14 high voltage input pin  
Battery cell 14 low voltage input and Battery cell 13 high voltage input pin  
Battery cell 13 low voltage input and Battery cell 12 high voltage input pin  
Battery cell 12 low voltage input and Battery cell 11 high voltage input pin  
Battery cell 11 low voltage input and Battery cell 10 high voltage input pin  
4
5
6
7
8
9
V15  
V14  
V13  
V12  
V11  
V10  
I
I
I
I
I
I
Battery cell 10 low voltage input and Battery cell 9 high voltage input pin  
For the 5 cell series connected battery pack application, connect this pin to  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
V9  
V8  
V7  
V6  
V5  
V4  
V3  
V2  
V1  
V0  
I
I
I
I
I
I
I
I
I
I
Battery cell 9 low voltage input and Battery cell 8 high voltage input pin  
For the 5 to 6 cell series connected battery pack application, connect this pin  
to GND  
Battery cell 8 low voltage input and Battery cell 7 high voltage input pin  
For the 5 to 7 cell series connected battery pack application, connect this pin  
to GND  
Battery cell 7 low voltage input and Battery cell 6 high voltage input pin  
For the 5 to 8 cell series connected battery pack application, connect this pin  
to GND  
Battery cell 6 low voltage input and Battery cell 5 high voltage input pin  
For the 5 to 9 cell series connected battery pack application, connect this pin  
to GND  
Battery cell 5 low voltage input and Battery cell 4 high voltage input pin  
For the 5 to 10 cell series connected battery pack application, connect this  
pin to GND  
Battery cell 4 low voltage input and Battery cell 3 high voltage input pin  
For the 5 to 11 cell series connected battery pack application, connect this  
pin to GND  
Battery cell 3 low voltage input and Battery cell 2 high voltage input pin  
For the 5 to 12 cell series connected battery pack application, connect this  
pin to GND  
Battery cell 2 low voltage input and Battery cell 1 high voltage input pin  
For the 5 to 13 cell series connected battery pack application, connect this  
pin to GND  
Battery cell 1 low voltage input pin  
For the 5 to 14 cell series connected battery pack application, connect this  
pin to GND  
Ground pin.  
20, 34  
21  
GND  
ISM  
−
Current sensing resistor connecting pin. Connect this pin to the low voltage  
terminal of the lowest level battery cell.  
I
Current sensing resistor connecting pin. The voltage of this pin should be  
higher than the ISM pin in discharging state.  
22  
23  
ISP  
I
Discharging NMOS-FET control signal pin. Connect this pin to the gate pin of  
the external NMOS FET. Output voltage is 14V (typ) for setting ON, output  
voltage is 0V for setting OFF.  
D_FET  
O
3/30  
FEDL5238-10  
ML5238  
Pin No.  
25  
Pin name  
C_FET  
I/O  
O
Description  
Charging NMOS-FET control signal output pin. Connect this pin to the gate  
pin of the external NMOS FET. Output voltage is 14V (typ) for setting ON,  
output is Hi-Z for setting OFF.  
Input pin for detecting the load disconnection. Connect this pin to the  
negative side of the load.  
27  
28  
30  
RSENSE  
PSENSE  
CDLY  
I
I
Input pin for detecting the charger disconnection. Connect this pin to the  
negative side of the charger. If charger is connected to the same node as  
the load, connect this pin to the RSENSE pin.  
Short current detection delay time setting pin. Connect a capacitor between  
GND and this pin.  
IO  
Current monitor output pin. The voltage amplified the voltage between  
ISP-ISM by 10 or 50 is outputted. When current is not flowing, 1V (typ) is  
outputted.  
31  
IMON  
O
Cell voltage monitor output pin. The voltage amplified a cell voltage by 0.5  
is outputted.  
32  
33  
VMON  
VREF  
O
O
Reference voltage output (3.3V) for external ADC. Connect a 4.7F capacitor  
between this pin and the GND pin.  
Serial interface data output pin. If /CS input is “H”, output of this pin is Hi-Z  
state.  
35  
36  
SDO  
SDI  
O
I
Serial interface data input pin.  
Serial interface clock input pin. Capture the SDI input at the rising edge of  
the SCK clock. Output the data from the SDO pin at the falling edge of the  
SCK.  
37  
SCK  
I
Serial interface chip select pin. The serial interface is active if the input is  
38  
39  
/CS  
I
“L”.  
Interrupt signal output to external MCU. This pin is a NMOS open drain  
output pin and output is “L” level if interrupted.  
/INTO  
O
Reset signal input and a reset signal output to external MCU. Since this pin is  
a NMOS open drain output pin, connect a 0.1F capacitor between this pin  
and GND pin and pull-up resisitor. When recovered power-down state, ”L”  
level reset pulse will be outputted and both ML5238 and external MCU will be  
initialized.  
40  
/RES  
IO  
Built-in 3.3V regulator output pin. Connect a 4.7F capacitor between this pin  
and GND pin. It can be used as a power supply to the external MCU. And it is  
also used as a power supply to the MCU interface circuit in this IC.  
Test input pin. Fix to GND level.  
41  
42  
43  
VREG  
TEST  
O
I
Power-up trigger input pin. If input is “L” level, the state of the ML5238  
changes from power-down state to Initial state. A 100kΩ pull-up resistor is  
built-in between this pin and the VDD pin.  
/PUPIN  
I
Power supply input pin for internal regulator.  
Connect CR filters for noise rejection.  
No connection pin. Open this pin.  
−
−
44  
VDDP  
NC  
24, 26, 29  
4/30  
FEDL5238-10  
ML5238  
◼
ABSOLUTE MAXIMUM RATINGS  
（GND=0 V, Ta=25°C）  
Parametor  
Symbol  
VDD  
Condition  
Rating  
Unit  
Power supply  
voltage  
VDD, VDDP , VDD_SW  
-0.3 to +86.5  
V
V16 ~ V0, Voltage difference  
between Vn+1 – Vn pin (note)  
VIN1  
VIN2  
-0.3 to +6.5  
V
V
RSENSE, PSENSE  
VDD - 86.5 to VDD+0.3  
Input voltage  
VIN3  
VIN4  
/PUPIN  
-0.3 to VDD + 0.3  
-0.3 to VREG + 0.3  
-0.3 to VDD + 0.3  
V
V
V
/CS, SCK, SDI, ISM, ISP  
D_FET  
VOUT1  
VOUT2  
VOUT3  
C_FET  
VDD - 86.5 to VDD + 0.3  
-0.3 to + 6.5  
V
V
Output voltage  
/RES, /INTO  
VDD=50V,  
VREG, SDO, /RES, /INTO,  
C_FET, D_FET  
Output short  
current  
IOS  
20  
mA  
Cell balancing  
curren  
ICB  
PD  
Per a cell balancing switch  
200  
1.2  
mA  
W
Allowable power  
Dissipation  
Ta = 25°C  
Junction  
temperature  
TjMAX  
−
125  
°C  
Package thermal  
resistance  
θja  
JEDEC 2 layer board  
83  
°C /W  
°C  
Storage  
tempetrature  
TSTG  
−
-55 to +150  
Note : When the battery connecting and disconnecting , absolute maximum rating is exceeded across the LSI and  
it may damage input pins of Vn+1 pin and Vn. It is suggested a good enough evaluation.  
Package allowable dissipation  
Package loss tolerant decreases as  
1.4  
the atmosphere temperature (Ta)  
1.2  
increase. If VREG pin output load  
current is large, make the power loss  
smaller than the value shown in this  
1
figure.  
0.8  
0.6  
0.4  
0.2  
0
-50  
0
50  
100  
150  
Atmosphere temperature Ta [°C]  
◼
RECOMMENDED OPERATING CONDITIONS  
（GND= 0 V）  
Parameter  
Symbol  
VDD  
Condition  
VDD, VDDP, VDD_SW  
VREG no-loaded  
Range  
7 to 80  
unit  
V
Power supply voltage  
Opereating temperature  
Ta  
-40 to +85  
°C  
5/30  
FEDL5238-10  
ML5238  
◼
•
ELECTRICAL CHARACTERISTICS  
DC CHARACTERISTICS  
VDD=7 to 80V，GND=0 V，Ta=-40 to +85°C，VREG output no-loaded  
Parameter  
Digital ”H” input voltage  
(note1)  
Symbol  
Condition  
Min.  
Typ.  
Max.  
unit  
VIH  
−
0.8×VREG  
−
VREG  
V
Digital ”L” input voltage  
(note1)  
VIL  
−
0
−
0.2×VREG  
V
/PUPIN-pin ”H” input voltage  
/PUPIN-pin ”L” input voltage  
VIHP  
VILP  
IIH  
−
−
0.8×VDD  
−
−
−
−
−
VDD  
V
0
−
-2  
0.2×VDD  
V
Digital ”H” input current(note1)  
Digital ”L” input current (note1)  
/PUPIN-pin ”H” input current  
/PUPIN-pin ”L” input current  
Digital ”H” output voltage  
(note2)  
VIH = VREG  
VIL = GND  
VIH = VDD  
2
−
2
µA  
µA  
µA  
µA  
IIL  
IIHP  
IILP  
−
-128  
VDD= 64V, VIL = GND  
-64  
-32  
VOH  
VOL  
IOH= -100A  
VREG - 0.2  
−
−
VREG  
0.2  
2
V
V
Digital ”L” output voltage  
(note3)  
IOL= 1mA  
0
Digital output Leak current  
(note3)  
VOH=3V  
VOL=0V  
IOLK  
-2  
-5  
-5  
10  
−
µA  
µA  
µA  
V
Cell monitoring pin  
Input current (note 4)  
Cell monitoring pin  
If measuring battery  
cell voltage  
IINVC  
IILVC  
VOHF  
−
15  
5
If not measuring  
battery cell voltage  
IOH=-10µA  
VDD=18V to 72V  
IOL = 100µA  
−
Input leak current (note4)  
FET “H” output voltage (note5)  
14  
18  
FET “L” output voltage (note6)  
VOLF  
ILVC  
0
−
−
3.3  
0.3  
5
V
µA  
V
C_FET output leak current  
VCFET=0V to VDD  
Output No-loaded  
10V<VDD<64V  
-5  
VREG  
3.1  
3.6  
VREG1  
VREG2  
VREG3  
VREG4  
Ta＝-10 to 60℃  
Load current < 10mA  
10V<VDD<64V  
Ta＝-40 to 70℃  
Load current < 10mA  
7V<VDD<10V  
Ta = -10 to 60°C  
Load current < 5mA  
7V<VDD<10V  
Ta = -40 to 85°C  
Load current < 5mA  
Ta = -10 to 60°C  
Load current < 1mA  
Ta = -40 to 85°C  
Load current < 1mA  
Internal balancing FET  
VDS = 0.6V  
3.1  
3.0  
3.1  
3.0  
3.3  
3.3  
3.3  
3.3  
3.5  
3.6  
3.5  
3.6  
V
V
V
V
VREG output voltage  
VREF1  
VREF2  
3.28  
3.25  
3.30  
3.30  
3.34  
3.35  
V
V
VREF output voltage  
Cell balancing switch ON  
resistance  
RBL  
3
6
12  
Ω
VDD = 18V to 64V  
Note 1: Applied to pins: /CS, SCK, SDI  
Note2: Applied to SDO pin  
Note3: Applied to pins: SDO, /RES, /INTO  
Note4: Applied to pins V16 to V0  
Note5: Applied to pins C_FET, D_FET  
Note6: Applied to D_FET pin  
6/30  
FEDL5238-10  
ML5238  
•
SUPPLY CURRENT CHARACTERISTICS  
VDD=7 to 64V，GND=0 V，Ta=-40 to +85°C，VREG, VREF output no noaded  
Parameter  
Symbol  
Condition  
No-loaded  
No-loaded  
No-loaded  
Min.  
Typ.  
50  
Max.  
100  
50  
Unit  
µA  
Normal operating Current  
Power save Current  
Power down Current  
IDD  
−
−
−
１
IDD  
25  
µA  
２
IDDS  
0.1  
1.0  
µA  
(note) These power supply current is defined as the total current of VDD-pin and the VDDP-pin.  
(note) The load current is added to these power supply current, using the load with VREG connector.  
•
DETECTING VOLTAGE CHARACTERISTICS (TA=25°C)  
VDD=48V，GND=0 V，Ta=25°C，VREG output no-loaded  
Parameter  
Symbol  
VSHRT0  
VSHRT1  
VSHRT2  
VSHRT3  
Condition  
Min.  
0.06  
0.1  
Typ.  
0.1  
0.2  
0.3  
0.4  
Max.  
0.14  
0.3  
Unit  
V
SC1,SC0 bit = (0,0)  
SC1,SC0 bit = (0,1)  
SC1,SC0 bit = (1,0)  
SC1,SC0 bit = (1,1)  
V
Short current detecting  
voltage  
0.2  
0.4  
V
0.3  
0.5  
V
Short current detecting  
delay time  
tSHRT  
VRD  
VRR  
CDLY = 1nF  
50  
2.3  
2.5  
100  
2.45  
2.75  
200  
2.6  
2.9  
µs  
V
VREG low detecting  
voltage  
−
VREG recovery detecting  
voltage  
−
V
(note) Short detecting delay time tSC [µs]=CDLY[nF] x 100.  
•
DETECTING VOLTAGE CHARACTERISTICS (TA= -10 ~ 60°C)  
VDD=48V，GND=0 V，Ta=-10~+60°C，VREG output no-loaded  
Parameter  
Symbol  
VSHRT0  
VSHRT1  
VSHRT2  
VSHRT3  
Condition  
Min.  
0.06  
0.09  
0.19  
0.29  
Typ.  
0.1  
0.2  
0.3  
0.4  
Max.  
0.14  
0.31  
0.41  
0.51  
Unit  
V
SC1,SC0 bit = (0,0)  
SC1,SC0 bit = (0,1)  
SC1,SC0 bit = (1,0)  
SC1,SC0 bit = (1,1)  
V
Short current detecting  
voltage  
V
V
Short current detecting  
delay time  
tSHRT  
VRD  
VRR  
CDLY = 1nF  
40  
100  
2.45  
2.75  
220  
2.70  
3.00  
µs  
V
VREG low detecting  
voltage  
−
2.20  
2.40  
VREG recovery detecting  
voltage  
−
V
(note) Short detecting delay time tSC [µs]=CDLY[nF] x 100.  
7/30  
FEDL5238-10  
ML5238  
•
VOLTAGE AND CURRENT MONITORING CHARACTERISTICS (TA=25°C)  
VDD=48V，GND=0V，Ta=25°C，VREG output no-loaded  
Parameter  
Cell voltage  
measurement range  
Symbol  
VVMR  
Condition  
Min.  
Typ.  
Max.  
Unit  
−
0.1  
−
4.5  
V
Cell voltage = 3.6V  
Output no-loaded  
Cell voltage = 1V  
Output no-loaded  
ISP-ISM voltage  
difference = 0V  
GIM bit = ”0”  
VVMC1  
VVMC2  
1.79  
0.48  
1.8  
1.81  
0.52  
V
V
VMON output voltage  
0.50  
VIMON0  
0.9  
0.5  
1.0  
1.0  
1.1  
1.5  
V
V
IMON output voltage  
ISP-ISM voltage  
difference = 0V  
GIM bit = ”1”  
VIMON1  
GIM0  
GIM1  
GIM bit = ”0”  
9
10  
50  
11  
55  
V/V  
V/V  
IMON output voltage gain  
GIM bit = ”1”  
45  
•
VOLTAGE AND CURRENT MONITORING CHARACTERISTICS (TA=-10 ~60°C)  
VDD=48V，GND=0V，Ta=-10~+60°C，VREG output no-loaded  
Parameter  
Cell voltage  
measurement range  
Symbol  
VVMR  
Condition  
Min.  
Typ.  
Max.  
Unit  
−
0.1  
−
4.5  
V
Cell voltage = 3.6V  
Output no-loaded  
Cell voltage = 1V  
Output no-loaded  
ISP-ISM voltage  
difference = 0V  
GIM bit = ”0”  
VVMC1  
VVMC2  
1.78  
0.47  
1.8  
1.82  
0.53  
V
V
VMON output voltage  
0.50  
VIMON0  
0.85  
0.4  
1.0  
1.0  
1.15  
1.6  
V
V
IMON output voltage  
ISP-ISM voltage  
difference = 0V  
GIM bit = ”1”  
VIMON1  
GIM0  
GIM1  
GIM bit = ”0”  
8.5  
44  
10.0  
50  
11.5  
56  
V/V  
V/V  
IMON output voltage gain  
GIM bit = ”1”  
8/30  
FEDL5238-10  
ML5238  
•
LOAD DISCONNECTION, CHARGER CONNECTION AND DISCONNECTION  
DETECTING VOLTAGE CHARACTERISTIC (TA=25°C)  
VDD=48V，GND=0V，Ta=25°C  
Parameter  
Detecting Charger  
connection PSENSE pin  
voltage  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
At power up from power  
down state  
VPC  
VDD× 0.2  
VDD×0.5  
VDD×0.8  
V
PSENSE register  
PSL bit threshold  
PSENSE register  
PSH bit threshold  
VPLU  
VPLD  
0.1  
0.2  
0.3  
V
V
Detecting charger  
disconnection PSENSE  
pin voltage  
VDD × 0.7 VDD×0.75  
VDD×0.8  
Detecting load  
disconnection RSENSE  
pin voltage  
RSENSE register  
RRS bit threshold  
VRL  
2.2  
2.4  
2.6  
V
PSENSE register  
EPSL、EPSH = ”1”  
RSENSE register  
ERS = ”1”  
pull-up resistor is not  
connected  
PSENSE pull-up resistor  
RPU  
RPD  
ILPS  
ILRS  
300  
1
500  
2
850  
3
kΩ  
MΩ  
µA  
RSENSE pull-down  
resistor  
PSENSE input leakage  
current  
RSENSE input leakage  
current  
-2  
−
2
Pull-down resistor is not  
connected  
-2  
−
2
µA  
•
LOAD DISCONNECTION, CHARGER CONNECTION AND DISCONNECTION  
DETECTING VOLTAGE CHARACTERISTIC (TA=-10 ~60°C)  
VDD=48V，GND=0V，Ta=-10~60°C  
Parameter  
Detecting Charger  
connection PSENSE pin  
voltage  
Symbol  
Condition  
Min.  
Typ.  
Max.  
Unit  
At power up from power  
down state  
VPC  
VDD× 0.2  
VDD×0.5  
VDD×0.8  
V
PSENSE register  
PSL bit threshold  
PSENSE register  
PSH bit threshold  
VPLU  
VPLD  
0
0.2  
0.4  
V
V
Detecting charger  
disconnection PSENSE  
pin voltage  
VDD  
0.65  
×
VDD×0.75 VDD×0.85  
Detecting load  
disconnection RSENSE  
pin voltage  
RSENSE register  
RRS bit threshold  
VRL  
2.0  
2.4  
2.8  
V
PSENSE register  
EPSL、EPSH = ”1”  
RSENSE register  
ERS = ”1”  
pull-up resistor is not  
connected  
PSENSE pull-up resistor  
RPU  
RPD  
ILPS  
ILRS  
200  
0.5  
-2  
500  
2
1000  
kΩ  
MΩ  
µA  
RSENSE pull-down  
resistor  
PSENSE input leakage  
current  
RSENSE input leakage  
current  
4
2
2
−
Pull-down resistor is not  
connected  
-2  
−
µA  
9/30  
FEDL5238-10  
ML5238  
•
AC CHARACTERISTICS  
VDD=7 to 80V，GND=0V，Ta=-40 to +85°C，VREG output no-loaded  
Parameter  
/CS-SCK setup time  
SCK-/CS hold time  
SCK “H” pulse width  
SCK “L” pulse width  
SCK-SDI setup time  
SCK-SDI hold time  
SCK-SDO output delay time  
/CS “H” pulse width  
Symbol  
Condition  
Min.  
100  
100  
500  
500  
50  
Typ.  
−
−
−
−
−
−
−
−
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tCSS  
tCSH  
tWH  
tWL  
−
−
−
−
−
−
−
−
−
−
−
−
−
−
400  
tDIS  
tDIH  
tDOD  
tCS  
50  
−
500  
−
tCSS  
tCS  
/CS  
tWH tWL  
tCSH  
SCK  
tDIH  
tDIS  
SDI  
tDOD  
Hi-Z  
Hi-Z  
SDO  
10/30  
FEDL5238-10  
ML5238  
◼
FUNCTIONAL DESCRIPTION  
•
MCU INTERFACE  
SPI interface is built in the ML5238.  
Setting and control is held by writing /reading control registers.  
/CS  
SCK  
A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0  
SDI  
Control register  
address  
Write data  
Read=”1”  
Write=”0”  
O7 O6 O5 O4 O3 O2 O1 O0  
Hi-Z  
Hi-Z  
SDO  
Read data  
Set the RW bit “0” to write data, and set the RW bit “1” to read data.  
•
CONTROL REGISTER  
Control register map is shown below.  
Initial  
Address  
Register  
R/W  
Register setting  
value  
00H  
00H  
00H  
00H  
00H  
00H  
01H  
02H  
03H  
04H  
NOOP  
VMON  
IMON  
FET  
PSENSE  
R/W  
R/W  
R/W  
R/W  
R/W  
No function assigned  
Battery cell voltage Measurement  
Current measurement setting  
FET setting  
PSENSE pin comparator setting  
Short current detection setting  
RSENSE pin comparator setting  
Power save, Power down control  
Internal Status  
05H  
RSENSE  
R/W  
00H  
06H  
07H  
POWER  
STATUS  
R/W  
R/W  
00H  
00H  
Upper 8 cell balancing switch ON/OFF  
setting  
Lower 8 cell balancing switch ON/OFF  
setting  
08H  
09H  
CBALH  
CBALL  
R/W  
R/W  
00H  
00H  
0AH  
others  
SETSC  
TEST  
R/W  
R/W  
00H  
00H  
Short current detecting voltage setting  
TEST (Don’t use)  
11/30  
FEDL5238-10  
ML5238  
1. NOOP REGISTER (ADRS = 00H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
NO7  
NO6  
NO5  
NO4  
NO3  
NO2  
NO1  
R/W  
0
NO0  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Initial value  
No function is assigned to NOOP register, there is no status changes in the LSI even if this register is  
written or read. In the read operation written data is read  
2. VMON REGISTER (ADRS = 01H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
OUT  
CN3  
CN2  
CN1  
CN0  
−
−
−
R
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Initial value  
VMON register sets the battery cell outputted to the VMON pin.  
Select the battery cell by CN0, CN1, CN2, CN3 bits, and OUT bit enable the output from VMON  
pin.  
OUT  
0
1
CN3  
−
0
0
CN2  
−
0
0
CN1  
−
0
0
CN0  
−
0
1
Battery cell selection  
VMON pin = 0V (initial value)  
V1 cell (lower most)  
V2 cell  
1
1
0
0
1
0
V3 cell  
1
0
0
1
1
V4 cell  
1
0
1
0
0
V5 cell  
1
0
1
0
1
V6 cell  
1
0
1
1
0
V7 cell  
1
0
1
1
1
V8 cell  
1
1
0
0
0
V9 cell  
1
1
0
0
1
V10 cell  
1
1
0
1
0
V11 cell  
1
1
0
1
1
V12 cell  
1
1
1
0
0
V13 cell  
1
1
1
0
1
V14 cell  
1
1
1
1
0
V15 cell  
1
1
1
1
1
V16 cell (upper most)  
12/30  
FEDL5238-10  
ML5238  
3. IMON REGISTER (ADRS = 02H)  
7
6
5
4
3
2
1
0
−
−
−
Bit name  
R/W  
OUT  
GCAL1 GCAL0 ZERO  
GIM  
R
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Initial value  
IMON register set the current measuring.  
GIM bit set the voltage gain of current measuring amplifier.  
GIM  
0
1
Voltage gain GIM  
10 times (initial value)  
50 times  
ZERO bit set the zero-correction of current measuring amplifier.  
ZERO  
ISP input  
Pin input  
GND level  
ISM input  
Pin input  
GND level  
0
1
Voltage gain of current measuring amplifier is corrected by GCAL0, GCAL1 bits.  
GCAL0 bit changes the ISP and ISM pin input to GND or internal reference voltage (20mV/100mV).  
GCAL1 bit changes the IMON pin output to internal reference voltage output.  
GCAL1 GCAL0  
ISP input  
Pin input  
ISM input  
Pin input  
GND level  
GND level  
Pin input  
IMON output  
Amplified output  
2V (typ)  
0
0
1
0
1
0
GIM=0  
GIM=1  
100mV  
20mV  
2V (typ)  
Pin input  
Amplified output  
Reference voltage  
output 100mV (typ)  
Reference voltage  
output 20mV (typ)  
GIM=0  
GIM=1  
100mV  
20mV  
GND level  
GND level  
1
1
If the ZERO bit is set “1”, setting GCAL1 and GCAL0 bits are neglected.  
OUT bit enables to output the current measuring amplifier from IMON pin. If zero correction and  
gain correction is held, OUT bit is set “1” too.  
OUT  
0
1
IMON pin output  
0V (initial value)  
Current measuring amplifier output  
Current measurement is executed with current sensin resistor (RSENSE) connected between ISP pin  
and ISM pin and by measuring input voltage difference between these pins.  
Voltage difference between ISP and ISM is converted to voltage, its center is 1.0V (typ), and  
outputted from IMON pin. IMON pin output voltage VIMON is given by the following equation with  
the current sensing resistor RSENSE and its current ISENSE  
.
VIMON (ISENSE × RSENSE) × GIM + 1.0  
=
13/30  
FEDL5238-10  
ML5238  
The circuit of current measuring amplifier is shown below.  
ML5238  
PACK(+)  
Current measuring amplifier  
R1=R2×GIM  
R2  
ISM  
ISP  
R1  
GCAL0  
ZERO  
GCAL0  
ZERO  
RSENSE  
PACK(-)  
R1  
IMON  
GCAL1  
R2  
GCAL0  
20mV/100mV  
ZERO  
1.0V  
If the current is zero,VIMON = 1.0V, in the discharging state, VIMON > 1.0V, in the charging state,  
VIMON < 1.0V.  
When the ZERO bit is set “1”, the input of ISM pin and ISM pin is switched to GND level in the  
LSI and set the input difference voltage of the current measuring amplifier to zero. The IMON pin  
output voltage in this state is set as the reference voltage of zero current, and internal 1.0V reference  
voltage and offset voltage of amplifier is corrected.  
If the GCAL0 bit is set “1”; the ISM pin input is switched to GND level in the LSI; the ISP pin  
input is switched to 100mV (internal reference voltage) if the GIM bit is “0”, and else if GIM bit is “1”  
the ISP pin input is switched to 20mV (internal reference voltage). The gain error is corrected with the  
difference between the IMON output voltage at this state and it at current zero, and internal reference  
voltage.  
Internal reference voltage is outputted from IMON pin by setting the GCAL1 bit “1”.  
Short current detection characteristic is not depended on the IMON pin output setting.  
14/30  
FEDL5238-10  
ML5238  
The example flowchart of calibration for current measuring amplifier is shown below.  
(Voltage gain is 10)  
START  
IMON  
Write IMON register “12H” and set the current zero.  
Write = 12H  
Measure IMON output  
Voltage  
Measure the IMON pin output voltage when the  
current is zero with external ADC. Store its result in  
the variable VIM0.  
IMON  
Write IMON register “14H” and set the IMON output  
Write = 14H  
the amplified internal reference voltage.  
Measure IMON output  
voltage  
Measure the IMON pin output voltage (amplified  
internal reference voltage) with external ADC. Store  
its result in the variable VIM1.  
IMON  
Write IMON register “1CH” and set the IMON output  
the internal reference voltage.  
Write = 1CH  
Measure IMON output  
voltage  
Measure the IMON pin output voltage (outputted  
internal reference voltage) with external ADC. Store  
its result in the variable VR.  
Current correcting  
expression is  
Calculate the voltage gain and zero correcting value  
with VIM0, VIM1 and VR.  
Voltage gain: GIM = (VIM1-VIM0)/VR  
Zero correcting value: VIMZ = VIM0  
Measured current ISENSE is given with the following  
expression.  
END  
Current sensing resistor = RSENSE  
IMON voltage measured value = VIMON  
ISENSE = (VIMON - VIMZ) / GIM / RSENSE  
15/30  
FEDL5238-10  
ML5238  
4. FET REGISTER (ADRS = 03H)  
7
6
5
4
3
2
1
0
−
−
−
−
−
Bit name  
R/W  
DRV  
CF  
R/W  
0
DF  
R
0
R
0
R
0
R/W  
0
R
0
R
0
R/W  
0
Initial value  
FET register control the turn ON/OFF of the C_FET and D_FET pin, and read the state of its output.  
DF bit sets the D_FET pin output state. If the short current is detected, the DF bit is automatically  
cleared to ”0”. Because the DF bit is not automatically set “1” even if the state is changed from short  
detection to normal state, external MCU must set this bit “1”.  
DF  
0
1
Discharge FET  
OFF （initial value）  
ON  
D_FET pin output  
0V  
14V (typ)  
CF bit set the C_FET pin output state. If the short current is detected, the CF bit is automatically  
cleared tot “0”. Because the CF bit is not automatically set “1” even if the state is changed from short  
detection to normal state, external MCU must set this bit “1”.  
CF  
0
1
Charge FET  
OFF (initial value)  
ON  
C_FET pin output  
Hi-Z  
14V (typ)  
DRV bit set the output current drive capacity of internal FET driver. If the DRV bit is set “1”, the  
rising time of D_FET, C_FET pins is short.  
The duration to set the DRV bit “1” should be set depend on the capacitance load of the D_FET,  
C_FET pins. DRV bit should be cleared to “0”, after the D_FET, C_FET pin output level is fully risen  
to “H”.  
If the DRV bit is left “1”, power consumption or the “H” output voltage of D_FET, C_FET might be  
higher than the level specified in the electrical characteristics.  
DRV  
0
1
FET driver output capacity  
Normal (initial value)  
enhanced  
16/30  
FEDL5238-10  
ML5238  
5. PSENSE REGISTER (ADRS = 04H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
EPSH  
IPSH  
RPSH  
PSH  
EPSL  
IPSL  
RPSL  
R/W  
0
PSL  
R/W  
0
R/W  
0
R/W  
0
R
0
R/W  
0
R/W  
0
R
0
Initial value  
PSENSE register set the parameters of comparators which detect charger connection/disconnection  
with PSENSE pin input.  
Two comparators with difference threshold are connected to PSENSE pin to manage ON and OFF  
states of discharge FET.  
For detecting charger disconnection in the state of discharge FET ON, low level threshold (0.2V  
(typ) ) type comparator is selected, because PSENSE pin voltage is clamped by the body-diode of  
charge FET.  
Low level threshold type comparator is selected mainly for detecting charger open in the state of  
charge over-current detected,  
Parameters of the low level threshold type comparator for detecting the charger open is set in EPSL,  
IPSL, and RPSL bits. Comparator output is assigned to PSL bit.  
EPSL bit set the run/stop of the comparator for detecting charger open. If EPSL bit is set running,  
500kΩ pull-up resistor is connected to PSENSE pin in the LSI.  
State of comparator for  
EPSL  
PSENSE pin status  
detecting charger open  
Stop (initial value)  
Run  
0
1
Hi-Z (initial value)  
500kΩ pull-up  
IPSL bit enables asserting the interrupt from /INTO pin, if the output of comparator detecting  
charger open (PSL bit) is changed from “0” to “1”. IPSL bit should be set “1” more than 1 msec later  
from setting the EPSL bit “1”.  
IPSL  
0
1
Interrupt enable  
Disable (initial value)  
enable  
RPSL bit indicates the interrupt assertion if the output of comparator detecting charger open (PSL  
bit) is changed from “0” to “1”. To clear this interrupt, write “0” in the RPSL bit. Writing “1” in the  
RPSL bit is neglected. If IPSL bit is “0”, RPSL bit is fixed to “0”.  
RPSL  
Interrupt occurred  
No interrupt (initial value)  
Interrupted  
0
1
PSL bit indicates the state of charger connected. If the EPSL bit is “0”, PSL bit is fixed to “0”.  
Writing “1” in the PSL bit is neglected.  
PSL  
Charger connection  
Charger connected  
(initial value)  
PSENSE pin voltage  
0
0.2V or less  
1
Charger disconnected  
Larger than 0.2V  
17/30  
FEDL5238-10  
ML5238  
For detecting charger disconnection in the state of discharge FET OFF, high level threshold  
(VDD×0.75) type comparator is selected, because PSENSE pin voltage rise up to power supply voltage  
(VDD).  
High level threshold comparator is selected mainly for detecting charger open if the status changes to  
power down state.  
Parameters of the high level threshold type comparator for detecting the charger open is set in EPSH,  
IPSH, and RPSH bits. Comparator output is assigned to PSH bit.  
EPSH bit set the run/stop of the comparator for detecting charger open. If EPSH bit is set running,  
500kΩ pull-up resistor is connected to PSENSE pin in the LSI.  
State of comparator for  
EPSH  
PSENSE pin status  
detecting charger open  
Stop （initial value）  
Running  
0
1
Hi-Z (initial value)  
500kΩ pull-up  
IPSH bit enables asserting the interrupt from /INTO pin, if the output of comparator detecting  
charger open (PSH bit) is changed from “0” to “1”. IPSH bit should be set “1” more than 1 msec later  
from setting the EPSH bit “1”.  
IPSH  
0
1
Interrupt enable  
Disable (initial value)  
enabled  
RPSH bit indicates the interrupt assertion if the output of comparator detecting charger open (PSH  
bit) is changed from “0” to “1”. To clear this interrupt, write “0” in the RPSH bit. Writing “1” in the  
RPSH bit is neglected. If IPSH bit is “0”, RPSH bit is fixed to “0”.  
RPSH  
Interrupt occurred  
No interrupt (initial value)  
interrupted  
0
1
PSH bit indicates the state of charger connected. If the EPSH bit is “0”, PSH bit is fixed to “0”.  
Writing “1” in the PSH bit is neglected.  
PSH  
Charger connection  
Charger connected  
(initial value)  
PSENSE pin voltage  
VDD×0.75 or less  
0
1
Charger disconnected  
Larger than VDD×0.75  
18/30  
FEDL5238-10  
ML5238  
6. RSENSE REGISTER (ADRS = 05H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
ESC  
ISC  
RSC  
SC  
ERS  
IRS  
RRS  
R/W  
0
RS  
R/W  
0
R/W  
0
R/W  
0
R
0
R/W  
0
R/W  
0
R
0
Initial value  
RSENSE register set the parameters of detecting short current and the parameters of comparator  
which detect load connection/disconnection with RSENSE pin input.  
ESC bit set the run/stop of the circuit detecting short current.  
Status of the circuit detecting  
ESC  
short current  
0
1
Stop (initial value)  
Run  
ISC bit enables asserting the interrupt from /INTO pin, if the short current is detected.  
ISC  
0
1
Interrupt enable  
Disable (initial value)  
enable  
RSC bit indicates the interrupt assertion if the short current is detected. To clear the interrupt, write  
“0” in the RSC bit. Writing “1” in the RSC bit is neglected. If ISC bit is “0”, RSC bit is fiexed to “0”.  
RSC  
0
1
Interrupt occurred  
No interrupt (initial value)  
interrupted  
SC bit indicates the output from the comparator detecting short current.  
If the SC bit is changed from “0” to “1”, charging the capacitor connected to CDLY pin is started. If  
this charging is finished, the RSC bit is automatically changed to “1” and the DF bit and the CF bit in  
the FET register is automatically cleared to “0”. If the short current status is cleared before charging  
the capacitor connected to CDLY pin is finished, charging the CDLY pin is stopped and the CDLY pin  
is fixed to GND level.  
If the ESC bit is “0”, SC bit is fixed to “0”. Writing “1” in the SC bit is neglected.  
Status of the comparator  
SC  
0
ISP-ISM voltage  
output detecting short current  
Short current is not detected  
(initial value)  
Short current detecting  
voltage or lower  
Higher than short current  
detecting voltage  
1
Short current is detected  
Short current detecting delay time is set with the charging time of capacitor CDLY which is connected  
to CDLY pin ; calculated with following formula.  
Short current detecting delay time tsc [s] = CDLY[nF] ×100  
19/30  
FEDL5238-10  
ML5238  
ERS bit set the run/stop of the comparator for detecting load open. If ERS bit is set running, 2MΩ  
pull-down resistor is connected to RSENSE pin in the LSI.  
State of comparator for  
ERS  
RSENSE pin status  
detecting load open  
Stop (initial value)  
Running  
0
1
Hi-Z (initial value)  
2MΩ pull-down  
IRS bit enables asserting the interrupt from /INTO pin, if the output of comparator detecting load  
open (RS bit) is changed from “0” to “1”. IRS bit should be set “1” more than 1 msec later from setting  
the ERP bit “1”.  
IRS  
0
1
Interrupt enable  
Disable (initial value)  
enabled  
RRS bit indicates the interrupt assertion if he output of comparator detecting load open(RS bit) is  
changed from “0” to “1”. To clear this interrupt, write “0” in the RRS bit. Writing “1” in the RRS bit is  
neglected. If IRS bit is “0”, RRS bit is fixed to “0”.  
RRS  
0
1
Interrupt occurred  
No interrupt (initial value)  
interrupted  
RS bit indicates the state of load connected. If the ERS bit is “0”, RS bit is fixed to “0”. Writing “1”  
in the RS bit is neglected.  
RS  
0
1
Load connection  
Load connected (initial value)  
Load disconnected  
RSENSE pin voltage  
2.4V or higher  
Lower than 2.4V  
20/30  
FEDL5238-10  
ML5238  
7. POWER REGISTER (ADRS = 06H)  
7
6
5
4
3
2
1
0
−
−
−
−
−
Bit name  
R/W  
PUPIN  
PDWN  
PSV  
R
0
R
0
R
0
R/W  
0
R
0
R
0
R
0
R/W  
0
Initial value  
Power register control the power save and the power down.  
PSV bit set the state transition to power save.  
PSV  
0
1
Power save  
Normal state (initial value)  
Power save state  
In the power save state, circuits for VREG output and VREF output is operating, cell voltage  
measuring and current measuring is stopped, and the power consumption is reduced. FET driving and  
short detecting circuit works in the power save state. Comparators in the PSENSE pin and the  
RSENSE pin are stopped.  
Clearing the PSV bit to “0” and the status is recovered from power save state to normal state.  
To set the comparators in the PSENSE pin and the RSENSE pin running, set these comparators to  
run after recovering from the power save state.  
PDWN bit set the state transition to power down  
PDWN  
Power down  
Normal state (initial value)  
Power down state  
0
1
If the PDWN bit is set “1”, 500kΩ pull-up resistor is automatically connected to PSENSE pin in the  
LSI and all the circuit is stopped, and the /RES pin output is “L”.  
Before setting the PDWN bit “1”, C_FET and D_FET should be set OFF and charger disconnection  
should be confirmed with the PSENSE register. When the /PUPIN pin input is “L”, even if PDOWN  
bit is set to “1”, the state doesn’t get changed to power-down until the /PUPIN pin input rises to “H”.  
Before setting the PDWN bit “1”, it should be confirmed that /PUPIN pin is not “L” by reading the  
PUPIN bit.  
PUPIN  
/PUPIN pin state  
“H” level  
0
1
“L” level  
If charger connection is detected with PSENSE pin or if /PUPIN pin is asserter “L” input, the LSI is  
recovered from power down state to normal state.  
In the power down state, VREG output which is power supply for external micro-computer is set  
GND level. In recovering from power down state, every initial setting should be held after VREG is  
fully risen and after /RES pin output is fully changed from “L” level to “H” level.  
21/30  
FEDL5238-10  
ML5238  
8. STATUS REGISTER (ADRS = 07H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
RSC  
RRS  
RPSH  
RPSL  
INT  
PSV  
CF  
R
DF  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Initial value  
0
STATUS register indicates each status.  
DF bit indicates the D_FET pin output status.  
DF  
0
1
D_FET pin status  
OFF (initial value)  
ON  
CF bit indicates the C_FET pin output status.  
CF  
0
1
C_FET pin status  
OFF (initial value)  
ON  
PSVbit indicates the power save state.  
PSV  
Power save state  
0
1
Normal state (initial value)  
Power save state  
INT bit indicates the /INTO pin output status.  
INT  
0
1
/INTO pin output status  
No interrupt (initial value)  
Interrupted  
RPSL bit indicates interrupt status of charger disconnecting interrupt if charge over-current detected.  
RPSL  
Status of charger disconnecting interrupt if charge over-current detected.  
No interrupt (initial value)  
0
1
Charger disconnecting interrupt  
RPSH bit indicates interrupt status of charger disconnecting interrupt if the status is power down.  
RPSH  
Status of charger disconnecting interrupt if the status is power down  
No interrupt (initial value)  
0
1
Charger disconnecting interrupt  
RRS bit indicates interrupt status of load disconnecting interrupt  
RRS  
0
1
Status of load disconnecting interrupt  
No interrupt (initial value)  
Load disconnecting interrupt  
RSC bit indicates interrupt status of short current detecting interrupt.  
RSC  
0
1
Status of short current detecting interrupt  
No interrupt (initial value)  
Short current detecting interrupt.  
22/30  
FEDL5238-10  
ML5238  
9. CBALH REGISTER (ADRS = 08H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
SW16  
SW15  
SW14  
SW13  
SW12  
SW11  
SW10  
R/W  
0
SW9  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Initial value  
CBALH register set the cell balancing switches turning ON/OFF of upper 8 cells.  
SW16~SW9 bit sets switches turning ON/OFF of each cell.  
SW16 SW15 SW14 SW13 SW12 SW11 SW10 SW9  
Switch ON/OFF  
Upper 8 cells OFF  
(initial value)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
V9-V8 pin switch ON  
V10-V9 pin switch ON  
V11-V10 pin switch ON  
V12-V11 pin switch ON  
V13-V12 pin switch ON  
V14-V13 pin switch ON  
V15-V14 pin switch ON  
V16-V15 pin switch ON  
More than one switch can be turned on in the same time, but following settings are inhibited because  
internal cell balancing switch might be broken.  
(1) Side-by-side cell balancing switches are inhibited to be turned on in the same time.  
(2) the cell balancing switches of both side of a cell balancing switch which is turned off is inhibited  
to be turned on in the same time.  
OFF  
ON  
ON  
OFF  
ON  
ON  
OFF  
OFF  
IC heats by cell balancing current and cell balancing switch resistor, restrict the number of switches  
of ON and time of ON, in order to keep the power consumption of cell balancing switch less than  
allowable power dissipation,  
If cell voltage is outputted from VMON pin, the voltage of a cell whose cell balancing switch is  
turned on is measured as the voltage difference between two ports of cell balancing switch.  
23/30  
FEDL5238-10  
ML5238  
10. CBALL REGISTER (ADRS = 09H)  
7
6
5
4
3
2
1
0
Bit name  
R/W  
SW8  
SW7  
SW6  
SW5  
SW4  
SW3  
SW2  
R/W  
0
SW1  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Initial value  
CBALL register set the cell balancing switches turning ON/OFF of lower 8 cells.  
SW8~SW1 bit sets switches turning ON/OFF of each cell.  
SW8  
SW7  
SW6  
SW5  
SW4  
SW3  
SW2 SW1  
Switch ON/OFF  
lower 8 cells OFF  
(initial value)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
V1-V0 pin switch ON  
V2-V1 pin switch ON  
V3-V2 pin switch ON  
V4-V3 pin switch ON  
V5-V4 pin switch ON  
V6-V5 pin switch ON  
V7-V6 pin switch ON  
V8-V7 pin switch ON  
More than one switch can be turned on in the same time, but following settings are inhibited because  
internal cell balancing switch might be broken.  
(1) Side-by-side cell balancing switches are inhibited to be turned on in the same time.  
(2) the cell balancing switches of both side of a cell balancing switch which is turned off is inhibited  
to be turned on in the same time.  
OFF  
ON  
ON  
OFF  
ON  
ON  
OFF  
OFF  
IC heats by cell balancing current and cell balancing switch resistor, restrict the number of switches  
of ON and time of ON, in order to keep the power consumption of cell balancing switch less than  
allowable power dissipation,  
If cell voltage is outputted from VMON pin, the voltage of a cell whose cell balancing switch is  
turned on is measured as the voltage difference between two ports of cell balancing switch.  
24/30  
FEDL5238-10  
ML5238  
11. SETSC REGISTER (ADRS = 0AH)  
7
6
5
4
3
2
1
0
−
−
−
−
−
−
Bit name  
R/W  
SC1  
R/W  
0
SC0  
R
0
R
0
R
0
R
0
R
0
R
0
R/W  
0
Initial value  
SETSC register sets the short current detecting voltage.  
Short current detecting voltage is selected with SC0 and SC1 bit depend on current sensing resistor  
value.  
Short current detecting  
Short current detecting current if  
Current sensing resistor value = 3mΩ  
SC1  
SC0  
voltage  
0.1V (initial value)  
0.2V  
0
0
1
1
0
1
0
1
33.3A  
66.6A  
100A  
0.3V  
0.4V  
133.3A  
•
CONNECTING POWER SUPPLY (VDDP, VDD, VDD_SW)  
VDDP pin is the power supply pin only for internal 3.3V regulator (VREG pin, VREF pin). If the output  
current of 3.3V regulator is large, it is recommended to make the voltage drop of RC filter resistor (for  
removing noise at the VDDP pin) smaller than 1V.  
VDD_SW pin is the power supply pin only for cell selection switches and cell balancing switches.  
Connect this pin to VDD via 51Ω resistor.  
VDD pin is the power supply pin for all the circuit other than internal 3.3V regulator and cell selection  
switches and cell balancing switches.  
Power supply path  
for external circuit  
ML5238  
VDD  
VDDP  
VDD_SW  
Power supply for  
VREG  
external circuit  
VREF  
GND  
25/30  
FEDL5238-10  
ML5238  
•
POWER-ON / POWER-OFF SEQUENCE  
POWER-ON: Recommended battery connecting sequence is; connect the GND first, then connect the  
VDD, VDDP, VDD_SW, and after doing that connect each cells from lower level.  
When the sequence is not kept, absolute maximum rating is exceeded across the LSI and it may damage  
input pins of Vn+1 pin and Vn.  
POWER-OFF: Recommended battery disconnecting sequence is; disconnect each cell from higher level  
first, then disconnect the VDD, VDDP, VDD_SW, and lastly disconnect the GND.  
And also in testing and evaluating with using a battery simulator cases, pay attention to the connect and  
disconnect sequence not to make an excessive voltage to absolute maximum rating of each Vn+1 pin and Vn  
pin.  
As shown in the diagram bellow, it is recommend to use Zener diode circuit for input pin protection.  
Prior to decision, however, it is suggested that a good enough evaluation should be performed with Zener  
diode.  
ML5238  
Vn+1  
6.2V  
Vn  
6.2V  
Vn-1  
Prior to battery connection to Vn pins of LSI, all of cell must be in a serial connection each other.  
Connecting of individual battery cells to Vn pins of LSI without being a serial connection is forbidden  
because there is a possibility that absolute maximum rating is exceeded across the LSI and it may damage  
input pins of Vn+1 and Vn.  
Power supply voltage rising time of power-on, power off order, power supply voltage falling time of  
power-off is not defined.  
Following the power-on, the ML5238 normally enter into normal state. ML5238 may rarely enter into the  
Power down state by the chattering or another reason during the connection of the battery cells. In this case,  
input the voltage lower than or equal to the Detecting charger connection PSENSE pin voltage (VPC) to  
PSENSE pins, or input the “L” level to the /PUPIN pin, in order to power-up.  
Else after the power-on or after the power-up, cell voltage measurement and current measurement should  
be done after the internal analog circuit is settled. To get the settling time of analog circuit, confirm the  
output settling time of VREF pin, VMON pin, and IMON pin in the application system.  
•
CELL CONNECTING  
If the number of connected cells is less than 16, connecting order in following table is recommended.  
Number of  
Connected  
V15 to  
V10  
V16  
V9  
V8  
V7  
V6  
V5  
V4  
V3  
V2  
V1  
V0  
cells  
15  
14  
13  
12  
11  
10  
9
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
GND  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
GND  
GND  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
cell  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
VDD_SW  
cell  
cell  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
cell  
cell  
cell  
cell  
cell  
cell  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
cell  
cell  
cell  
cell  
cell  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
cell  
cell  
cell  
cell  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
cell  
cell  
cell  
GND  
GND  
GND  
GND  
GND  
GND  
cell  
cell  
GND  
GND  
GND  
GND  
GND  
8
cell  
GND  
GND  
GND  
GND  
7
GND  
GND  
GND  
6
5
26/30  
FEDL5238-10  
ML5238  
◼
EXAMPLE OF APPLICATION CIRCUIT  
(10 cells, charge/discharge path is isolated)  
PACK(+)  
MCU  
RVDDP  
CVDDP  
CPUP  
CREG  
CRES  
RVDD  
CVDD  
RSW  
CREF  
RCEL  
CCEL  
VDD  
VDD_SW  
V16  
1
2
3
4
5
6
7
8
9
33 VREF  
32 VMON  
31 IMON  
30 CDLY  
29 NC  
28 PSENSE  
27 RSENSE  
26 NC  
V15  
V14  
V13  
V12  
V11  
V10  
V9 10  
V8 11  
CDLY  
ML5238  
25 C_FET  
24 NC  
23 D_FET  
RRS  
RPS  
RISIN  
CISIN  
RG  
RG  
PACK(-)  
CHG(-)  
RIS  
RGS  
◼
PARTS LIST  
Symbol  
RVDD  
Symbol  
RISIN  
CISIN, CRES  
CREG, CREF  
CDLY  
Value  
1kΩ  
0.1F  
4.7F  
Value  
510Ω  
10F or more  
100Ω  
10F or more  
51Ω  
CVDD  
RVDDP  
CVDDP  
RSW  
1nF to 10nF  
CPUP  
1F  
RG  
RGS  
RRS  
RPS  
10kΩ  
1MΩ  
10kΩ  
1kΩ  
RCEL  
CCEL  
RIS  
18Ω or more  
0.1F or more  
3mΩ  
Notice: Example of application circuit and the recommend value to parts list shall not be guaranteed performance  
under all of conditions. Prior to decision, however, it is suggested that a good enough evaluation should  
be done.  
27/30  
FEDL5238-10  
ML5238  
◼
PACKAGE DIMENSIONS  
Notes for Mounting the Surface Mount Type Package  
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in  
storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions (reflow method,  
temperature and times).  
28/30  
FEDL5238-10  
ML5238  
◼
REVISION HISTORY  
Page  
Previous Current  
Description  
Document No.  
Date  
Edition  
Edition  
FEDL5238-01  
FEDL5238-02  
FEDL5238-03  
FEDL5238-04  
2013.04.24  
2013.05.16  
2013.06.06  
2013.09.25  
First Edition  
−
−
1
1
“Note” is revised.  
1,30  
1,30  
“Note” and “Notice” are revised.  
Absolute maximum rating :  
Add notice to Input voltage VIN1  
Power-on, Power-off sequence :  
5
5
26  
27  
26  
27  
Add notice to damage and recommend circuit for  
input pin protection.  
Example of application circuit :  
Add Zener diode for input pin protection.  
Symbols of “FET “H” output voltage” and “FET  
“L” output voltage” are corrected.  
Package dimension is revised.  
FEDL5238-05  
FEDL5238-06  
2014.01.22  
2014.03.12  
6
6
28  
28  
Detection Voltage Characteristics(TA=25℃):  
Minimum and Maximum rating of short current  
detecting voltage at SC1,SC0 bit =(0,0) are  
revised.  
7
8
7
8
Detection Voltage Characteristics(TA=-10~60℃):  
Minimum and Maximum rating of short current  
detecting voltage at SC1,SC0 bit =(0,0) are  
revisd.  
FEDL5238-07  
FEDL5238-08  
2016.01.12  
2020.04.10  
Voltage and Current Monitoring Characteristics,  
Cell voltage measurement range is added  
V16 pin description is revised.  
3
3
27  
27  
Application circuit exapmle; capacitor connection of  
lowest cell is modified.  
FEDL5238-09  
FEDL5238-10  
2020.12.1  
2023.6.9  
-
-
Changed Company name  
30  
28  
30  
28  
Changed “Notes”  
Changed "Package dimensions"  
29/30  
FEDL5238-10  
ML5238  
Notes  
1) The information contained herein is subject to change without notice.  
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,  
application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating  
conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any  
malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products  
outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within such  
usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.  
Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of LAPIS  
Technology Products, please take safety at your own risk measures such as complying with the derating  
characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe  
procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.  
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate  
the standard operation of semiconductor products and application examples. You are fully responsible for the  
incorporation or any other use of the circuits, software, and information in the design of your product or system.  
And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS  
Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising  
from the use of these circuits, software, and other related information.  
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS  
Technology or any third party with respect to LAPIS Technology Products or the information contained in this  
document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and application  
examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute,  
concerning such rights owned by third parties, arising out of the use of such technical information.  
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer  
systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our  
Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a  
LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,  
trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical  
systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all  
liability for any losses and damages incurred by you or third parties arising by using the Product for purposes not  
intended by us. Do not use our Products in applications requiring extremely high reliability, such as aerospace  
equipment, nuclear power control systems, and submarine repeaters, etc.  
6) The Products specified in this document are not designed to be radiation tolerant.  
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document.  
However, LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall  
have no responsibility for any damages arising from any inaccuracy or misprint of such information.  
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS  
Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance  
with any applicable laws or regulations.  
9) When providing our Products and technologies contained in this document to other countries, you must abide by  
the procedures and provisions stipulated in all applicable export laws and regulations, including without  
limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..  
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this  
document or LAPIS Technology's Products.  
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS  
Technology.  
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.  
Copyright 2023 LAPIS Technology Co., Ltd.  
2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan  
https://www.lapis-tech.com/en/  
30/30  

ML5238 相关器件

型号 制造商 描述 价格 文档
ML5238GA ROHM Cell voltage, current　measurementshort current detectionFET driver built-incell balance switch built-inmicrocontroller Interface: SPIBuilt-in regulator for external microcontroller 获取价格
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ML5239TB ROHM Cell voltage, current　measurementmultistage connectionmicrocontroller Interface : SPICell balancing switch driving pin 获取价格
ML5241 ROHM 电池电压检测断线检测警报输出睡眠功能省时测试模式 获取价格
ML5241-001MD ROHM Overvoltage detectionOpen-wire detectionAlarm outputSleep functionQuick test mode 获取价格
ML5243 ROHM 支持3～5节电池、具有电池电压、电流、温度和断线检测功能的电池监控保护LSI电池电压检测过电流检测温度检测断线检测充放电许可信号输出短路电流检测省时测试模式 获取价格
ML5243-001TD(Tray) ROHM 3 to 5-cells supported, cell voltage, current, temperature,open wire protection LSIOvervoltage 获取价格
ML5243-002TD(Taping) ROHM 3 to 5-cells supported, cell voltage, current, temperature,open wire protection LSIOvervoltage 获取价格
ML5243-003TD(Taping) ROHM 3 to 5-cells supported, cell voltage, current, temperature,open wire protection LSIOvervoltage 获取价格
ML5243-004TD(Taping) ROHM 3 to 5-cells supported, cell voltage, current, temperature,open wire protection LSIOvervoltage 获取价格

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