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ML5248

更新时间：2025-07-10 05:36:08
品牌：ROHM
描述：电池电压、电流和温度测量短路电流检测内置高边NMOS-FET驱动器MCU接口：I2C内置电池均衡开关内置外部微控制器用电源

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ML5248 概述

电池电压、电流和温度测量短路电流检测内置高边NMOS-FET驱动器MCU接口：I2C内置电池均衡开关内置外部微控制器用电源

ML5248 数据手册

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FEDL5248-02  
30, November. 2020  
ML5248  
7-Series Cell Li-ion Rechargeable Battery Protection analog-front-end IC  
■ General Description  
The ML5248 is a analog-front-end protection IC for the 7-cell Li-ion rechargeable battery pack. It has  
individial cell voltage monitoring and charge/discharge current monitoring function, and external MCU controls  
each cell overcharge/undervoltage protection and overcurrent protection.  
And the ML5248 detects short current without external MCU and automatically turns on or turns off the  
external charege/discharge NMOS-FET.  
■ Features  
• 3 to 7 cell high precision cell voltage monitoring function : output cell voltage multiplied by 0.5 from  
VMON pin  
• Built-in cell balancing switch on each cell : Switch ON resistance 6Ω(typ)  
• charge/discharge current monitoring function :  
IMON pin outputs ISP-ISM voltage amplified by selected rate.  
Voltage amplifying rate selection: 10 / 50  
• short-current protection function :  
Detection threshold voltage is selected from; ISP-ISM pin voltage =50mV/100mV/150mV/200mV(typ)  
• external charge/discharge FET control : Built-in gate driver for highside NMOS-FET  
• MCU interface : I2C compatible serial interface  
• Built-in 3.3V regulator for and external MCU : 10mA (max) output current  
• Built-in voltage reference for extrernal ADC (2.5V) : output currnet 100μA (max)  
• PSNS/DFS pin voltage monitoring function  
• Low current consumption  
Operating state  
Power-save state  
Power-down state  
: 32A(typ), 65A（max）  
:
2A(typ), 10A(max)  
: 0.1A(typ), 1A(max)  
• supply voltage  
: +5V to +31.5V  
• operating temperature : -40℃ to +85℃  
• package  
: 30 pinSSOP (P-SSOP30-56-0.65-ZK6)  
Note) This product is not intended for automotive use and for any equipment, device, or system that requires a  
specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace  
machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure whether  
your application corresponds to such special purposes, please contact your local ROHM sales  
representative in advance.  
Confidential  
FEDL5248-02  
ML5248  
■ Block Diagram  
CPLC  
DFS  
C_FET  
CPHD  
CFS  
CPLD  
CPHC  
D_FET  
VDD  
Charge Pump & FET Driver  
Charger  
V7  
V6  
PSNS  
Divider  
Detector  
VDDR  
VREG  
V5  
V4  
V3  
Clock stop  
Detector  
Voltage  
Regulator  
Reference  
Generator  
Clock  
Generator  
VREF  
SCL  
SDA  
V2  
V1  
MCU I/F  
Cell Voltage  
Monitor  
Control  
Logic  
/INTO  
/PUPIN  
V0  
Short  
Detector  
Current  
Monitor  
IMON  
GND  
VMON  
ISM ISP  
■ Pin Configuration (Top View)  
VDD  
VDDR  
V7  
1
30  
29  
28  
27  
26  
25  
24  
23  
22  
CFS  
2
3
C_FET  
CPHC  
CPLC  
CPLD  
CPHD  
D_FET  
DFS  
PSNS  
/PUPIN  
VREG  
VREF  
SCL  
4
5
6
7
8
9
V6  
V5  
V4  
V3  
V2  
V1  
V0  
GND  
ISM  
10  
11  
21  
20  
12  
13  
19  
18  
ISP  
IMON  
VMON  
SDA  
/INTO  
14  
15  
17  
16  
Confidential  
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FEDL5248-02  
ML5248  
■ Pin Description  
Pin No.  
1
Pin  
I/O  
Description  
Power supply input pin.  
VDD  
―
Connect an external CR filter for noise rejection.  
Power supply input pin only for internal regulator.  
Connect an external CR filter for noise rejection.  
Battery cell 7 positive terminal voltage input pin.  
2
3
VDDR  
V7  
―
I
Battery cell 7 negative terminal voltage input and battery cell 6positive terminal  
voltage input pin.  
4
5
6
V6  
V5  
V4  
I
I
I
Battery cell 6 negative terminal voltage input and battery cell 5 positive terminal  
voltage input pin.  
Battery cell 5 negative terminal voltage input and battery cell 4 positive terminal  
voltage input pin.  
Battery cell 4 negative terminal voltage input and battery cell 3 positive terminal  
voltage input pin. Should be connected to GND for the 3 cell series connected  
battery pack application.  
7
8
V3  
V2  
V1  
V0  
I
I
I
I
Battery cell 3 negative terminal voltage input and battery cell 2 positive terminal  
voltage input pin. Should be connected to GND for the 3 to 4cell series  
connected battery pack application.  
Battery cell 2 negative terminal voltage input and battery cell 1 positive terminal  
voltage input pin. Should be connected to GND for the 3 to 5 cell series  
connected battery pack application.  
9
Battery cell 1 negative terminal voltage input pin.  
10  
Should be connected to GND for the 3 to 6 cell series connected battery pack  
application.  
11  
12  
GND  
ISM  
―
Ground pin.  
Current sense resistor negative terminal voltage input pin. Connected to the  
negative terminal of the most negative battery cell.  
I
Current sense resistor positive termimal voltage input pin. The ISP pin level  
should be higher than the ISM pin level in discharge state.  
Current monitor output pin. ISP-ISM voltage multiplied by 10/50 is outputted.  
Cell voltage monitor output pin and PSNS and DFS pin voltage monitor pin.  
For cell voltage monitor, cell voltage multiplied by 0.5 is outputted. For PSNS  
and DFS pin voltage monitor, each voltage multiplied by 1/16 is outputted.  
Interrupt output pin for externla MCU. NMOS open drain output and output  
level is “L” if interrupt is asseerted.  
13  
14  
ISP  
I
IMON  
O
15  
VMON  
O
16  
/INTO  
O
17  
18  
19  
SDA  
SCL  
IO  
I
Serial interface data input/output pin. Should be pulled up externally.  
Serial interface clock input pin. Should be pulled up externally.  
2.5V reference level output . Shold be tied to GND through a 4.7μF capacitor.  
VREF  
O
Built-in 3.3V regulator output. Should be tied to GND through a 4.7μF  
capacitor. This pin can be used as power supply for an external MCU.  
VREG  
O
I
20  
Power-up trigger input pin. If input is “L” level, the state changes from  
power-down state to power-up state. A 1MΩ pull-up resistor is built-in  
between this pin and the VDD pin. should be connected capacitor larger than  
0.1μF between this pin and the GND pin.  
21  
/PUPIN  
Input pin for detecting the charger connection in power-down state.  
If the PSNS pin voltage is higher than VDD/2, this LSI power-up. The VMON  
pin can output the voltage of this pin multiplied by 1/16.  
22  
PSNS  
I
Confidential  
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ML5248  
Pin No.  
23  
Pin  
I/O  
Description  
D_FET pin charge pump reference voltage input pin. Should be tied to source  
pin of the extrernal charge/dischrarge Nch-FET. The VMON pin can output  
the voltage of this pin divided by 16.  
DFS  
I
Discharge Nch-FET control signal output pin. should be tied to the gate pin of  
the external Nch-FET. If this output is “ON”, output level is DFS pin voltage of  
+11V(typ), and if this output is “OFF”, output level is DFS pin voltage.  
Charge pump capacitor for D_FET drive is connected. Connect a capacitor  
with approximately twice the gate capacitance of the discharge Nch-FET,  
24  
25  
D_FET  
CPHD  
O
O
26  
27  
28  
CPLD  
CPLC  
CPHC  
O
O
O
between the CPHD and CPLD pins.  
Charge pump capacitor for C_FET drive is connected. Connect a capacitor  
with approximately twice the gate capacitance of the charge Nch-FET,  
between the CPHC and CPLC pins.  
Charge Nch-FET control signal output pin. Should be tied to the gate pin of  
the external Nch-FET. If this output is “ON”, output level is CFD pin voltage of  
+11V(typ), and if this output is “OFF”, output level is CFS pin voltage.  
C_FET pin charge pump reference voltage input pin. should be tied to to  
source pin of the external charge/discharge Nch-FET.  
29  
30  
C_FET  
CFS  
O
I
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FEDL5248-02  
ML5248  
■ Absolute Maximum Ratings  
（GND= 0 V, Ta = 25 °C）  
Item  
Symbol  
Condition  
Rating  
Unit  
Supply voltage  
VDD  
Applied to VDD, VDDR pins  
－0.3 to +50  
－0.3 to +6.5  
V
Applied to V7 to V0 pins  
Vn+1 – Vn pin voltage difference  
(Note1), V0 – GND pin voltage difference  
VIN1  
V
VIN2  
VIN3  
VIN4  
VIN5  
Applied to CFS,DFS,PSNS pins  
Applied to /PUPIN pin  
－0.3 to 50  
－0.3 to VDD+0.3  
－0.3 to VREG+0.3  
－0.3 to +4.8  
V
V
V
V
Input voltage  
Applied to ISM, and ISP pins  
Applied to SCL, SDA pins  
Applied to D_FET pin  
VDFS=DFS pin voltage  
VOUT1  
VOUT2  
VDFS－0.3 to +50.0  
V
V
Applied to C_FET pin  
VCFS=CFS pin voltage  
VCFS－0.3 to +50.0  
Output voltage  
VOUT3  
VOUT4  
Applied to SDA, /INTO and VREG pins  
Applied to VMON, IMON and VREF pins  
－0.3 to +4.8  
V
V
－0.3 to VREG+0.3  
If VDD=36.5V,  
VREF, SDA, /INTO, VMON, IMON,  
C_FET and D_FET  
Applied to VREG,  
Short-circuit  
output current  
IOS  
20  
mA  
Cell balancing  
current  
ICB  
PD  
Per one cell balancing switch  
100  
0.95  
125  
mA  
W
Allowable Power  
dissipation  
Ta=25℃  
Junction  
emperature  
TjMAX  
―
°C  
Package thermal  
resistance  
θja  
JEDEC 2 layer board  
105  
℃/W  
Storage  
temperature  
TSTG  
—
－55 to +150  
°C  
Note : When battery connecting and disconnecting , Vn+1 – Vn pin voltage may exeed absolute maximum rating  
and it may damage input pins. It is suggested enough evaluation.  
Package allowable power dissipation  
Package allowable power dissipation  
decreases as the atmosphere temperature  
(Ta) increase. If VREG pin output load current  
is large, make the power loss smaller than the  
value shown in this figure.  
Atmosphere temperature[℃]  
Confidential  
5/34  
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ML5248  
■ Recommended Operating Conditions  
Item  
Symbol  
VDD  
Condition  
Range  
5～31.5  
－40～85  
Unit  
V
Applied to VDD, VDDR pins  
If VREG output no-loaded  
Supply voltage  
Operating temperature  
Ta  
°C  
■ Electrical Characteristics  
⚫ DC Characteristics  
VDD=5 to 31.5V，GND=0 V，Ta=－40 to 85°C，VREG output no-loaded  
Symb  
ol  
Item  
Condition  
Min.  
Typ.  
—
Max.  
Unit  
V
Digital "H" input voltage  
VIH  
―
0.8×VREG  
VREG  
(Note 1)  
Digital "L" input voltage  
VIL  
―
―
0
—
0.2×VREG  
V
(Note 1)  
/PUPIN pin ”H” input  
VIHP  
0.8×VDD  
—
VDD  
V
voltage  
/PUPIN pin ”L” input  
VILP  
―
0
—
–2  
―
–70  
0
—
0.2×VDD  
V
voltage  
Digital "H" input current  
IIH  
VIH = VREG  
VIL = GND  
VIH = VDD  
VDD=31.5V, VIL = GND  
IOL=1mA  
—
2
—
µA  
µA  
µA  
µA  
V
(Note 1)  
Digital "L" input current  
IIL  
—
(Note 1)  
/PUPIN pin ”H” input  
IIHP  
―
2
current  
/PUPIN pin ”L” input  
IILP  
－32  
―
－11  
0.2  
2
current  
Digital "L" output voltage  
VOL  
(Note 2)  
Digital output leakage  
IOLK  
VOH=3V  
VOL=0V  
–2  
―
µA  
current (Note 2)  
When measuring battery  
cell voltage,  
Cell balancing switches  
are off  
Cell monitoring pin  
IINVC  
－1.5  
－1.5  
―
―
5
µA  
µA  
Input current (Note 3)  
Except when measuring  
battery cell voltage,  
Cell balancing switches  
are off  
Cell monitoring pin  
Input leakage current  
(Note 3)  
IILVC  
1.5  
IOH=－1µA  
FET “H” output voltage  
VOHF  
VDD=VS=16V to 31.5V  
VS：CFS, DFS pin voltage  
IOL=1µA  
VDD=VS=16V to 31.5V  
VS：CFS, DFS pin voltage  
VS+8  
VS  
VS+11  
VS+13.5  
VS+0.3  
V
V
(Note 4)  
FET “L” output voltage  
VOLF  
―
(Note 4)  
Confidential  
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FEDL5248-02  
ML5248  
Symb  
ol  
Item  
Condition  
Min.  
3.0  
Typ.  
3.3  
Max.  
Unit  
V
VREG  
If output is no loaded  
10V＜VDD＜31.5V  
Output load current ＜  
10mA  
3.6  
3.6  
VREG1  
VREG2  
VREF1  
VREF2  
3.0  
3.0  
3.3  
3.3  
V
V
V
V
VREG output voltage  
5V＜VDD＜10V  
Output load current＜  
5mA  
3.6  
2.515  
2.55  
Ta＝0～60℃  
Output load current＜  
100uA  
2.485  
2.45  
2.50  
2.50  
VREF output voltage  
Ta＝－40～85℃  
Output load current＜  
100uA  
VREG low voltage  
Detection voltage  
VREG low voltage  
Release voltage  
VRD  
VRR  
―
―
2.2  
2.4  
2.45  
2.75  
2.7  
3.0  
V
V
Internal balancing FET  
VDS=0.3V  
VDD=16V to 31.5V  
Cell balancing switch ON  
resistance  
RBL  
2.5  
6
12  
Ω
Note 1: Applied to SCL, SDA pins  
Note 2: Applied to SDA, /INTO pins  
Note 3: Applied to V7 to V0 pins  
Note 4: Applied to C_FET, D_FET pins  
Confidential  
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FEDL5248-02  
ML5248  
● Supply Current Characteristics  
VDD=5 to 31.5V，GND=0 V，Ta=－40 to 85°C，VREG, VREF output no-loaded  
Symb  
ol  
Item  
Condition  
Min.  
Typ.  
Max.  
Unit  
No output loaded  
VMEN bit=”1”  
IMEN bit=”1”  
ENSC bit=”1”  
Current consumption in  
operation  
IDD  
―
32  
65  
µA  
１
Current consumption in  
Power save  
IDD2  
IDDS  
No output loaded  
No output loaded  
―
―
2
10  
µA  
µA  
Current consumption in  
power down  
0.1  
1.0  
(Note) These current consumption are sum of two current, VDD pin and VDDR pin.  
● Cell Voltage Monitor Output Characteristics (Ta=0～60℃）  
VDD=28V，GND=0V，Ta=0 to 60°C，VMON output no-loaded  
Symb  
ol  
Item  
Condition  
Min.  
0.1  
Typ.  
―
Max.  
4.5  
Unit  
V
Cell voltage monitor  
range  
VVMR  
VVMC4  
VVMC1  
VECEL4  
―
Cell voltage=4.2V  
No output loaded  
Cell voltage =1V  
No output loaded  
Cell voltage =4.2V  
No output loaded  
Cell voltage =1V  
No output loaded  
―
2.05  
0.4  
2.10  
0.50  
―
2.15  
0.6  
V
VMON output voltage  
(when cell voltage  
monitoring )  
V
-20  
+20  
mV  
Cell voltage  
measurement accuracy  
(Note1)  
VECEL1  
IOVM  
-30  
―
―
+30  
mV  
VMON output current  
VMON output settling  
time (when cell voltage  
monitoring)  
-100  
+100  
A  
tSVM  
No output loaded  
―
―
1
ms  
(Note 1) In case if corrected by calculation below with values stored in VGAIN register and OFFSET register.  
Cell voltage＝VGAIN × [ VMON output voltage ] + OFFSET  
SCL  
4.2V  
Cell  
voltage  
VMON  
0V  
tSVM  
tSVM  
state  
VMEN bit=”0”  
VMON output state  
VMEN bit=”1”  
VMEN bit=”0”  
VMON output state  
VMEN bit=”1”  
Confidential  
8/34  
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ML5248  
● Current monotor output characteristic (Ta=0 to 60℃)  
VDD=28V，GND=0V，Ta=0 to 60°C，shunt resistor=1mΩ, IMON output no-loaded  
Symb  
ol  
Item  
Condition  
Min.  
Typ.  
Max.  
Unit  
IMR1  
IMR0  
GIM bit = “0”  
-180  
-30  
―
―
36  
6
A
A
Current monitor range  
(Note1)  
GIM bit = “1”  
ISP-ISM voltage  
difference =0V  
GIM bit=”0”  
ISP-ISM voltage  
difference =0V  
GIM bit=”1”  
GIM bit=”0”  
GIM bit=”1”  
―
VIMON0  
0.4  
0.2  
0.5  
0.5  
0.6  
0.8  
V
V
IMON output voltage  
VIMON1  
GIM0  
GIM1  
IOIM  
9.5  
10  
50  
―
10.5  
52.5  
+100  
V/V  
V/V  
A  
IMON output voltage  
amplify rate (Note 2)  
IMON output current  
47.5  
-100  
ISP=SIM=0V  
GIM bit = “0”  
ZERO bit=”0”  
GIM bit=”0”  
GIM bit=”1”  
ISP、ISM pin input current  
IIS  
0.05  
0.46  
1.2  
A  
(Note 2)  
tSIM0  
tSIM1  
―
―
―
―
1
3
ms  
ms  
IMON output settling time  
(Note1) Current monitor range is positive in charging.  
(Note2) When 1kΩ resistors are connected to ISP pin and ISM pin each.  
SCL  
0V  
ISP-ISM  
IMON  
State  
0V  
0V  
tSIM1  
tSIM0  
IMEN bit=”0”  
GIM bit =”0”  
×10 amplified output  
state  
IMEN bit=”0”  
GIM bit =”1”  
×50 amplified output  
state  
IMEN bit=”1”  
GIM bit=”0”  
IMEN bit=”1”  
GIM bit=”1”  
Confidential  
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ML5248  
● Detection Threshold Characteristics (Ta=25℃）  
VDD=31.5V，GND=0 V，Ta=25°C，VREG output no-loaded  
Symb  
ol  
Item  
Condition  
Min.  
Typ.  
Max.  
Unit  
VSHRT0  
VSHRT1  
VSHRT2  
VSHRT3  
tSHRT0  
tSHRT1  
tSHRT2  
tSHRT3  
SC1,SC0 bit=(0,0)  
SC1,SC0 bit=(0,1)  
SC1,SC0 bit=(1,0)  
SC1,SC0 bit=(1,1)  
TD1,TD0 bit=(0,0)  
TD1,TD0 bit=(0,1)  
TD1,TD0 bit=(1,0)  
TD1,TD0 bit=(1,1)  
30  
85  
50  
70  
mV  
mV  
mV  
mV  
µs  
100  
150  
200  
100  
200  
300  
400  
115  
165  
215  
125  
250  
375  
500  
Short circuit detection  
threshold  
135  
185  
75  
150  
225  
300  
µs  
Short circuit detection  
delay time (Note1)  
µs  
µs  
Note1) Short circuit detection delay time assumes that there is no capacitor between ISM-ISP.  
● Detection Threshold Characteristics (Ta=0 to 60℃)  
VDD=31.5V，GND=0 V，Ta=0 to 60°C，VREG output no-loaded  
Symb  
ol  
Item  
Condition  
Min.  
Typ.  
Max.  
Unit  
VSHRT0  
VSHRT1  
VSHRT2  
VSHRT3  
tSHRT0  
tSHRT1  
tSHRT2  
tSHRT3  
SC1,SC0 bit=(0,0)  
SC1,SC0 bit=(0,1)  
SC1,SC0 bit=(1,0)  
SC1,SC0 bit=(1,1)  
TD1,TD0 bit=(0,0)  
TD1,TD0 bit=(0,1)  
TD1,TD0 bit=(1,0)  
TD1,TD0 bit=(1,1)  
30  
80  
50  
70  
mV  
mV  
mV  
mV  
µs  
µs  
µs  
µs  
100  
150  
200  
100  
200  
300  
400  
120  
170  
220  
150  
300  
450  
600  
Short circuit detection  
threshold  
130  
180  
50  
100  
150  
200  
Short circuit detection  
delay time (Note1)  
Note1) Short circuit detection delay time assumes that there is no capacitor between ISM-ISP.  
VSHRTn  
0V  
ISP-ISM  
tSHRT  
Hi-Z  
/INTO  
VDFS＋11V  
D_FET  
VDFS  
VCFS＋11V  
C_FET  
VCFS  
Confidential  
10/34  
FEDL5248-02  
ML5248  
● PSNS, DFS Pin Monitor Output Characteristic and Charger Detecting Voltage  
Characteristic (Ta=0 to 60℃)  
VDD=31.5V，GND=0 V，Ta=0 to 60°C，VREG output lo-loaded  
Sym  
Item  
bol  
Condition  
Min.  
1.9  
Typ.  
2.0  
Max.  
2.1  
Unit  
V
VMON output voltage,  
VPCO  
Input voltage = 32V  
Input voltage = 32V  
PSNS，DFS pin monitoring  
VMON output voltage  
settling time,  
tPC  
―
―
(3  
ms  
PSNS，DFS pin monitoring  
Charger detection  
Power-up from power down  
state  
VPC  
RPD  
RPU  
VDDX0.2  
200  
VDDX0.5  
VDDX0.8  
1000  
4
V
PSNS voltage  
PSNS pin voltage is not  
monitored  
PSNS pull-down resistor  
DFS pull-up resistor  
500  
2
kΩ  
kΩ  
DFS pin voltage is not  
measured  
0.5  
PSNS pin voltage  
monitoring  
pull-down resistor  
DFS pin voltage  
monitoring  
Pull-down resistor is  
removed (register PD=”0”)  
RDM1  
8
8
20  
20  
50  
50  
MΩ  
MΩ  
Pull-up resistor is  
removed (register PU=”0”)  
RDM2  
pull-down resistor  
Pull-down resistor is  
removed.  
PSNS pin voltage is not  
monitored  
PSNS input current  
leakage  
ILPS  
-2  
-2  
―
―
2
2
µA  
µA  
Pull-up resistor is removed.  
D_FET=OFF  
DFS input current leakage  
ILFS  
DFS pin voltage is not  
monitored  
SCL  
32VV  
PSNS, DFS voltage  
VMON  
0V  
0V  
tPC  
tPC  
State  
VMON output state  
VMEN bit=”1”  
PSNS, DFS selected  
VMEN bit=”0”  
VMON output state  
VMENT bit=”1”  
PSNS, DFS selected  
VMEN bit=”0”  
Confidential  
11/34  
FEDL5248-02  
ML5248  
● AC Characteristic  
VDD=5 to 31.5V，GND=0 V，Ta=－40 to 85°C，VREG ouptput no-loaded  
Item  
Symbol  
fSCL  
Condition  
―
Min.  
―
Typ.  
―
Max.  
400  
Unit  
kHz  
SCL clock frequency  
SCL hold time  
(start condition)  
SCL “L” hold time  
SCL “H” hold time  
SDA hold time  
tHD:STA  
―
0.6  
―
―
s  
tLOW  
―
―
―
―
1.3  
0.6  
0
―
―
―
―
―
―
―
―
s  
s  
s  
s  
dtHIGH  
tHD:DAT  
tSU:DAT  
SDA setup time  
SDA setup time  
(stop condition)  
Bus free time  
0.1  
tSU:STO  
―
0.6  
―
―
s  
tBUF  
tPUP  
―
―
1.3  
1
―
―
―
―
s  
ms  
/PUPIN “L” pulse width  
Stop  
condition  
Start  
condition  
SDA  
SCL  
tSU:DAT tHD:DAT tSU:STO tBUF  
tLOW tHIGH  
tHD:STA  
Confidential  
12/34  
FEDL5248-02  
ML5248  
■ Functional Description  
● I2C compatible serial Interface  
The ML5248 is equipped with the I2C compatible serial interface. This interface is not fully compatible  
with I2C communication format, and it doesn’t have slave address, the MCU communication is one-to  
–one.  
Setting and control is executed by writing/reading control registers.  
address  
data  
SCL  
SDA  
MSB  
LSB  
MSB  
LSB  
A5  
A2 A1  
ACK D7 D6  
D2  
D0 ACK  
D1  
A6  
A4 A3  
A0  
D5 D4 D3  
R/W  
Start  
condition  
Stop  
condition  
To write data set the RW bit “0”, to read data set the RW bit “1”  
● Control Register  
The control register map is shown below.  
address  
Register name  
R/W  
Default  
Description  
00H  
NOOP  
R/W  
00H  
No function assigned  
Cell voltage and PSNS/DFS pin voltage  
monitoring control  
01H  
VMON  
R/W  
00H  
02H  
03H  
04H  
05H  
06H  
07H  
08H  
IMON  
FET_INT  
POWER  
CBAL  
SETSC  
VGAIN  
OFFSET  
R/W  
R/W  
R/W  
R/W  
R/W  
R
00H  
00H  
00H  
00H  
00H  
－
Current measurement control  
FET control, interrupt control  
Power-save/ power-down control  
Cell balancing contorl  
Short circuit detection control  
VMON output voltage gain correction  
VMON output voltage offset correction  
VREF output voltage offset correction  
test(don’t use)  
R
－
09H  
other  
VREFOF  
TEST  
R
R/W  
－
00H  
Confidential  
13/34  
FEDL5248-02  
ML5248  
1. NOOP register（Adrs=00H）  
7
6
5
4
3
2
1
0
Bit  
NO7  
NO6  
NO5  
NO4  
NO3  
NO2  
NO1  
R/W  
0
NO0  
name  
R/W  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Default  
No function is assigned to the NOOP register. Read/write access to this register does not change the  
LSI status. The written data can be read as it is.  
2. VMON register（Adrs=01H）  
7
6
5
4
3
2
1
0
Bit  
―
―
―
VMEN  
VM3  
VM2  
VM1  
VM0  
R/W  
R
0
R
0
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
dafault  
VMON register select the voltage measuring battery cell number, select which pin voltage of PSNS  
or DFS to output from VMON pin.  
VM0, VM1, VM2, VM3 select the battery cell voltage or PSNS pin or DFS pin voltage divided by  
16, and VMEN bit enables VMON pin to output selected voltage.  
VM3  
―
0
0
0
0
0
0
0
VMEN  
VM2  
―
0
0
0
0
1
1
1
VM1  
―
0
0
1
1
0
0
1
VM0  
―
0
1
0
1
0
1
0
Selected battery cell  
VMON pin=0V(default)  
VMON pin=0V(default)  
V1 cell (lowest)  
V2 cell  
0
1
1
1
1
1
1
1
1
1
1
V3 cell  
V4 cell  
V5 cell  
V6 cell  
0
1
1
1
0
0
1
0
0
1
0
1
V7 cell (uppsermost)  
PSNS divided  
DFS divided  
Confidential  
14/34  
FEDL5248-02  
ML5248  
3. IMON register（Adrs=02H）  
7
6
5
4
3
2
1
0
bit  
―
―
―
IMEN  
―
―
ZERO  
R/W  
0
GIM  
R/W  
R
0
R
0
R
0
R/W  
0
R
0
R
0
R/W  
0
default  
IMON register controls current measurement and its conditions.  
The GIM bit selects the volgtage gain of the current measurement amplifier.  
GIM  
0
1
Voltage gain GIM  
10 times (default)  
50 times  
The ZERO bit executres zero corrention of the current measurement amplifier.  
ZERO  
ISP input  
Pin input level Pin input level  
GND revel GND level  
ISM input  
0
1
The IMEN bit enables current measuring amplifiere result to output from IMON pin. If zero  
correnction and gain correction is held, IMEN bit is set “1”.  
IMEN  
0
IMON pin output  
0V(default)  
Current measuring amplifier  
output  
1
Current measurement is executed with current sensing resistor RSENSE connected between ISP and  
ISM pins, and measure input voltage difference of these pins.  
Voltage difference between ISP and ISM pins is converted to voltage, its center is 0.5V(typ.), and  
output from IMON pin. IMON pin output voltage VIMON is geven by the following equation with the  
current sensing resistor RSENSE and its current ISENSE  
.
VIMON = (ISENSE × RSENSE)×GIM＋0.5  
Confidential  
15/34  
FEDL5248-02  
ML5248  
The current measuring amplifier circuit is shown below.  
ML5248  
PACK(+)  
Current amplifier for monitoring  
GIM=R2/(R1+1kΩ)  
R2  
1kΩ ISM  
R1  
ZERO  
ZERO  
RSENSE  
PACK(-)  
IMON  
R1  
1kΩ  
R2  
ISP  
0.5V  
If the current is zero,VIMON = 0.5V in the discharging state, VIMON > 0.5V in the charging state,  
VIMON < 0.5V.  
When the ZERO bit is set “1”, the input of ISM pin and ISP pin is switched to GND level in the LSI  
and set the input voltage difference of the current measuring amplifier is set to zero. By setting the  
IMON pin output voltage in this state as the reference voltage of zero current, internal 0.5V reference  
voltage and offset voltage of amplifier are corrected.  
Short current detection characteristic does not depend on the IMON register setting.  
Confidential  
16/34  
FEDL5248-02  
ML5248  
The example flowchart of calibration for current measuring amplifier is shown below.  
(Voltage gain is 10)  
START  
IMON  
Write IMON register “12H” (*1) and set the zero  
current state.  
Write=12H(*1)  
Measure IMON  
output voltage  
Measure the IMON pin output voltage of zero  
current state with external ADC. Store its result in  
the variable VIM0.  
Zero correction is held with the variable.  
Zero correction value VIMZ=VIM0  
Calculate  
current correct  
If Current sensing resistor value=RSENSE、IMON  
voltage measured value=VIMON, measured  
current ISENSE is given with the following  
expression.  
END  
ISENSE =(VIMON - VIMZ) / GIM / RSENSE  
(*1) In order to set voltage gain 50, 13H is written in the IMON register.  
Confidential  
17/34  
FEDL5248-02  
ML5248  
4. FET_INT register（Adrs=03H）  
7
INTO  
R
6
―
R
0
5
4
3
PU  
R/W  
0
2
PD  
R/W  
0
1
0
DF  
R/W  
0
bit  
DEDCK DETSC  
CF  
R/W  
0
R/W  
R
0
R
0
default  
0
FET_INT register controls C_FET、D_FET turn ON/OFF, PSNS pin pull-down resistor connection,  
DFS pin pull-up resistor connection, and indicates intrerrupt requests.  
DF bit sets the D_FET pin output state. If the short current is detected, the DF bit is automatically  
cleared to “0”. But even if the state is recovered from short current detection to normal state, this bit is  
not set “1” automatically, external MCU should set this bit “1”.  
DF  
0
1
Discharge FET  
OFF（default）  
ON  
D_FET pin output  
DFS pin voltageVDFS  
VDFS+11V(typ)  
CF bit sets the C_FET pin output state. If the short current is detected, the CF bit is automatically  
delaerd to “0”. But even if the state is recovered ftrom short current detection to normal state, this bit is  
not set “1” automatically, external MCU should set this bit “1”.  
CF  
0
1
Charge FET  
OFF(default)  
ON  
C_FET pin output  
CFS pin voltageVCFS  
VCFS+11V(typ)  
PD bit sets the PSNS pin pull-down resistor connection.  
PD  
0
1
PSNS pin  
Pull-down removed (default)  
500kΩ pull-down  
PU bit sets the DFS pin pull-up resistor connection  
PU  
0
1
DFS pin  
Pull-up removed (default)  
2MΩ pull-up  
DETSC bit indicates the /INTO pin output state when short circuit is detected.  
DETSC  
Short current detection interrupt state  
No interrupt（default）  
Interrupt occured(short current is detected)  
0
1
DEDCK bit indicates the /INTO pin output state when internal clock stop was detected. If the  
internal clock stop is detected, DF bit and CF bit are automatically cleared to “0”. But even if the  
internal clock stop is not detected, DF bit and CF bit are not set “1” automatically, external MCU  
should set these bits “1”.  
DEDCK  
Clock stop detection interrupt state  
No interrupt（default）  
Interrupt occured(clock stop is detected)  
0
1
INTO bit indicates the /INTO pin output state  
INTO  
/INTO pin output state  
0
1
No interrupt（default）  
Interrupt occured  
Confidential  
18/34  
FEDL5248-02  
ML5248  
After the FET_INT resister is read, each bit of INTO、DETSC、DEDCK is cleared to default value,  
and /INTO pin is set Hi-Z state.  
5. POWER register（Adrs=04H）  
7
6
5
4
3
2
1
0
bit  
PUPIN  
―
―
PDWN  
―
―
―
PSV  
R/W  
R
0
R
0
R
0
R/W  
0
R
0
R
0
R
0
R/W  
0
default  
Power register control the power-down and the power-save.  
PSV bit set the state transition to power save  
PDWN  
Power-save  
0
1
Normal state（default）  
Power-save state  
If the PSV bit is set “1”, the state is changed to the Power-save state. In the power-save state, VMON,  
IMON, FET_INT, CBAL, and SETSC registers are initialized. Changing these registers is disabled.  
When the PSV bit is cleared to “0”, the status is recovered from power-save state to the normal state,  
and setting the VMON, IMON, FET_INT, CBAL, and SETSC registers is enabled. Wait for the VREF  
output to be stable, before measuring actions.  
Before setting the PDWN bit “1” to be into the Power-down state, power-save state should be  
cleared and the state is changed to the normal state,.  
The state of each functions are shown below.  
Function  
VREG pin output  
VREF pin output  
Operation in the power-save state  
Same as the normal state, output 3.3V(typ)  
Stopped, output is 0V(typ)  
Same as the normal state, register read/write is enabled.  
But VMON, IMON, FET_INT, CBAL, and SETSC bits are  
initrialized and write is disabled.  
Stopped  
MCU serial interface  
Cell voltage monitoring  
Current monitoring  
Short current detection  
PSNS, DFS pin  
monitoring  
Stopped  
Stopped  
Stopped  
Stopped  
Charge/discharge FET  
control  
Internal clock stop  
detection  
Stopped  
Cell balancing switches  
All switches are OFF  
PDWN bit set the state transition to power down  
PDWN  
Power-down  
0
1
Normal state（default）  
Power-down state  
If the PDWN bit is set “1”, 500kΩ pull-down resistor is automatically connected to PSENSE pin in  
the LSI and all the circuit is stopped.  
Confidential  
19/34  
FEDL5248-02  
ML5248  
Before setting the PDWN bit “1”, C_FET and D_FET should be set OFF and charger disconnection  
should be confirmed with the PSENSE pin voltage. When the /PUPIN pin input is “L”, even if  
PDOWN bit is set to “1”, the state doesn’t get changed to power-down until the /PUPIN pin input rises  
to “H”. Before setting the PDWN bit “1”, it should be confirmed that /PUPIN pin is not “L” by reading  
the PUPIN bit which indicated /PUPIN pin state..  
PUPIN  
/PUPIN pin state  
“H” level  
0
1
“L” level  
If charger connection is detected with PSENSE pin or if /PUPIN pin is asserted “L” input, the LSI is  
recovered from power-down state to normal state.  
In the power down state, VREG output which is power supply for external micro-controller is set  
GND level. In recovering from power down state, every initial setting should be held after VREG has  
fully rised.  
The example flow chart of powr-down is shown below.  
START  
Write FET register “04H” and set the C_FET and  
D_FET pins OFF. And in order to detect charger  
removal , connect 500kΩ(typ) pull-down resister to  
PSNS pin.  
FET_INT  
Write=04H  
Wait  
Wait for PSNS pin stable.  
Several ms  
VMON Write=18H  
Monitor PSNS  
voltage  
Write VMON register “18H” and monitor the VMON  
pin output voltage with external ADC to confirm that  
PSNS pin is not connected to charger.  
Wait for PSNS pin voltage to be lower than V PC to  
detect that charger is removed  
Charger  
removed？  
Read the PUPIN bit of POWER register and confirm  
that the value is ”0” (/PUPIN pin is ”H”).  
POWER  
Read  
If the PUPIN bit =”1”, wait for PUPIN bit to be “0”,  
because setting PDWN bit =”1” is neglected if the  
PUPIN bit =”1”.  
PUPIN=”0”？  
POWER  
Write POWER register ”10H” to set the PDWN bit “1”  
and make the ML5248 power-down. In the  
Write=10H  
power-down state, all the circuits are stopped and all  
the registers are initialized. The 500kΩ(typ)  
pull-down resistor is connected to the PSNS pin and  
wait for charger connection detection.  
END  
(power-down)  
Confidential  
20/34  
FEDL5248-02  
ML5248  
Output state of each pins in power-down state is shown below.  
Pin name  
VREG  
State in power-down  
0V  
0V  
VREF  
/INTO  
Hi-Z  
C_FET  
CFS pin lev  
D_FET  
DFS pin level  
Recovering from power-down state is executed by charger connect detection by PSNS pin or “L”  
level linput to /PUPIN pin. If recovered from power-down state, wait for VREF and VREF become  
stable before each setttings.  
Confidential  
21/34  
FEDL5248-02  
ML5248  
6. CBAL register（Adrs=05H）  
7
6
5
4
3
2
1
0
bit  
―
SW7  
SW6  
SW5  
SW4  
SW3  
SW2  
R/W  
0
SW1  
R/W  
R
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
default  
CBAL register set the cell balancing switches ON/OFF.  
SW7 to SW1 bit sets switches turning ON/OFF of each cell.  
SW7  
SW6  
SW5  
SW4  
SW3  
SW2 SW1  
Switch ON/OFF  
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
7cell OFF（default）  
V1-V0 pin switch ON  
V2-V1 pin switch ON  
V3-V2 pin switch ON  
V4-V3 pin switch ON  
V5-V4 pin switch ON  
V6-V5 pin switch ON  
V7-V6 pin switch ON  
More than one switch can be turned on in the same time, but following settings are inhibited because  
internal cell balancing switch might be broken.  
(1) Side-by-side cell balancing switches are inhibited to be turned on in the same time.  
(2) The cell balancing switches of both side of a cell balancing switch which is turned off is inhibited  
to be turned on in the same time.  
OFF  
ON  
ON  
OFF  
ON  
ON  
OFF  
OFF  
As IC heats by cell balancing current and cell balancing switch resistor, restrict the number of  
switches of ON and time of ON, in order to keep the power consumption of cell balancing switch less  
than allowable power dissipation,  
If cell voltage is outputted from VMON pin, the voltage of a cell whose cell balancing switch is  
turned on is measured as the voltage difference between two ports of cell balancing switch.  
Confidential  
22/34  
FEDL5248-02  
ML5248  
7. SETSC register（Adrs=06H）  
7
6
5
4
3
2
1
0
bit  
ENSC  
―
TD1  
TD0  
―
―
SC1  
R/W  
0
SC0  
R/W  
R/W  
0
R
0
R/W  
0
R/W  
0
R
0
R
0
R/W  
0
default  
SETSC register sets the short current detecting voltage and short current detecting delay time.  
Short current detecting voltage is selected with SC0 and SC1 bit depend on current sensing resistor  
value. While short current is detected, writing this register is inhibited.  
Short current detecting  
current if current sending  
Short current detecting  
voltage  
SC1  
SC0  
(ISP-ISM pin voltage)  
50mV (default)  
100mV  
resistor value =1mΩ  
0
0
1
1
0
1
0
1
50A  
100A  
150A  
200A  
150mV  
200mV  
TD0, TD1 bits select the short current detecting delay ime. While short current is detected, writing  
this register is inhibited.  
TD1  
0
0
TD0  
0
1
Short current detecting delay time  
100s (default)  
200s  
1
0
300s  
1
1
400s  
ENSC bit sets the short current detection circuit run/stop.  
ENSC  
Short current detection circuit state  
Stop (default)  
0
1
Running  
Confidential  
23/34  
FEDL5248-02  
ML5248  
The example flow chart of setting short current detection and control flow after chort current  
detection is shown below.  
START  
Set the short current detecting voltage in the SC0 and  
SC1 bits of SETSC register, and set the ENSC bit “1”  
to start the short current detection circuit.  
SETSC  
Write  
If the /INTO pin output is changed to ”L” level, read the  
FET_INT register and check the interrupt requests.  
Now, only DETSC bit is assumed to be set “1”.  
/INTO=”L”  
DETSC=”1”  
Set the PU bit of FET_INT register “1” to connect the  
pull-up resistor to DFS pin. If the short current detection  
state is kept, DFS pin voltage stays GND level.,  
FET_INT  
Write=08H  
Write VMON register 19H and monitor the VMON  
output voltage with external ADC, and check that  
short current state is kept with DFS pin voltage。  
VMON  
Write=19H  
Monitor DFS  
voltage  
If the DFS pin voltage is still GND level, short current  
state is kept and wait until the voltage of DFS rise to  
VDD.  
If the state is not in short current state, the voltage of  
DFS will be VDD level by its pull-up resistor  
Short state  
Is cleared  
FET_INT  
If recovery from short current state is recognized, set  
the DF and CF bit of the FET register “1”to enable  
charge and discharge.  
Write=1BH  
END  
Confidential  
24/34  
FEDL5248-02  
ML5248  
8. VGAIN register（Adrs=07H）  
7
6
5
4
3
2
1
0
bit  
―
VG6  
VG5  
VG4  
VG3  
VG2  
VG1  
R
VG0  
R/W  
R
R
R
R
R
R
R
default  
―
―
―
―
―
―
―
―
VGAIN register stores the gain correction value of the VMON output voltage.  
Cell voltage is calcurated from VMON output voltage by following corrention equation.  
cell voltage = VAGIN × [VMON output voltage] + OFFSET  
VGAIN: gain corrention value of the VGAIN register  
OFFSET: offset corrention value of the OFFSET register  
The VGAIN register value and gain corrention value are shown in thefollowing table.  
Register  
value[Hex]  
Register  
value[Hex]  
Gain correction value  
Gain correction value  
40  
41  
42  
43  
44  
45  
46  
47  
…
1.936  
1.937  
1.938  
1.939  
1.940  
1.941  
1.942  
1.943  
…
00  
01  
02  
03  
04  
05  
06  
07  
…
2.000  
2.001  
2.002  
2.003  
2.004  
2.005  
2.006  
2.007  
…
4F  
50  
…
1.951  
1.952  
…
0F  
10  
…
2.015  
2.016  
…
5F  
60  
…
1.967  
1.968  
…
1F  
20  
…
2.031  
2.032  
…
6F  
70  
…
7F  
1.983  
1.984  
…
2F  
30  
…
3F  
2.047  
2.048  
…
1.999  
2.063  
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ML5248  
9. OFFSET register（Adrs=08H）  
7
6
5
4
3
2
1
0
bit  
OF7  
OF6  
OF5  
OF4  
OF3  
OF2  
OF1  
R
OF0  
R/W  
R
R
R
R
R
R
R
default  
―
―
―
―
―
―
―
―
OFFSET register stores the VMON output voltage offset correction value.  
Cell voltage is calcurated from monitored VMON output voltage by following correction equation.  
Cell voltage = VAGIN × [VMON output voltage] + OFFSET  
VGAIN: gain correction value of the VGAIN register  
OFFSET: off set correctin value of the OFFSET register  
The OFFSET register value nd the offset correction value are shown in the following table.  
Register  
value[Hex]  
00  
Offset correctin value  
[mV]  
＋0  
01  
02  
03  
…
＋1  
＋2  
＋3  
…
7F  
80  
81  
82  
83  
…
＋127  
－128  
－127  
－126  
－125  
…
FD  
FE  
FF  
－3  
－2  
－1  
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ML5248  
10. VREFOF register（Adrs=09H）  
7
6
5
4
3
2
1
0
bit  
VOF7  
VOF6  
VOF5  
VOF4  
VOF3  
VOF2  
VOF1  
R
VOF0  
R/W  
R
R
R
R
R
R
R
default  
―
―
―
―
―
―
―
―
VREFOF register stores the offset correction value of the VREF output voltage from 2.5V.  
VREF voltage is calcurated by following correction equation.  
VREF output voltage＝2,500 [mV] + VREFOF  
VREFOF: offset value of the VREFOF register  
If VREFG outpu voltage is used as the reference voltage of the external A/D converter and if VMON  
output voltage is measured with the external A/D converter, cell voltage is calcuragted by the  
following equation.  
Cell voltage [mV] = VGAIN × ADC measuring code × LSB + OFFSET  
VGAIN: VGAIN register gain correction value  
OFFSET: OFFSET register offset corrention value  
LSB: external N-bit ADC resolution = (2,500 [mV] + VREGFOF) / (2^N-1)  
The VREFOF register value and the offset correction value is shown in the following table.  
Register  
value[Hex]  
00  
Offset correction value  
[mV]  
＋0  
01  
02  
03  
…
＋1  
＋2  
＋3  
…
7F  
80  
81  
82  
83  
…
＋127  
－128  
－127  
－126  
－125  
…
FD  
FE  
FF  
－3  
－2  
－1  
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FEDL5248-02  
ML5248  
● CONNECTING POWER SUPPLY (VDDR, VDD)  
VDDR pin is the power supply pin only for the internal 3.3V regulator (VREG). If the output current of  
3.3V regulator is large, it is recommended to make the voltage drop of RC filter register (for removing  
noise at the VDDR) smaller than 1V.  
VDD pin is the power supply pin for all the ciurcuit other than internal 3.3V regulator.  
Power supply  
path for external  
circuit  
ML5248  
VDD  
VDDR  
VREG  
Power supply  
for external  
circuit  
GND  
● LOW VREG DETECTING FUNCTION  
If a large output load is connected and the VREG pin voltage falls under the VREG low voltage detection  
voltage (VRD), all registers are initialized.  
If the VREG pin voltage rise over the VREG low voltage release voltage (VRR), regster setting with I2C  
interface become effective. Wait for the VREG and VREF output voltage be stable, and start initial setting  
and monitoring.  
Initial setting  
SCL  
VRR  
VREG  
VRD  
operating initialization  
I2C impossible  
operating  
State  
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ML5248  
● POWER-ON / POWER-OFF SEQUENCE  
For POWER-ON, recommended battery connecting sequence is; connect the GND first, then connect the  
VDD, VDDR, and connect each cells from lower level.  
If this sequence is not kept, absolute maximum rating is exceeded across the LSI and it may damage input  
pins of Vn+1 pin and Vn.  
For POWER-OFF, recommended battery disconnecting sequence is; disconnect each cell from higher  
level first, then disconnect the VDD, VDDR, and lastly disconnect the GND.  
And also in testing and evaluating with battery simulator, pay attention to the connecting and  
disconnecting sequence not to make an excessive voltage to absolute maximum rating of each Vn+1 pin and  
Vn pin.  
As shown in the diagram bellow, it is recommend to use zener diode circuit for input pin protection, and  
good enough evaluation is requested.  
ML5248  
Vn+1  
6.2V  
Vn  
6.2V  
Vn-1  
Before battery connection to Vn pins of LSI, all of cell must be in a serial connection each other.  
Connecting of individual battery cells to Vn pins of LSI without being a serial connection is forbidden  
because there is a possibility that absolute maximum rating is exceeded across the LSI and it may damage  
input pins of Vn+1 and Vn.  
There is no limitation on Power supply voltage rising time of power-on, power off order, and power  
supply voltage falling time of power-off.  
Following the power-on, the ML5248 normally enter into normal state. ML5248 may rarely enter into the  
Power down state by the chattering or another reason during the connection of the battery cells. In this case,  
input the voltage lower than or equal to the Detecting charger connection PSENSE pin voltage (VPC) to  
PSENSE pins, or input the “L” level to the /PUPIN pin, in order to power-up.  
And, after the power-on or after the power-up, cell voltage measurement and current measurement should  
be done after the internal analog circuit is settled. To get the settling time of analog circuit, confirm the  
output settling time of VREF pin, VMON pin, and IMON pin in the application system.  
● CELL CONNECTING  
If the number of connected cells is 3 to 6, connecting order in following table is recommended.  
Number of  
Connected  
cells  
V7  
V6  
V5  
V4  
V3  
V2  
V1  
V0  
6
5
4
3
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
Cell  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
Cell  
GND  
GND  
GND  
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ML5248  
■ EXAMPLE OF APPLICATION CIRCUIT  
(7 cells, charge/discharge path isolated, MCU power supply =VREG)  
CHG(+)  
RVDD  
PACK(+)  
CVDD  
CVDDR  
RG  
RFS  
RPS  
RFS  
RG  
RVDDR  
RCEL  
CCEL  
VDD  
VDDR  
V7  
1
2
3
4
5
6
7
8
9
30 CFS  
29 C_FET  
28 CPHC  
27 CPLC  
26 CPLD  
25 CPHD  
24 D_FET  
23 DFS  
22 PSNS  
21 /PUPIN  
20 VREG  
19 VREF  
18 SCL  
CCP  
CCP  
V6  
V5  
V4  
V3  
V2  
V1  
V0 10  
GND 11  
ISM 12  
ML5248  
RINT  
RI2C  
ISP 13  
MCU  
IMON 14  
VMON 15  
17 SDA  
16 /INTO  
CREF  
CREG  
CISIN  
CPUP  
RISIN  
PACK(-)  
RIS  
■PARTS LIST  
Symbol  
RVDD (Note1)  
CVDD  
Value  
Symbol  
RISIN  
CISIN, CRES  
CREG, CREF  
Value  
Symbol  
RPS  
RI2C  
Value  
510Ω  
2.2~10F  
100Ω  
2.2~10F  
150Ω~10kΩ  
0.1F or larger  
1mΩ  
1kΩ  
0.1F  
4.7F  
1kΩ  
47kΩ  
51kΩ  
RVDDR  
CVDDR  
RCEL  
CCEL  
RIS  
RINT  
CCP  
CPUP  
RG  
20nF (Note2)  
1F  
1kΩ  
1kΩ  
RFS  
(Note 1) If CVDD=2.2F, RVDD=1.5kΩ is recommended.  
(Note 2) If external Nch-FET gate capacitance=10nF.  
(Notice) Example of application circuit and the recommended values to parts list shall not guarantee  
performance under all conditions. Full and detailed tests are suggested on your actual application.  
Confidential  
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FEDL5248-02  
ML5248  
■ EXAMPLE OF APPLICATION CIRCUIT-2  
(5 cells, charge/discharge path isolated, MCU power supply =VREG)  
CHG(+)  
RVDD  
PACK(+)  
CVDD  
CVDDR  
RG  
RFS  
RPS  
RFS  
RG  
RVDDR  
RCEL  
CCEL  
VDD  
VDDR  
V7  
1
2
3
4
5
6
7
8
9
30 CFS  
29 C_FET  
28 CPHC  
27 CPLC  
26 CPLD  
25 CPHD  
24 D_FET  
23 DFS  
22 PSNS  
21 /PUPIN  
20 VREG  
19 VREF  
18 SCL  
CCP  
CCP  
V6  
V5  
V4  
V3  
V2  
V1  
V0 10  
GND 11  
ISM 12  
ML5248  
RINT  
RI2C  
ISP 13  
MCU  
IMON 14  
VMON 15  
17 SDA  
16 /INTO  
CREF  
CREG  
CISIN  
CPUP  
RISIN  
PACK(-)  
RIS  
■ Parts List  
Symbol  
RVDD (Note1)  
CVDD  
Value  
Symbol  
RISIN  
CISIN, CRES  
CREG, CREF  
Value  
Symbol  
RPS  
RI2C  
Value  
510Ω  
2.2~10F  
100Ω  
2.2~10F  
150Ω~10kΩ  
0.1F 以上  
1mΩ  
1kΩ  
0.1F  
4.7F  
1kΩ  
47kΩ  
51kΩ  
RVDDR  
CVDDR  
RCEL  
CCEL  
RIS  
RINT  
CCP  
CPUP  
RG  
20nF (Note2)  
1F  
1kΩ  
1kΩ  
RFS  
(Note 1) If CVDD=2.2F, RVDD=1.5kΩ is recommended.  
(Note 2) If external Nch-FET gate capacitance=10nF.  
(Notice) Example of application circuit and the recommended values to parts list shall not guarantee  
performance under all conditions. Full and detailed tests are suggested on your actual application.  
Confidential  
31/34  
FEDL5248-02  
ML5248  
■ PACKAGE DIMENSIONS  
Notes for Mounting the Surface Mount Type Package  
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in  
storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the  
product name, package name, pin number, package code and desired mounting conditions (reflow method,  
temperature and times).  
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ML5248  
■ REVISION HISTORY  
Page  
Document No.  
FEDL5248-01  
Date  
Description  
Previous Current  
Edition  
―
Edition  
―
2018.5.21  
First edition  
Changed Company name  
―
―
FET_INT register, comment for the DEDCK bit is  
added.  
FEDL5248-02  
2020.11.30  
18  
34  
18  
34  
Changed “Notes”  
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ML5248  
Notes  
1) The information contained herein is subject to change without notice.  
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application  
notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are  
within the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident  
arising out of or in connection with the use of LAPIS Technology Products outside of such usage conditions specified  
ranges, or without observing precautions. Even if it is used within such usage conditions specified ranges,  
semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury,  
fire or the other damage from break down or malfunction of LAPIS Technology Products, please take safety at your own  
risk measures such as complying with the derating characteristics, implementing redundant and fire prevention designs,  
and utilizing backups and fail-safe procedures. You are responsible for evaluating the safety of the final products or  
systems manufactured by you.  
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the  
standard operation of semiconductor products and application examples. You are fully responsible for the incorporation  
or any other use of the circuits, software, and information in the design of your product or system. And the peripheral  
conditions must be taken into account when designing circuits for mass production. LAPIS Technology disclaims any  
and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits,  
software, and other related information.  
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS  
Technology or any third party with respect to LAPIS Technology Products or the information contained in this document  
(including but not limited to, the Product data, drawings, charts, programs, algorithms, and application examples、etc.).  
Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by  
third parties, arising out of the use of such technical information.  
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,  
gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in  
applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS  
Technology representative: transportation equipment (cars, ships, trains, etc.), primary communication equipment, traffic  
lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems, etc.  
LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by  
using the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high  
reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.  
6) The Products specified in this document are not designed to be radiation tolerant.  
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document.  
However, LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no  
responsibility for any damages arising from any inaccuracy or misprint of such information.  
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS  
Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any  
applicable laws or regulations.  
9) When providing our Products and technologies contained in this document to other countries, you must abide by the  
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US  
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..  
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or  
LAPIS Technology’s Products.  
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.  
(Note) “LAPIS Technology” as used in this document means LAPIS Technology r Co., Ltd.  
Copyright 2020 LAPIS Technology Co., Ltd.  
2-4-8 Shinyokohama, Kouhoku-ku,  
Yokohama 222-8575, Japan  
http://www.lapis-tech.com/en/  
Confidential  
34/34  

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