E-L6386D
更新时间：2025-01-13 14:53:44
描述：0.65A HALF BRDG BASED MOSFET DRIVER, PDSO14, SOP-14
概述
规格参数
数据手册E-L6386D 概述
0.65A HALF BRDG BASED MOSFET DRIVER, PDSO14, SOP-14 MOSFET 驱动器
E-L6386D 规格参数
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | SOP, | 针数： | 14 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.84 |
| 高边驱动器： | YES | 接口集成电路类型： | HALF BRIDGE BASED MOSFET DRIVER |
| JESD-30 代码： | R-PDSO-G14 | JESD-609代码： | e0 |
| 长度： | 8.65 mm | 功能数量： | 1 |
| 端子数量： | 14 | 标称输出峰值电流： | 0.65 A |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 认证状态： | Not Qualified | 座面最大高度： | 1.75 mm |
| 最大供电电压： | 17 V | 标称供电电压： | 15 V |
| 表面贴装： | YES | 端子面层： | TIN LEAD |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 断开时间： | 0.015 µs |
| 接通时间： | 0.015 µs | 宽度： | 3.9 mm |
| Base Number Matches： | 1 |
E-L6386D 数据手册
通过下载E-L6386D数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载L6386
®
HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER
HIGH VOLTAGE RAIL UP TO 600V
dV/dt IMMUNITY +- 50 V/nsec iN FULL TEM-
PERATURE RANGE
DRIVER CURRENT CAPABILITY:
400 mA SOURCE,
650 mA SINK
SWITCHING TIMES 50/30 nsec RISE/FALL
WITH 1nF LOAD
SO14
DIP14
CMOS/TTL SCHMITT TRIGGER INPUTS
WITH HYSTERESIS AND PULL DOWN
UNDER VOLTAGE LOCK OUT ON LOWER
AND UPPER DRIVING SECTION
ORDERING NUMBERS:
L6386D
L6386
INTEGRATED BOOTSTRAP DIODE
OUTPUTS IN PHASE WITH INPUTS
pendent referenced Chael Power MOS or
IGBT. The Upper (Fating) Section is enabled to
work with voltage Rail up to 600V. The Logic In-
puts are CMOSTTL compatible for ease of inter-
facing with controlling devices.
DESCRIPTION
The L6386 is an high-voltage device, manufac-
tured with the BCD "OFF-LINE" technology. It has
a Driver structure that enables to drive inde-
BLOCK DIAGRAM
BOOTSTRAP DRIVER
Vboot
14
CBOOT
H.V.
VCC
UV
UV
HVG
DRIVER
DETECTION
DETECTION
4
3
R
HVG
R
13
S
LEVEL
SHIFTER
HIN
SD
OUT
12
9
TO LOAD
VCC
LOGIC
2
1
LVG
LVG
DRIVER
PGND
DIAG
8
5
LIN
-
VREF
+
SGND
7
6
CIN
D97IN520D
July 1999
1/10
L6386
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
-3 to Vboot - 18
- 0.3 to +18
-1 to 618
Unit
V
Vout
Vcc
Output Voltage
Supply Voltage
V
Vboot
Vhvg
Vlvg
Vi
Floating Supply Voltage
V
Upper Gate Output Voltage
Lower Gate Output Voltage
Logic Input Voltage
- 1 to Vboot
-0.3 to Vcc +0.3
-0.3 to Vcc +0.3
-0.3 to Vcc +0.3
-0.3 to Vcc +0.3
50
V
V
V
Vdiag
Vcin
dVout/dt
Ptot
Open Drain Forced Voltage
Comparator Input Voltage
Allowed Output Slew Rate
Total Power Dissipation (Tj = 85 °C)
Junction Temperature
V
V
V/ns
mW
°C
°C
750
Tj
150
Ts
Storage Temperature
-50 to 150
Note:
ESD immunity for pins 12, 13 and 14 is guaranteed up to 900V (Human Body Model)
PIN CONNECTION
LIN
SD
1
2
3
4
5
6
7
14
13
12
11
10
9
Vboot
HVG
OUT
N.C.
N.C.
LVG
PGND
HIN
VCC
DIAG
CIN
SGND
8
D97IN521A
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction to Ambient
SO14
DIP14
100
Unit
Rth j-amb
165
°C/W
PIN DESCRIPTION
N.
Name
LIN
Type
Function
1
I
I
Lower Driver Logic Input
Shut Down Logic Input
Upper Driver Logic Input
Low Voltage Supply
Open Drain Diagnostic Output
Comparator Input
2
SD (*)
HIN
3
4
I
VCC
I
5
DIAG
CIN
O
I
6
7
SGND
PGND
LVG (*)
N.C.
Ground
8
Power Ground
9
O
Low Side Driver Output
Not Connected
10, 11
12
13
14
OUT
O
O
Upper Driver Floating Driver
High Side Driver Output
Bootstrapped Supply Voltage
HVG (*)
Vboot
(*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA), with VCC >3V. This allows to omit the "bleeder" resistor connected
between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also
in SD condition.
2/10
L6386
RECOMMENDED OPERATING CONDITIONS
Symbol Pin
Parameter
Output Voltage
Test Condition
Min.
Note1
Note1
Typ.
Max.
580
17
Unit
V
Vout
12
14
Vboot-
Vout
Floating Supply Voltage
V
fsw
Vcc
Tj
Switching Frequency
Supply Voltage
HVG,LVG load CL = 1nF
400
17
kHz
V
4
Junction Temperature
-45
125
°C
Note 1:
if the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V.
ELECTRICAL CHARACTERISTICS
AC Operation (Vcc = 15V; Tj = 25°C)
Symbol Pin
Parameter
Test Condition
Vout = 0V
Min.
Typ.
Max.
Unit
ton
toff
tsd
1.3
High/Low Side Driver Turn-On
110
150
ns
vs 9, Propagation Delay
13
High/Low Side Driver Turn-Off
Propagation Delay
Vout = 0V
Vout = 0V
105
105
150
150
ns
ns
2 vs Shut Down to High/Low Side
9,13 Propagation Delay
tr
tf
13,9 Rise Time
13,9 Fall Time
CL = 1000pF
CL = 1000pF
50
30
ns
ns
DC Operation (Vcc = 15V; Tj = 25°C)
Symbol Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Low Supply Voltage Section
Vcc
Vccth1
Vccth2
Vcchys
Iqccu
4
Supply Voltage
17
V
V
Vcc UV Turn On Threshold
Vcc UV Turn Off Threshold
Vcc UV Hysteresis
11.5
9.5
12
10
2
12.5
10.5
V
V
Undervoltage Quiescent Supply Current Vcc ≤ 11V
200
250
µA
µA
Iqcc
Quiescent Current
Vcc = 15V
320
Bootstrapped Supply Section
Vboot
Vbth1
Vbth2
Vbhys
Iqboot
Ilk
14
Bootstrapped Supply Voltage
Vboot UV Turn On Threshold
Vboot UV Turn Off Threshold
Vboot UV Hysteresis
17
12.9
10.7
V
V
10.7
8.8
11.9
9.9
2
V
V
Vboot Quiescent Current
Leakage Current
Bootstrap Driver on Resistance (*)
Vout = Vboot
200
10
µA
µA
Ω
Vout = Vboot = 600V
Vcc ≥ 12.5V; Vin = 0V
Rdson
125
Driving Buffers Section
Iso
9, 13 High/Low Side Driver Short Circuit
VIN = Vih (tp < 10µs)
300
500
400
650
mA
mA
Source Current
Isi
High/Low Side Driver Short Circuit
Sink Current
Logic Inputs
Vil
Vih
Iih
Iil
1,2,3 Low Level Logic Threshold Voltage
High Level Logic Threshold Voltage
High Level Logic Input Current
1.5
V
V
3.6
VIN = 15V
VIN = 0V
50
70
1
µA
µA
Low Level Logic Input Current
(VCC − VCBOOT1) − (VCC − VCBOOT2
)
(*)
=
R
DSON is tested in the following way: RDSON
I1(VCC,VCBOOT1) − I2(VCC,VCBOOT2
)
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
.
3/10
L6386
DC OPERATION (continued)
Symbol Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Sense Comparator
Vio
Iio
Input Offset Voltage
-10
10
mV
µA
V
6
2
Input Bias Current
Vcin ≥ 0.5
0.2
0.5
Vol
Open Drain Low Level Output
Voltage, Iod = -2.5mA
0.8
Vref
Comparator Reference voltage
0.460
0.540
V
Figure 1. Timing Waveforms
HIN
LIN
SD
HOUT
LOUT
V
REF
V
CIN
DIAG
D97IN522A
Note: SD active condition is latched until next negative IN edge.
Figure 2. Typical Rise and Fall Times vs.
Load Capacitance
Figure 3. Quiescent Current vs. Supply
Voltage
D99IN1054
time
(nsec)
Iq
(µA)
D99IN1057
104
250
200
150
100
50
Tr
Tf
103
102
10
0
0
1
2
3
4
5
C (nF)
0
2
4
6
8
10 12 14 16 V (V)
S
For both high and low side buffers @25˚C Tamb
4/10
L6386
µ
. This charge on a 1µF ca-
supply 1 C to CEXT
BOOTSTRAP DRIVER
pacitor means a voltage drop of 1V.
A bootstrap circuitry is needed to supply the high
voltage section. This function is normally accom-
plished by a high voltage fast recovery diode (fig.
4a). In the L6386 a patented integrated structure
replaces the external diode. It is realized by a
high voltage DMOS, driven synchronously with
the low side driver (LVG), with in series a diode,
as shown in fig. 4b
The internal bootstrap driver gives great advan-
tages: the external fast recovery diode can be
avoided (it usually has great leakage current).
This structure can work only if VOUT is close to
GND (or lower) and in the meanwhile the LVG is
on. The charging time (Tcharge ) of the CBOOT is
the time in which both conditions are fulfilled and
it has to be long enough to charge the capacitor.
An internal charge pump (fig. 4b) provides the
DMOS driving voltage .
The diode connected in series to the DMOS has
been added to avoid undesirable turn on of it.
The bootstrap driver introduces a voltage drop
due to the DMOS RDSON (typical value: 125
Ohm). At low frequency this drop can be ne-
glected. Anyway increasing the frequency it
must be taken in to account.
CBOOT selection and charging
:
To choose the proper CBOOT value the external
MOS can be seen as an equivalent capacitor.
This capacitor CEXT is related to the MOS total
gate charge :
The following equation is useful to compute the
drop on the bootstrap DMOS:
Qgate
Tcharge
=
→
=
V
drop
Vdrop IchargeRdson
R
dson
Qgate
Vgate
=
CEXT
where Qgate is the gate charge of the external
power MOS, Rdson is the on resistance of the
bootstrap DMOS, and Tcharge is the charging time
of the bootstrap capacitor.
The ratio between the capacitors CEXT and CBOOT
is proportional to the cyclical voltage loss .
It has to be:
For example: using a power MOS with a total
gate charge of 30nC the drop on the bootstrap
CBOOT>>>CEXT
µ
DMOS is about 1V, if the Tcharge is 5 s. In fact:
e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is
3nF. With CBOOT = 100nF the drop would be
300mV.
30nC
µ
5 s
=
125Ω ~ 0.8V
Vdrop
Vdrop has to be taken into account when the volt-
age drop on CBOOT is calculated: if this drop is
too high, or the circuit topology doesn’t allow a
sufficient charging time, an external diode can be
used.
If HVG has to be supplied for a long time, the
CBOOT selection has to take into account also the
leakage losses.
e.g.: HVG steady state consumption is lower than
µ
200 A, so if HVG TON is 5ms, CBOOT has to
Figure 4. Bootstrap Driver.
DBOOT
VS
VBOOT
H.V.
VBOOT
VS
H.V.
HVG
LVG
HVG
CBOOT
CBOOT
VOUT
VOUT
TO LOAD
TO LOAD
LVG
D99IN1056
a
b
5/10
L6386
Figure 5. Turn On Time vs. Temperature
Figure 8. VBOOT UV Turn On Threshold vs.
Temperature
250
15
@ Vcc = 15V
14
@ Vcc = 15V
200
13
Typ.
12
150
11
10
9
Typ.
100
50
0
8
7
-45 -25
0
25
50
75 100 125
-45 -25
0
25
50
75 100 125
Tj (°C)
Tj (°C)
Figure 6. Turn Off Time vs. Temperature
Figure 9. VBOOT UV Turn Off Threshold vs.
Temperature
15
250
@ Vcc = 15V
@ Vcc = 15V
14
13
12
11
10
9
200
150
Typ.
100
Typ.
50
0
8
7
-45 -25
0
25
50
75 100 125
-45 -25
0
25
50
75 100 125
Tj (°C)
Tj (°C)
Figure 7. Shutdown Time vs. Temperature
Figure 10. VBOOT UV Hysteresis
3
250
@ Vcc = 15V
@ Vcc = 15V
200
2.5
2
150
Typ.
Typ.
100
1.5
1
50
0
-45 -25
0
25
50
75 100 125
-45 -25
0
25
50
75 100 125
Tj (°C)
Tj (°C)
6/10
L6386
Figure 11. Vcc UV Turn On Threshold vs. Tem-
perature
Figure 14. Output Source Current vs. Tem-
perature
1000
800
600
400
200
0
15
14
13
@ Vcc = 15V
Typ.
12
Typ.
11
10
9
-45 -25
0
25
50
75 100 125
-45 -25
0
25 50 75 100 125
Tj (°C)
Tj (°C)
Figure 12. Vcc UV Turn Off Threshold vs.
Temperature
Figure 15. Output Sink Current vs. Tempera-
ture
12
11
10
1000
@ Vcc = 15V
800
Typ.
600
400
200
0
Typ.
9
8
7
-45 -25
0
25
50
75 100 125
-45 -25
0
25
50
75 100 125
Tj (°C)
Tj (°C)
Figure 13. Vcc UV Hysteresis vs. Tempera-
ture
3
2.5
Typ.
2
1.5
1
-45 -25
0
25
50
75 100 125
Tj (°C)
7/10
L6386
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.
a1
B
b
0.51
1.39
0.020
1.65 0.055
0.065
0.787
0.5
0.020
0.010
b1
D
E
e
0.25
20
8.5
2.54
15.24
0.335
0.100
0.600
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
DIP14
Z
1.27
2.54 0.050
0.100
8/10
L6386
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN.. TYP. MAX.. MIN.. TYP.. MAX..
A
a1
a2
b
1.75
0.069
0.009
0.063
0.018
0.010
0.1
0.25 0.004
1.6
0.35
0.19
0.46 0.014
0.25 0.007
b1
C
0.5
0.020
c1
D (1)
E
45˚ (typ.)
8.55
5.8
8.75 0.336
0.344
0.244
6.2
0.228
e
1.27
7.62
0.050
0.300
e3
F (1)
G
3.8
4.6
0.4
4
0.150
0.181
0.157
0.209
0.050
0.027
5.3
L
1.27 0.016
0.68
M
SO14
S
8˚ (max.)
(1) D and F do not include mold flash or protrusions. Mold flash or
potrusions shall not exceed 0.15mm (.006inch).
9/10
L6386
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
10/10
E-L6386D 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| E-L6386D013TR | STMICROELECTRONICS | 0.65A HALF BRDG BASED MOSFET DRIVER, PDSO14, SOP-14 | 获取价格 |
|
| E-L6452 | STMICROELECTRONICS | Dual 13x16 Matrix Head Ink Jet Driver | 获取价格 |
|
| E-L6506D | STMICROELECTRONICS | STEPPER MOTOR CONTROLLER, PDSO20, SOP-20 | 获取价格 |
|
| E-L6561 | STMICROELECTRONICS | 0.7A POWER FACTOR CONTROLLER, PDIP8, MINI, DIP-8 | 获取价格 |
|
| E-L6561D | STMICROELECTRONICS | 0.7A POWER FACTOR CONTROLLER, PDSO8, SO-8 | 获取价格 |
|
| E-L6561D013TR | STMICROELECTRONICS | 0.7A POWER FACTOR CONTROLLER, PDSO8, SO-8 | 获取价格 |
|
| E-L6562D | STMICROELECTRONICS | Transition mode | 获取价格 |
|
| E-L6563 | STMICROELECTRONICS | IC,POWER FACTOR CONTROLLER,SOP,14PIN | 获取价格 |
|
| E-L6563TR | STMICROELECTRONICS | 0.003A POWER FACTOR CONTROLLER WITH POST REGULATOR, PDSO14, SO-14 | 获取价格 |
|
| E-L6565D | STMICROELECTRONICS | Quasi-resonant Controller | 获取价格 |
|
E-L6386D 相关文章
英伟达CEO黄仁勋本周将访问中国，业界高度关注
- 2025-01-15
- 4
美出台禁令：禁止进口中国联网汽车软硬件技术，引发产业震荡
- 2025-01-15
- 3
中美科技博弈升级：中国加强美企出口审查，东南亚、印度扩产路受阻
- 2025-01-15
- 6
台积电美国厂面临封装能力挑战，4nm芯片进入质量验证最后阶段
- 2025-01-15
- 4
