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L6206D013TR

更新时间：2025-07-10 10:24:56
品牌：STMICROELECTRONICS
描述：DMOS双全桥驱动器

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L6206D013TR 概述

DMOS双全桥驱动器 电机驱动器 运动控制电子器件

L6206D013TR 规格参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SOIC包装说明：SOP, SOP24,.4
针数：24Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：12 weeks风险等级：0.74
模拟集成电路 - 其他类型：STEPPER MOTOR CONTROLLERJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：15.4 mm
湿度敏感等级：3功能数量：1
端子数量：24最高工作温度：150 °C
最低工作温度：-40 °C最大输出电流：5.6 A
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：250
电源：48 V认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Motion Control Electronics
最大供电电流 (Isup)：10 mA最大供电电压 (Vsup)：52 V
最小供电电压 (Vsup)：8 V标称供电电压 (Vsup)：48 V
表面贴装：YES技术：BCDMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

L6206D013TR 数据手册

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L6206  
DMOS DUAL FULL BRIDGE DRIVER  
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V  
■ 5.6A OUTPUT PEAK CURRENT (2.8A DC)  
0.3Ω TYP. VALUE @ T = 25 °C  
■ R  
DS(ON)  
j
■ OPERATING FREQUENCY UP TO 100KHz  
■
PROGRAMMABLE HIGH SIDE OVERCURRENT  
DETECTION AND PROTECTION  
DIAGNOSTIC OUTPUT  
SO24  
(20+2+2)  
PowerSO36  
PowerDIP24  
(20+2+2)  
■
■
PARALLELED OPERATION  
ORDERING NUMBERS:  
L6206N (PowerDIP24)  
L6206PD (PowerSO36)  
L6206D (SO24)  
■ CROSS CONDUCTION PROTECTION  
■ THERMAL SHUTDOWN  
■ UNDER VOLTAGE LOCKOUT  
■
INTEGRATED FAST FREE WHEELING DIODES  
BCD technology, which combines isolated DMOS  
Power Transistors with CMOS and bipolar circuits on  
the same chip. Available in PowerDIP24 (20+2+2),  
PowerSO36 and SO24 (20+2+2) packages, the  
L6206 features thermal shutdown and a non-dissipa-  
tive overcurrent detection on the high side Power  
MOSFETs plus a diagnostic output that can be easily  
used to implement the overcurrent protection.  
TYPICAL APPLICATIONS  
■ BIPOLAR STEPPER MOTOR  
■ DUAL OR QUAD DC MOTOR  
DESCRIPTION  
The L6206 is a DMOS Dual Full Bridge designed for  
motor control applications, realized in MultiPower-  
BLOCK DIAGRAM  
VBOOT  
VCP  
VBOOT  
VSA  
VBOOT  
VBOOT  
CHARGE  
PUMP  
PROGCLA  
OCDA  
OVER  
CURRENT  
DETECTION  
OCDA  
OUT1A  
OUT2A  
10V  
10V  
THERMAL  
PROTECTION  
ENA  
IN1A  
IN2A  
GATE  
LOGIC  
SENSEA  
10V  
VOLTAGE  
REGULATOR  
5V  
BRIDGE A  
OCDB  
OVER  
OCDB  
CURRENT  
DETECTION  
VSB  
PROGCLB  
OUT1B  
OUT2B  
SENSEB  
GATE  
LOGIC  
ENB  
IN1B  
IN2B  
BRIDGE B  
D99IN1088A  
September 2003  
1/23  
L6206  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Supply Voltage  
Test conditions  
Value  
60  
Unit  
V
V
S
V
=
=
V
V
= V  
S
SA  
SB  
V
OD  
Differential Voltage between  
V
V
= V = 60V;  
60  
V
SA  
SB  
S
VS , OUT1 , OUT2 , SENSE and  
= V  
= GND  
A
A
A
A
SENSEA  
SENSEB  
VS , OUT1 , OUT2 , SENSE  
B
B
B
B
OCD ,OCD OCD pins Voltage Range  
-0.3 to +10  
-0.3 to +7  
V
V
A
B
PROGCL , PROGCL pins Voltage Range  
A
PROGCL  
B
V
Bootstrap Peak Voltage  
Input and Enable Voltage Range  
Voltage Range at pins SENSE  
V
=
=
V
V
= V  
V + 10  
V
V
V
BOOT  
SA  
SB  
S
S
V ,V  
IN EN  
-0.3 to +7  
-1 to +4  
V
SENSEA,  
A
V
and SENSE  
B
SENSEB  
I
Pulsed Supply Current (for each  
V pin), internally limited by the  
S
V
t
= V ;  
7.1  
A
S(peak)  
SA  
SB  
S
< 1ms  
PULSE  
overcurrent protection  
I
RMS Supply Current (for each  
V
SA  
=
V
SB  
= V  
S
2.8  
A
S
V pin)  
S
T
, T  
stg OP  
Storage and Operating  
Temperature Range  
-40 to 150  
°C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Supply Voltage  
Test Conditions  
MIN  
MAX  
Unit  
V
V
S
V
=
=
V
V
= V  
S
8
52  
52  
SA  
SB  
V
OD  
Differential Voltage Between  
V
V
= V ;  
V
SA  
SB  
S
VS , OUT1 , OUT2 , SENSE and  
= V  
A
A
A
A
SENSEA  
SENSEB  
VS , OUT1 , OUT2 , SENSE  
B
B
B
B
V
V
Voltage Range at pins SENSE  
(pulsed t < t )  
(DC)  
-6  
-1  
6
1
V
V
SENSEA,  
A
W
rr  
and SENSE  
SENSEB  
B
I
RMS Output Current  
2.8  
+125  
100  
A
OUT  
T
Operating Junction Temperature  
Switching Frequency  
-25  
°C  
j
f
KHz  
sw  
2/23  
L6206  
THERMAL DATA  
Symbol  
Description  
PowerDIP24  
SO24  
14  
PowerSO36  
Unit  
°C/W  
°C/W  
°C/W  
R
MaximumThermal Resistance Junction-Pins  
Maximum Thermal Resistance Junction-Case  
18  
-
-
1
-
th-j-pins  
th-j-case  
th-j-amb1  
R
-
1
R
R
R
R
43  
51  
MaximumThermal Resistance Junction-Ambient  
2
-
-
-
-
35  
15  
62  
°C/W  
°C/W  
°C/W  
th-j-amb1  
th-j-amb1  
th-j-amb2  
Maximum Thermal Resistance Junction-Ambient  
3
MaximumThermal Resistance Junction-Ambient  
Maximum Thermal Resistance Junction-Ambient  
4
58  
77  
2
(1)  
(2)  
(3)  
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm (with a thickness of 35 µm).  
2
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a thickness of 35 µm).  
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm (with a thickness of 35 µm), 16 via holes  
2
and a ground layer.  
(4)  
Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.  
PIN CONNECTIONS (Top View)  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
GND  
N.C.  
GND  
2
N.C.  
3
N.C.  
N.C.  
4
VSA  
VSB  
IN1A  
IN2A  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
PROGCLA  
ENA  
5
OUT2A  
N.C.  
OUT2B  
N.C.  
2
6
SENSEA  
OCDA  
OUT1A  
GND  
3
VCP  
7
VCP  
VBOOT  
ENB  
4
OUT2A  
VSA  
8
ENA  
9
PROGCLA  
IN1A  
PROGCLB  
IN2B  
5
10  
11  
12  
13  
14  
15  
16  
17  
18  
6
GND  
IN2A  
IN1B  
GND  
7
GND  
SENSEA  
OCDA  
N.C.  
SENSEB  
OCDB  
N.C.  
OUT1B  
OCDB  
SENSEB  
IN1B  
8
VSB  
9
OUT2B  
VBOOT  
ENB  
10  
11  
12  
OUT1A  
N.C.  
OUT1B  
N.C.  
N.C.  
N.C.  
IN2B  
PROGCLB  
GND  
GND  
D99IN1089A  
D99IN1090A  
(5)  
PowerDIP24/SO24  
PowerSO36  
(5) The slug is internally connected to pins 1,18,19 and 36 (GND pins).  
3/23  
L6206  
PIN DESCRIPTION  
PACKAGE  
SO24/  
PowerDIP24  
PowerSO36  
Name  
Type  
Function  
PIN #  
PIN #  
10  
1
2
3
IN1  
IN2  
Logic input  
Logic input  
Bridge A Logic Input 1.  
Bridge A Logic Input 2.  
A
A
11  
12  
SENSE  
Power Supply Bridge A Source Pin. This pin must be connected to Power  
Ground directly or through a sensing power resistor.  
A
4
13  
OCD  
Open Drain  
Output  
Bridge A Overcurrent Detection and thermal protection pin.  
An internal open drain transistor pulls to GND when  
overcurrent on bridge A is detected or in case of thermal  
protection.  
A
5
15  
OUT1  
Power Output Bridge A Output 1.  
A
6, 7,  
1, 18,  
GND  
GND Signal Ground terminals. In Power DIP and SO packages,  
18, 19  
19, 36  
these pins are also used for heat dissipation toward the  
PCB.  
8
9
22  
24  
OUT1  
Power Output Bridge B Output 1.  
B
OCD  
Open Drain  
Output  
Bridge B Overcurrent Detection and thermal protection pin.  
B
An internal open drain transistor pulls to GND when  
overcurrent on bridge B is detected or in case of thermal  
protection.  
10  
25  
SENSE  
Power Supply Bridge B Source Pin. This pin must be connected to Power  
Ground directly or through a sensing power resistor.  
B
11  
12  
13  
26  
27  
28  
IN1  
IN2  
Logic Input  
Logic Input  
R Pin  
Bridge B Input 1  
Bridge B Input 2  
B
B
PROGCL  
Bridge B Overcurrent Level Programming. A resistor  
connected between this pin and Ground sets the  
programmable current limiting value for the bridge B. By  
connecting this pin to Ground the maximum current is set.  
This pin cannot be left non-connected.  
B
14  
15  
29  
30  
EN  
Logic Input  
Bridge B Enable. LOW logic level switches OFF all Power  
MOSFETs of Bridge B.  
If not used, it has to be connected to +5V.  
B
VBOOT  
Supply  
Voltage  
Bootstrap Voltage needed for driving the upper Power  
MOSFETs of both Bridge A and Bridge B.  
16  
17  
32  
33  
OUT2  
Power Output Bridge B Output 2.  
B
VS  
Power Supply Bridge B Power Supply Voltage. It must be connected to  
B
the supply voltage together with pin VS .  
A
20  
21  
4
5
VS  
Power Supply Bridge A Power Supply Voltage. It must be connected to  
A
the supply voltage together with pin VS .  
B
OUT2  
Power Output Bridge A Output 2.  
A
4/23  
L6206  
PIN DESCRIPTION (continued)  
PACKAGE  
SO24/  
PowerDIP24  
PowerSO36  
Name  
Type  
Function  
PIN #  
22  
PIN #  
7
8
VCP  
EN  
Output  
Charge Pump Oscillator Output.  
23  
Logic Input  
Bridge A Enable. LOW logic level switches OFF all Power  
MOSFETs of Bridge A.  
A
If not used, it has to be connected to +5V.  
24  
9
PROGCL  
R Pin  
Bridge A Overcurrent Level Programming. A resistor  
connected between this pin and Ground sets the  
programmable current limiting value for the bridge A. By  
connecting this pin to Ground the maximum current is set.  
This pin cannot be left non-connected.  
A
ELECTRICAL CHARACTERISTICS  
(T = 25 °C, V = 48V, unless otherwise specified)  
amb  
Symbol  
s
Parameter  
Turn-on Threshold  
Test Conditions  
Min  
6.6  
5.6  
Typ  
7
Max  
7.4  
6.4  
10  
Unit  
V
V
Sth(ON)  
V
Turn-off Threshold  
6
V
Sth(OFF)  
I
S
Quiescent Supply Current  
All Bridges OFF;  
T = -25°C to 125°C  
5
mA  
(6)  
j
T
Thermal Shutdown Temperature  
165  
°C  
j(OFF)  
Output DMOS Transistors  
High-Side Switch ON Resistance T = 25 °C  
R
DS(ON)  
0.34  
0.53  
0.4  
Ω
Ω
j
(6)  
(6)  
0.59  
T =125 °C  
j
Low-Side Switch ON Resistance T = 25 °C  
0.28  
0.47  
0.34  
0.53  
Ω
Ω
j
T =125 °C  
j
I
Leakage Current  
EN = Low; OUT = V  
2
mA  
mA  
DSS  
S
EN = Low; OUT = GND  
-0.15  
Source Drain Diodes  
V
Forward ON Voltage  
I
= 2.8A, EN = LOW  
1.15  
300  
200  
1.3  
V
SD  
SD  
t
Reverse Recovery Time  
Forward Recovery Time  
I = 2.8A  
f
ns  
ns  
rr  
t
fr  
Logic Input  
V
Low level logic input voltage  
High level logic input voltage  
Low Level Logic Input Current  
-0.3  
2
0.8  
7
V
V
IL  
IH  
IL  
V
I
GND Logic Input Voltage  
-10  
µA  
5/23  
L6206  
ELECTRICAL CHARACTERISTICS (continued)  
(T  
amb  
= 25 °C, V = 48V, unless otherwise specified)  
s
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
10  
Unit  
µA  
V
I
IH  
High Level Logic Input Current  
Turn-on Input Threshold  
Turn-off Input Threshold  
Input Threshold Hysteresis  
7V Logic Input Voltage  
V
th(ON)  
1.8  
1.3  
0.5  
2.0  
V
V
0.8  
V
th(OFF)  
th(HYS)  
0.25  
V
Switching Characteristics  
(7)  
t
I
I
=2.8A, Resistive Load  
=2.8A, Resistive Load  
100  
250  
1.6  
400  
ns  
µs  
D(on)EN  
LOAD  
Enable to out turn ON delay time  
t
Input to out turn ON delay time  
D(on)IN  
LOAD  
(dead time included)  
(7)  
t
I
=2.8A, Resistive Load  
=2.8A, Resistive Load  
40  
250  
800  
ns  
ns  
RISE  
LOAD  
LOAD  
Output rise time  
(7)  
t
I
300  
550  
600  
D(off)EN  
Enable to out turn OFF delay time  
Input to out turn OFF delay time  
t
I
I
=2.8A, Resistive Load  
=2.8A, Resistive Load  
ns  
ns  
D(off)IN  
LOAD  
(7)  
t
40  
250  
1
FALL  
LOAD  
Output Fall Time  
t
Dead Time Protection  
0.5  
1
µs  
dt  
f
-25°C<T <125°C  
0.6  
MHz  
CP  
j
Charge pump frequency  
Over Current Detection  
I
Input Supply Over Current  
DetectionThreshold  
-25°C<T <125 °C; RCL= 39 kΩ  
-10%  
-10%  
-30%  
0.57  
4.42  
5.6  
+10%  
+10%  
+30%  
A
A
A
s over  
j
-25°C<T <125 °C; RCL= 5 kΩ  
j
-25°C<T <125 °C; RCL= GND  
j
R
Open Drain ON Resistance  
OCD Turn-on Delay Time (8)  
OCD Turn-off Delay Time (8)  
I = 4mA  
40  
60  
Ω
OPDR  
t
I = 4mA; C < 100pF  
200  
100  
ns  
ns  
OCD(ON)  
EN  
t
I = 4mA; C < 100pF  
EN  
OCD(OFF)  
(6)  
(7)  
(8)  
Tested at 25°C in a restricted range and guaranteed by characterization.  
See Fig. 1.  
See Fig. 2.  
6/23  
L6206  
Figure 1. Switching Characteristic Definition  
EN  
V
th(ON)  
V
th(OFF)  
t
I
OUT  
90%  
10%  
t
D01IN1316  
t
t
RISE  
FALL  
t
t
D(ON)EN  
D(OFF)EN  
Figure 2. Overcurrent Detection Timing Definition  
I
OUT  
OCD  
Threshold  
t
V
OCD  
90%  
10%  
t
D01IN1222  
t
t
OCD(OFF)  
OCD(ON)  
7/23  
L6206  
CIRCUIT DESCRIPTION  
these pins. Two configurations are shown in Fig. 5  
and Fig. 6. If driven by an open drain (collector) struc-  
POWER STAGES and CHARGE PUMP  
ture, a pull-up resistor R and a capacitor C are  
EN EN  
The L6206 integrates two independent Power MOS  
Full Bridges. Each Power MOS has an Rd-  
son=0.3ohm (typical value @ 25°C), with intrinsic  
fast freewheeling diode. Cross conduction protection  
connected as shown in Fig. 5. If the driver is a stan-  
dard Push-Pull structure the resistor R and the ca-  
EN  
pacitor C are connected as shown in Fig. 6. The  
EN  
resistor R  
should be chosen in the range from  
EN  
is achieved using a dead time (td = 1  
µ
s typical) be-  
2.2kΩ  
to 180K  
Ω. Recommended values for R and  
EN  
tween the switch off and switch on of two Power MOS  
in one leg of a bridge.  
C
are respectively 100KΩ and 5.6nF. More infor-  
EN  
mation on selecting the values is found in the Over-  
current Protection section.  
Using N Channel Power MOS for the upper transis-  
tors in the bridge requires a gate drive voltage above  
the power supply voltage. The Bootstrapped (Vboot)  
supply is obtained through an internal Oscillator and  
few external components to realize a charge pump  
circuit as shown in Figure 3. The oscillator output  
(VCP) is a square wave at 600kHz (typical) with 10V  
amplitude. Recommended values/part numbers for  
the charge pump circuit are shown in Table1.  
Figure 4. Logic Inputs Internal Structure  
5V  
ESD  
PROTECTION  
D01IN1329  
Figure 5. EN and EN Pins Open Collector  
A
B
Table 1. Charge Pump External Components  
Values  
Driving  
OCDA or OCDB  
C
C
R
220nF  
10nF  
BOOT  
5V  
5V  
P
P
REN  
100Ω  
OPEN  
COLLECTOR  
OUTPUT  
D1  
D2  
1N4148  
1N4148  
ENA or ENB  
CEN  
D02IN1355  
Figure 3. Charge Pump Circuit  
VS  
Figure 6. EN and EN Pins Push-Pull Driving  
A
B
OCDA or OCDB  
D1  
D2  
CBOOT  
5V  
RP  
CP  
REN  
PUSH-PULL  
OUTPUT  
ENA or ENB  
CEN  
D01IN1328  
VCP  
VBOOT  
VSA VSB  
D02IN1356  
LOGIC INPUTS  
Pins IN1 , IN2 , IN1 , IN2 , EN and EN are TTL/  
TRUTH TABLE  
A
A
B
B
A
B
INPUTS  
OUTPUTS  
CMOS and uC compatible logic inputs. The internal  
structure is shown in Fig. 4. Typical value for turn-on  
and turn-off thresholds are respectively Vthon=1.8V  
and Vthoff = 1.3V.  
EN  
L
IN1  
X
IN2  
X
OUT1  
OUT2  
High Z  
GND  
GND  
Vs  
High Z  
GND  
Vs  
H
L
L
Pins EN and EN are commonly used to implement  
A
B
H
H
L
Overcurrent and Thermal protection by connecting  
them respectively to the outputs OCD and OCD ,  
H
L
H
GND  
Vs  
A
B
H
H
H
Vs  
which are open-drain outputs. If that type of connec-  
tion is chosen, some care needs to be taken in driving  
X
= Don't care  
High Z = High Impedance Output  
8/23  
L6206  
NON-DISSIPATIVE OVERCURRENT DETECTION AND PROTECTION  
In addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated. This circuit can be  
used to provides protection against a short circuit to ground or between two phases of the bridge as well as a  
roughly regulation of the load current. With this internal over current detection, the external current sense resis-  
tor normally used and its associated power dissipation are eliminated. Fig. 7 shows a simplified schematic of  
the overcurrent detection circuit for the Bridge A. Bridge B is provided of an analogous circuit.  
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-  
put current is implemented with each high side power MOS. Since this current is a small fraction of the output  
current there is very little additional power dissipation. This current is compared with an internal reference cur-  
rent I  
. When the output current reaches the detection threshold Isover the OCD comparator signals a fault  
REF  
condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4mA  
connected to OCD pin is turned on. Fig. 8 shows the OCD operation.  
This signal can be used to regulate the output current simply by connecting the OCD pin to EN pin and adding  
an external R-C as shown in Fig.7. The off time before recovering normal operation can be easily programmed  
by means of the accurate thresholds of the logic inputs.  
I
and, therefore, the output current detection threshold are selectable by R value, following the equations:  
CL  
REF  
– Isover = 5.6A ±30% at -25°C < T < 125°C if R = 0  
Ω
(PROGCL connected to GND)  
< 40k  
j
CL  
22100  
----------------  
– Isover =  
±10% at -25°C < T < 125°C if 5KΩ <  
R
Ω
j
CL  
R
CL  
Fig. 9 shows the output current protection threshold versus R value in the range 5k  
Ω
to 40kΩ.  
CL  
The Disable Time t  
before recovering normal operation can be easily programmed by means of the accu-  
DISABLE  
rate thresholds of the logic inputs. It is affected whether by C and R values and its magnitude is reported in  
EN  
EN  
Figure 10. The Delay Time t  
before turning off the bridge when an overcurrent has been detected depends  
DELAY  
only by C value. Its magnitude is reported in Figure 11.  
EN  
C
EN  
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C should  
EN  
be chosen as big as possible according to the maximum tolerable Delay Time and the R value should be chosen  
EN  
according to the desired Disable Time.  
The resistor R should be chosen in the range from 2.2K  
Ω
to 180KΩ. Recommended values for R and C  
EN EN  
EN  
are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time.  
9/23  
L6206  
Figure 7. Overcurrent Protection Simplified Schematic  
OUT1A VSA OUT2A  
POWER SENSE  
1 cell  
HIGH SIDE DMOSs OF  
THE BRIDGE A  
I1A  
I2A  
POWER SENSE  
1 cell  
POWER DMOS  
n cells  
POWER DMOS  
n cells  
µC or LOGIC  
TO GATE  
LOGIC  
+
+5V  
I1A / n  
I2A / n  
OCD  
COMPARATOR  
RENA  
CENA  
ENA  
(I1A+I2A) / n  
IREF  
INTERNAL  
OPEN-DRAIN  
1.2V  
-
OCDA  
RDS(ON)  
40Ω TYP.  
+
OVER  
TEMPERATURE  
IREF  
PROGCLA,  
D02IN1354  
RCLA  
.
Figure 8. Overcurrent Protection Waveforms  
IOUT  
ISOVER  
VEN  
VDD  
Vth(ON)  
Vth(OFF)  
VEN(LOW)  
ON  
OCD  
OFF  
ON  
tDELAY  
tDISABLE  
BRIDGE  
OFF  
tOCD(ON) tEN(FALL)  
tOCD(OFF)  
tEN(RISE)  
tD(ON)EN  
tD(OFF)EN  
D02IN1400  
10/23  
L6206  
Figure 9. Output Current Protection Threshold versus R Value  
CL  
5
4.5  
4
3.5  
3
2.5  
ISOVER  
[A]  
2
1.5  
1
0.5  
0
5k  
10k  
15k  
20k  
RCL  
25k  
30k  
35k  
40k  
[
]
Ω
Figure 10. t  
versus C and R (V = 5V).  
EN EN DD  
DISABLE  
Ω
Ω
R E N = 220 k  
R E N = 100 k  
3
.
Ω
Ω
R E N = 47 k  
R E N = 33 k  
1 10  
Ω
R E N = 10 k  
100  
10  
1
1
10  
100  
C E N [nF ]  
11/23  
L6206  
Figure 11. t  
versus C (V = 5V).  
EN DD  
DELAY  
10  
1
0.1  
1
10  
100  
Cen [nF]  
THERMAL PROTECTION  
In addition to the Ovecurrent Detection, the L6206 integrates a Thermal Protection for preventing the device  
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible  
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)  
with 15°C hysteresis (typ. value).  
12/23  
L6206  
APPLICATION INFORMATION  
A typical application using L6206 is shown in Fig. 12. Typical component values for the application are shown  
in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power  
pins (VS and VS ) and ground near the L6206 to improve the high frequency filtering on the power supply and  
A
B
reduce high frequency transients generated by the switching. The capacitors connected from the EN /OCD  
A
A
and EN /OCD nodes to ground set the shut down time for the Brgidge A and Bridge B respectively when an  
B
B
over current is detected (see Overcurrent Protection). The two current sources (SENSE and SENSE ) should  
A
B
be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immu-  
nity, unused logic pins are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin descrip-  
tion). It is recommended to keep Power Ground and Signal Ground separated on PCB.  
Table 2. Component Values for Typical Application  
C
C
C
C
C
C
C
100uF  
100nF  
220nF  
10nF  
D
D
R
R
R
R
R
1N4148  
1N4148  
5KΩ  
1
1
2
2
BOOT  
P
CLA  
CLB  
ENA  
ENB  
P
5KΩ  
5.6nF  
5.6nF  
68nF  
100kΩ  
100kΩ  
100Ω  
ENA  
ENB  
REF  
Figure 12. Typical Application  
VSA  
VSB  
+
VS  
8-52VDC  
20  
17  
OCDA  
ENA  
4
RENA  
CENA  
C2  
C1  
23  
ENA  
ENB  
POWER  
GROUND  
-
D1  
RP  
VCP  
22  
OCDB  
ENB  
9
RENB  
CENB  
CP  
D2  
CBOOT  
14  
VBOOT  
SIGNAL  
GROUND  
15  
3
SENSEA  
SENSEB  
IN1B  
IN2B  
IN1A  
IN2A  
10  
11  
12  
1
IN1B  
LOADA  
LOADB  
OUT1A  
OUT2A  
IN2B  
IN1A  
IN2A  
5
21  
OUT1B  
OUT2B  
8
2
16  
PROGCLA  
PROGCLB  
24  
13  
18  
19  
6
RCLA  
GND  
GND  
GND  
GND  
RCLB  
7
D02IN1344  
13/23  
L6206  
PARALLELED OPERATION  
The outputs of the L6206 can be paralleled to increase the output current capability or reduce the power dissi-  
pation in the device at a given current level. It must be noted, however, that the internal wire bond connections  
from the die to the power or sense pins of the package must carry current in both of the associated half bridges.  
When the two halves of one full bridge (for example OUT1 and OUT2 ) are connected in parallel, the peak  
A
A
current rating is not increased since the total current must still flow through one bond wire on the power supply  
or sense pin. In addition the over current detection senses the sum of the current in the upper devices of each  
bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detec-  
tion threshold.  
For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge  
1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 13. The current in the two devices  
connected in parallel will share very well since the R  
of the devices on the same die is well matched.  
DS(ON)  
When connected in this configuration the over current detection circuit, which senses the current in each bridge  
(A and B), will sense the current in upper devices connected in parallel independently and the sense circuit with  
the lowest threshold will trip first. With the enables connected in parallel, the first detection of an over current in  
either upper DMOS device will turn of both bridges. Assuming that the two DMOS devices share the current  
equally, the resulting over current detection threshold will be twice the minimum threshold set by the resistors  
R
CLA  
or R  
in figure 13. It is recommended to use R  
= R  
.
CLB  
CLA  
CLB  
In this configuration the resulting Bridge has the following characteristics.  
- Equivalent Device: FULL BRIDGE  
- R  
0.15Ω Typ. Value @ T = 25°C  
J
DS(ON)  
- 5.6A max RMS Load Current  
- 11.2A max OCD Threshold  
Figure 13. Parallel connection for higher current  
VSA  
+
VS  
8-52VDC  
20  
VSB  
OCDB  
ENB  
C2  
C1  
17  
9
14  
POWER  
GROUND  
D1  
RP  
-
VCP  
OCDA  
ENA  
22  
4
REN  
CEN  
CP  
23  
EN  
D2  
CBOOT  
VBOOT  
SENSEA  
SENSEB  
OUT1A  
OUT2A  
OUT1B  
OUT2B  
SIGNAL  
GROUND  
15  
3
IN1A  
IN2A  
1
2
IN1  
10  
5
IN1B  
IN2B  
21  
8
11  
12  
LOAD  
IN2  
16  
PROGCLA  
PROGCLB  
24  
13  
18  
19  
6
RCLA  
GND  
GND  
GND  
GND  
RCLB  
7
D02IN1364  
14/23  
L6206  
To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge  
2 of the Bridge A can be connected in parallel and the same done for the Bridge B as shown in Figure 14. In  
this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense  
pins so the dissipation in the device will be reduced, but the peak current rating is not increased.  
When connected in this configuration the over current detection circuit, senses the sum of the current in upper  
devices connected in parallel. With the enables connected in parallel, an over current will turn of both bridges.  
Since the circuit senses the total current in the upper devices, the over current threshold is equal to the threshold  
set the resistor R  
or R  
in figure 14. R  
sets the threshold when outputs OUT1 and OUT2 are high  
CLA  
CLB  
CLA  
A
A
and resistor R  
sets the threshold when outputs OUT1 and OUT2 are high.  
CLB  
B B  
It is recommended to use R  
= R  
.
CLB  
CLA  
In this configuration, the resulting bridge has the following characteristics.  
- Equivalent Device: FULL BRIDGE  
- R  
0.15Ω Typ. Value @ T = 25°C  
J
DS(ON)  
- 2.8A max RMS Load Current  
- 5.6A max OCD Threshold  
Figure 14. Parallel connection with lower Overcurrent Threshold  
VSA  
+
VS  
8-52VDC  
20  
17  
VSB  
C1  
C2  
OCDA  
ENA  
4
POWER  
GROUND  
-
23  
D1  
RP  
VCP  
22  
OCDB  
ENB  
9
REN  
CEN  
CP  
D2  
CBOOT  
14  
EN  
VBOOT  
SENSEA  
SENSEB  
OUT1A  
OUT2A  
OUT1B  
OUT2B  
SIGNAL  
GROUND  
15  
3
IN1A  
IN2A  
10  
5
1
2
INA  
INB  
21  
8
IN1B  
IN2B  
11  
12  
LOAD  
16  
PROGCLA  
PROGCLB  
24  
13  
18  
19  
6
RCLA  
GND  
GND  
GND  
GND  
RCLB  
7
D02IN1361  
15/23  
L6206  
It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Fig. 15. In this  
configuration the, the over current threshold is equal to twice the minimum threshold set by the resistors R  
CLA  
or R  
in Figure 15. It is recommended to use R  
= R  
.
CLB  
CLA  
CLB  
The resulting half bridge has the following characteristics.  
- Equivalent Device: HALF BRIDGE  
- R  
0.075Ω Typ. Value @ T = 25°C  
J
DS(ON)  
- 5.6A max RMS Load Current  
- 11.2A max OCD Threshold  
Figure 15. Paralleling the four Half Bridges  
VSA  
+
VS  
8-52VDC  
20  
17  
OCDA  
ENA  
VSB  
4
C2  
C1  
23  
POWER  
GROUND  
-
D1  
RP  
VCP  
22  
OCDB  
ENB  
9
REN  
CEN  
CP  
D2  
CBOOT  
14  
EN  
VBOOT  
SENSEA  
SENSEB  
OUT1A  
SIGNAL  
GROUND  
15  
3
IN1A  
IN2A  
10  
5
1
2
OUT2A  
IN  
21  
IN1B  
IN2B  
LOAD  
11  
12  
OUT1B  
OUT2B  
8
16  
18  
19  
6
PROGCLA  
24  
13  
RCLA  
GND  
GND  
GND  
GND  
PROGCLB  
D02IN1365  
RCLB  
7
16/23  
L6206  
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION  
In Fig. 16 and Fig. 17 are shown the approximate relation between the output current and the IC power dissipa-  
tion using PWM current control driving two loads, for two different driving types:  
– One Full Bridge ON at a time (Fig.16) in which only one load at a time is energized.  
– Two Full Bridges ON at the same time (Fig.17) in which two loads at the same time are energized.  
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to  
establish which package should be used and how large must be the on-board copper dissipating area to guar-  
antee a safe operating junction temperature (125°C maximum).  
Figure 16. IC Power Dissipation versus Output Current with One Full Bridge ON at a time.  
ONE FULL BRIDGE ON AT A TIME  
10  
8
IA  
IOUT  
IB  
6
PD [W]  
IOUT  
4
2
0
Test Conditions:  
Supply Voltage = 24V  
No PWM  
f
SW = 30kHz (slow decay)  
0
0.5  
1
1.5  
2
2.5  
3
I
OUT [A]  
Figure 17. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.  
TWO FULL BRIDGES ON AT THE SAME TIME  
IA  
10  
IOUT  
8
IB  
6
IOUT  
PD [W]  
4
2
0
Test Conditions:  
Supply Voltage = 24V  
No PWM  
fSW = 30kHz (slow decay)  
0
0.5  
1
1.5  
IOUT [A]  
2
2.5  
3
THERMAL MANAGEMENT  
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be de-  
liver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the  
available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can  
be achieved using copper on the PCB with proper area and thickness. Figures 19, 20 and 21 show the Junction-to-  
Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages.  
For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board  
2
with 6cm dissipating footprint (copper thickness of 35µm), the R  
is about 35°C/W. Fig. 18 shows mount-  
th j-amb  
ing methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be  
reduced down to 15°C/W.  
17/23  
L6206  
Figure 18. Mounting the PowerSO package.  
Slug soldered  
to PCB with  
dissipating area  
Slug soldered  
Slug soldered to PCB with  
dissipating area plus ground layer  
contacted through via holes  
to PCB with  
dissipating area  
plus ground layer  
Figure 19. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.  
ºC / W  
43  
38  
33  
W ithout Ground Layer  
28  
W ith Ground Layer  
W ith Ground Layer+16 via  
H oles  
23  
On-Board Copper Area  
18  
13  
1
2
3
4
5
6
7
8
9
10 11 12 13  
sq. cm  
Figure 20. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.  
ºC / W  
On-Board Copper Area  
49  
48  
Copper Are a is on Bottom  
S ide  
47  
46  
Copper Are a is on To p Side  
45  
44  
43  
42  
41  
40  
39  
1
2
3
4
5
6
7
8
9
10 11 12  
sq. cm  
Figure 21. SO24 Junction-Ambient thermal resistance versus on-board copper area.  
ºC / W  
On-Board Copper Area  
68  
66  
64  
62  
60  
C o pp er Are a is on Top Sid e  
58  
56  
54  
52  
50  
48  
1
2
3
4
5
6
7
8
9
10 11 12  
sq. cm  
18/23  
L6206  
Figure 22. Typical Quiescent Current vs.  
Figure 25. Typical High-Side RDS(ON) vs.  
Supply Voltage  
Supply Voltage  
Iq [mA]  
Ω
[ ]  
RDS(ON)  
5.6  
0.380  
0.376  
0.372  
0.368  
0.364  
0.360  
0.356  
0.352  
0.348  
0.344  
0.340  
0.336  
f
= 1kHz  
T = 25°C  
j
sw  
T = 85°C  
j
5.4  
5.2  
5.0  
4.8  
4.6  
T = 25°C  
j
T = 125°C  
j
0
5
10  
15  
VS [V]  
20  
25  
30  
0
10  
20  
30  
40  
50  
60  
VS [V]  
Figure 23. Normalized Typical Quiescent  
Figure 26. Normalized R  
vs.Junction  
DS(ON)  
Current vs. Switching Frequency  
Iq / (Iq @ 1 kHz)  
Temperature (typical value)  
RDS(ON) / (RDS(ON) @ 25 °C)  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0
20  
40  
60  
80  
100  
120  
140  
0
20  
40  
60  
80  
100  
Tj [°C]  
fSW [kHz]  
Figure 24. Typical Low-Side R  
Supply Voltage  
vs.  
Figure 27. Typical Drain-Source Diode  
Forward ON Characteristic  
ISD [A]  
DS(ON)  
Ω
[ ]  
RDS(ON)  
0.300  
3.0  
T = 25°C  
j
0.296  
0.292  
0.288  
0.284  
0.280  
0.276  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
T = 25°C  
j
700  
800  
900  
1000  
SD [mV]  
1100  
1200  
1300  
0
5
10  
15  
20  
25  
30  
V
V
S [V]  
19/23  
L6206  
mm  
inch  
DIM.  
MIN. TYP. MAX. MIN. TYP. MAX.  
OUTLINE AND  
MECHANICAL DATA  
A
a1  
a2  
a3  
b
3.60  
0.141  
0.012  
0.130  
0.004  
0.015  
0.012  
0.630  
0.385  
0.570  
0.10  
0.30 0.004  
3.30  
0
0.10  
0
0.22  
0.23  
0.38 0.008  
0.32 0.009  
16.00 0.622  
9.80 0.370  
14.50 0.547  
c
D (1) 15.80  
D1  
E
9.40  
13.90  
e
0.65  
0.0256  
0.435  
e3  
11.05  
E1 (1) 10.90  
E2  
11.10 0.429  
2.90  
0.437  
0.114  
0.244  
0.126  
0.004  
0.626  
0.043  
0.043  
E3  
E4  
G
H
5.80  
2.90  
0
6.20 0.228  
3.20 0.114  
0.10  
0
15.50  
15.90 0.610  
1.10  
h
L
0.80  
1.10 0.031  
10°(max.)  
8 °(max.)  
N
S
PowerSO36  
(1): "D" and "E1" do not include mold flash or protrusions  
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)  
- Critical dimensions are "a3", "E" and "G".  
N
N
a2  
A
c
a1  
e
A
DETAIL B  
lead  
E
DETAIL A  
e3  
H
DETAIL A  
D
slug  
a3  
BOTTOM VIEW  
36  
19  
E3  
B
E1  
E2  
D1  
DETAIL B  
0.35  
Gage Plane  
- C -  
SEATING PLANE  
1
1
8
S
L
G
C
M
b
0.12  
A B  
PSO36MEC  
h x 45˚  
(COPLANARITY)  
20/23  
L6206  
mm  
MIN. TYP. MAX. MIN. TYP. MAX.  
4.320 0.170  
inch  
DIM.  
OUTLINE AND  
MECHANICAL DATA  
A
A1  
A2  
B
0.380  
0.015  
3.300  
0.130  
0.410 0.460 0.510 0.016 0.018 0.020  
1.400 1.520 1.650 0.055 0.060 0.065  
0.200 0.250 0.300 0.008 0.010 0.012  
31.62 31.75 31.88 1.245 1.250 1.255  
B1  
c
D
E
7.620  
8.260 0.300  
0.325  
e
2.54  
0.100  
E1  
6.350 6.600 6.860 0.250 0.260 0.270  
0.300  
7.620  
e1  
L
3.180  
3.430 0.125  
0.135  
Powerdip 24  
M
0˚ min, 15˚ max.  
E1  
A2  
A
A1  
L
B
B1  
e
e1  
D
24  
1
13  
12  
c
M
SDIP24L  
21/23  
L6206  
mm  
inch  
DIM.  
OUTLINE AND  
MECHANICAL DATA  
MIN.  
2.35  
0.10  
0.33  
0.23  
15.20  
TYP. MAX. MIN.  
2.65 0.093  
0.30 0.004  
0.51 0.013  
0.32 0.009  
15.60 0.598  
TYP. MAX.  
0.104  
A
A1  
B
0.012  
0.200  
Weight: 0.60gr  
C
0.013  
(1)  
0.614  
D
E
e
7.40  
7.60 0.291  
1.27  
0.299  
0.050  
H
10.0  
0.25  
0.40  
10.65 0.394  
0;75 0.010  
1.27 0.016  
0˚ (min.), 8˚ (max.)  
0.10  
0.419  
h
0.030  
L
0.050  
k
ddd  
0.004  
SO24  
(1) “D” dimension does not include mold flash, protusions or gate  
burrs. Mold flash, protusions or gate burrs shall not exceed  
0.15mm per side.  
0070769 C  
22/23  
L6206  
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences  
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted  
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject  
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not  
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.  
The ST logo is a registered trademark of STMicroelectronics.  
All other names are the property of their respective owners  
© 2003 STMicroelectronics - All rights reserved  
STMicroelectronics GROUP OF COMPANIES  
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www.st.com  
23/23  

L6206D013TR CAD模型

原理图符号

PCB 封装图

3D模型

L6206D013TR 替代型号

型号 制造商 描述 替代类型 文档
L6206D STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER 完全替代
L6206N STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER 完全替代
L6208N STMICROELECTRONICS FULLY INTEGRATED STEPPER MOTOR DRIVER 类似代替

L6206D013TR 相关器件

型号 制造商 描述 价格 文档
L6206N STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER 获取价格
L6206PD STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER 获取价格
L6206PD013TR STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER 获取价格
L6206Q STMICROELECTRONICS DMOS dual full bridge driver 获取价格
L6206QTR STMICROELECTRONICS DMOS dual full bridge driver 获取价格
L6207 STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER 获取价格
L6207D STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER 获取价格
L6207D013TR STMICROELECTRONICS 双全桥驱动器 采用PWM电流控制器 获取价格
L6207N STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER 获取价格
L6207PD STMICROELECTRONICS DMOS DUAL FULL BRIDGE DRIVER WITH PWM CURRENT CONTROLLER 获取价格

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