U2352B
Pin Description
Pin
1
Symbol
Osc
Function
1
2
3
4
8
7
6
5
Osc
V
S
Oscillator
2
V
Contr
Control voltage input
V
Output
GND
3
I
Setpoint value current
monitoring
Contr
Set
4
5
6
7
8
S OUT Output, current switch S
2 2
I
Set
S IN
2
Input, current switch S
Ground
2
GND
S OUT
S IN
2
Output
Output
2
V
S
Supply voltage
95 9701
Supply, Pin 8
Pulse Width Control, Pins 1 and 2
Internal voltage limitation in the U2352B allows a simple
At the frequency-determining capacitor, C , at Pin 1,
switching over of two internal current sources gives rise
osc
supply via a series resistor R . This enables operation of
1
the circuit under different operating voltages. Supply
to a triangular voltage which comparator, K , compares
1
voltage between Pin 8 (V ) and Pin 6 (GND) builds up via
S
with the control voltage at Pin 2. If the voltage, V , is
1
R and is smoothed by C .
1
1
more negative than the control voltage V , the output
2
stage is switched on via the output stage logic. When C
is charged, the whole process then runs in reverse order
(see figure 3).
osc
The series resistor R is calculated as follows:
1
VBmin VSmax
R1max
Itot
Load Current Monitoring, Pins 3, 4, 5
where
Load current can be measured with the aid of an external
shunt resistor, but this is only appropriate for decreased
loads due to additional power loss and component size
and costs. This involves the shunt voltage being fed
directly to Pin 4 via a protective resistor (see figure 5).
V
V
= Minimum operating voltage
= Maximum supply voltage
Bmin
Smax
I
I
I
= I + I
Smax X
tot
= Maximum current consumption of the IS
= Current consumption of the external elements
Smax
X
In order to save component costs and additional power
loss, the integrated load current monitoring allows the
load current to be directly measured via the voltage drop
Various thresholds are derived from an internal reference
voltage source.
at the on-state resistance, R
, of the FET, without an
DS(on)
Voltage Monitoring
additional shunt resistor. The drain voltage of the FET is
supplied via an external protective resistor to Pin 5.
During the off-state of the FET, a diode clamp circuit
protects the detection input, Pin 5. In the on state, the load
During build-up and reduction of the operating voltage,
uncontrolled output pulses with excessively low ampli-
tude are suppressed by the internal monitoring circuit. All
latches are reset and the output of the load current detec-
tion Pin 4 is switched to ground.
current flowing through the FET generates
a
corresponding voltage drop at its R
, which is in turn
DS(on)
converted into a current at Pin 5 by the protective resistor.
This current reaches the integration element at Pin 4 via
the switch S , which is only closed in the on-state of the
FET. If the voltage at Pin 4 exceeds the setpoint value set
at Pin 3, as a result of a high load current, the shutdown
latch is set and the output stage is blocked. To enable the
circuit again, it is necessary to switch the operating
voltage off and then back on again.
Chip Temperature Monitoring
2
U2352B has integrated chip temperature monitoring
which switches off the output stage when a temperature
of approximately 140°C is reached. The device is not
enabled again until cooling has taken place and the supply
voltage has been switched off and then back on again.
Switch-off behavior is adjusted with the resistors at Pin 4
and Pin 5 and also with the capacitor at Pin 4.
TELEFUNKEN Semiconductors
3 (8)
Rev. A1, 29-May-96