CY74FCT373CTSOCR
更新时间：2025-05-19 18:21:23
品牌：TI
描述：IC FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, SOIC-20, Bus Driver/Transceiver
概述
规格参数
数据手册CY74FCT373CTSOCR 概述
IC FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, SOIC-20, Bus Driver/Transceiver 总线驱动器/收发器
CY74FCT373CTSOCR 规格参数
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | SOP, | 针数： | 20 |
| Reach Compliance Code： | unknown | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.06 | 系列： | FCT |
| JESD-30 代码： | R-PDSO-G20 | JESD-609代码： | e4 |
| 长度： | 12.8 mm | 逻辑集成电路类型： | BUS DRIVER |
| 位数： | 8 | 功能数量： | 1 |
| 端口数量： | 2 | 端子数量： | 20 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 输出极性： | TRUE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 传播延迟（tpd）： | 5.5 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 2.65 mm | 最大供电电压 (Vsup)： | 5.25 V |
| 最小供电电压 (Vsup)： | 4.75 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | CMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | NICKEL PALLADIUM GOLD |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 宽度： | 7.5 mm |
| Base Number Matches： | 1 |
CY74FCT373CTSOCR 数据手册
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PDF下载CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
CY54FCT373T . . . D PACKAGE
CY74FCT373T . . . Q OR SO PACKAGE
(TOP VIEW)
Function and Pinout Compatible With FCT
and F Logic
Reduced V
of Equivalent FCT Functions
(Typically = 3.3 V) Versions
OH
OE
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
V
CC
O
O
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
0
7
D
0
D
7
6
D
D
1
O
O
D
D
O
O
O
1
2
2
3
3
6
5
5
4
I
Supports Partial-Power-Down Mode
off
Operation
D
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
O
4
GND 10
11 LE
– 1000-V Charged-Device Model (C101)
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
3-State Outputs
CY54FCT373T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT373T
– 64-mA Output Sink Current
– 32-mA Output Source Current
description
The ’FCT373T devices consist of eight latches with 3-state outputs for bus-organized applications. When the
latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup
times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE)
input is low. When OE is high, the bus output is in the high-impedance state. In this mode, data can be entered
into the latches.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
SPEED
(ns)
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
CY74FCT373CTQCT
CY74FCT373CTSOC
CY74FCT373CTSOCT
CY74FCT373ATQCT
CY74FCT373ATSOC
CY74FCT373ATSOCT
CY74FCT373TSOC
CY74FCT373TSOCT
CY54FCT373ATDMB
QSOP – Q
SOIC – SO
QSOP – Q
SOIC – SO
Tape and reel
Tube
4.7
4.7
4.7
5.2
5.2
5.2
8
FCT373C
FCT373C
FCT373A
FCT373
Tape and reel
Tape and reel
Tube
–40°C to 85°C
–55°C to 125°C
Tape and reel
Tube
SOIC – SO
CDIP – D
FCT373
Tape and reel
Tube
8
5.6
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
OUTPUT
O
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
H = High logic level, L = Low logic level,
X = Don’tcare,Z=High-impedancestate,
Q
= Previous state of flip flops (Q
)
n–1
n
logic diagram (positive logic)
1
OE
11
LE
CP
Q
D
2
O
0
3
D
0
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
†
absolute maximum rating over operating free-air temperature range (unless otherwise noted)
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, θ (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
JA
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
Ambient temperature range with power applied, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperatingconditions”isnotimplied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
CY54FCT373T
CY74FCT373T
MIN NOM MAX
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
IH
0.8
–12
32
0.8
–32
64
V
IL
I
I
mA
mA
°C
OH
OL
T
A
–55
125
–40
85
NOTE 2: All unused inputs of the device must be held at V
or GND to ensure proper device operation.
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CY54FCT373T
CY74FCT373T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
= 4.75 V,
= 4.5 V,
I
I
I
I
I
I
I
= –18 mA
= –18 mA
–0.7
–1.2
CC
CC
CC
IN
V
V
IK
–0.7
–1.2
IN
= –12 mA
= –32 mA
= –15 mA
= 32 mA
= 64 mA
2.4
3.3
OH
OH
OH
OL
OL
V
OH
2
V
V
CC
= 4.75 V
2.4
3.3
V
V
= 4.5 V,
0.3
0.2
0.55
CC
V
V
V
V
OL
= 4.75 V,
0.3
0.2
0.55
CC
All inputs
hys
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 5.5 V,
= 5.25 V,
= 0 V,
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= V
= V
5
±1
IN
IN
IN
IN
IN
IN
CC
CC
I
I
I
I
I
µA
I
5
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
µA
µA
µA
µA
IH
±1
IL
±1
= 2.7 V
= 2.7 V
= 0.5 V
= 0.5 V
= 0 V
10
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OZH
OZL
10
–10
–225
–10
–60
–120
‡
mA
µA
I
I
I
OS
= 0 V
–60
–120
–225
±1
= 4.5 V
±1
off
= 5.5 V,
= 5.25 V,
≤ 0.2 V,
V
V
≥ V
≥ V
– 0.2 V
– 0.2 V
0.1
0.5
0.2
IN
IN
IN
CC
mA
CC
≤ 0.2 V,
0.1
0.5
0.2
2
IN
CC
§
= 5.5 V, V = 3.4 V , f = 0, Outputs open
IN
2
1
∆I
CC
mA
§
= 5.25 V, V = 3.4 V , f = 0, Outputs open
IN
1
†
‡
Typical values are at V
CC
= 5 V, T = 25°C.
A
Notmorethanoneoutputshouldbeshortedatatime.Durationofshortshouldnotexceedonesecond.Theuseofhigh-speedtestapparatusand/or
sample-and-holdtechniquesarepreferabletominimizeinternalchipheatingandmoreaccuratelyreflectoperationalvalues.Otherwise,prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, I
Per TTL-driven input (V = 3.4 V); all other inputs at V
tests should be performed last.
OS
§
or GND
IN CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
CY54FCT373T
CY74FCT373T
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
= 5.5 V, Outputs open,
CC
One input switching at 50% duty cycle, OE = GND,
0.06
0.12
V
≤ 0.2 V or V ≥ V
– 0.2 V
IN
IN CC
mA/
MHz
¶
I
CCD
V
CC
= 5.25 V, Outputs open,
One input switching at 50% duty cycle, OE = GND,
0.06
0.12
V
IN
≤ 0.2 V or V ≥ V
– 0.2 V
IN CC
V
V
≤ 0.2 V or
One bit switching
at f = 10 MHz
1
at 50% duty cycle
IN
IN
0.7
1
1.4
2.4
≥ V
– 0.2 V
CC
V
= 5.5 V,
CC
V
IN
= 3.4 V or GND
Outputs open,
OE = GND,
LE = V
CC
V
IN
V
IN
≤ 0.2 V or
Eight bits switching
at f = 2.5 MHz
1
at 50% duty cycle
||
2.6
1.3
≥ V
– 0.2 V
CC
||
V
IN
= 3.4 V or GND
3.3 10.6
#
I
C
mA
V
V
≤ 0.2 V or
One bit switching
at f = 10 MHz
1
at 50% duty cycle
IN
IN
0.7
1
1.4
2.4
≥ V
– 0.2 V
CC
V
= 5.25 V,
CC
V
IN
= 3.4 V or GND
Outputs open,
OE = GND,
LE = V
CC
V
IN
V
IN
≤ 0.2 V or
Eight bits switching
at f = 2.5 MHz
1
at 50% duty cycle
||
||
1.3
2.6
≥ V
– 0.2 V
CC
V
IN
= 3.4 V or GND
3.3 10.6
C
C
6
8
10
12
6
8
10
12
pF
pF
i
o
†
¶
#
Typical values are at V
CC
= 5 V, T = 25°C.
A
This parameter is derived for use in total power-supply calculations.
= I + ∆I × D × N + I (f /2 + f × N )
I
C
CC
CC
H
T
CCD
0
1
1
Where:
I
I
∆I
D
N
= Total supply current
= Power-supply current with CMOS input levels
C
CC
CC
H
T
= Power-supply current for a TTL high input (V = 3.4 V)
IN
= Duty cycle for TTL inputs high
= Number of TTL inputs at D
H
I
f
f
= Dynamic current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
CCD
0
1
N
= Number of inputs changing at f
1
1
All currents are in milliamperes and all frequencies are in megahertz.
||
Values for these conditions are examples of the I
CC
formula.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY54FCT373T
CY54FCT373AT
UNIT
MIN
6
MAX
MIN
6
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↑
Hold time, data after LE↑
ns
ns
ns
2
2
1.5
1.5
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
CY74FCT373T
CY74FCT373AT
CY74FCT373CT
UNIT
MIN
6
MAX
MIN
5
MAX
MIN
5
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↑
Hold time, data after LE↑
ns
ns
ns
2
2
2
1.5
1.5
1.5
switching characteristics over operating free-air temperature range (see Figure 1)
CY54FCT373AT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
2
MAX
5.6
5.6
9.8
9.8
7.5
7.5
6.5
6.5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
O
O
O
O
LE
OE
OE
ns
2
1.5
1.5
1.5
1.5
ns
ns
switching characteristics over operating free-air temperature range (see Figure 1)
CY74FCT373T CY74FCT373AT CY74FCT373CT
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
1.5
1.5
2
MAX
8
MIN
1.5
1.5
2
MAX
5.2
5.2
8.5
8.5
6.5
6.5
5.5
5.5
MIN
1.5
1.5
2
MAX
4.7
4.7
5.5
5.5
5.5
5.5
5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
O
O
O
O
8
13
13
12
12
7.5
7.5
LE
OE
OE
ns
2
2
2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CY54FCT373T, CY74FCT373T
8-BIT LATCHES
WITH 3-STATE OUTPUTS
SCCS021B – MAY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
S1
500 Ω
From Output
Under Test
From Output
Under Test
Test
Point
TEST
/t
S1
t
Open
7 V
PLH PHL
C
= 50 pF
C
= 50 pF
L
L
500 Ω
500 Ω
t
/t
PLZ PZL
/t
(see Note A)
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
h
t
3 V
su
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
t
t
t
t
PLH
PHL
PLH
PZL
PZH
PLZ
≈3.5 V
V
Output
Waveform 1
(see Note B)
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
V
+ 0.3 V
OL
V
OL
V
OL
t
t
PHL
PHZ
V
V
V
OH
OH
Output
Waveform 2
(see Note B)
Out-of-Phase
Output
– 0.3 V
OH
1.5 V
1.5 V
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
5962-9221701MRA
5962-9221702MRA
5962-9221703M2A
CY54FCT373ATDMB
CY74FCT373ATQCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CDIP
LCCC
CDIP
SSOP
J
J
20
20
20
20
20
1
1
TBD
TBD
TBD
TBD
A42
N / A for Pkg Type
Call TI
Call TI
FK
J
1
POST-PLATE N / A for Pkg Type
A42 N / A for Pkg Type
1
DBQ
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CY74FCT373ATQCTE4
CY74FCT373ATQCTG4
CY74FCT373ATSOC
CY74FCT373ATSOCE4
CY74FCT373ATSOCG4
CY74FCT373ATSOCT
CY74FCT373ATSOCTE4
CY74FCT373ATSOCTG4
CY74FCT373TSOC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DBQ
DBQ
DW
DW
DW
DW
DW
DW
DW
DW
DW
20
20
20
20
20
20
20
20
20
20
20
2500
2500
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CY74FCT373TSOCE4
CY74FCT373TSOCG4
25
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2012
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CY74FCT373ATQCT
CY74FCT373ATSOCT
SSOP
SOIC
DBQ
DW
20
20
2500
2000
330.0
330.0
16.4
24.4
6.5
9.0
2.1
2.7
8.0
16.0
24.0
Q1
Q1
10.8
13.0
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Aug-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CY74FCT373ATQCT
CY74FCT373ATSOCT
SSOP
SOIC
DBQ
DW
20
20
2500
2000
367.0
367.0
367.0
367.0
38.0
45.0
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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Applications
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Copyright © 2012, Texas Instruments Incorporated
CY74FCT373CTSOCR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| CY74FCT373CTSOCT | TI | 8-Bit Latches | 获取价格 |
|
| CY74FCT373CTSOCT | CYPRESS | Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20 | 获取价格 |
|
| CY74FCT373CTSOCTE4 | TI | FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, SOIC-20 | 获取价格 |
|
| CY74FCT373CTSOCTG4 | TI | FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, SOIC-20 | 获取价格 |
|
| CY74FCT373DTSOCT | CYPRESS | Bus Driver, FCT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, PLASTIC, SOIC-20 | 获取价格 |
|
| CY74FCT373T | TI | 8-BIT LATCHES WITH 3-STATE OUTPUTS | 获取价格 |
|
| CY74FCT373TDIP | TI | 8-Bit Latches | 获取价格 |
|
| CY74FCT373TQSOP | TI | 8-Bit Latches | 获取价格 |
|
| CY74FCT373TSOC | TI | 8-Bit Latches | 获取价格 |
|
| CY74FCT373TSOC | CYPRESS | 暂无描述 | 获取价格 |
|
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