概述
规格参数
数据手册
替代型号DRV8804PWPR 概述
具有串行控制的 60V、2.3A、四路低侧电机驱动器 | PWP | 16 | -40 to 125 电机驱动器 运动控制电子器件
DRV8804PWPR 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | TSSOP |
| 包装说明： | HTSSOP, | 针数： | 16 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 0.75 |
| 模拟集成电路 - 其他类型： | STEPPER MOTOR CONTROLLER | JESD-30 代码： | R-PDSO-G16 |
| JESD-609代码： | e4 | 长度： | 5 mm |
| 湿度敏感等级： | 3 | 功能数量： | 1 |
| 端子数量： | 16 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 最大输出电流： | 2 A |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | HTSSOP |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH |
| 峰值回流温度（摄氏度）： | 260 | 座面最大高度： | 1 mm |
| 最大供电电流 (Isup)： | 2.1 mA | 最大供电电压 (Vsup)： | 60 V |
| 最小供电电压 (Vsup)： | 8.2 V | 标称供电电压 (Vsup)： | 24 V |
| 表面贴装： | YES | 温度等级： | INDUSTRIAL |
| 端子面层： | Nickel/Palladium/Gold (Ni/Pd/Au) | 端子形式： | GULL WING |
| 端子节距： | 0.65 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 宽度： | 4.4 mm |
| Base Number Matches： | 1 |
DRV8804PWPR 数据手册
通过下载DRV8804PWPR数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载DRV8804
www.ti.com
SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC
Check for Samples: DRV8804
1
FEATURES
•
•
8.2-V to 60-V Operating Supply Voltage Range
Thermally Enhanced Surface Mount Package
•
4-Channel Protected Low-Side Driver
–
Four NMOS FETs With Overcurrent
Protection
APPLICATIONS
•
•
•
•
Relay Drivers
–
–
Integrated Inductive Catch Diodes
Serial Interface
Unipolar Stepper Motor Drivers
Solenoid Drivers
•
1.5-A (Single Channel On) / 800-mA (Four
Channels On) Maximum Drive Current per
Channel (at 25°C)
General Low-Side Switch Applications
DESCRIPTION
The DRV8804 provides a 4-channel low side driver with overcurrent protection. It has built-in diodes to clamp
turn-off transients generated by inductive loads and can be used to drive unipolar stepper motors, DC motors,
relays, solenoids, or other loads.
The DRV8804 can supply up to 1.5-A (single channel on) or 800-mA (four channels on) continuous output
current (with adequate PCB heatsinking at 25°C).
A serial interface is provided including a serial data output, which can be daisy-chained to control multiple
devices with one serial interface.
Internal shutdown functions are provided for over current protection, short circuit protection, under voltage
lockout and overtemperature and faults are indicated by a fault output pin.
The DRV8804 is available in a 20-pin thermally-enhanced SOIC package and a 16-pin HTSSOP package
(Eco-friendly: RoHS & no Sb/Br).
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
TA
PACKAGE(2)
(SOIC) - DW
(HTSSOP) - PWP
Reel of 2000
Tube of 25
DRV8804DWR
DRV8804DW
Consult Factory
DRV8804
DRV8804
–40°C to 85°C
(1) For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DRV8804
SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
8.2V – 60V
Optional
Zener
8.2V – 60V
VM
Internal
Reference
Regs
Int. VCC
LS Gate
Drive
UVLO
VCLAMP
OUT1
nENBL
LATCH
SDATIN
OCP
&
Inductive
Load
Gate
Drive
OUT2
OCP
&
Inductive
Load
SDATOUT
SCLK
Gate
Drive
Control
Logic
OUT3
OUT4
OCP
&
RESET
Inductive
Load
Gate
Drive
nFAULT
OCP
&
Thermal
Shut down
Inductive
Load
Gate
Drive
GND
(multiple pins)
2
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NAME
SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
Table 1. TERMINAL FUNCTIONS
PIN
(SOIC)
PIN
(HTSSOP)
EXTERNAL COMPONENTS
OR CONNECTIONS
I/O(1)
DESCRIPTION
POWER AND GROUND
5, 6, 7,
14, 15, 16
5, 12,
PPAD
GND
-
-
Device ground
All pins must be connected to GND.
Connect to motor supply (8.2 V - 60 V).
VM
1
1
Device power supply
CONTROL
nENBL
10
11
8
9
I
I
Enable input
Reset input
Active low enables outputs – internal pulldown
Active-high reset input initializes internal
logic – internal pulldown
RESET
Rising edge latches shift register to output
stage – internal pulldown
LATCH
13
18
19
17
11
14
15
13
I
I
Latch input
SDATIN
SDATOUT
Serial data input
Serial data output
Serial clock
Serial data input – internal pulldown
Serial data output – has weak internal
pullup – see serial interface section for details
O
I
SCLK
Serial clock input – internal pulldown
STATUS
Logic low when in fault condition (overtemp,
overcurrent)
nFAULT
20
16
OD
Fault
OUTPUT
OUT1
3
4
8
9
3
4
6
7
O
O
O
O
Output 1
Output 2
Output 3
Output 4
Connect to load 1
Connect to load 2
Connect to load 3
Connect to load 4
OUT2
OUT3
OUT4
Connect to VM supply, or zener diode to VM
supply
VCLAMP
2
2
-
Output clamp voltage
(1) Directions: I = input, O = output, OD = open-drain output
DW (WIDE SOIC) PACKAGE
(TOP SIDE)
20
19
18
17
16
15
14
13
12
11
1
2
VM
VCLAMP
OUT1
OUT2
GND
nFAULT
SDATAO
SDATAIN
SCLK
GND
3
4
5
6
GND
GND
7
GND
GND
8
OUT3
OUT4
nENBL
LATCH
NC
9
10
RESET
PWP (HTSSOP) PACKAGE
(TOP SIDE)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VM
VCLAMP
OUT1
nFAULT
SDATAO
SDATAIN
SCLK
OUT2
GND
GND
GND
OUT3
LATCH
NC
OUT4
nENBL
RESET
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SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2)
VALUE
UNIT
VM
Power supply voltage range
Output voltage range
–0.3 to 65
–0.3 to 65
–0.3 to 65
V
V
V
VOUTx
VCLAMP
Clamp voltage range
SDATOUT,
nFAULT
Output current
20
mA
Peak clamp diode current
1.5
1
A
A
V
DC or RMS clamp diode current
Digital input pin voltage range
–0.5 to 7
SDATOUT,
nFAULT
Digital output pin voltage range
–0.5 to 7
V
A
Peak motor drive output current, t < 1 μS
Continuous total power dissipation
Operating virtual junction temperature range
Storage temperature range
Internally limited
See Dissipation Ratings table
TJ
–40 to 150
–60 to 150
°C
°C
Tstg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
DRV8804
THERMAL METRIC
DW
20 PINS
67.7
UNITS
θJA
Junction-to-ambient thermal resistance(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
Junction-to-top characterization parameter(4)
Junction-to-board characterization parameter(5)
Junction-to-case (bottom) thermal resistance(6)
θJCtop
θJB
32.9
35.4
°C/W
ψJT
8.2
ψJB
34.9
θJCbot
N/A
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
4
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SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX
60
UNIT
V
VM
VCLAMP Output clamp voltage range
Continuous output current, single channel on, TA = 25°C, SOIC package(1)
Power supply voltage range
8.2
8.2
60
V
1.5
0.8
1.5
0.8
Continuous output current, four channels on, TA = 25°C, SOIC package(1)
Continuous output current, single channel on, TA = 25°C, HTSSOP package(1)
Continuous output current, four channels on, TA = 25°C, HTSSOP package(1)
IOUT
A
(1) Power dissipation and thermal limits must be observed.
ELECTRICAL CHARACTERISTICS
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
POWER SUPPLIES
TEST CONDITIONS
MIN
TYP
MAX UNIT
IVM
VM operating supply current
VM = 24 V
VM rising
1.6
2.1
8.2
mA
V
VM undervoltage lockout
voltage
VUVLO
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL
Input low voltage
Input high voltage
Input hysteresis
0.6
0.7
V
V
VIH
VHYS
IIL
2
0.45
V
Input low current
Input high current
Pulldown resistance
VIN = 0
–20
20
μA
μA
kΩ
IIH
VIN = 3.3 V
100
RPD
100
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
IOH
Output low voltage
IO = 5 mA
VO = 3.3 V
0.5
1
V
Output high leakage current
μA
SDATAOUT OUTPUT (OPEN-DRAIN OUTPUT WITH INTERNAL PULLUP)
VOL
VOH
IOH
Output low voltage
IO = 5 mA
0.5
5.5
1
V
V
Output high voltage
IO = 100 µA, VM = 24 V
VO = 3.3 V
2.5
4.5
Output high leakage current
µA
LOW-SIDE FETS
VM = 24 V, IO = 700 mA, TJ = 25°C
VM = 24 V, IO = 700 mA, TJ = 85°C
0.5
RDS(ON) FET on resistance
Ω
0.75
0.8
50
IOFF
Off-state leakage current
–50
–50
μA
HIGH-SIDE DIODES
VF
Diode forward voltage
VM = 24 V, IO = 700 mA, TJ = 25°C
VM = 24 V, TJ = 25°C
1.2
V
IOFF
Off-state leakage current
50
μA
OUTPUTS
tR
tF
Rise time
Fall time
VM = 24 V, IO = 700 mA, Resistive load
VM = 24 V, IO = 700 mA, Resistive load
50
50
300
300
ns
ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level
2.3
3.8
A
Overcurrent protection deglitch
time
tOCP
tRETRY
tTSD
3.5
µs
Overcurrent protection retry
time
Thermal shutdown temperature Die temperature(1)
1.2
ms
150
160
180
°C
(1) Not production tested.
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SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
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TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted)(1)
NO.
1
PARAMETER
DESCRIPTION
MIN
62
25
25
5
MAX UNIT
tCYC
Clock cycle time
Clock high time
Clock low time
ns
ns
ns
ns
ns
2
tCLKH
tCLKL
3
4
tSU(SDATIN)
tH(SDATIN)
tD(SDATOUT)
tW(LATCH)
tOE(ENABLE)
tD(LATCH)
tRESET
Setup time, SDATIN to SCLK
Hold time, SDATIN to SCLK
Delay time, SCLK to SDATOUT
Pulse width, LATCH
5
1
6
15
ns
ns
ns
ns
µs
µs
µs
7
200
8
Enable time, nENBL to output low
Delay time, LATCH to output change
RESET pulse width
50
50
9
-
20
20
55
10
11
tD(RESET)
tSTARTUP
Reset delay before clock
Startup delay VM applied before clock
(1) Not production tested.
10
RESET
VM
nENBL
7
11
1
LATCH
SCLK
2
3
OUTx
Data in
valid
SDATIN
8
9
4
5
Data out valid
SDATOUT
6
Figure 1. DRV8804 Timing Requirements
6
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SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
FUNCTIONAL DESCRIPTION
Output Drivers
The DRV8804 contains four protected low-side drivers. Each output has an integrated clamp diode connected to
a common pin, VCLAMP.
VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a zener or TVS
diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be
beneficial when driving loads that require very fast current decay, such as unipolar stepper motors.
In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.
Serial Interface Operation
The DRV8804 is controlled with a simple serial interface. Logically, the interface is shown in Figure 2.
nENBL
LATCH
RESET
SCLK
SDATIN
D
Q
D
OUT1
Q
CLR
CLR
D
Q
D
OUT2
OUT3
OUT4
Q
CLR
CLR
D
Q
D
Q
CLR
CLR
D
Q
D
Q
CLR
CLR
D
Q
CLR
SDATOUT
Figure 2. Serial Interface Operation
Data is shifted into a temporary holding shift register in the part using the SDATIN pin, one bit at each rising
edge of the SCLK pin. Data is simultaneously shifted out of the SDATOUT pin, allowing multiple devices to be
daisy-chained onto one serial port. Note that the SDTAOUT pin has a weak pullup to an internal power supply,
which can support driving another DRV8804 SDATAIN pin at clock frequencies of up to 1 MHz without an
external pullup. To operate at faster than 1-MHz clock frequency, or to interface to devices operating at other
supply voltages, a pullup resistor of approximately 1 kΩ to the chosen logic supply voltage should be used.
A rising edge on the LATCH pin latches the data from the temporary shift register into the output stage.
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nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does
not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic, including the OCP fault. All serial interface
registers are cleared. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so
it is not required to drive RESET at power-up.
Protection Circuits
The DRV8804 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and re-applied.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
8
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SLVSAW4B –JULY 2011–REVISED NOVEMBER 2011
THERMAL INFORMATION
Thermal Protection
The DRV8804 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8804 is dominated by the power dissipated in the output FET resistance, or
RDS(ON). Average power dissipation of each FET when running a static load can be roughly estimated by
Equation 1:
P = RDS(ON) · (IOUT)2
(1)
where P is the power dissipation of one FET, RDS(ON) is the resistance of each FET, and IOUT is equal to the
average current drawn by the load. Note that at start-up and fault conditions this current is much higher than
normal running current; these peak currents and their duration also need to be taken into consideration. When
driving more than one load simultaneously, the power in all active output stages must be summed.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
Heatsinking
The DRV8804 package uses a standard SOIC outline, but has the center pins internally fused to the die pad in
order to more efficiently remove heat from the device. The two center leads on each side of the package should
be connected together to as large a copper area on the PCB as is possible to remove heat from the device. If the
copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
In general, the more copper area that can be provided, the more power can be dissipated.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DRV8804DW
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
20
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
DRV8804DWR
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8804DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
DRV8804DWR
2000
Pack Materials-Page 2
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DRV8804PWPR CAD模型
引脚图
封装焊盘图
DRV8804PWPR 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| DRV8804PWP | TI | QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC | 功能相似 |
|
DRV8804PWPR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| DRV8805 | TI | UNIPOLAR STEPPER MOTOR DRIVER IC | 获取价格 |
|
| DRV8805DW | TI | UNIPOLAR STEPPER MOTOR DRIVER IC | 获取价格 |
|
| DRV8805DWR | TI | UNIPOLAR STEPPER MOTOR DRIVER IC | 获取价格 |
|
| DRV8805PWP | TI | UNIPOLAR STEPPER MOTOR DRIVER IC | 获取价格 |
|
| DRV8805PWPR | TI | UNIPOLAR STEPPER MOTOR DRIVER IC | 获取价格 |
|
| DRV8805_12 | TI | UNIPOLAR STEPPER MOTOR DRIVER IC | 获取价格 |
|
| DRV8806 | TI | DRV8803/04/05/06 Evaluation Module | 获取价格 |
|
| DRV8806PWP | TI | QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC | 获取价格 |
|
| DRV8806PWPR | TI | QUAD SERIAL INTERFACE LOW-SIDE DRIVER IC | 获取价格 |
|
| DRV8806_16 | TI | Quad Serial Interface Low-Side Driver IC | 获取价格 |
|
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