LM5107SD/NOPB
更新时间：2024-12-04 05:34:59
品牌：TI
描述：具有 8V UVLO 的 1.4A、100V 半桥栅极驱动器 | NGT | 8 | -40 to 125
概述
规格参数
数据手册
替代型号LM5107SD/NOPB 概述
具有 8V UVLO 的 1.4A、100V 半桥栅极驱动器 | NGT | 8 | -40 to 125 FET驱动器 MOSFET 驱动器
LM5107SD/NOPB 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | SON |
| 包装说明： | HVSON, SOLCC8,.15,32 | 针数： | 8 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 1.45 | 高边驱动器： | YES |
| 接口集成电路类型： | HALF BRIDGE BASED MOSFET DRIVER | JESD-30 代码： | S-PDSO-N8 |
| JESD-609代码： | e3 | 长度： | 4 mm |
| 湿度敏感等级： | 1 | 功能数量： | 1 |
| 端子数量： | 8 | 最高工作温度： | 125 °C |
| 最低工作温度： | -40 °C | 最大输出电流： | 1.4 A |
| 标称输出峰值电流： | 1.4 A | 输出极性： | TRUE |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | HVSON |
| 封装等效代码： | SOLCC8,.15,32 | 封装形状： | SQUARE |
| 封装形式： | SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 12 V | 认证状态： | Not Qualified |
| 座面最大高度： | 0.8 mm | 子类别： | MOSFET Drivers |
| 最大压摆率： | 3.4 mA | 最大供电电压： | 14 V |
| 最小供电电压： | 8 V | 标称供电电压： | 12 V |
| 表面贴装： | YES | 温度等级： | AUTOMOTIVE |
| 端子面层： | Matte Tin (Sn) | 端子形式： | NO LEAD |
| 端子节距： | 0.8 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 断开时间： | 0.056 µs |
| 接通时间： | 0.056 µs | 宽度： | 4 mm |
| Base Number Matches： | 1 |
LM5107SD/NOPB 数据手册
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
LM5107 100V / 1.4A Peak Half Bridge Gate Driver
Check for Samples: LM5107
1
FEATURES
DESCRIPTION
The LM5107 is a low cost high voltage gate driver,
designed to drive both the high side and the low side
N-Channel MOSFETs in a synchronous buck or a
half bridge configuration. The floating high-side driver
is capable of working with rail voltages up to 100V.
The outputs are independently controlled with TTL
compatible input thresholds. An integrated on chip
high voltage diode is provided to charge the high side
gate drive bootstrap capacitor. A robust level shifter
technology operates at high speed while consuming
low power and providing clean level transitions from
the control input logic to the high side gate driver.
Under-voltage lockout is provided on both the low
side and the high side power rails. The device is
available in the SOIC and the thermally enhanced
WSON packages.
•
Drives Both a High Side and Low Side N-
Channel MOSFET
•
High Peak Output Current (1.4A Sink / 1.3A
Source)
•
•
•
•
•
Independent TTL compatible inputs
Integrated Bootstrap Diode
Bootstrap Supply Voltage to 118V DC
Fast Propagation Times (27 ns Typical)
Drives 1000 pF Load with 15ns Rise and Fall
Times
•
Excellent Propagation Delay Matching (2 ns
Typical)
•
•
•
Supply Rail Under-Voltage Lockout
Low Power Consumption
Package
Pin Compatible with ISL6700
•
•
SOIC
WSON (4 mm x 4 mm)
TYPICAL APPLICATIONS
•
•
•
•
Current Fed Push-Pull Converters
Half and Full Bridge Power Converters
Solid State Motor Drives
Two Switch Forward Power Converters
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM5107
SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
www.ti.com
Simplified Block Diagram
HV
HB
HO
HS
DRIVER
LEVEL
SHIFT
UVLO
HI
V
DD
UVLO
LO
DRIVER
LI
V
SS
Connection Diagrams
VDD
HI
VDD
HI
1
2
3
4
8
7
6
5
HB
HO
HS
LO
1
2
3
4
8
7
6
5
HB
HO
HS
LO
LI
LI
VSS
VSS
Figure 1. 8-Lead SOIC
See D Package
Figure 2. 8-Lead WSON
See NGT0008A Package
PIN DESCRIPTIONS(1)
Pin #
WSON
Name
VDD
Description
Application Information
SOIC
Locally decouple to VSS using low ESR/ESL capacitor located as
close to IC as possible.
1
1
2
3
Positive gate drive supply
High side control input
Low side control input
The LM5107 HI input is compatible with TTL input thresholds.
Unused HI input should be tied to ground and not left open
2
3
HI
LI
The LM5107 LI input is compatible with TTL input thresholds. Unused
LI input should be tied to ground and not left open.
4
5
4
5
VSS
LO
Ground reference
All signals are referenced to this ground.
Low side gate driver output
Connect to the gate of the low side N-MOS device.
Connect to the negative terminal of the bootstrap capacitor and to the
source of the high side N-MOS device.
6
7
6
7
HS
HO
High side source connection
High side gate driver output
Connect to the gate of the low side N-MOS device.
Connect the positive terminal of the bootstrap capacitor to HB and
the negative terminal of the bootstrap capacitor to HS. The bootstrap
capacitor should be placed as close to IC as possible.
High side gate driver positive
supply rail
8
8
HB
(1) For WSON package it is recommended that the exposed pad on the bottom of the LM5107 be soldered to ground plane on the PCB
board and the ground plane should extend out from underneath the package to improve heat dissipation.
2
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VDD to VSS
-0.3V to 18V
−0.3V to 18V
HB to HS
LI or HI to VSS
LO to VSS
−0.3V to VDD +0.3V
−0.3V to VDD +0.3V
HS −0.3V to VHB +0.3V
−5V to 100V
HO to VSS
V
(3)
HS to VSS
HB to VSS
118V
Junction Temperature
Storage Temperature Range
ESD Rating HBM(4)
-40°C to +150°C
−55°C to +150°C
2 kV
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is specified. Operating Ratings do not imply performance limits. For performance limits and associated test
conditions, see the Electrical Characteristics .
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
(4) The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. Pin 6 , Pin 7 and Pin 8 are rated at
500V.
Recommended Operating Conditions
VDD
HS(1)
8V to 14V
−1V to 100V
HB
VHS +8V to VHS +14V
< 50 V/ns
HS Slew Rate
Junction Temperature
−40°C to +125°C
(1) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally
not exceed -1V. However in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur on HS, the HS voltage must never be more negative than VDD - 15V. For example, if VDD
= 10V, the negative transients at HS must not exceed -5V.
Copyright © 2004–2013, Texas Instruments Incorporated
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
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Electrical Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
VDD Operating Current
LI = HI = 0V
0.3
2.1
0.6
3.4
0.2
3.0
10
mA
mA
mA
mA
µA
IDDO
IHB
f = 500 kHz
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
LI = HI = 0V
f = 500 kHz
0.06
1.6
IHBO
IHBS
IHBSO
VHS = VHB = 100V
f = 500 kHz
0.1
0.5
mA
INPUT PINS LI and HI
VIL
VIH
RI
Low Level Input Voltage Threshold
0.8
100
6.0
5.7
1.8
1.8
180
V
V
High Level Input Voltage Threshold
Input Pulldown Resistance
2.2
500
kΩ
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
VDDR = VDD - VSS
6.9
0.5
6.6
0.4
7.4
7.1
V
V
V
V
VHBR = VHB - VHS
HB Threshold Hysteresis
BOOT STRAP DIODE
VDL
IVDD-HB = 100 µA
VDL = VDD - VHB
Low-Current Forward Voltage
0.58
0.9
V
VDH
RD
IVDD-HB = 100 mA
VDH = VDD - VHB
High-Current Forward Voltage
Dynamic Resistance
0.82
0.8
1.1
1.5
V
IVDD-HB = 100 mA
Ω
LO GATE DRIVER
VOLL
ILO = 100 mA
VOHL = VLO – VSS
Low-Level Output Voltage
0.28
0.45
0.45
0.75
V
V
VOHL
ILO = −100 mA,
VOHL = VDD– VLO
High-Level Output Voltage
IOHL
IOLL
Peak Pullup Current
VLO = 0V
1.3
1.4
A
A
Peak Pulldown Current
VLO = 12V
HO GATE DRIVER
VOLH
IHO = 100 mA
VOLH = VHO– VHS
Low-Level Output Voltage
0.28
0.45
0.45
0.75
V
V
VOHH
IHO = −100 mA
VOHH = VHB– VHO
High-Level Output Voltage
IOHH
IOLH
Peak Pullup Current
VHO = 0V
1.3
1.4
A
A
Peak Pulldown Current
VHO = 12V
THERMAL RESISTANCE
(2)
θJA
SOIC
WSON(3)
160
40
Junction to Ambient
°C/W
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) The θJA is not a constant for the package and depends on the printed circuit board design and the operating conditions.
(3) 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm
ground and power planes embedded in PCB. See Application Note AN-1187.
4
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
Switching Characteristics
Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction
temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO.
Symbol
LM5100A
tLPHL
Parameter
Conditions
Min(1)
Typ
Max(1)
Units
Lower Turn-Off Propagation Delay
(LI Falling to LO Falling)
27
27
29
29
2
56
56
56
56
15
ns
ns
ns
ns
ns
tHPHL
tLPLH
tHPLH
tMON
tMOFF
Upper Turn-Off Propagation Delay
(HI Falling to HO Falling)
Lower Turn-On Propagation Delay
(LI Rising to LO Rising)
Upper Turn-On Propagation Delay
(HI Rising to HO Rising)
Delay Matching: Lower Turn-On and Upper
Turn-Off
Delay Matching: Lower Turn-Off and Upper
Turn-On
2
15
ns
ns
ns
ns
tRC, tFC
tPW
Either Output Rise/Fall Time
CL = 1000 pF
15
-
Minimum Input Pulse Width that Changes
the Output
50
tBS
Bootstrap Diode Turn-Off Time
IF = 100 mA, IR = 100 mA
105
(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Copyright © 2004–2013, Texas Instruments Incorporated
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Typical Performance Characteristics
VDD Operating Current vs Frequency
HB Operating Current vs Frequency
100
10
1
100
V
= V = 12V
HB
V
= V = 12V
HB
DD
DD
C
L
= 1000 pF
V
= V = 0V
HS
SS
V
= V = 0V
HS
SS
C
= 1000 pF
L
10
C
= 2200 pF
L
C
L
= 2200 pF
C
= 4400 pF
L
C
L
= 4400 pF
1
C
L
= 0 pF
0.1
0.01
C
= 0 pF
L
C
L
= 470 pF
C
L
= 470 pF
0.1
1
10
100
1000
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 3.
Figure 4.
Operating Current vs Temperature
Quiescent Current vs Temperature
0.45
2.4
2.2
2.0
1.8
1.6
1.4
1.2
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
I
DDO
I
DDO
C
= 0 pF
L
f = 500 kHz
LI = HI = 0V
V
= V = 12V
HB
DD
SS
V
V
= V = 12V
HB
DD
SS
V
= V = 0V
HS
= V = 0V
HS
I
HBO
50
I
HBO
50
20 35
65
80 95 110 125
-40 -25 -10 5
20 35
65
80 95 110 125
-40 -25 -10 5
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 5.
Figure 6.
Quiescent Current vs Voltage
Propagation Delay vs Temperature
600
500
44
40
36
32
28
24
20
C
= 0 pF
L
t
LI = HI = 0V
LPHL
t
HPHL
V
V
= V = 12V
HB
DD
SS
V
V
= V
HB
DD
= V
HS
= 0V
= V = 0V
SS HS
I
DD
400
300
200
turn off
t
HPLH
t
LPLH
I
HB
turn on
100
0
8
10
12
14
, V (V)
16
18
50
20 35
65
-40 -25 -10 5
80 95 110 125
TEMPERATURE (oC)
V
DD HB
Figure 7.
Figure 8.
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
Typical Performance Characteristics (continued)
LO and HO High Level Output Voltage vs Temperature
LO and HO Low Level Output Voltage vs Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.5
Output Current : -100 mA
Output Current : -100 mA
= V = 0V
V
= V = 0V
HS
SS
V
SS
HS
0.4
0.3
0.2
0.1
V
= V = 8V
HB
DD
V
= V = 8V
HB
DD
V
DD
= V = 12V
HB
V
= V = 12V
HB
DD
V
= V =16V
V
= V =16V
HB
DD
HB
DD
50
-40 -25 -10
5
20 35
65
80 95 110 125
50
20 35
65 80 95 110 125
-40 -25 -10
5
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 9.
Figure 10.
HO and LO Peak Output Current vs Output Voltage
Doide Forward Voltage
1.6
1.00E-01
1.00E-02
1.00E-03
1.00E-04
1.00E-05
1.00E-06
V
V
= V = 12V
HB
DD
SS
1.4
1.2
1
150°C
25°C
= V = 0V
HS
0.8
0.6
0.4
0.2
0
Pull-up Current
-40°C
Pull-down Current
0
2
4
8
10
12
6
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
, V (V)
LO HO
FORWARD VOLTAGE
Figure 11.
Figure 12.
Undervoltage Rising Thresholds vs Temperature
Undervoltage Hysteresis vs Temperature
0.50
7.0
V
V
= V - V
DD
DDR
SS
0.48
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.32
0.30
6.9
6.8
6.7
6.6
6.5
6.4
6.3
= V - V
HB
HBR
HS
V
DDH
V
DDR
V
HBR
V
HBH
50
-40 -25 -10
5
20 35
65
80 95 110 125
50
20 35
65
80 95 110 125
-40 -25 -10 5
TEMPERATURE (oC)
TEMPERATURE (oC)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Input Thresholds vs Temperature
Input Thresholds vs Supply Voltage
1.92
1.91
1.90
1.89
1.88
1.87
1.86
1.85
1.84
1.83
1.82
1.81
1.80
2.00
1.95
1.90
1.85
1.80
1.75
1.70
V
= 12V
= 0V
DD
Rising
V
SS
Rising
Falling
Falling
12
(V)
8
9
10
11
13
14 15 16
50
-40 -25 -10
5
20 35
65
80 95 110 125
V
DD
TEMPERATURE (oC)
Figure 15.
Figure 16.
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
Timing Diagram
LI
LI
HI
HI
t
HPLH
t
LPLH
t
HPHL
t
LPHL
LO
LO
HO
HO
t
t
MOFF
MON
Figure 17.
Layout Considerations
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR / ESL capacitor must be connected close to the IC, and between VDD and VSS pins and between
HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
–
The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
–
The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
HS Transient Voltages Below Ground
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate
parasitic transistors resulting in excessive current to flow from the HB supply possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less . Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. A low ESR bypass capacitor between HB to HS as well as VDD to VSS is essential for proper operation. The
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capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any series inductances with the bypass capacitor will cause voltage ringing at the
leads of the IC which must be avoided for reliable operation.
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SNVS333D –NOVEMBER 2004–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
LM5107MA/NOPB
LM5107MAX/NOPB
LM5107SD/NOPB
LM5107SDX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
95
Green (RoHS
& no Sb/Br)
CU SN
CU SN
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L5107
MA
ACTIVE
ACTIVE
ACTIVE
D
2500
1000
4500
Green (RoHS
& no Sb/Br)
L5107
MA
WSON
WSON
NGT
NGT
Green (RoHS
& no Sb/Br)
L5107SD
Green (RoHS
& no Sb/Br)
SN
L5107SD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5107MAX/NOPB
LM5107SD/NOPB
LM5107SDX/NOPB
SOIC
WSON
WSON
D
8
8
8
2500
1000
4500
330.0
178.0
330.0
12.4
12.4
12.4
6.5
4.3
4.3
5.4
4.3
4.3
2.0
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
NGT
NGT
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5107MAX/NOPB
LM5107SD/NOPB
LM5107SDX/NOPB
SOIC
WSON
WSON
D
8
8
8
2500
1000
4500
367.0
210.0
367.0
367.0
185.0
367.0
35.0
35.0
35.0
NGT
NGT
Pack Materials-Page 2
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
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LM5107SD/NOPB CAD模型
引脚图
封装焊盘图
LM5107SD/NOPB 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| LM5107SD | TI | LM5107 100V / 1.4A Peak Half Bridge Gate Driver | 类似代替 |
|
LM5107SD/NOPB 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LM5107SDX | TI | LM5107 100V / 1.4A Peak Half Bridge Gate Driver | 获取价格 |
|
| LM5108 | TI | 具有使能和互锁功能的 2.6A、110V 半桥栅极驱动器 | 获取价格 |
|
| LM5108DRCR | TI | 具有使能和互锁功能的 2.6A、110V 半桥栅极驱动器 | DRC | 10 | -40 to 125 | 获取价格 |
|
| LM5108DRCT | TI | 具有使能和互锁功能的 2.6A、110V 半桥栅极驱动器 | DRC | 10 | -40 to 125 | 获取价格 |
|
| LM5109 | NSC | 100V / 1A Peak Half Bridge Gate Driver | 获取价格 |
|
| LM5109 | TI | 100V/1A Peak Half Bridge Gate Driver | 获取价格 |
|
| LM5109A | NSC | L5109又名:LM5109，封装上丝印是L5109 | 获取价格 |
|
| LM5109A | TI | LM5109A High Voltage 1A Peak Half Bridge Gate Driver | 获取价格 |
|
| LM5109AMA | NSC | High Voltage 1A Peak Half Bridge Gate Driver | 获取价格 |
|
| LM5109AMA | TI | LM5109A High Voltage 1A Peak Half Bridge Gate Driver | 获取价格 |
|
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