LM5134BMF/NOPB
更新时间：2024-12-04 05:36:02
品牌：TI
描述：具有 4V UVLO 和互补分离输出的 7.6A/4.5A 单通道栅极驱动器 | DBV | 6 | -40 to 125
概述
规格参数
数据手册
替代型号LM5134BMF/NOPB 概述
具有 4V UVLO 和互补分离输出的 7.6A/4.5A 单通道栅极驱动器 | DBV | 6 | -40 to 125 FET驱动器 MOSFET 驱动器
LM5134BMF/NOPB 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 包装说明： | LSSOP, TSOP6,.11,37 |
| Reach Compliance Code： | compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 1.62 |
| 接口集成电路类型： | BUFFER OR INVERTER BASED MOSFET DRIVER | JESD-30 代码： | R-PDSO-G6 |
| JESD-609代码： | e3 | 长度： | 2.9 mm |
| 湿度敏感等级： | 1 | 端子数量： | 6 |
| 最大输出电流： | 7.6 A | 标称输出峰值电流： | 7.6 A |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | LSSOP |
| 封装等效代码： | TSOP6,.11,37 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE, LOW PROFILE, SHRINK PITCH | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 12 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.45 mm | 子类别： | MOSFET Drivers |
| 标称供电电压： | 12 V | 表面贴装： | YES |
| 温度等级： | AUTOMOTIVE | 端子面层： | Matte Tin (Sn) |
| 端子形式： | GULL WING | 端子节距： | 0.95 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 1.6 mm | Base Number Matches： | 1 |
LM5134BMF/NOPB 数据手册
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PDF下载LM5134
Single 7.6A Peak Current Low-Side Gate Driver with a PILOT Output
General Description
Features
The LM5134 is a high-speed single low-side driver capable of
sinking and sourcing 7.6A/4.5A peak currents. The LM5134
has inverting and non-inverting inputs that give the user
greater flexibility in controlling the FET. The LM5134 features
one main output, OUT, and an extra gate drive output, PILOT.
The PILOT pin logic is complementary to the OUT pin, and
can be used to drive a small MOSFET located close to the
main power FET. This configuration minimizes the turn-off
loop and reduces the consequent parasitic inductance. It is
particularly useful for driving high-speed FETs or multiple
FETs in parallel. The LM5134 is available in the SOT23 6-pin
package and the LLP-6 package with an exposed pad to aid
thermal dissipation.
7.6A/4.5A peak sink/source drive current for main output
●
●
●
●
820mA/660mA peak sink/source current for PILOT output
+4V to +12.6V single power supply
Matching delay time between inverting and non–inverting
inputs
TTL/CMOS logic inputs
●
●
●
Up to +14V logic inputs (regardless of VDD voltage)
-40°C to 125°C junction temperature range
Package
SOT23-6
●
●
LLP-6 (3mm x 3mm)
Typical Applications
Motor Drive
●
●
●
Solid-State Power Controller
Power Factor Correction Converter
Block Diagram
30192803
FIGURE 1. Block Diagram
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
301928 SNVS808A
Copyright © 1999-2012, Texas Instruments Incorporated
LM5134
Input/Output Options
Base Part Number
Logic Input
CMOS
LM5134A
LM5134B
TTL
Truth Table
IN
L
INB
L
OUT
PILOT
L
L
H
H
L
L
H
H
H
L
H
L
H
H
Connection Diagram
30192802
Ordering Information
Order Number
LM5134AMF
LM5134AMFX
LM5134BMF
LM5134BMFX
LM5134ASD
LM5134ASDX
LM5134BSD
LM5134BSDX
Package Type
Package Drawing
MF06A
Supplied As
SOT23-6
SOT23-6
SOT23-6
SOT23-6
LLP-6
1000 Units / Tape & Reel
3000 Units / Tape & Reel
1000 Units / Tape & Reel
3000 Units / Tape & Reel
1000 Units / Tape & Reel
4500 Units / Tape & Reel
1000 Units / Tape & Reel
4500 Units / Tape & Reel
MF06A
MF06A
MF06A
SDE06A
SDE06A
SDE06A
SDE06A
LLP-6
LLP-6
LLP-6
2
Copyright © 1999-2012, Texas Instruments Incorporated
LM5134
Pin Descriptions
Pin No.
Name Description
Applications Information
Locally decouple to VSS using low ESR/ESL capacitor located as close as possible
to the IC.
1
VDD
Gate drive supply
Gate drive output for
PILOT an external turn-off
FET
Connect to the gate of a small turn-off MOSFET with a short, low inductance path.
The turn-off FET provides a local turn-off path.
2
3
Gate drive output for Connect to the gate of the power FET with a short, low inductance path. A gate
OUT
the power FET
Ground
resistor can be used to eliminate potential gate oscillations.
All signals are referenced to this ground.
4
5
VSS
INB
Inverting logic input Connect to VSS when not used.
Non-inverting logic
Connect to VDD when not used.
input
6
IN
It is recommended that the exposed pad on the bottom of the package be soldered
EP
EP
Exposed Pad
to ground plane on the PC board, and that ground plane extend out from beneath
the IC to help dissipate heat.
Copyright © 1999-2012, Texas Instruments Incorporated
3
LM5134
Absolute Maximum Ratings (Note 1)
VDD to VSS
IN, INB to VSS
Storage Temperature Range
Junction Temperature
ESD Rating HBM
−0.3V to 14V
−0.3V to 14V
−55°C to +150°C
+150°C
2kV
Recommended Operating Conditions
VDD
+4.0V to 12.6V
Operating Junction
Temperature
−40°C to +125°C
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = +12V
(Note 2).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
VDD
VDD Operating Voltage
4.0
12.6
4.00
V
V
V
UVLO
VDD Undervoltage Lockout
VDD Rising
3.25
3.6
VDD Undervoltage Lockout Hysteresis
0.36
VDD Undervoltage lockout to Main
output delay time
VDD Rising
500
0.8
ns
IDD
VDD Quiescent Current
IN = INB = VDD
2
mA
OUTPUT
VDD = 10V, IOUT = -100mA
VDD = 4.5V, IOUT = -100mA
VDD = 10V, IOUT = -100mA
VDD = 4.5V, IOUT = -100mA
VDD = 0V, IOUT = -10mA
VDD = 0V, IOUT = -10mA
CL = 10,000pF
0.15
0.2
0.2
0.25
1.5
0.7
7.6
0.7
1
0.45
0.5
RON-DW
Ω
Ω
Ω
Ω
Ω
V
Main output Resistance – Pulling Down
Main output Resistance – Pulling Down
(SOT23-6)
0.5
RON-DW (LLP)
0.55
10
Power-off Pull Down Resistance
Power-off Pull Down Clamp Voltage
Peak Sink Current
1.0
A
VDD = 10V, IOUT = 50mA
VDD = 4.5V, IOUT = 50mA
VDD = 10V, IOUT = 50mA
VDD = 4.5V, IOUT = 50mA
CL = 10,000pF
1.3
1.9
RON-UP
Ω
Ω
Ω
Ω
A
Main output Resistance - Pulling Up
(SOT23-6)
0.75
1.14
4.5
1.2
RON-UP (LLP)
Main output Resistance - Pulling Up
Peak Source Current
1.85
PILOT
VDD = 10V,IOUT = -100mA
VDD = 4.5V, IOUT = -100mA
CL = 330pF
3.7
4.7
820
6
9
Ω
Ω
PILOT Output Resistance – Pulling
Down
RONP-DW
12
Peak Sink Current
mA
VDD = 10V, IOUT = 50mA
VDD = 4.5V, IOUT = 50mA
CL = 330pF
11
20
Ω
Ω
RONP-UP
PILOT output Resistance – Pulling Up
Peak Source Current
10.7
660
mA
LOGIC INPUT
0.67x
VDD
LM5134A
LM5134B
LM5134A
LM5134B
V
V
V
V
VIH
Logic 1 Input Voltage
Logic 0 Input Voltage
2.4
0.33x
VDD
VIL
0.8
4
Copyright © 1999-2012, Texas Instruments Incorporated
LM5134
Symbol
Parameter
Conditions
LM5134A
Min
Typ
0.9
Max
10
Units
V
VHYS
Logic-Input Hysteresis
LM5134B
0.68
0.001
Logic-Input Current
INB = VDD or 0
µA
THERMAL RESISTANCE
SOT23-6
LLP-6
90
60
°C/W
°C/W
θJA
Junction to Ambient
SWITCHING CHARACTERISTICS FOR VDD = +10V
CL = 1000pF
CL = 5000pF
CL = 10,000pF
CL = 1000pF
CL = 5000pF
CL = 10,000pF
CL = 1000pF
CL = 1000pF
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tR
OUT Rise Time
OUT Fall Time
10
20
2
tF
4.7
7.2
17
12
2.5
5.3
3.9
tD-ON
OUT Turn-On Propagation Delay
OUT Turn-Off Propagation Delay
Main Output Break-Before-Make Time
PILOT Rise Time
40
25
tD-OFF
tPR
tPF
CL = 330pF
CL = 330pF
PILOT Fall Time
OUT Turn-Off to PILOT Turn-On
Propagation Delay
tPD-ON
CL = 330pF
CL = 330pF
4.2
6.4
ns
ns
PILOT Turn-Off to OUT Turn-On
Propagation Delay
tPD-OFF
SWITCHING CHARACTERISTICS FOR VDD = +4.5V
CL = 1000pF
CL = 5000pF
CL = 10,000pF
CL = 1000pF
CL = 5000pF
CL = 10,000pF
CL = 1000pF
CL = 1000pF
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tR
Rise Time
Fall Time
14
24
2.3
5.4
7.2
26
tF
tD-ON
OUT Turn-On Propagation Delay
OUT Turn-Off Propagation Delay
Main output Break-Before-Make Time
PILOT Rise Time
50
45
tD-OFF
20
4.2
9.6
3.7
tPR
tPf
CL = 330pF
CL = 330pF
PILOT Fall Time
OUT Turn-Off to PILOT Turn-On
Propagation Delay
tPD-ON
CL = 330pF
CL = 330pF
7.5
ns
ns
PILOT Turn-Off to OUT Turn-On
Propagation Delay
tPD-OFF
11.8
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.
Note 2: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
Copyright © 1999-2012, Texas Instruments Incorporated
5
LM5134
Timing Diagram
30192805
30192806
6
Copyright © 1999-2012, Texas Instruments Incorporated
LM5134
Typical Performance Characteristics
OUT Source Current vs. OUT Voltage
OUT Sink Current vs. OUT Voltage
30192807
30192808
OUT Peak Source Current vs. VDD Voltage
OUT Peak Sink Current vs. VDD Voltage
30192809
30192810
PILOT Source Current vs. PILOT Voltage
PILOT Sink Current vs. PILOT Voltage
30192811
30192812
Copyright © 1999-2012, Texas Instruments Incorporated
7
LM5134
PILOT Peak Source Current vs. VDD Voltage
PILOT Peak Sink Current vs. VDD Voltage
30192813
30192814
OUT Turn-On Propagation Delay vs. VDD
OUT Turn-Off Propagation Delay vs. VDD
30192815
30192816
OUT Turn-Off to PILOT Turn-On
Propagation Delay vs. VDD
PILOT Turn-Off to OUT Turn-On
Propagation Delay vs. VDD
30192817
30192818
8
Copyright © 1999-2012, Texas Instruments Incorporated
LM5134
Supply Current vs. OUT Capacitive Load
Supply Current vs. PILOT Capacitive Load
30192826
30192827
Supply Current vs. Frequency
Quiescent Current vs. Temperature
30192828
30192829
LM5134A Input Threshold vs. Temperature
LM5134A Input Threshold vs. Temperature
30192830
30192831
Copyright © 1999-2012, Texas Instruments Incorporated
9
LM5134
LM5134B Input Threshold vs. Temperature
LM5134B Input Threshold vs. Temperature
30192832
30192834
UVLO Threshold vs. Temperature
30192835
10
Copyright © 1999-2012, Texas Instruments Incorporated
LM5134
Detailed Operating Description
The LM5134 is a single low-side gate driver with one main output, OUT, and a complementary output PILOT. The OUT pin has
high 7.6A/4.5A peak sink/source current and can be used to drive large power MOSFETs or multiple MOSFETs in parallel. The
PILOT pin has 820mA/660mA peak sink/source current, and is intended to drive an external turn-off MOSFET, as shown in Figure
1. The external turn-off FET can be placed close to the power MOSFETs to minimize the loop inductance, and therefore helps
eliminate stray inductance induced oscillations or undesired turn-on. This feature also provides the flexibility to adjust turn-on and
turn-off speed independently.
When using the external turn-off switch, it is important to prevent the potential shoot-through between the external turn-off switch
and the LM5134 internal pull-up switch. The propagation delay, TPD-ON and TPD-OFF, has been implemented in the LM5134 between
the PILOT and the OUT pins, as depicted in the timing diagram. The turn-on delay TPD-ON is designed to be shorter than the turn-
off delay TPD-OFF because the rising time of the external turn-off switch can attribute to the additional delay time. It is also desirable
to minimize TPD-ON to favor the fast turn-off of the power MOSFET.
The LM5134 offers both inverting and non-inverting inputs to satisfy requirements for inverting and non-inverting gate drive signals
in a single device type. Inputs of the LM5134 are TTL and CMOS Logic compatible and can withstand input voltages up to 14V
regardless of the VDD voltage. This allows inputs of the LM5134 to be connected directly to most PWM controllers.
The LM5134 includes an Under-voltage Lockout (UVLO) circuit. When the VDD voltage is below the UVLO threshold voltage, the
IN and INB inputs are ignored, and if there is sufficient VDD voltage, the OUT is pulled low. In addition, the LM5134 has an internal
PNP transistor in parallel with the output NMOS. Under the UVLO condition, the PNP transistor will be on and clamp the OUT
voltage below 1V. This feature ensures the OUT remains low even with insufficient VDD voltage.
Application Information
PILOT MOSFET Selection
In general, a small sized 20V MOSFET with logic level gates can be used as the external turn-off switch. To achieve a fast switching
speed and avoid the potential shoot-through, it is suggested to select a MOSFET with the total gate charge less than 3nC. It is
good practice to verify that no shoot-through occurs for the entire operating temperature range. In addition, a small Rds(on) is
preferred to obtain the strong sink current capability. The power losses of the PILOT MOSFET can be estimated as:
where Qgo is the total input gate charge of the power MOSFET.
Power Dissipation
It is important to keep the power consumption of the driver below the maximum power dissipation limit of the package at the operating
temperature. The total power dissipation of the LM5134 is the sum of the gate charge losses and the losses in the driver due to
the internal CMOS stages used to buffer the output as well as the power losses associated with the quiescent current.
The gate charge losses include the power MOSFET gate charge losses as well as the PILOT FET gate charge losses and can be
calculated as follows:
Or
where Fsw is switching frequency, Qgo is the total input gate charge of the power MOSFET, Qgp is the total input gate charge of the
PILOT MOSFET. Co and Cp are the load capacitance at OUT and PILOT outputs respectively. It should be noted that due to the
use of an external turn-off switch, part of the gate charge losses are dissipated in the external turn-off switch. Therefore, the actual
gate charge losses dissipated in the LM5134 is less than predicted by the above expressions. However, they are a good conser-
vative design estimate.
The power dissipation associated with the internal circuit operation of the driver can be estimated with the characterization curves
of the LM5134. For a given ambient temperature, the maximum allowable power losses of the IC can be defined as:
Copyright © 1999-2012, Texas Instruments Incorporated
11
LM5134
where P is the total power dissipation of the driver.
Layout Considerations
Attention must be given to board layout when using LM5134. Some important considerations include:
1. The first priority in designing the layout of the driver is to confine the high peak currents that charge and discharge the FETs
gate into a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate.
2. To reduce the loop inductance, the driver should be placed as close as possible to the FETs. The gate trace to and from the
FETs are recommended to be placed closely side by side, or directly on top of one another.
3. A low ESR/ESL ceramic capacitor must be connected close to the IC, between VDD and VSS pins to support the high peak
current being drawn from VDD during turn-on of the FETs. It is most desirable to place the VDD decoupling capacitor on the
same side of the PC board as the driver. The inductance of via holes can impose excessive ringing on the IC pins.
4. The parasitic source inductance, along with the gate capacitor and the driver pull-down path, can form a LCR resonant tank,
resulting in gate voltage oscillations. An optional resistor or ferrite bead can be used to damp the ringing.
12
Copyright © 1999-2012, Texas Instruments Incorporated
LM5134
Physical Dimensions inches (millimeters) unless otherwise noted
SOT23-6 Outline Drawing
NS Package Number MF06A
LLP-6 Outline Drawing
NS Package Number SDE06A
Copyright © 1999-2012, Texas Instruments Incorporated
13
Notes
Copyright © 1999-2012, Texas Instruments
Incorporated
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LM5134BMF/NOPB CAD模型
引脚图
封装焊盘图
LM5134BMF/NOPB 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| LM5134BMFX/NOPB | TI | 7.6-A/4.5-A single channel gate driver with 4-V UVLO and complementary pilot output 6-SOT- | 类似代替 |
|
LM5134BMF/NOPB 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| LM5134BMFX/NOPB | TI | 7.6-A/4.5-A single channel gate driver with 4-V UVLO and complementary pilot output 6-SOT-23 -40 to 125 | 获取价格 |
|
| LM5134BSD/NOPB | TI | 7.6-A/4.5-A single channel gate driver with 4-V UVLO and complementary pilot output 6-WSON -40 to 125 | 获取价格 |
|
| LM5134BSDX/NOPB | TI | 具有 4V UVLO 和互补分离输出的 7.6A/4.5A 单通道栅极驱动器 | NGG | 6 | -40 to 125 | 获取价格 |
|
| LM5140-Q1 | TI | 宽输入电压、双路 2.2MHz 低 Iq 同步降压控制器 | 获取价格 |
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| LM5140QRWGRQ1 | TI | 宽输入电压、双路 2.2MHz 低 Iq 同步降压控制器 | RWG | 40 | -40 to 150 | 获取价格 |
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| LM5140QRWGTQ1 | TI | 宽输入电压、双路 2.2MHz 低 Iq 同步降压控制器 | RWG | 40 | -40 to 150 | 获取价格 |
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| LM5141 | TI | 低 IQ、宽输入范围同步降压控制器 | 获取价格 |
|
| LM5141-Q1 | TI | 汽车类宽输入 2.2MHz 低 IQ 同步降压控制器 | 获取价格 |
|
| LM5141-Q1_V01 | TI | LM5141-Q1 Wide Input Range Synchronous Buck Controller | 获取价格 |
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| LM5141QRGERQ1 | TI | 汽车类宽输入 2.2MHz 低 IQ 同步降压控制器 | RGE | 24 | -40 to 150 | 获取价格 |
|
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