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SN74AHCT273DWR

更新时间：2025-06-28 07:18:44
品牌：TI
描述：OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

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SN74AHCT273DWR 概述

OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 八路D型触发器与Clear 触发器 触发器/锁存器

SN74AHCT273DWR 规格参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：1.05
Is Samacsys：N系列：AHCT/VHCT/VT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：45000000 Hz
最大I（ol）：0.008 A湿度敏感等级：1
位数：8功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TR
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：11 ns
传播延迟（tpd）：11 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mm最小 fmax：65 MHz
Base Number Matches：1

SN74AHCT273DWR 数据手册

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SN54AHCT273, SN74AHCT273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS375E – JUNE 1997 – REVISED APRIL 2002  
SN54AHCT273 . . . J OR W PACKAGE  
SN74AHCT273 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Contain Eight Flip-Flops With Single-Rail  
Outputs  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
Direct Clear Input  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
Individual Data Input to Each Flip-Flop  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
– Pattern Generators  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
13 5D  
12 5Q  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
11  
GND  
CLK  
SN54AHCT273 . . . FK PACKAGE  
(TOP VIEW)  
– 1000-V Charged-Device Model (C101)  
description  
Thesedevicesarepositive-edge-triggeredD-type  
flip-flops with a direct clear (CLR) input.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
17 7D  
4
5
6
7
8
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the transition time of the positive-going pulse.  
When CLK is at either the high or low level, the  
D input has no effect at the output.  
16  
15  
14  
7Q  
6Q  
6D  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT273N  
SN74AHCT273N  
Tube  
SN74AHCT273DW  
SN74AHCT273DWR  
SN74AHCT273NSR  
SN74AHCT273DBR  
SN74AHCT273PWR  
SOIC – DW  
AHCT273  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
AHCT273  
HB273  
SSOP – DB  
TSSOP – PW  
TVSOP – DGV  
CDIP – J  
HB273  
SN74AHCT273DGVR HB273  
SNJ54AHCT273J  
SNJ54AHCT273W  
SNJ54AHCT273FK  
SNJ54AHCT273J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT273W  
SNJ54AHCT273FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
SN54AHCT273, SN74AHCT273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS375E – JUNE 1997 – REVISED APRIL 2002  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLK  
D
X
H
L
CLR  
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
logic diagram (positive logic)  
1D  
2D  
3D  
4D  
5D  
13  
6D  
14  
7D  
17  
8D  
18  
3
4
7
8
11  
CLK  
1D  
C1  
1D  
C1  
1D  
1D  
C1  
1D  
C1  
1D  
C1  
1D  
C1  
1D  
C1  
C1  
R
R
R
R
R
R
R
R
1
CLR  
2
5
6
9
12  
5Q  
15  
6Q  
16  
7Q  
19  
8Q  
1Q  
2Q  
3Q  
4Q  
logic diagram, each flip-flop (positive logic)  
C
C
D
TG  
C
TG  
C
Q
C
C
TG  
CLK(I)  
TG  
C
C
C
C
R
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
SN54AHCT273, SN74AHCT273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS375E – JUNE 1997 – REVISED APRIL 2002  
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V  
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V  
+ 0.5 V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA  
IK  
I
Output clamp current, I  
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA  
OK  
O O CC  
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA  
Continuous current through V  
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W  
O
O
CC  
CC  
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA  
JA  
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W  
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C  
stg  
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Note 3)  
SN54AHCT273 SN74AHCT273  
UNIT  
MIN  
4.5  
2
MAX  
MIN  
4.5  
2
MAX  
V
V
V
V
V
Supply voltage  
5.5  
5.5  
V
V
CC  
IH  
IL  
High-level input voltage  
Low-level input voltage  
Input voltage  
0.8  
5.5  
0.8  
5.5  
V
0
0
0
0
V
I
Output voltage  
V
V
V
O
CC  
CC  
I
I
High-level output current  
Low-level output current  
Input transition rise or fall time  
Operating free-air temperature  
–8  
–8  
mA  
mA  
ns/V  
°C  
OH  
OL  
8
8
20  
85  
∆t/∆v  
20  
T
–55  
125  
–40  
A
NOTE 3: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
SN54AHCT273, SN74AHCT273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS375E – JUNE 1997 – REVISED APRIL 2002  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
A
= 25°C  
TYP  
SN54AHCT273 SN74AHCT273  
PARAMETER  
TEST CONDITIONS  
= –50  
V
UNIT  
CC  
MIN  
4.4  
MAX  
MIN  
4.4  
MAX  
MIN  
4.4  
MAX  
I
A
4.5  
OH  
V
4.5 V  
4.5 V  
V
OH  
OL  
3.94  
3.8  
3.8  
I
= –8 mA  
OH  
OL  
I
= 50  
A
0.1  
0.36  
±0.1  
4
0.1  
0.44  
±1*  
40  
0.1  
0.44  
±1  
V
V
I
= 8 mA  
OL  
I
I
V = 5.5 V or GND  
0 V to 5.5 V  
5.5 V  
A
A
I
I
V = V  
or GND,  
I = 0  
O
40  
CC  
I
CC  
One input at 3.4 V,  
Other inputs at V  
†
5.5 V  
5 V  
1.35  
10  
1.5  
1.5  
10  
A
∆I  
CC  
or GND  
CC  
V = V or GND  
CC  
C
2.5  
pF  
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V  
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V  
CC  
= 0 V.  
CC  
†
.
timing requirements over recommended operating free-air temperature range, V  
(unless otherwise noted) (see Figure 1)  
= 5 V ± 0.5 V  
CC  
T
= 25°C  
SN54AHCT273 SN74AHCT273  
A
UNIT  
MIN  
5
MAX  
MIN  
6
MAX  
MIN  
6
MAX  
CLR low  
t
Pulse duration  
ns  
w
CLK high or low  
Data before CLK↑  
CLR before CLK↑  
5
6.5  
5
6.5  
5
5
t
t
ns  
ns  
Setup time  
su  
2.5  
0
2.5  
0
2.5  
0
Hold time, data after CLK↑  
h
switching characteristics over recommended operating free-air temperature range,  
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)  
V
CC  
T = 25°C  
A
SN54AHCT273 SN74AHCT273  
FROM  
(INPUT)  
TO  
LOAD  
PARAMETER  
UNIT  
(OUTPUT) CAPACITANCE  
MIN  
TYP  
MAX  
MIN  
65**  
45  
MAX  
MIN  
65  
45  
1
MAX  
C
C
C
= 15 pF  
= 50 pF  
= 15 pF  
75** 120**  
L
L
L
f
MHz  
ns  
max  
50  
75  
7.5**  
5.5**  
5.8**  
8.5  
t
t
t
t
t
t
t
10**  
7.5**  
8.2**  
11  
1** 11.6**  
11.6  
8.8  
10  
CLR  
CLK  
Q
Q
Q
Q
PHL  
PLH  
PHL  
PHL  
PLH  
PHL  
sk(o)  
1**  
1**  
1
8.8**  
10**  
12.6  
9.8  
1
C
C
C
C
= 15 pF  
= 50 pF  
= 50 pF  
= 50 pF  
ns  
L
L
L
L
1
1
12.6  
9.8  
11  
ns  
CLR  
CLK  
6.5  
8.5  
1
1
ns  
6.8  
9.2  
1
11  
1
1***  
1
ns  
** On products compliant to MIL-PRF-38535, this parameter is not production tested.  
*** On products compliant to MIL-PRF-38535, this parameter does not apply.  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
SN54AHCT273, SN74AHCT273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS375E – JUNE 1997 – REVISED APRIL 2002  
noise characteristics, V  
= 5 V, C = 50 pF, T = 25°C (see Note 4)  
CC  
L
A
SN74AHCT273  
UNIT  
PARAMETER  
MIN  
TYP  
MAX  
V
V
V
V
V
Quiet output, maximum dynamic V  
0.76  
V
V
V
V
V
OL(P)  
OL(V)  
OH(V)  
IH(D)  
IL(D)  
OL  
Quiet output, minimum dynamic V  
Quiet output, minimum dynamic V  
High-level dynamic input voltage  
Low-level dynamic input voltage  
–0.48  
OL  
4.4  
2
OH  
0.8  
NOTE 4: Characteristics are for surface-mount packages only.  
operating characteristics, T = 25°C  
A
PARAMETER  
TEST CONDITIONS  
No load, f = 1 MHz  
TYP  
UNIT  
C
Power dissipation capacitance  
27  
pF  
pd  
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
SN54AHCT273, SN74AHCT273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS375E – JUNE 1997 – REVISED APRIL 2002  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
Open  
GND  
S1  
R
= 1 kΩ  
L
TEST  
S1  
From Output  
Under Test  
Test  
Point  
From Output  
Under Test  
t
t
/t  
Open  
PLH PHL  
/t  
C
C
L
t
V
CC  
L
PLZ PZL  
/t  
(see Note A)  
(see Note A)  
GND  
PHZ PZH  
Open Drain  
V
CC  
LOAD CIRCUIT FOR  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
3-STATE AND OPEN-DRAIN OUTPUTS  
3 V  
1.5 V  
Timing Input  
0 V  
t
w
t
h
3 V  
t
su  
3 V  
0 V  
1.5 V  
1.5 V  
Input  
Input  
1.5 V  
1.5 V  
Data Input  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
3 V  
0 V  
3 V  
0 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
t
t
t
t
t
PZL  
PLZ  
PLH  
PHL  
Output  
Waveform 1  
V
≈V  
OH  
CC  
In-Phase  
Output  
50% V  
50% V  
50% V  
CC  
50% V  
CC  
CC  
V
S1 at V  
(see Note B)  
CC  
V
V
+ 0.3 V  
OL  
V
OL  
OL  
t
t
t
PHL  
PLH  
PZH  
PHZ  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
OH  
Out-of-Phase  
Output  
– 0.3 V  
OH  
50% V  
50% V  
CC  
CC  
CC  
V
≈0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.  
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.  
Figure 1. Load Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Jul-2006  
PACKAGING INFORMATION  
Orderable Device  
SN74AHCT273DBR  
SN74AHCT273DBRE4  
SN74AHCT273DGVR  
SN74AHCT273DGVRE4  
SN74AHCT273DW  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SSOP  
DB  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SSOP  
TVSOP  
TVSOP  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
DB  
DGV  
DGV  
DW  
DW  
DW  
DW  
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AHCT273DWE4  
SN74AHCT273DWR  
SN74AHCT273DWRE4  
SN74AHCT273N  
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SN74AHCT273NE4  
SN74AHCT273NSR  
SN74AHCT273NSRE4  
SN74AHCT273PWR  
SN74AHCT273PWRE4  
SN74AHCT273PWRG4  
PDIP  
N
20  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SO  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
NS  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
PW  
PW  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Jul-2006  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
MECHANICAL DATA  
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000  
DGV (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0,23  
0,13  
M
0,07  
0,40  
24  
13  
0,16 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
0°–ā8°  
0,75  
1
12  
0,50  
A
Seating Plane  
0,08  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
38  
48  
56  
DIM  
A MAX  
A MIN  
3,70  
3,50  
3,70  
3,50  
5,10  
4,90  
5,10  
4,90  
7,90  
7,70  
9,80  
9,60  
11,40  
11,20  
4073251/E 08/00  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.  
D. Falls within JEDEC: 24/48 Pins – MO-153  
14/16/20/56 Pins – MO-194  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°–ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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Following are URLs where you can obtain information on other Texas Instruments products and application  
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Amplifiers  
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www.ti.com/audio  
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Copyright 2006, Texas Instruments Incorporated  

SN74AHCT273DWR CAD模型

原理图符号

PCB 封装图

SN74AHCT273DWR 替代型号

型号 制造商 描述 替代类型 文档
SN74AHCT273DBR TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 完全替代
SN74AHCT273PWR TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 完全替代
SN74AHCT273DW TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 类似代替

SN74AHCT273DWR 相关器件

型号 制造商 描述 价格 文档
SN74AHCT273DWRE4 TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273DWRG4 TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273N TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273NE4 TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273NSR TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273NSRE4 TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273NSRG4 TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273PW TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格
SN74AHCT273PWLE TI AHCT/VHCT SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20 获取价格
SN74AHCT273PWR TI OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 获取价格

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