首页 > 信号电路 > 运动控制电子器件 > TLS2205PM

TLS2205PM

更新时间：2025-07-01 13:11:05
品牌：TI
描述：Voice-Coil Motor Driver, Spindle-Motor Driver, and Voltage Monitor 64-LQFP 0 to 70

PDF下载

中文翻译

免费 PCB/SMT

TLS2205PM 概述

Voice-Coil Motor Driver, Spindle-Motor Driver, and Voltage Monitor 64-LQFP 0 to 70 运动控制电子器件

TLS2205PM 规格参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：QFP, QFP64,.5SQ
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.91
模拟集成电路 - 其他类型：VOICE COIL MOTOR CONTROLLERJESD-30 代码：S-PQFP-G64
功能数量：1端子数量：64
最高工作温度：70 °C最低工作温度：
最大输出电流：1.4 A封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP64,.5SQ
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified子类别：Motion Control Electronics
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

TLS2205PM 数据手册

通过下载TLS2205PM数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载
SLFS040 – DECEMBER 1993  
DL PACKAGE  
(TOP VIEW)  
Single-Chip Voice-Coil Motor Driver and  
Spindle-Motor Driver  
Precision Dual-Voltage Monitor  
Operates From Single 5-V Supply  
LinBiCMOS Technology  
SCLK  
SDATA  
SPSZ  
PORN  
UV  
1
56 MTRCLK  
2
DV  
55  
CC  
3
54 AUXIN  
53 AUXOUT  
52 NC  
4
Low Power Dissipation  
5
Internal Overtemperature Shutdown  
Circuitry  
CPOR  
NC  
6
51 HU  
7
50 HV  
Low-Profile 56-Terminal DL Package and  
64-Terminal PM Package Available  
NC  
8
49 HW  
AV  
V
9
48 DGND  
CC  
10  
47  
U
4-V Reference Buffer  
System Power-On Reset  
Monotonic 8-Bit DAC  
DD  
VCMGND 11  
VCMA 12  
46 SPNV  
CC  
45 SPNSNSR2  
44 SPNGND  
43 SPNGND  
SPNGND 13  
SPNGND 14  
SUBSTRATE  
GROUND  
AND  
description  
15  
42  
SPNGND  
SPNGND 16  
VCMB 17  
SPNGND  
HEAT SINK  
The TLS2205 is a combination voice-coil and  
spindle-motor driver with voltage monitor  
integrated circuit. This circuit is designed for  
small-form-factor, high-performance hard disk  
drives. The TLS2205 integrates a three-phase  
brushless dc motor driver with a linear full-bridge  
voice-coil driver. Additional circuitry is added for  
power-up and power-down sequencing of the  
driver amplifiers used for motor speed control. A  
brake function can be invoked on the spindle  
motor after the head is in a safe landing zone.  
External sense resistors are used for precision  
spindle motor and VCM current monitoring.  
Automatic head retract is provided for voltage or  
thermal fault conditions. The TLS2205 operates  
with only 5 V of supply voltage and has a  
sleep-mode option for low-power applications. All  
41 SPNGND  
40 SPNSNSR1  
VCMV  
18  
19  
20  
39  
38  
37  
V
CC  
AGND  
W
RETOUT  
RETSET 21  
NC 22  
CRET  
36 REFBUF  
35 SPNCOMP  
34 CTS  
23  
24  
25  
RSENP  
RSENN  
CMPI  
CMPO 26  
VIVCM 27  
33  
32  
VPHASE  
COMDLY2  
31 COMDLY1  
30 SPNSW  
29 CTDRV  
28  
VCMREF  
NC–No internal connection  
devicefunctionsare controlledfrom a three-wireserial port. Devicepackagingisa 56-terminal DL or 64-terminal  
PM package. Center pins are tied to the die mount tab for improved heat dissipation on both packages.  
Voice-Coil Motor Driver  
Spindle-Motor Driver  
–
0.4-A MOS H-Bridge Power Amplifier  
– Hall- or Back-EMF Commutation Circuitry  
– 3-Phase Driver With 1.3-A MOS Output  
– Bipolar or Unipolar Drive Modes  
– Programmable Frequency-Locked Speed  
Control Loop  
– No Crossover Distortion  
– Precision VCM Control Loop With External Sense  
Resistor  
– Internal 8-Bit Control DAC With Four Gain Ranges  
– Controlled-Velocity Head Retract  
– Compensation Adjust Terminals for Bandwidth  
Control  
– Programmable Start-Up Current  
– Linear Spindle Current Control  
– Low r  
, 1.3 Total  
DS(on)  
– Capability for External Velocity Feedback  
– Sector Data Tachometer Signal Input  
(Optional)  
– Low r  
, 2 Total  
DS(on)  
– No External Retract Power Supply Isolation  
– Speed Sense Tachometer Output  
– Internal Schottky Diodes for Retract Power  
Source  
Components Required  
– Controlled Brake Function  
LinBiCMOS is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PM PACKAGE  
(TOP VIEW)  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
AV  
1
48  
HW  
DGND  
U
CC  
NC  
NC  
2
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
3
V
4
U
DD  
NC  
5
SPNV  
CC  
NC  
VCMGND  
VCMGND  
VCMGND  
VCMGND  
VCMA  
6
SPNSNSR1  
SPNGND  
SPNGND  
SPNGND  
SPNGND  
SPNSNSR2  
V
7
8
9
10  
11  
12  
13  
14  
15  
16  
VCMB  
VCMV  
W
CC  
AGND  
RETOUT  
RETSET  
W
CRET  
REFBUF  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
NC–No internal connection  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
Terminal Functions  
TERMINAL  
§
I/O  
DESCRIPTION  
SUBSYSTEM  
†
‡
NAME  
AGND  
NO.  
19  
54  
53  
9
NO.  
14  
54  
53  
1
Analog GND  
VM  
SPN  
SPN  
VM  
AUXIN  
I
Spindle-phase commutate input  
Spindle-system status output  
Analog 5-V supply voltage  
AUXOUT  
O
I
AV  
CC  
CMPI  
25  
26  
31  
32  
6
20  
21  
26  
27  
62  
34  
24  
29  
47  
55  
52  
51  
48  
56  
60  
33  
15  
16  
19  
18  
57  
58  
30  
I
VCM frequency-compensation input  
VCM frequency-compensation output  
Spindle back-EMF commutation delay control input  
Spindle back-EMF commutation delay control output  
Power-on-reset delay capacitor output  
Retract power full-wave-rectifier output  
Center-tap pnp drive output  
Spindle center-tap sense input  
Logic GND  
VCM  
VCM  
SPN  
SPN  
VM  
CMPO  
COMDLY1  
COMDLY2  
CPOR  
O
I
O
O
O
O
I
CRET  
37  
29  
34  
48  
55  
51  
50  
49  
56  
4
VM  
CTDRV  
CTS  
SPN  
SPN  
SP  
DGND  
DV  
HU  
HV  
I
Logic power supply voltage  
Hall-phase U input  
SP  
CC  
I
SPN  
SPN  
SPN  
SPN  
VM  
I
I
Hall-phase V input  
HW  
Hall-phase W input  
MTRCLK  
PORN  
I
Spindle-motor reference clock input  
Power-on-reset node, open-drain output/reset input  
4-V reference  
I/O  
O
O
I
REFBUF  
RETOUT  
RETSET  
RSENN  
RSENP  
SCLK  
36  
20  
21  
24  
23  
1
VCM  
VM  
Retract voltage set output  
Retract voltage set input  
VM  
I
VCM current-sense negative input  
VCM current-sense positive input  
Serial input clock  
VCM  
VCM  
SP  
I
I
SDATA  
2
I/O  
O
Serial input/output port  
SP  
SPNCOMP  
SPNGND  
35  
Spindle charge-pump filter  
SPN  
SPN  
13, 14, 15, 16,  
41, 42, 43, 44  
39, 40, 41, 42  
Spindle ground  
SPNSNSR1  
SPNSNSR2  
SPNSW  
40  
45  
30  
46  
3
43  
38  
25  
44  
59  
I
O
O
I
Spindle-sense-resistor kelvin input  
Spindle-sense-resistor output  
SPN  
SPN  
SPN  
SPN  
SP  
Spindle compensation capacitor switch  
Spindle-driver supply voltage  
SPNV  
CC  
SPSZ  
I
Serial I/O port select. When low, data goes into port.  
When high, data goes out of port.  
U
47  
5
45, 46  
61  
O
I
Spindle-phase U connection  
SPN  
VM  
UV  
Undervoltage, power-on-reset voltage sense input  
†
‡
§
56-terminal DL package  
64-terminal PM package  
SPN = spindle, VCM = voice-coil motor, VM = voltage monitor, SP = serial port  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
Terminal Functions (Continued)  
TERMINAL  
§
I/O  
DESCRIPTION  
SUBSYSTEM  
†
‡
NO.  
NAME  
NO.  
V
39  
12  
37  
O
O
O
Spindle-phase V connection  
VCM driver output A  
SPN  
VCM  
VCMA  
11  
VCMB  
17  
11  
28  
18  
10  
27  
33  
38  
12  
VCM driver output B  
VCM  
VCM  
VCM  
VCM  
SPN  
VCM  
SPN  
SPN  
VCMGND  
VCMREF  
7, 8, 9, 10  
VCM driver supply ground  
23  
13  
O
VCM voltage reference  
VCMV  
CC  
VCM driver supply voltage  
V
4
O
O
O
O
Charge-pump voltage-tripler output  
VCM current-sense output (VCM = 2 V)  
Spindle-back-EMF-phase voltage  
Spindle-phase W connection  
DD  
VIVCM  
VPHASE  
W
22  
28  
35, 36  
†
‡
§
56-terminal DL package  
64-terminal PM package  
SPN = spindle, VCM = voice-coil motor, VM = voltage monitor, SP = serial port  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Motor supply voltage, SPNV , VCMV  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V  
CC CC  
Power supply voltage, AV , DV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V  
CC  
CC  
Maximum voltage at U, V, W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V  
Spindle current at U, V, W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A  
VCM current, VCMA, VCMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.41 A  
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C  
J
Thermal resistance (DL package): Junction-to-ambient, R  
(see Note 2) . . . . . . . . . . . . . . . . . . . . . 89 C/W  
JA  
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 14 C/W  
Junction-to-case, R  
JC  
Thermal resistance (PM package): Junction-to-ambient, R  
(see Note 2) . . . . . . . . . . . . . . . . . . . . . 71 C/W  
JA  
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . 14 C/W  
Junction-to-case, R  
JC  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 125 C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values are with respect to ground.  
2. The device is mounted on a printed-circuit board with 0.22 square inches of copper connected to the package tabs.  
DISSIPATION RATING TABLE  
T
25 C  
DERATING FACTOR  
ABOVE T = 25 C  
A
T = 70 C  
A
POWER RATING  
A
PACKAGE  
POWER RATING  
DL  
1125 mW  
9.0 mW/ C  
9.0 mW/ C  
720 mW  
PM  
1125 mW  
720 mW  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
recommended operating conditions  
MIN NOM  
MAX  
UNIT  
Supply voltage, DV , AV  
CC  
SPNV , VCMV  
CC CC  
4.5  
3.5  
5
5.5  
V
V
V
CC,  
High-level input voltage, V  
Low-level input voltage, V  
DV +0.3  
CC  
IH  
SCLK, SDATA, AUXIN, MTRCLK, PORN,  
HU, HV, HW, SPSZ  
1.5  
IL  
Level change on SDATA or SPSZ before  
SCLK  
Setup time, t  
su  
25  
ns  
Speed reference clock frequency  
Speed reference clock duty cycle  
Speed reference clock duration  
Clock frequency  
1
50%  
41.6  
1
12  
75%  
62.5  
10  
MHz  
MTRCLK  
SCLK  
25%  
20.8  
ns  
MHz  
Clock duty cycle  
25%  
25  
0
50%  
50  
75%  
75  
Pulse duration, t  
ns  
C
w
Operating free-air temperature, T  
70  
A
Operating virtual junction temperature, T  
0
150  
C
J
electrical characteristics over recommended supply voltage range, T = 25 C  
A
PARAMETER  
OH  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
High-level output voltage, V  
I
I
= 5  
= 5  
A
A
3.5  
O
Low-level output voltage, V  
1.5  
V
OL  
CC  
O
Operating supply current, I  
Sleep supply current, I  
20  
3
mA  
mA  
A
DV , AV  
CC  
CC  
CC  
High-level input current, I  
1
IH  
Low-level input current, I  
– 1  
A
IL  
voltage and temperature monitor electrical characteristics over recommended supply voltage  
range, T = 25 C  
A
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
Power-on-reset voltage  
1.21  
Power-on-reset sense bias current  
Hysteresis  
UV  
100  
nA  
mV  
V
25  
4
Internal power-on-reset threshold voltage, AV  
Power-on-reset timing voltage  
Power-on-reset timing current  
Output voltage  
CC  
1.21  
5
V
CPOR  
PORN  
See Note 4  
A
I
= 1 mA  
0.4  
0.8  
10  
15  
V
PORN  
Output leakage current  
A
Charge-pump voltage-tripler output voltage  
V
12  
13  
0.25  
20  
V
DD  
Charge-pump voltage-tripler output voltage load regulation  
Thermal shutdown hysteresis  
See Note 5  
V/ A  
mV  
Voltage monitor accuracy  
10 %  
160  
Thermal shutdown temperature  
C
NOTES: 3. PORN reset timing is time reset = C  
(V ).  
/I  
CPOR  
CPOR CPOR  
4.  
V
can be used to drive external NMOS switches; however, the effective dc loading should be less than 1 A.  
DD  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
voice-coil motor driver electrical characteristics over recommended range of supply voltage,  
T = 25 C  
A
PARAMETER  
Total output drain-to-source on-state  
resistance, 2  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VCMA, VCMB  
2
3
r
DS(on)  
I
I
I
= 200 mA  
0.6  
1.2  
1.3  
V
V
V
O
Total VCM driver voltage drop  
= 400 mA  
= 50 mA, RETSET grounded  
O
VCM driver voltage drop on retract  
VCM gain accuracy  
VCM differential linearity  
Slew rate  
CRET  
4%  
1.6%  
.05  
0.7  
V/ s  
V
Control voltage  
RETSET  
CRET,  
RETOUT  
Pullup resistance  
20  
Output voltage  
Output impedance  
Source current  
Output voltage  
Clamp voltage  
3.88  
1.94  
4
4.12  
V
REFBUF  
f = 10 kHz  
6.1  
7
mA  
V
VCMREF  
CRET  
2
9
2.06  
See Note 6  
V
NOTE 5: Optional Zener diode may be required on CRET for filtering narrow voltage spikes  
spindle-motor driver electrical characteristics over recommended supply voltage range, T = 25 C  
A
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Total output drain-to-source on-state resistance,  
U, V, W  
1.3  
1.6  
2
r
DS(on)  
Source-driver output voltage slew rate  
Sink-driver output voltage slew rate  
Retract clamp diode forward voltage  
Center tap driver-output saturation resistance  
Speed discriminator count range  
Maximum compensation voltage  
Maximum spin compensation voltage  
Minimum spin compensation voltage  
Charge-pump leakage current  
0.07  
0.07  
0.5  
V/ s  
V/ s  
V
See Note 7  
I = 50 mA  
RETOUT  
U, V, W, CRET  
CTDRV  
See Note 8  
150  
See Note 9  
8
8333 16384  
VCM DAC word = FFhex  
RUN MODE  
4
5
V
V
0.8  
V
3
5
nA  
A
Charge-pump output current  
SPNCOMP  
U, V, W  
50  
Charge-pump output current matching  
Spindle-driver start current  
1%  
1.2  
A
NOTES: 6. This slew rate is determined by the percentage of programmed current.  
7. CTDRV is an open-drain switch.  
8. The typical count (1041) f  
= 3600 (RPM) at f(MTRCLK) = 1 MHz  
spindle  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
voltage monitor  
The TLS2205 voltage-monitor circuit is designed to monitor the voltage of the system’s 5-V power supply. The  
device has an internal lockout threshold voltage of 4 V. If the power supply drops below 4 V, an internal fault is  
generated and PORN goes low. In applications where a more accurate threshold is desired (greater than 4 V),  
an external resistor divider may be connected to UV. If UV is not used, it must be tied to V  
Figure 1). The following equations can be used to determine the voltage divider resistor values:  
(refer to  
CC  
V
= 1.21 / [R2 / (R1 + R2)]  
CC(trip)  
where:  
UV sense bias current = 10 nA  
R1 is resistor connected from V  
to UV  
CC  
R2 is resistor connected from UV to ground  
> 4 V  
V
CC(trip)  
Hysteresis at UV 25 mV  
Note:  
A capacitor (Cuv1) may be considered for short-duration power loss.  
The voltage monitor incorporates a deglitch timing delay circuit for applications where PORN is used to reset  
the system’s microprocessor. A delaycan be implemented on PORN byconnecting a capacitor between CPOR  
and ground. The reset time (see Figure 2) is calculated by using the following equation:  
TR = C  
CPOR  
(V  
I
)
CPOR  
CPOR  
where:  
TR = reset time in seconds  
C
= capacitor value in farads  
CPOR  
CPOR  
V
= 1 V  
I
= 5 A  
CPOR  
Figure 1 represents the voltage-monitor circuit, and Figure 2 represents the power-on reset (PORN) timing  
diagram. The following is a functional overview of the voltage monitor system. (V = 4.2 V).  
CC(trip)  
capacitor to start charging. As  
Time 1: During startup, Comp1 resets the R-S flip-flop and allows the C  
CPOR  
the supply voltage increases, V  
becomes greater than 1.21 V (band-gap voltage), which allows  
CPOR  
Comp2 to pull PORN high, disabling the retract control circuit.  
Time 2: Time 2 represents the normal run mode. At this time, the R-S flip-flop is reset, CPOR is high, PORN  
is high, and the retract control circuit is disabled.  
Time 3: An external fault is generated by the microprocessor (or external device) by pulling PORN low. No other  
parts of the voltage-monitor circuit are affected.  
Time 4: If the system’s supply voltage drops below the preset value (V  
= 4.2 V, see Figure 2), the  
drops below  
1.21 V, PORN is pulled low and a fault is generated that triggers the retract control circuit. Once  
CC(trip)  
R-S flip-flop is set and allows the capacitor across CPOR to discharge. When V  
CPOR  
V
V
increases above the trip level, the R-S flip-flop is reset and C  
begins to charge towards  
is greater than 1.21 V and the retract control circuit  
CPOR  
CC(trip)  
. After TR seconds, the voltage across C  
CPOR  
CC  
is disabled along with PORN being pulled high.  
Time 5: Time5 representsthe power down/emergency retract mode. If the system’s supply voltagedropsbelow  
the preset value (V = 4.2 V, see Figure 2), the R-S flip-flop is set and allows the capacitor  
CC(trip)  
across CPOR to discharge. When Vcpor drops below 1.21 V, PORN is pulled low and a fault is  
generated.  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
V
CC  
Overtemperature  
Voltage Reference  
Fault  
V
CC  
Vlt  
I Vref  
CPOR  
V
1.21 V  
CC  
PORN  
CPOR  
Comp1  
Comp2  
+
+
_
RDY  
0.25 V  
+
_
R1  
_
5
A
UV  
V
CPOR  
Cuv1  
R
Q
R2  
V
CC  
Cpor  
S
+
_
45.6 k  
20 k  
V
= 4.1 V  
CC (enable)  
NOTE: Vlt = Low voltage threshold = 0.25 V  
V
I
= Voltage across the power-on-reset capacitor  
CPOR  
CPOR  
= Current supplied to the CPOR terminal  
5 A  
Vref = Reference voltage = 1.21 V  
Area within the dotted line is internal to the device  
Figure 1. Voltage Monitor Circuit  
Time 1  
Time 2  
Time 3  
= 4.2 V  
Time 4  
Time 5  
5 V  
0 V  
5 V  
0 V  
5 V  
0 V  
AV  
CC  
V
CC(trip)  
CPOR  
PORN  
Band-Gap Voltage = 1.21 V  
TR = Reset Time  
Time  
Figure 2. Power-On Reset Timing Diagram  
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
voice-coil driver system  
The voice-coil full-bridge power amplifier is capable of 0.4-A output current and has a total drain-to-source  
on-state resistance (2 ) of 2 . The voice-coil control system includes a precision current-sense  
r
DS(on)  
amplifier that detects load current with a single resistor in series with the voice-coil motor (VCM). The VCM  
current is commanded via serial port A. Full-scale current is controlled by the value of the VCM current sense  
resistor (Rsvcm). The retract control circuitry is fully integrated and does not require external isolation of the  
device power supply terminals such as an external isolation transistor/diodes. Voice-coil driver auxiliary digital  
control functions include an output-disable and low-power sleep mode following a retract of the VCM to the  
landing zone. During a fault condition, the VCM drivers are disabled.  
VCM current control  
The voice-coil motor current is controlled by an internal 8-bit digital-to-analog converter (DAC), four adjustable  
gain ranges, and the external current-sense resistor (Rsvcm). The four gain ranges (see functional block  
diagram) are system dependent and provide the current needed to ensure that the head assembly swings  
across the whole platter. Selecting one of the four gain ranges is accomplished via port A, bits 8 and 9 (see  
Table 1 for gain settings and Table 4 for bit definitions). During the start mode, the 8-bit DAC is used to start the  
spindle (see Figure 5). In the run mode, the 8-bit DAC is used to program the VCM current. Port A (bits 0–7)  
controls the 8-bit DAC (see Table 4). The VCM current-control equation is given as follows:  
I
= I [ B7 + 1/2 B6 + 1/4 B5 + 1/8 B4 + 1/16 B3 + 1/32 B2 + 1/64 B1 + 1/128 B0–1] [A]  
X
VCM  
where:  
I = (V  
G)/(16 Rsvcm)  
I (+ full scale) at V = $FF  
X
ref  
X
I (– full scale) at V = $00  
X
V
(the internal system voltage reference) = 2 V  
ref  
Rsvcm (the external VCM current sense resistor) typically 0.47  
G (the VCM current gain scale)  
1%  
B0–B7 (port-A control bits)  
Maximum VCM current is load dependent. The following equation should be used as a guideline to determine  
maximum VCM current:  
I
max = V max / Rtotal  
CC  
VCM  
where:  
V
max = 5.5 V  
CC  
Rtotal = Rsvcm + 2  
r
+ Rvcm  
DS(on)  
Table 1. VCM Gain-Range Scale Truth Table  
GAIN SWITCH SETTING  
(see functional block diagram)  
SERIAL PORT A GAIN SETTINGS  
(see Table 4)  
GS1  
Open  
Closed  
Open  
Open  
GS2  
Open  
Open  
Closed  
Open  
GS3  
Open  
Open  
Open  
Closed  
GR0  
GR1  
GAIN (G)  
0.250  
0
0
1
1
0
1
0
1
0.333  
0.500  
1.000  
10  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
VCM current-loop stability is accomplished using the filter at CMPI and CMPO. This filter has the following  
transfer function:  
(Rcmp (Ccmp2 + Cmp1) s + 1)  
Ccmp2  
s
(Rcmp Ccmp1 s + 1)  
where:  
s is a Laplace operator  
VCM retract  
The TLS2205 integrated retract circuit eliminates the need for external power supply isolation devices. The  
retract mode is triggered by the voltage monitor fault logic signal. The retract power path is coupled from the  
spindle-motor back-EMF to the RETOUT MOS high-side driver via CRET. After the retract control block has  
been triggered by a loss of power, the following events occur:  
1. The system control logic is reset to the power-up state. All bias is disabled (including V ); all power  
DD  
outputs are disabled.  
2. The retract control circuit locks the VCMB low-side driver on and disables the VCMB high-side driver.  
3. The retract control circuit disables the VCMA low- and high-side drivers.  
4. RETOUT is enabled, and RETSET is used to control the voltage applied to RETOUT.  
The spindle back-EMF-mode voltage supplies the energy necessary to retract the VCM (see Figure 3). The  
energy stored in the capacitor (CV ) connected to V  
is used to control the RETOUT and VCMB power  
DD  
DD  
devices. The value of this capacitor can be calculated based on ~ 2 A of retract-mode discharge current and  
the time to retract t the VCM. The RETOUT control equation is:  
V
= V  
= 2 A ( t)  
[1 + (Rrset1/Rrset2)]  
VCMA  
CV  
be  
DD  
V
VCMA  
is the base-to-emitter junction voltage 0.7 V.  
where:  
Example:  
V
be  
Assume: Rrset1 = 62 k  
Rrset2 = 100 k  
t = 6 ms max  
Therefore: CV  
DD  
=
2 A (5 ms)  
0.7 V (1 + 62 k /100 k )  
= 0.009 F  
0.01 F  
t = 0.01 F [0.7 V (1 + 62 k /100 k )]  
2 A  
= 5.7 ms  
11  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
Figure 3 shows a block diagram of the TLS2205 retract equivalent circuit (retract mode only).  
N
Spindle Motor  
V
DD  
U
V
W
CRET  
Cret  
RETOUT  
CV  
DD  
R
RETRACT  
(or shorted)  
VCMA  
Clamp  
Rsvcm  
Rrset1  
VCM  
RETSET  
VCMB  
1
Vbe  
Rrset2  
Rlsd  
NOTE: Area within the dotted line is internal to the device  
Figure 3. Retract Equivalent Circuit  
spindle-driver system  
The spindle-driver system is capable of 1-A output current and has a total drain-to-source on-state resistance  
(2 ) of 1.3 Soft switching on the output drivers eliminates the need for external snubbers or flyback  
r
DS(on)  
diodes. An internal voltage clamp circuit helps protect against flyback voltages, while internal Schottky diodes  
provide a low-loss power path for the VCM retract function. Internal logic and analog detection circuitry provide  
complete sequencing of the power outputs in all run modes. Support for unipolar operation is provided by  
disabling the spindle high-side drivers and pulling the motor center tap to 5 V using an external pnp or PMOS  
transistor. CTDRV is used to control the base of the transistor during unipolar operation and is open otherwise.  
During a fault condition, the spindle-motor drivers are disabled.  
12  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
spindle-driver system (continued)  
For active braking, all the spindle low-side drivers are disabled and the high-side drivers are enabled, thereby  
shorting out the spindle windings at or near the supply voltage, SPNV  
.
CC  
spindle commutation  
Hall- or back-EMF-spindle commutation is selected from serial port C. See the port-C system control bit  
definitions in Table 6 for additional information.  
Hall mode  
In the Hall mode, the spindle position information is input to the TLS2205 via the HU, HV, and HW logic input  
terminals. Start current can be controlled with the internal 8-bit DAC, which is normally used to control the VCM  
current or the internal charge pump. If the DAC option is selected, the VCM driver is normally disabled during  
spindle start for power conservation. In either case, the spindle motor starts without microprocessor  
intervention.  
back-EMF mode  
For the back-EMF mode, the system microprocessor is used in conjunction with the TLS2205 internal circuitry  
to start the spindle motor.  
Start current is controlled the same way as in the Hall mode by using the DAC. Two schemes can be used to  
start commutation in the back-EMF mode. The first scheme is to use AUXIN; this method requires a pulse  
generated from the microprocessor as aninput signal toAUXIN. Variousfrequenciesandstartcurrentsare used  
to start the spindle motor. The second scheme is to use the COMM bit (bit 4) in port C. This method requires  
the microprocessor to write to port C to change the state of bit 4. For every 1-to-0 state change of  
bit 4, the spindle inverters advance one state. Different frequencies and start currents are used to start the  
spindle motor. Oncethemotor hasreached approximately10%of itsratedspeed, the TLS2205maybeswitched  
into the run mode via port C.  
Figure 4 shows the TLS2205 commutation delay circuit and the required external components.  
2 V  
V
100 mV  
ref  
+
_
+
_
NHphase  
Rcom2  
Ccom2  
COMDLY 2  
Ccom1  
Rcom1  
VPHASE  
COMDLY 2  
Figure 4. Commutation Delay Circuit  
This circuit is composed of an operational amplifier (OPA) followed by a hysteresis comparator. The TLS2205  
spindle inverter is advanced for every transition of the NHphase signal. The transition of NHphase occurs every  
time the COMDLY2 signal crosses the common-mode reference, V . The required external components are  
ref  
defined as:  
Rcom1 – Integrator gain-set resistor  
Ccom1 – DC-blocking capacitor  
Rcom2 – Integrator dc-set resistor  
Ccom2 – Integrator gain-set capacitor  
13  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
back-EMF mode (continued)  
The transfer function between COMDLY2 and VPHASE is :  
s
(Rcom2 Ccom1) VPHASE  
Vcomdly2 =  
[1+s (Rcom1 Ccom1)] [1+ s (Rcom2 Ccom2)]  
where:  
s is a Laplace operator  
The component design procedures include the following:  
Choose Rcom2 with a value as large as possible to permit small capacitor values. The typical value for  
Rcom2 is 1 M  
Calculate Ccom2so that thereisat least 45 of phaseshiftatthe phase frequencywheretheTLS2205is  
switched into the internally commutated mode. The approximate value is 10% of the target frequency.  
Calculate Rcom1 based on the desired COMDLY2 signal swing at the target frequency. The  
recommended signal swing is 1.25 V peak. Near the target frequency the integrator function,  
VCOMDLY2/VPHASE, becomes:  
1
VCOMDLY2[Mag] =  
VPHASE  
(Rcom1 Ccom2) (3 num motor poles/2) Wmotor  
VCOMDLY2[Phase] = –90  
VPHASE  
0.433 Kb Wmotor sin(Wmotor t)  
(Rcom1 Ccom2) (3 num motor poles/2) Wmotor  
VCOMDLY2 =  
0.433 Kb sin(Wmotor t)  
VCOMDLY2 =  
(Rcom1 Ccom2) (3 num motor poles/2)  
The peak value of this function is independent of the frequency.  
0.433 Kb  
Rcom1 =  
1.25 Ccom2 (3 Num Motor Poles/2)  
Choose Ccom1 such that the dc-blocking pole, 1/(Rcom1 Ccom1), occurs at a frequency below the  
integrationpole, 1/(Rcom2 Ccom2). Typically the dc-blocking pole is placedat 1/2theintegrationpole.  
Where:  
Wmotor = Mechanical frequency of the motor, r/s  
Kb = Back-EMF constant, V/(r/s)  
The internal speed-regulation feedback loop then takes control of spindle commutation, and further  
microprocessor intervention is not required. Figure  
5 shows the timing relationships for the  
spindle-motor-control sequencing in both Hall and back-EMF modes. Internal logic and analog filtering provide  
the commutation function in the commonly used back-EMF mode. In this mode, VPHASE (the difference  
between the undriven phase and the center tap voltage) is filtered to generate a signal that determines  
commutation timing (NHphase).  
14  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
High Phase  
V
W
W
U
U
V
Off Phase  
W
U
V
U
U
V
W
V
V
U
Low Phase  
W
W
V
W
U
VPHASE  
COMDLY2  
NHphase  
Phase  
(speed clock)  
Padv  
(commutate)  
(no Hall mode)  
HV  
HW  
HU  
HPhase  
(commutate)  
Figure 5. Spindle-Motor Control Sequencing  
15  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
spindle-current control  
Spindle-current control is accomplished by regulating the current through the external sense resistor, Rsspn,  
via the spindle low-side drivers (LSD). Figure 6 illustrates the arrangement for the spindle-current control  
(port C, bit 5) during the start mode (SPNMODE = 1) and the run mode (SPNMODE = 0). During startup  
(SPNMODE = 1), the 8-bit DAC is used to command the spindle start current. Upon switching to the run mode  
(SPNMODE = 0), the 8-bit DAC is used to control the VCM and the spindle motor is switched into closed-loop  
operation (see Figure 6). The transconductance function is:  
I
= (0.079 SPNCOMP – 0.057) / Rsspn  
spindle  
Note:  
Rsspn is typically 0.2  
1 V  
V
gs  
Maximum spindle current is load dependent. The following equation should be used as a guideline to determine  
maximum spindle current:  
I
= V (max) / Rtotal  
CC  
spindle  
where:  
V
(max) = 5.5 V  
CC  
Rtotal = Rsspn + 2  
r
+ Rspindle  
DS(on)  
V
CC  
SPNV  
CC  
HSD  
+
_
SPNCOMP  
EN  
S
8-B  
D/A  
8
U, V, or W  
To VCM  
(see Functional  
Block Diagram)  
2
(0–2 V)  
R4  
Cspn1  
+
R3  
LSD  
_
SPNMODE  
Cspn2  
SPNSW  
Rspn  
R1  
R2  
V
ref  
SPNSNSR1  
Rsspn  
SPNSNSR2  
NOTE: For startup mode (SPNMODE = 1), S = closed  
For run mode (SPNMODE = 0), S = open  
Area within the dotted line is internal to the device  
Figure 6. Spindle-Current Control  
16  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
spindle-speed control  
The TLS2205 provides a frequency-locked-loop speed-control system. Figure 7 is an illustration of the  
spindle-speed control loop. This system operates by generating a once-around signal from either Hall or  
back-EMF state changes. This signal is then divided by either 12 (for 8-pole motor) or 18 (for 12-pole motor)  
(port B bit 11). This signal is called Fspn. Fspn is a once-around spindle-motor clock. Fspn is compared to a  
signal that is generated from the MTRCLK (Fref). Fref is generated by dividing the MTRCLK by 16, then dividing  
again by the value stored in the spindle-reference counter (port B bits 0–10). The Fref and Fspn signals are  
compared, and the time domain error is fed to the charge pump every other rotation. The charge-pump output  
is a speed error signal that is filtered by a PI filter at SPNCOMP. The output of this filter commands the spindle  
current. The spindlerotationTACH output (Fspn) or theback-EMFcommutationclock(NHphase)canbedirectly  
measured at AUXOUT. AUXIN can be used to provide an external index signal for motor commutation instead  
of using the speed feedback circuit. See Table 7 for a description of the spindle-motor operating modes.  
Spindle rotational speed is calculated from the equation below:  
f
= f  
/[(16 R) + 1] [Hz]  
MTRCLK  
spindle  
where:  
R is the value stored in port B bits 0–11 (0 < R < 2047)  
Spindle-speed regulation 1 / [(8 R) + 1] (%)  
17  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
Motor  
V
I
SPNCOMP  
Padv  
spindle  
Kt  
Js  
Speed  
Detect  
GA  
1440 Hz @ Fspn = 3600 RPM  
8-Pole Motor  
Fspn  
Fref  
Up  
/12 or /18  
Charge  
Pump  
Time-Difference  
Detector  
Down  
(/R) + 1  
0<R<2047  
MTRCLK  
/2  
/8  
SPNMODE  
SPNSW  
SPNCOMP  
Cspn2  
Count_Enable  
Count_Clear  
Cspn1  
Rspn  
Speed Up  
Slow Down  
Fspn  
Fref  
Up  
Down  
Count_Enable  
Count_Clear  
NOTE: Area within dotted line is internal to the device  
Figure 7. Spindle-Control Loop Block Diagram and Timing Waveforms  
serial port  
The TLS2205 serial port is designed to receive 16-bit data in three-wire serial format and distribute the data to  
internal data and control ports. The serial-port interface is designed to be compatible with the TexasInstruments  
TMS320C2x digital signal processor (DSP) family or standard 8- or 16-bit microprocessors. Data can be  
transmitted in either 8- or 16-bit format. The data is sent MSB first for the 16-bit word. The first four MSBs  
determine theport address. Theother 12 bitsare used for data or port control functions. The first two MSBs must  
both be 0 to select the device. The received data is routed to one of three internal 12-bit register ports. Port A  
controls the VCM DAC and gain range of eight data bits with four gain ranges. Port B is used to set the spindle  
reference counter. Port C is used for system controls.  
18  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
serial-port timing  
The TLS2205 is designed to receive data in four basic formats: TMS320C2x burst mode, TMS320C2x  
continuous mode, 8-bit microprocessor format mode, and 16-bit microprocessor format mode.  
The serial port usesthreecontrollines:SCLK (serial-port clock), SDATA (serial-port data), and SPSZ(serial-port  
select not). The SCLK line is a serial data clock with data rates up to 12 MHz; SCLK should have a 50% duty  
cycle. The SDATA line is the actual serial data input and must be synchronous with the leading edge of SCLK.  
SPSZ is the serial-port select input and is internally tied low to be synchronous with the leading edge of SCLK.  
If the TMS320C2x DSP is used in burst or continuous modes, the following bits in the ST1 register should be  
set (1) or reset (0) as indicated:  
BIT NAME  
TXM (transmit mode)  
FO (format)  
BIT #  
SET/RESET  
RESULT  
2
3
5
1
0
1
FSX is configured as an output  
16-bit mode selected  
FSM (framing sync)  
A framing sync is generated  
Refer to the TMS320C2x User’s Guide for further details.  
burst mode  
In the serial-port burst-mode operation, transfers are separated in time by periods of no serial-port activity (the  
serial port does not operate continuously). For burst-mode operation, the SPSZ line must be low on the  
negative-going edge of SCLK before data is read in; then 16 data bits can be read in. All continuing data bits  
are ignored until the SPSZ line is toggled from low to high to low. Then data is valid on the first negative-going  
clock. See Figure 8 for details.  
SCLK  
Frame Sync  
12 Data Bits  
SPSZ  
SR11  
Device  
Port  
SDATA  
ID1 ID0 PT1 PT0  
SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0  
ID1 ID0 PT1 PT0  
SR11  
NOTE: ID1 must be the first bit shifted into the register; after 15 shifts, the TLS2205 is selected and the desired port is loaded with valid data.  
Figure 8. Serial-Port Burst-Mode Operation  
19  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
continuous mode  
In the continuous-mode serial-port operation, transfers are continuous in time. In the continuous mode, the  
SPSZ line is toggled from high to low every falling edge (16 SCLK cycles). See Figure 9 for details.  
SCLK  
Frame Sync  
12 Data Bits  
SPSZ  
Device  
Port  
SDATA  
ID1 ID0 PT1 PT0 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 ID1 ID0 PT1 PT0 SR11  
Figure 9. Serial-Port Continuous-Mode Operation  
8-bit/16-bit microprocessor mode  
In 8- or 16-bit serial-port operation, transfer of data must meet the following criteria:  
1. SDATA must change on the leading edge of SCLK.  
2. SPSZ must go high after the falling edge of SCLK at the end of byte 1 of the data transmission.  
3. SPSZ must go low on the leading edge of SCLK during the first bit of the second byte of the data  
transmission.  
4. SPSZ must stay low until SCLK goes low on the last bit of the second byte of the data transmission.  
After the second byte has been transmitted, the data is decoded and sent to the proper port. If the SPSZ line  
goes high during an invalid bit time, the serial port resets and waits for a valid address. See Figure 10 for details.  
SCLK  
SPSZ Must Go High After Falling  
Edge Of Eighth Clock  
Byte 1  
SPSZ Must Go High After Falling  
Edge Of Sixteenth Clock  
Byte 2  
SPSZ  
SDATA  
ID1 ID0 PT1 PT0 SR11 SR10 SR9 SR8  
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0  
Figure 10. Serial-Port Microprocessor-Mode Operation  
NOTE: ID1 must be the first bit shifted into the register; after 15 shifts, the TLS2205 is selected and the desired port is loaded with valid data.  
20  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
port and data-bit definitions  
The TLS2205 incorporates three programmable ports that must be programmed via the serial port (SCLK,  
SDATA, and SPSZ). ID0 must be the first bit shifted into the register; after 15 shifts, the following occurs:  
1. If ID0 = 0 and ID1 = 0, the TLS2205 is selected (see Table 2) and the rest of the data is processed.  
2. PT0 and PT1 determine which port is selected (see Table 3).  
3. The 16 bits of data are serially loaded into the serial port register.  
4. The selected port is loaded with all 16 bits of data. Port A controls the VCM (see Table 4), port B controls  
the spindle motor (see Table 5), and port C controls the device functions (see Table 6).  
Table 2. Device Select  
DEVICE SELECT  
ID1  
0
ID0  
0
DESCRIPTION  
Chip selected  
The TLC2205 serial port is selected.  
0
1
Chip not selected  
1
0
1
1
Table 3. Port Selection  
PORT SELECT  
PT1  
0
PT0  
0
DESCRIPTION  
No port  
Null  
A
B
C
0
1
VCM port A  
1
0
Spindle-speed port B  
System control port C  
1
1
21  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
Table 4. Port-A Definition (VCM Control)  
BIT #  
0
NAME  
B0  
DESCRIPTION  
VCM DAC control word LSB  
VCM DAC control word  
VCM DAC control word  
VCM DAC control word  
VCM DAC control word  
VCM DAC control word  
VCM DAC control word  
VCM DAC control word MSB  
VCM gain-control LSB  
VCM gain-control MSB  
Future expansion  
1
B1  
2
B2  
3
B3  
4
B4  
5
B5  
6
B6  
7
B7  
8
GR0  
GR1  
—
9
10  
11  
12  
13  
14  
15  
—
Future expansion  
PT0  
PT1  
ID0  
ID1  
Port-select LSB  
Port-select MSB  
Device-select LSB  
Device-select MSB  
Table 5. Port-B Definition (Spindle-Speed Regulator Control Word)  
BIT #  
NAME  
R0  
DESCRIPTION  
Spindle reference-counter LSB  
Spindle reference counter  
Spindle reference counter  
Spindle reference counter  
Spindle reference counter  
Spindle reference counter  
Spindle reference counter  
Spindle reference counter  
Spindle reference counter  
Spindle reference counter  
Spindle reference-counter MSB  
COUNT  
1
0
1
R1  
2
2
R2  
4
3
R3  
8
4
R4  
16  
5
R5  
32  
6
R6  
64  
7
R7  
128  
256  
512  
1024  
8
R8  
9
R9  
10  
R10  
Spindle-motor pole switch (8 or 12)  
0 = 8 pole, 1 = 12 pole  
11  
MTR POLE  
12  
13  
14  
15  
PT0  
PT1  
ID0  
ID1  
Port-select LSB  
Port-select MSB  
Device-select LSB  
Device-select MSB  
22  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
Table 6. Port-C Definition (System Control Functions)  
BIT #  
0
NAME  
SPNENA  
START  
NHALLS  
UPOLAR  
COMM  
SPNMODE  
VCMENA  
BRAKE  
BEMF GAIN  
AUX0  
SUBSYSTEM  
SPN  
DESCRIPTION  
Spindle power-inverter enable  
Spindle-operation mode  
1
SPN  
2
SPN  
No Hall-commutation-mode select  
Spindle-inverter unipolar select  
Spindle-inverter advance (no hall mode)  
Select DAC current-control mode  
VCM power output enable  
Spindle BRAKE enable  
3
SPN  
4
SPN  
5
SPN  
6
VCM  
SPN  
7
8
SPN  
Back-EMF amplifier sense gain  
AUXOUT function select MSB  
AUXOUT function select LSB  
System power enable  
9
SYS  
10  
11  
12  
13  
14  
15  
AUX1  
SYS  
AWAKE  
PT0  
SYS  
SYS  
Port-select LSB  
PT1  
SYS  
Port-select MSB  
ID0  
SYS  
Device-select LSB  
ID1  
SYS  
Device-select MSB  
Port-C system control bit definitions  
AWAKE  
This bit controls the dc bias conditions in the device. When this bit is low, the device is in the sleep mode and  
all dc bias sources, with the exception of the voltage monitor, are disabled. All logic, with the exception of the  
serial register, is disabled, and device power dissipation is minimized. When this bit is high, the device is awake  
and power dissipation is maximum.  
AUX1  
AUX1 is the MSB of the auxiliary logic control functions (see Table 7).  
AUX0  
AUX0 is the LSB of the auxiliary logic control functions (see Table 7).  
BEMF GAIN  
This bit controls the gain of the back-EMF sense amplifier. Whenthe bit is low, the forward back-EMF gainsense  
(measured at Vphase) is one. When the bit is high, the forward sense gain is five. This function is intended to  
start the spindle motor in back-EMF mode.  
BRAKE  
BRAKE enables the high-side power inverters and disables the low-side power drivers. The brake is normally  
implemented after a retract has occurred and the head has reached the head stop.  
VCMENA  
VCMENA enables the VCM output drivers. In the disabled state, theVCM output power amplifier outputs go low.  
However, the power amplifiers still have dc bias applied and can be enabled in a short period of time.  
23  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
Port-C system control bit definitions (continued)  
SPNMODE  
SPNMODE is used to determine whether the spindle charge pump or DAC is driving the spindle-control  
amplifiers. When SPNMODE is asserted, the spindle current is controlled by the DAC.  
COMM  
The COMM bit is used to commutate the spindle driver in the start mode. For every low-to-high state change,  
the spindle inverter advances one step.  
UPOLAR  
UPOLARcontrols the spindle-motordrivemode. When thisbitislow, the TLS2205drivesthemotorinastandard  
bipolar mode. When this bit is high, CTDRV is switched low and the internal high-side drivers are disabled. An  
external pnp transistor can be switched on using CTDRV, and the device operates in the unipolar mode.  
NHALLS  
The NHALLS bit controls which commutation mode is used by the spindle-control logic. When this bit is 0, the  
TLS2205 uses the Hall sense inputs (HU, HV, HW) to directly commutate the spindle motor. When this bit is 1,  
theTLS2205 switchesintotheback-EMF commutation mode. TheHall inputs haveno meaning intheback-EMF  
commutation mode. However, the Hall logic inputs determine the motor inverter power-up initial state. The Hall  
inputs are internally tied low.  
START  
This bit controls the spindle-motor driver logic inputs and auxiliary I/O signals (see Table 7).  
SPNENA  
The SPNENA bit enables the spindle-motor drivers. The charge-pump control path (SPNCOMP) is not affected  
by this bit. When this bit is 0, the spindle-motor power drivers are disabled (motor phases U, V, W are Hi-Z) but  
not powered down. When this bit is 1, the spindle drivers are enabled.  
AUXIN/AUXOUT functional description  
Port-C controls (for spindle-motor operation in back-EMF mode)  
The spindle-motor operation modes are shown in the description section of Table 7. To fully understand this  
figure, the functional block diagram must be used in conjunction with port C.  
As an example:  
1. To start the drive (START MODE), START (bit 1) = 0, AUX1 (bit 10) = 1, and AUX0 (bit 9) = 1. As a result,  
Phaseisthe signal seen on the internal PCLK line, SCK is thesignal seenonthe internal PADVline, and  
NHphase is the signal seen at AUXOUT.  
2. Once the spindle is spinning at approximately 20% of rated speed, the drive is switched into RUN  
MODE 0 (START = 0, AUX1 = 0, and AUX0 = 0). As a result, phase is the signal seen on the internal  
PCLK line and NHphase is the signal seen on the internal PADV line and at AUXOUT.  
3. After the spindle reaches operational speed, the drive is switched into RUN MODE 3 (START = 0,  
AUX1 = 1, AUX0 = 1). As a result, AUXIN is the signal seen on the internal PCLK line, NHphase is the  
signal seen on the internal PADV line, and Fspn is the signal seen at AUXOUT.  
24  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
PRINCIPLES OF OPERATION  
Table 7. Spindle-Motor Operating Modes  
PORT C  
AUXOUT  
PCLK  
PADV  
DESCRIPTION  
START  
BIT 1  
AUX1  
BIT 10  
AUX0  
BIT 9  
MULTIPLEXER MULTIPLEXER MULTIPLEXER  
OUTPUT  
NHphase  
NHphase  
Fspn  
OUTPUT  
Phase  
AUXIN  
Phase  
AUXIN  
AUXIN  
AUXIN  
AUXIN  
Phase  
OUTPUT  
NHphase  
NHphase  
NHphase  
NHphase  
SCK  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RUN MODE0  
RUN MODE1  
RUN MODE2  
RUN MODE3  
TEST MODE0  
TEST MODE1  
TEST MODE2  
Fspn  
†
†
†
Fref  
Fref  
SCK  
Fspn  
SCK  
NHphase  
SCK  
START MODE  
†
These test modes were developed for internal chip testing.  
descriptions  
AUXOUT:  
AUXIN:  
PCLK:  
PADV:  
START:  
AUX0:  
AUX1:  
COMM:  
Fspn:  
The auxiliary logic output multiplexer  
The auxiliary logic input (can be used to commutate spindle)  
The spindle-speed feedback clock (AUXIN or phase)  
The spindle phase-advance clock (back-EMF mode)  
Spindle start mode (from port C, bit 1, 1 = enable)  
Option control (from port C, bit 9)  
Option control (from port C, bit 10)  
Commutation via serial port (from port C, bit 4)  
The once-around signal and the frequency of PCLK divided by 12 for an 8 pole motor (bit 11  
on port B set low), or divided by 18 for a 12 pole motor (bit 11 on port B set high).  
The divided output of the speed-discriminator reference frequency (MTRCLK)  
The spindle-control logic output of the spindle even states (see Figure 4, SC 0,2,4)  
No Halls phase is the back-EMF zero-crossing clock  
Fref:  
Phase:  
NHphase:  
Hphase:  
SCK:  
Halls-phase clock from external Hall sensors  
Start clock, AUXIN ORed with COMM (from port C, bit 4)  
RUN MODE 0: Speed feedback information comes from motor commutation, AUXOUT = NHphase  
RUN MODE 1: Speed feedback information comes from AUXIN, AUXOUT = NHphase  
RUN MODE 2: Speed feedback information comes from motor commutation, AUXOUT = Fspn  
RUN MODE 3: Speed feedback information comes from AUXIN, AUXOUT = Fspn  
TEST MODE 0: AUXOUT = Fref: Fref = MTRCLK/N; N = value stored in port-B reference counter  
TEST MODE 1: AUXOUT = Fref: Fref = MTRCLK/(16 N); N = same as above  
TEST MODE 2: AUXOUT = Fspin: Fspin = AUXIN/12 or 18 depending on number of motor poles (port B, bit 11)  
START MODE: Spindle commutation is controlled externally via AUXIN  
25  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
APPLICATION INFORMATION  
5 V  
5 V  
55  
46  
9
AV  
CC  
DV  
CC  
18  
C11  
C13  
C10  
VCMV  
C12  
CC  
SPNV  
CC  
R1  
37  
29  
30  
CRET  
5
UV  
CTDVR  
SPNSW  
C1  
R2  
35  
SPNCOMP  
C8  
25  
C4  
R6  
CMPI  
TLS2205  
45  
R9  
SPNSNSR2  
C9  
R10  
26  
23  
12  
17  
24  
20  
40  
34  
CMP0  
SPNSNSR1  
C5  
RSENP  
VCMA  
CTS  
W
R5  
38  
39  
47  
VCM  
L
, R  
m
m
VCMB  
V
RSENN  
RETOUT  
U
4
2
PORN  
SDATA  
SPSZ  
R3  
21  
28  
27  
RETSET  
3
VCMREF  
VIVCM  
R4  
1
SCLK  
56  
54  
53  
MTRCLK  
AUXIN  
49  
HW  
50  
51  
36  
6
HV  
AUXOUT  
C7  
R8  
HU  
33  
31  
VPHASE  
REFBUF  
CPOR  
C2  
COMDLY1  
C3  
10  
11  
R7  
V
DD  
C6  
32  
VCMGND  
COMDLY2  
13  
14  
41  
42  
SPNGND  
SPNGND  
SPNGND  
SPNGND  
SPNGND  
SPNGND  
43  
44  
48  
15  
16  
SPNGND  
SPNGND  
19  
AGND  
DGND  
Pin numbers shown are for the DL package; see Table 8 for external component values.  
Figure 11. Spindle Motor-Driver Application  
26  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
APPLICATION INFORMATION  
L
m
, R  
m
VCM  
R5  
R6  
R4  
R3  
C5  
C4  
5 V  
5 V  
1
55  
44  
AV  
CC  
DV  
CC  
C10  
C11  
C12  
13  
SPNV  
CC  
VCMV  
CC  
60  
58  
PORN  
SDATA  
SPSZ  
R1  
61  
UV  
59  
57  
SCLK  
R2  
C1  
56  
54  
53  
28  
MTRCLK  
AUXIN  
48  
TLS2205  
5-V VCM SPINDLE-MOTOR DRIVER  
HW  
HV  
HU  
51  
52  
AUXOUT  
VPHASE  
R8  
C7  
26  
33  
62  
4
COMDLY1  
REFBUF  
CPOR  
C2  
C6  
R7  
C3  
27  
42  
41  
40  
39  
47  
V
COMDLY2  
DD  
7
8
VCMGND  
VCMGND  
VCMGND  
VCMGND  
AGND  
SPNGND  
SPNGND  
SPNGND  
SPNGND  
9
10  
14  
DGND  
C8  
R10  
C13  
R9  
C9  
Pin numbers shown are for the PM package; see Table 8 for external component values.  
Figure 12. Spindle Motor-Driver Application  
27  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
APPLICATION INFORMATION  
Table 8. External Components and Approximate Values  
†
NAME  
R1  
ALIAS  
Ruv1  
DESCRIPTION  
External voltage-set resistor  
VALUE  
100 k  
270 k  
62 k  
SUBSYSTEM  
VM  
R2  
Ruv2  
VM  
External voltage-monitor set resistor  
Retract velocity-limit-set resistor  
R3  
Rrset1  
Rrset2  
Rsvcm  
Rcmp  
Rcom2  
Rcom1  
Rspn  
SPN  
SPN  
VCM  
VCM  
SPN  
SPN  
SPN  
SPN  
VM  
R4  
Retract velocity-limit set resistor  
100 k  
0.33 k  
82 k  
R5  
VCM current-control resistor  
R6  
VCM frequency-compensation resistor  
Spindle commutation-control resistor  
Spindle commutation-control resistor  
Spindle speed-regulator compensation resistor  
Spindle transconductance-control resistor  
External voltage-set capacitor  
R7  
1 M  
R8  
56 k  
R9  
470 k  
0.33  
R10  
C1  
Rsspn  
Cuv1  
1
0.02  
0.01  
F
C2  
Cpor  
VM  
Reset-time-delay capacitor  
F
F
C3  
CV  
VM  
Charge-pump storage capacitor  
DD  
C4  
Ccmp2  
Ccmp1  
Ccom2  
Ccom1  
Cspn1  
Cspn2  
VCM  
VCM  
SPN  
SPN  
SPN  
SPN  
All  
VCM frequency-compensation capacitor  
VCM frequency-compensation capacitor  
Spindle commutation-delay capacitor  
Spindle commutation-delay capacitor  
Spindle-speed-regulator frequency-compensation capacitor  
120 pF  
1500 pF  
2000 pF  
C5  
C6  
C7  
0.2  
F
F
F
F
F
F
C8  
0.68  
C9  
Spindle-speed-regulator frequency-compensation capacitor 0.048  
C10  
C11  
C12  
CV  
CV  
CV  
1
2
3
Power-supply bypass capacitor  
Power-supply bypass capacitor  
Power-supply bypass capacitor  
0.1  
47  
CC  
CC  
CC  
All  
All  
0.1  
C13  
Cret  
SPN  
Option filter of back-EMF-mode voltage capacitor  
1
F
†
SPN = spindle, VCM = voice-coil motor, VM = voltage monitor  
28  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
MECHANICAL DATA  
PLASTIC SHRINK SMALL-OUTLINE PACKAGE  
DL/R-PDSO-G**  
48-PIN SHOWN  
0.012 (0,305)  
0.025 (0,635) TYP  
0.008 (0,203)  
(see Note C)  
** PINS  
28  
48  
56  
48  
25  
DIM  
0.380  
(9,65)  
0.630  
(16,00) (18,54)  
0.730  
A MAX  
0.370  
(9,40)  
0.620  
(15,75) (18,29)  
0.720  
0.299 (7,59)  
0.291 (7,39)  
A MIN  
0.420 (10,67)  
0.395 (10,03)  
0.009 (0,229)  
0.005 (0,127)  
1
24  
A
0 –8  
0.110 (2,79)  
0.095 (2,41)  
0.040 (1,02)  
0.020 (0,51)  
0.016 (0,406)  
0.008 (0,203)  
4040048/A–07/93  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Leads are within 0.0035 (0,089) radius of true postion at maximum material condition.  
D. Body dimensions do not include mold flash, protrusion, or gate burr.  
E. Mold flash, protrusion, or gate burr shall not exceed 0.015 (0,381).  
F. Lead tips coplanar within 0.004 (0,102).  
G. Lead length measured from lead top to point 0.010 (0,254) above seating plane.  
29  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLFS040 – DECEMBER 1993  
MECHANICAL DATA  
PM/S-PQFP-G64  
PLASTIC QUAD FLAT PACKAGE  
0,26  
0,14  
0,50 TYP  
48  
33  
32  
49  
Pin # 1  
Indicator  
64  
17  
0,177  
0,147  
1
16  
7,50 SQ TYP  
10,10  
SQ  
9,90  
12,20  
SQ  
11,80  
0 –10  
1,70 MAX  
0,70  
0,30  
0,00 MIN  
4040152/A–07/93  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Maximum deviation from coplanarity is 0,08 mm.  
D. Body dimensions do not include mold flash or protrusion.  
30  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1999, Texas Instruments Incorporated  

TLS2205PM 相关器件

型号 制造商 描述 价格 文档
TLS221 TOSHIBA Visible LED, SINGLE COLOR LED, RED, 2.5 mm 获取价格
TLS226 TOSHIBA Visible LED, SINGLE COLOR LED, RED, 2 mm 获取价格
TLS226J100C1B VISHAY CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 100V, 22uF, THROUGH HOLE MOUNT, AXIAL LEADED 获取价格
TLS226K025C1A VISHAY CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 25V, 22uF, THROUGH HOLE MOUNT, AXIAL LEADED 获取价格
TLS226M025C1A VISHAY CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 25V, 22uF, THROUGH HOLE MOUNT, AXIAL LEADED 获取价格
TLS226M100C1B VISHAY CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 100V, 22uF, THROUGH HOLE MOUNT, AXIAL LEADED 获取价格
TLS227J008C1B VISHAY CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 8V, 220uF, THROUGH HOLE MOUNT, AXIAL LEADED 获取价格
TLS227K008C1B VISHAY CAPACITOR, TANTALUM, NON SOLID, POLARIZED, 8V, 220uF, THROUGH HOLE MOUNT, AXIAL LEADED 获取价格
TLS231 TOSHIBA Visible LED, SINGLE COLOR LED, RED, 4 mm 获取价格
TLS232 TOSHIBA Visible LED, SINGLE COLOR LED, RED, 4 mm 获取价格

TLS2205PM 相关文章

  • 芯片化学机械抛光（CMP）技术：原理、应用与挑战
    2025-07-04
    3
  • 台积电新布局：CoPoS 将接棒 CoWoS 成高端芯片封装主流
    2025-07-04
    9
  • 震惊！英特尔 18A 制程对外代工或终止，聚焦 14A 工艺
    2025-07-03
    39
  • 南芯科技：电源到车身控制，车规核心场景的突破秘诀
    2025-07-03
    33

    • 热门型号

  • 1N5930
  • 1N5942B
  • 1N4001
  • MBR3050CT
  • RTA02-8D
  • 4116T
  • 5KP43A/4
  • 1N5260A
  • MC79L05
  • BZX85C30
  • 9510-G
  • W2PE-54WZ-P
  • 1N6063
  • 2SA673
  • 20IMX35
    • Hi,有什么可以帮您？ 在线客服 或 微信扫码咨询
  • 概述
  • 规格参数
  • 数据手册
    • 2025 ICPDF网 联系我们和版权申明:QQ 272164286