UC1706
UC2706
UC3706
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = –55°C to +125°C for
the UC1706, –25°C to +85°C for the UC2706 and 0°C to +70°C for the UC3706; VIN = VC = 20V. TA = TJ.
PARAMETERS
Output High Sat., VC-VO
TEST CONDITIONS
MIN
TYP
MAX UNITS
IO = -50mA
2.0
V
Output Low Sat., VO
Inhibit Threshold
IO = 50mA
IO = 500mA
VREF = 0.5V
VREF = 3.5V
VREF = 0
0.4
2.5
0.6
3.7
–20
160
–20
V
V
V
V
0.4
3.3
Inhibit Input Current
Analog Threshold
Input Bias Current
Thermal Shutdown
–10
130
–10
155
A
VCM = 0 to 15V
VCM = 0
100
mV
A
°C
TYPICAL SWITCHING CHARACTERISTICS: VIN = VC = 20V, TA = 25°C. Delays measured to 10% output change.
PARAMETERS
From Inv. Input to Output:
Rise Time Delay
TEST CONDITIONS
OUTPUT CL =
UNITS
open
1.0
130
40
2.2
nF
110
20
140
60
ns
10% to 90% Rise
ns
Fall Time Delay
80
90
110
50
ns
90% to 10% Fall
25
30
ns
From N. I. Input to Output:
Rise Time Delay
120
20
130
40
140
60
ns
ns
ns
ns
ns
ns
ns
ns
10% to 90% Rise
Fall Time Delay
100
25
120
30
130
50
90% to 10% Fall
VC Cross-Conduction Current Spike Duration Output Rise
Output Fall
25
0
Inhibit Delay
Inhibit Ref. = 1V, Inhibit Inv. = 0.5 to 1.5V
Stop Non-Inv. = 0V, Stop Inv. = 0 to 0.5V
250
180
Analog Shutdown Delay
CIRCUIT DESCRIPTION
Outputs
Digital Inputs
The totem-pole outputs have been designed to minimize With both an inverting and non-inverting input available,
cross-conduction current spikes while maximizing fast, either active-high or active-low signals may be accepted.
high-current rise and fall times. Current limiting can be These are true TTL compatible inputs—the threshold is
done externally either at the outputs or at the common approximately 1.2V with no hysteresis; and external pull-
VC pin. The output diodes included have slow recovery up resistors are not required.
and should be shunted with high-speed external diodes
when driving high-frequency inductive loads.
Inhibit Circuit
Although it may have other uses, this circuit is included to
Flip/Flop
eliminate the need for deadband control when driving
relatively slow bipolar power transistors. A diode from
each inhibit input to the opposite power switch collector
will keep one output from turning-on until the other has
turned-off. The threshold is determined by the voltage on
pin 15 which can be set from 0.5 to 3.5V. When this cir-
cuit is not used, ground pin 15 and leave 1 and 16 open.
Grounding pin 7 activates the internal flip-flop to alter-
nate the two outputs. With pin 7 open, the two outputs
operate simultaneously and can be paralleled for higher
current operation. Since the flip-flop is triggered by the
digital input, an off-time of at last 200nsec must be pro-
vided to allow the flip/flop to change states. Note that the
circuit logic is configured such that the “OFF” state is de-
fined as the outputs low.
3