概述
数据手册UCC27424-EP 概述
具有使能功能的增强型产品 4A/4A 双通道栅极驱动器
UCC27424-EP 数据手册
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UCC27423-EP
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SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
DUAL 4-A HIGH-SPEED LOW-SIDE MOSFET DRIVER WITH ENABLE
Check for Samples: UCC27424-EP, UCC27423-EP
1
FEATURES
2
•
•
•
•
Industry-Standard Pinout
SUPPORTS DEFENSE, AEROSPACE
AND MEDICAL APPLICATIONS
Enable Functions for Each Driver
High Current-Drive Capability of ±4 A
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Unique Bipolar and CMOS True-Drive Output
Stage Provides High Current at MOSFET Miller
Thresholds
Available in Military (–55°C/150°C)
Temperature Range(1)
•
•
•
TTL-/CMOS-Compatible Inputs Independent of
Supply Voltage
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
20-ns Typical Rise and 15-ns Typical Fall
Times With 1.8-nF Load
Typical Propagation Delay Times of 25 ns With
Input Falling and 35 ns With Input Rising
D OR DGN PACKAGE
(TOP VIEW)
•
•
4.5-V to 15-V Supply Voltage
Dual Outputs Can Be Paralleled for Higher
Drive Current
1
2
3
4
8
7
6
5
ENBB
OUTA
VDD
ENBA
INA
•
Available in Thermally-Enhanced MSOP
PowerPAD™ Package With 4.7°C/W θjc
GND
INB
APPLICATIONS
•
•
•
•
•
Switch-Mode Power Supplies
DC/DC Converters
OUTB
Motor Controllers
Line Drivers
Class-D Switching Amplifiers
(1) Custom temperature ranges available
DESCRIPTION/ORDERING INFORMATION
The UCC27423 and UCC27424 high-speed MOSFET drivers can deliver large peak currents into capacitive
loads. Two standard logic options are offered – dual inverting and dual noninverting drivers. The UCC27424
thermally enhanced 8-pin PowerPAD™ MSOP package (DGN) drastically lowers the thermal resistance to
improve long-term reliability. The UCC27423 is offered in a standard SOIC-8 (D) package.
Using a design that inherently minimizes shoot-through current, this driver delivers 4 A of current where it is
needed most – at the Miller plateau region during the MOSFET switching transition. A unique bipolar and
MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.
The UCC27423 and UCC27424 provide enable (ENB) functions to better control the operation of the driver
applications. ENBA and ENBB are implemented on pins 1 and 8, which previously were left unused in the
industry-standard pinout. ENBA and ENBB are pulled up internally to VDD for active-high logic and can be left
open for standard operation.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2012, Texas Instruments Incorporated
UCC27424-EP
UCC27423-EP
SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
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ORDERING INFORMATION(1)
TA
PACKAGE(2)
PART NUMBER
MEDIUM
QUANTITY
MSOP-8
PowerPAD™
(DGN)(3)
UCC27424MDGNREP
UCC27423MDREP
–55°C to 125°C
Tape and Reel
2500/Reel
SOIC 8 (D)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(3) The PowerPAD package is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate, which is the ground of the device.
BLOCK DIAGRAM
8
ENBB
ENBA
1
INVERTING
7
6
OUTA
VDD
VDD
INA
2
3
NONINVERTING
INVERTING
GND
5
OUTB
INB
4
NONINVERTING
UDG−01063
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
I/O
DESCRIPTION
Enable for driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and
disabled with this pin. It is pulled up internally to VDD with a 100-kΩ resistor for active-high operation. The output
state when the device is disabled is low, regardless of the input state.
ENBA
ENBB
1
8
I
Enable for driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and
disabled with this pin. It is pulled up internally to VDD with a 100-kΩ resistor for active-high operation. The output
state when the device is disabled is low, regardless of the input state.
I
Common ground. This ground should be connected very closely to the source of the power MOSFET that the
driver is driving.
GND
INA
3
2
4
Input A. Input signal of the A driver, which has logic-compatible threshold and hysteresis. If not used, this input
should be tied to either VDD or GND. It should not be left floating.
I
I
Input B. Input signal of the A driver, which has logic-compatible threshold and hysteresis. If not used, this input
should be tied to either VDD or GND. It should not be left floating.
INB
OUTA
OUTB
VDD
7
5
6
O
O
I
Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
Supply. Supply voltage and the power input connection for this device.
2
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SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
POWER DISSIPATION RATING TABLE
POWER RATING
(mW)
θJC
(°C/W)
θJA
(°C/W)
DERATING FACTOR
ABOVE 70°C (mW/°C)
PACKAGE
SUFFIX
TA = 70°C
MSOP-8 PowerPAD(1)
SOIC 8
DGN
D
4.7
42
50 – 59
1370(2)
344 - 655(3)(4)
17.1(2)
6.25 - 11.9(3)(4)
84 - 160
(1) The PowerPAD package is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate, which is the ground of the device.
(2) 150°C operating junction temperature is used for power-rating calculations.
(3) The range of values indicates the effect of PC board. These values are intended to give the system designer an indication of the best-
and worst-case conditions. In general, the system designer should attempt to use larger traces on the PC board, where possible, in
order to spread the heat away from the device more effectively. For information on the PowerPAD package, refer to technical brief,
PowerPad™ Thermally-Enhanced Package, literature number SLMA002, and application brief, PowerPad™ Made Easy, literature
number SLMA004.
(4) 125°C operating junction temperature is used for power-rating calculation.
Table 1. Inputs/Outputs
INPUTS (VIN_L, VIN_H)
OUTPUTS
ENBA
ENBB
INA
L
INB
L
OUTA
OUTB
H
H
H
H
L
H
H
H
H
L
L
L
L
H
L
L
H
H
L
H
H
L
H
H
H
L
X
X
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1000
100
Wirebond Voiding Fail Mode
Electromigration Fail Mode
10
1
100
110
120
130
140
150
160
ContinuousTj (°C)
A. See Datasheet for Absolute Maximum and Minimum Recommended Operating Conditions.
B. Silicon Operating Life Design Goal is 10 years @ 105°C Junction Temperature (does not include package
interconnect life).
C. Enhanced Plastic Product Disclaimer Applies.
Figure 1. UCC27424MDGNREP Operating Life Derating Chart
4
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SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
Absolute Maximum Ratings(1) (2)
over operating free-air temperature range (unless otherwise noted)
MN
MAX
16
UNIT
VDD Supply voltage range
–0.3
V
DC, IOUT_DC
Pulsed (0.5 μs), IOUT_PULSED
0.2
4.5
Output current
OUTA, OUTB
A
–5 to 6 or VDD + 0.3
(whichever is larger)
VIN Input voltage range
Enable voltage
INA, INB
V
V
–0.3 to 6 or VDD + 0.3
(whichever is larger)
ENBA, ENBB
D package
650
3
mW
W
Power dissipation at TA = 25°C
DGN package
TJ
Junction operating temperature range
–55
–65
150
150
300
°C
°C
°C
Tstg Storage temperature range
Lead temperature (soldering, 10 s)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.
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Electrical Characteristics
VDD = 4.5 V to 15 V, TA = –55°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCC27423
UCC27424
UNIT
MIN TYP MAX MIN TYP MAX
Input (INA, INB)
VIN_H Logic 1 input
threshold
2
2
V
V
VIN_L Logic 0 input
threshold
1
1
Input current
Output (OUTA, OUTB)
Output current
0 V ≤ VIN ≤ VDD
–10
0
4
10 –10
0
4
10
μA
VDD = 14 V(1) (2)
A
High-level
VOH
VOH = VDD – VOUT
,
IOUT = –10 mA
330 450
330 450
mV
mV
output voltage
Low-level output
level
22
30
40
22
30
40
VOL
IOUT = 10 mA
TA = 25°C
25
14
35
45
2.5
4
25
18
35
45
2.5
4
Output
resistance high
IOUT = –10 mA,
VDD = 14 V(3)
VDD = 14 V(3)
Ω
TA = full range
TA = 25°C
1.9
2.2
1.9
1.2
2.2
Output
resistance low
IOUT = –10 mA,
Ω
TA = full range
0.95
Latch-up
500
500
mA
protection(1)
Switching Time
Rise time
tR
CLOAD = 1.8 nF(1)
CLOAD = 1.8 nF(1)
CLOAD = 1.8 nF(1)
CLOAD = 1.8 nF(1)
20
15
35
25
40
40
55
60
20
15
35
25
40
40
50
45
ns
ns
ns
ns
(OUTA, OUTB)
Fall time
tF
(OUTA, OUTB)
Delay, IN rising
(IN to OUT)
tD1
Delay, IN falling
(IN to OUT)
tD2
Enable (ENBA, ENBB)
High-level input
voltage
VIN_H
LOW-to-HIGH transition
HIGH-to-LOW transition
1.7
1.1
2.4
1.8
3.1
1.7
1.1
2.4
1.8
2.9
V
Low-level input
voltage
VIN_L
2.3
1.1
2.2
0.9
V
V
Hysteresis
0.13 0.55
.10 0.55
RENB Enable
VDD = 14 V,
ENBL = GND
75 100 160
30 60
100 150
75 100 140
30 60
100 150
kΩ
impedance
L
Propagation
tD3
CLOAD = 1.8 nF(1)
CLOAD = 1.8 nF(1)
ns
ns
delay time(4)
Propagation
tD4
delay time(4)
(1) Specified by design. Not tested in production.
(2) The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
(3) The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of the
MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
(4) See Figure 2
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Electrical Characteristics (continued)
VDD = 4.5 V to 15 V, TA = –55°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCC27423
UCC27424
UNIT
MIN TYP MAX MIN TYP MAX
Overall
INB = 0 V
900 1350
750 1100
750 1100
600 900
300 450
450 700
450 700
600 900
300 450
750 1100
750 1100
1200 1800
300 450
450 700
450 700
600 900
Static operating
current,
VDD = 15 V,
ENBA =
INA = 0 V
INB = HIGH
INB = 0 V
INA = HIGH
INA = 0 V
ENBB = 15 V
INB = HIGH
INB = 0 V
IDD
μA
Disabled,
VDD = 15 V,
ENBA =
INA = HIGH
INB = 0 V
INA = HIGH
ENBB = 0 V
INB = HIGH
(a)
(b)
5 V
90%
90%
Input
Input
10%
10%
0 V
t
t
t
t
t
F
D1
D2
F
F
t
F
16 V
90%
90%
90%
t
D1
t
Output
Output
D2
10%
10%
0 V
D. The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 2. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
5 V
ENBx
V
IN_L
V
IN_H
0 V
t
t
D4
D3
V
DD
90%
90%
t
F
t
R
OUTx
10%
0 V
E. The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET
transition through the Miller regions of operation.
Figure 3. Switching Waveform for Enable to Output
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APPLICATION INFORMATION
General Information
High-frequency power supplies often require high-speed, high-current drivers such as the UCC27423 and
UCC27424. A leading application is the need to provide a high-power buffer stage between the pulse-width
modulation (PWM) output of the control IC and the gates of the primary power MOSFET or insulated gate bipolar
transistor (IGBT) switching devices. In other cases, the driver IC is used to drive the power-device gates through
a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple
devices, which can present an extremely large load to the control circuitry.
Driver ICs are used when it is not feasible to have the primary PWM regulator IC directly drive the switching
devices, for one or more reasons. The PWM IC may not have the brute drive capability required for the intended
switching MOSFET, limiting the switching performance in the application. In other cases, there may be a desire
to minimize the effect of high-frequency switching noise by placing the high-current driver physically close to the
load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at
all. Their PWM outputs are intended to drive only the high-impedance input to drivers such as the UCC27423
and UCC27424. Finally, the control IC may be under thermal stress due to power dissipation, and an external
driver can help by moving the heat from the controller to an external package.
Input Stage
The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltages, yet, they are equally
compatible with 0 to VDD signals. The inputs of the UCC27423 and UCC27424 are designed to withstand 500-
mA reverse current without either damage to the IC or logic upset. The input stage of each driver should be
driven by a signal with a short rise or fall time. This condition is satisfied in typical power-supply applications,
where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The
input stages to the drivers function as a digital gate, and they are not intended for applications where a slow-
changing input voltage is used to generate a switching output when the logic threshold of the input section is
reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high
frequency.
Users should not attempt to shape the input signals to the driver in an effort to slow down (or delay) the signal at
the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power
device. Then, an external resistance can be added between the output of the driver and the load device, which is
generally a power MOSFET gate. The external resistor also may help remove power dissipation from the device
package, as discussed in the section on Thermal Considerations.
Output Stage
Inverting outputs of the UCC27423 are intended to drive external P-channel MOSFETs. Noninverting outputs of
the UCC27424 are intended to drive external N-channel MOSFETs.
Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The
pullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is
the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of
the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot, due
to the body diode of the external MOSFET. This means that, in many cases, external Schottky clamp diodes are
not required.
The UCC27423 family delivers the 4-A gate drive where it is most needed during the MOSFET switching
transition - at the Miller plateau region - providing efficiency gains. A unique bipolar and MOSFET hybrid output
stage in parallel also allows efficient current sourcing at low supply voltages.
Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCC27423 and UCC27424 drivers have been optimized to provide maximum drive to a power
MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage
is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the
drain-gate capacitance with current supplied or removed by the driver device. [1]
8
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Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry is
added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is
applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test, there is a transient
period where the current peaked up and then settled down to a steady-state value. The noted current
measurements are made 200 ns after the input pulse is applied, following the initial transient.
The first circuit in Figure 4 is used to verify the current sink capability when the output of the driver is clamped
around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found to
sink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V.
Figure 4. Current Sinking
The circuit shown in Figure 5 is used to test the current source capability, with the output clamped to around 5 V
with a string of Zener diodes. The UCC27423 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V.
Figure 5. Current Sourcing
It should be noted that the current sink capability is slightly stronger than the current source capability at lower
VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the
current source is a P-channel MOSFET, and the current sink has an N-channel MOSFET.
In a large majority of applications, it is advantageous that the turn-off capability of a driver is stronger than the
turn-on capability. This helps to ensure that the MOSFET is held OFF during common power-supply transients,
which may turn the device back ON.
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Parallel Outputs
The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the
OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 6.
VDD
ENBA
1
2
3
4
ENBB
OUTA
8
7
6
5
INPUT
INA
GND
INB
VDD
OUTB
C
LOAD
2.2µF
1
F
µ
CER
UDG−01067
Figure 6. Parallel Outputs
Operational Waveforms and Circuit Layout
Sink and source currents of the driver are dependent upon VDD value and the output capacitive load. The larger
the VDD value, the higher the current capability. Also, the larger the capacitive load, the higher the current and
source capabilities.
Trace resistance and inductance, including wires and cables for testing, slow down the rise and fall times of the
outputs. Thus, the driver's current capabilities are reduced.
To achieve higher current results, reduce resistance and inductance on the board as much as possible and
increase the capacitive output load value in order to swamp out the effect of the inductance values.
Figure 7. Pulse Response
In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much
overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high
di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is
advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the
opposite side of the output, so the ground should be connected to the bypass capacitors and the load with
copper trace, as wide as possible. These connections also should be made with a small enclosed loop area to
minimize the inductance.
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VDD
Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB
current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the
average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from:
IOUT = Qg × f, where f is frequency
For the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise
problems. The use of surface-mount components is highly recommended. A 0.1-μF ceramic capacitor should be
located closest to the VDD-to-ground connection. In addition, a larger capacitor (such as 1 μF) with relatively low
ESR should be connected in parallel, to help deliver the high-current peaks to the load. The parallel combination
of capacitors should present a low-impedance characteristic for the expected current levels in the driver
application.
Drive Current and Power Requirements
The UCC27423 and UCC27424 are capable of delivering 4-A of current to a MOSFET gate for a period of
several-hundred nanoseconds. High-peak current is required to turn the device ON quickly. To turn the device
OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency
of the power device. A MOSFET is used in this discussion because it is the most common type of switching
device used in high-frequency power-conversion equipment.
References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching
devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.
When a driver IC is tested with a discrete, capacitive load, it is a fairly simple matter to calculate the power that is
required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor
is given by:
1
2
2
E + CV
, where C is the load capacitor and V is the bias voltage feeding the driver
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss, given by the following:
1
2
2
P + 2 CV f
, where f is the switching frequency
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as:
P = 10 nF × (12)2 × (300 kHz) = 0.432 W
With a 12-V supply, this equates to a current of:
0.432 W
12 V
P
V
I +
+
+ 0.036 A
The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the IDD
current that is due to the IC internal consumption should be considered. With no load, the IC current draw is
0.0027 A. Under this condition, the output rise and fall times are faster than with a load. This could lead to an
almost insignificant, yet measurable, current due to cross conduction in the output stages of the driver. However,
these small current differences are buried in the high-frequency switching spikes and are beyond the
measurement capabilities of a basic laboratory setup. The measured current with a 10-nF load is reasonably
close to that which is predicted.
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The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance, plus
the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge, Qg, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence, Qg = CeffV, to provide the following equation for
power:
P = C × V2 × f = Qg × f
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage.
Enable
The UCC27423 and UCC27424 provide dual enable inputs for improved control of each driver channel operation.
The inputs incorporate logic-compatible thresholds with hysteresis. They are pulled internally up to VDD with a
100-kΩ resistor for active-high operation. When ENBA and ENBB are driven high, the drivers are enabled and,
when ENBA and ENBB are low, the drivers are disabled. The default state of the enable pin is to enable the
driver and, therefore, can be left open for standard operation. The output states when the drivers are disabled is
low, regardless of the input state. See Table 1 for a truth table of the operation using enable logic.
Enable inputs are compatible with both logic signals and slow-changing analog signals. They can be driven
directly or a power-up delay can be programmed with a capacitor between ENBA, ENBB, and AGND. ENBA and
ENBB control input A and input B, respectively.
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SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
THERMAL INFORMATION
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the IC package. In order for a power driver to be useful over a particular temperature range, the
package must allow for the efficient removal of the heat produced, while keeping the junction temperature within
rated limits.
As shown in the power-dissipation rating table, the SOIC-8 (D) package has a power rating of around 0.5 W with
TA = 70°C. This limit is imposed in conjunction with the power derating factor also given in the table. Note that
the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD, switched at 300 kHz. Thus,
only one load of this size could be driven using the D package, even if the two onboard drivers are paralleled.
The difficulties with heat removal limit the drive available in the older packages.
The MSOP-8 PowerPAD (DGN) package significantly relieves this concern by offering an effective means of
removing the heat from the semiconductor junction. As shown in reference 3, the PowerPAD packages offer a
leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC
board directly underneath the IC package, reducing the θjc down to 4.7°C/W. Data is presented in reference 3 to
show that the power dissipation can be quadrupled in the PowerPAD package configuration when compared to
the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the
heat-removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking
over that available in the D package and is shown to more than double the power capability of the D package.
Note that the PowerPAD package is not directly connected to any leads of the package. However, it is electrically
and thermally connected to the substrate, which is the ground of the device.
References
1. Power Supply Seminar SEM-1400 Topic 2: Design and Application Guide For High-Speed MOSFET Gate Drive Circuits,
by Laszlo Balogh, Texas Instruments literature number SLUP133.
2. Application note, Practical Considerations in High-Performance MOSFET, IGBT, and MCT Gate Drive Circuits, by Bill
Andreycak, Texas Instruments literature number SLUA105.
3. Technical brief, PowerPad™ Thermally-Enhanced Package, Texas Instruments literature number SLMA002.
4. Application brief, PowerPad™ Made Easy, Texas Instruments literature number SLMA004.
Table 2. Related Products
PRODUCT
DESCRIPTION
Dual 4-A low-side drivers
PACKAGES
UCC37324
MSOP-8 PowerPAD, SOIC-8, PDIP-8
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREQUENCY (VDD = 4.5 V)
FREQUENCY (VDD = 8 V)
100
100
80
80
60
10 nF
10 nF
4.7 nF
60
40
4.7 nF
40
20
2.2 nF
2.2 nF
1 nF
20
0
1 nF
470 pF
1.5 M
0
470 pF
0
500 K
1 M
1.5 M
2 M
0
500 K
1 M
2 M
f − Frequency − Hz
f − Frequency − Hz
Figure 8.
Figure 9.
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREQUENCY (VDD = 12 V)
FREQUENCY (VDD = 15 V)
150
100
50
200
150
100
50
10 nF
10 nF
4.7 nF
4.7 nF
2.2 nF
2.2 nF
1 nF
1 nF
470 pF
1.5 M
470 pF
1.5 M
0
0
0
500 K
1 M
2 M
0
500 K
1 M
2 M
f - Frequency − Hz
f − Frequency − Hz
Figure 10.
Figure 11.
14
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SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE (CLOAD = 2.2 nF)
SUPPLY VOLTAGE (CLOAD = 4.7 nF)
90
80
70
160
140
120
100
80
2 MHz
60
50
40
30
2 MHz
1 MHz
1 MHz
60
500 kHz
500 kHz
40
20
10
200 kHz
100/50 kHz
200 kHz
20
100 kHz
50/20 kHz
0
0
4
6
8
10
12
14
16
4
9
14
19
V
DD
− Supply Voltage − V
V
DD
− Supply Voltage − V
Figure 12.
Figure 13.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.60
0.55
0.50
Input = V
DD
Input = 0 V
0.45
0.40
0.35
0.30
4
6
8
10
12
14
16
V
DD
− Supply Voltage − V
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
ENABLE THRESHOLD AND HYSTERESIS
vs
TEMPERATURE
3.0
2.5
ENBL − ON
2.0
1.5
1.0
ENBL − OFF
0.5
0
ENBL − HYSTERESIS
−50
−25
0
25
50
75
100
125
T − Temperature − °C
J
Figure 16.
Figure 17.
ENABLE RESISTANCE
vs
OUTPUT BEHAVIOR
vs
SUPPLY VOLTAGE (INVERTING)
TEMPERATURE
150
140
130
IN = GND
ENBL = V
DD
120
110
100
90
V
DD
80
70
60
50
OUT
0 V
10 nF Between Output and GND
−50
−25
0
25
50
75
100
125
50 µs/div
T − Temperature − °C
J
Figure 18.
Figure 19.
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SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
TYPICAL CHARACTERISTICS (continued)
OUTPUT BEHAVIOR
OUTPUT BEHAVIOR
vs
SUPPLY VOLTAGE (INVERTING)
vs
VDD (INVERTING)
IN = GND
ENBL = V
DD
IN = V
DD
ENBL = V
DD
V
DD
V
DD
OUT
0 V
OUT
0 V
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
Figure 20.
Figure 21.
OUTPUT BEHAVIOR
vs
VDD (INVERTING)
OUTPUT BEHAVIOR
vs
VDD (NONINVERTING)
IN = V
DD
ENBL = V
DD
IN = V
DD
ENBL = V
DD
V
DD
OUT
V
DD
OUT
0 V
0 V
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT BEHAVIOR
OUTPUT BEHAVIOR
vs
vs
VDD (NONINVERTING)
VDD (NONINVERTING)
IN = V
DD
ENBL = V
DD
IN = GND
ENBL = V
DD
V
DD
V
DD
OUT
OUT
0 V
0 V
10 nF Between Output and GND
50 µs/div
10 nF Between Output and GND
50 µs/div
Figure 24.
Figure 25.
OUTPUT BEHAVIOR
vs
VDD (NONINVERTING)
INPUT THRESHOLD
vs
TEMPERATURE
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
IN = GND
ENBL = V
V
= 15 V
DD
DD
V
DD
V
DD
= 10 V
OUT
V
DD
= 4.5 V
0 V
−50
−25
0
25
50
75
100
125
10 nF Between Output and GND
T − Temperature − °C
J
50 µs/div
Figure 26.
Figure 27.
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SLUS704B –FEBRUARY 2007–REVISED APRIL 2012
REVISION HISTORY
Changes from Revision A (November, 2009) to Revision B
Page
•
•
•
•
•
•
Changed minimum supply voltage from 4-V to 4.5-V in FEATURES section ...................................................................... 1
Changed Figure 4. Current Sinking ...................................................................................................................................... 9
Changed Figure 5. Current Sourcing .................................................................................................................................... 9
Changed first paragraph of Operational Waveforms and Circuit Layout section ............................................................... 10
Changed Figure 15. RISE TIME vs SUPPLY VOLTAGE ................................................................................................... 15
Changed Figure 16. FALL TIME vs SUPPLY VOLTAGE ................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
UCC27423MDREP
UCC27424MDGNREP
V62/07624-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
MSOP-
PowerPAD
DGN
DGN
D
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-1-260C-UNLIM
CU NIPDAUAGLevel-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
V62/07624-02YE
SOIC
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27423-EP, UCC27424-EP :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2012
Catalog: UCC27423, UCC27424
•
Automotive: UCC27423-Q1, UCC27424-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27423MDREP
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
UCC27424MDGNREP
MSOP-
Power
PAD
DGN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC27423MDREP
SOIC
D
8
8
2500
2500
367.0
367.0
367.0
367.0
35.0
35.0
UCC27424MDGNREP
MSOP-PowerPAD
DGN
Pack Materials-Page 2
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UCC27424-EP 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| UCC27424-Q1 | TI | DUAL 4-A HIGH-SPEED LOW-SIDE MOSFET DRIVERS WITH ENABLE | 获取价格 |
|
| UCC27424D | TI | DUAL 4-A HIGH SPEED LOW SIDE MOSFET DRIVERS WITH ENABLE | 获取价格 |
|
| UCC27424DG4 | TI | Dual 4-A High Speed Low-Side MOSFET Drivers With Enable | 获取价格 |
|
| UCC27424DGN | TI | DUAL 4-A HIGH SPEED LOW SIDE MOSFET DRIVERS WITH ENABLE | 获取价格 |
|
| UCC27424DGNG4 | TI | Dual 4-A High Speed Low-Side MOSFET Drivers With Enable | 获取价格 |
|
| UCC27424DGNR | TI | Dual 4-A High Speed Low-Side MOSFET Drivers With Enable | 获取价格 |
|
| UCC27424DGNRG4 | TI | Dual 4-A High Speed Low-Side MOSFET Drivers With Enable | 获取价格 |
|
| UCC27424DP | TI | 暂无描述 | 获取价格 |
|
| UCC27424DR | TI | Dual 4-A High Speed Low-Side MOSFET Drivers With Enable | 获取价格 |
|
| UCC27424DRG4 | TI | Dual 4-A High Speed Low-Side MOSFET Drivers With Enable | 获取价格 |
|
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