UCC27425DP中文资料_数据手册_规格书

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

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FEATURES

DESCRIPTION

D

Industry-Standard Pin-Out

Enable Functions for Each Driver

High Current Drive Capability of 4 A

The UCC27423/4/5 family of high-speed dual MOSFET

drivers can deliver large peak currents into capacitive

loads.Three standard logic options are offered –

dual-inverting, dual-noninverting and one-inverting and

Unique BiPolar and CMOS True Drive Output

Stage Provides High Current at MOSFET

Miller Thresholds

one-noninverting driver. The thermally enhanced 8-pin

TM

PowerPAD

MSOP package (DGN) drastically lowers

the thermal resistance to improve long-term reliability.

It is also offered in the standard SOIC-8 (D) or PDIP-8

(P) packages.

D

TTL/CMOS Compatible Inputs Independent of

Supply Voltage

20-ns Typical Rise and 15-ns Typical Fall

Times with 1.8-nF Load

Using a design that inherently minimizes shoot-through

current, these drivers deliver 4-A of current where it is

needed most at the Miller plateau region during the

MOSFET switching transition. A unique BiPolar and

MOSFET hybrid output stage in parallel also allows

efficient current sourcing and sinking at low supply

voltages.

Typical Propagation Delay Times of 25 ns with

Input Falling and 35 ns with Input Rising

D

4-V to 15-V Supply Voltage

D

Dual Outputs Can Be Paralleled for Higher

Drive Current

D

Available in Thermally Enhanced MSOP

The UCC27423/4/5 provides enable (ENBL) functions

to have better control of the operation of the driver

applications. ENBA and ENBB are implemented on pins

1 and 8 which were previously left unused in the industry

standard pin-out. They are internally pulled up to Vdd for

active high logic and can be left open for standard

operation.

TM

PowerPAD

Package with 4.7°C/W θjc

Rated From –40°C to 105°C

APPLICATIONS

D

Switch Mode Power Supplies

DC/DC Converters

BLOCK DIAGRAM

Motor Controllers

Line Drivers

8

ENBB

Class D Switching Amplifiers

ENBA

1

INVERTING

7

6

OUTA

VDD

INA

2

3

NON−INVERTING

INVERTING

GND

5

OUTB

INB

4

NON−INVERTING

UDG−01063

PowerPADt is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

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1

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

ORDERING INFORMATION

PACKAGED DEVICES

OUTPUT

CONFIGURATION

TEMPERATURE RANGE

= T

MSOP-8 PowerPAD

T

A

J

SOIC-8 (D)

PDIP-8 (P)

(DGN)}

Dual inverting

−40°C to +105°C

UCC27423D

UCC27424D

UCC27423DGN

UCC27424DGN

UCC27423P

UCC27424P

Dual nonInverting

One inverting,

one noninverting

−40°C to +105°C

UCC27425D

UCC27425DGN

UCC27425P

†

‡

D (SOIC−8) and DGN (PowerPAD−MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27423DR,

UCC27424DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.

^{The PowerPAD} is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which

is the ground of the device.

D, DGN, OR P PACKAGE

(TOP VIEW)

D, DGN, OR P PACKAGE

(TOP VIEW)

D, DGN, OR P PACKAGE

(TOP VIEW)

UCC27425

UCC27424

UCC27423

ENBA

1

8

7

6

5

ENBB

OUTA

VDD

ENBA

1

8

7

6

5

ENBB

OUTA

VDD

ENBA

1

8

7

6

5

ENBB

OUTA

VDD

INA 2

GND 3

INB 4

INA 2

GND 3

INB 4

INA 2

GND 3

INB 4

OUTB

(DUAL INVERTING)

(DUAL NON−INVERTING)

(ONE INVERTING AND

ONE NON−INVERTING)

power dissipation rating table

Derating Factor Above

Power Rating (mW)

= 70°C See Note 1

70°C (mW/5C) See

PACKAGE

SUFFIX

Θjc (°C/W)

Θja (°C/W)

T

A

Note 1

SOIC-8

PDIP-8

D

P

42

49

84 – 160}

344−655 See Note 2

500

6.25 − 11.9 See Note 2

9

110

MSOP PowerPAD-8

See Note 3

DGN

4.7

50 − 59}

1370

17.1

Notes: 1. 125°C operating junction temperature is used for power rating calculations

2. The range of values indicates the effect of pc−board. These values are intended to give the system designer an indication of the

best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc−board where possible

in order to spread the heat away form the device more effectively. For information on the PowerPADt package, refer to Technical

Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made

Easy, Texas Instruments Literature No. SLMA004.

3. ^{The PowerPAD} is not directly connected to any leads of the package. However, it is electrically and thermally connected to the

substrate which is the ground of the device.

Table 1. Input/Output Table

INPUTS (VIN_L, VIN_H)

UCC27423

UCC27424

UCC27425

ENBA

ENBB

INA

L

INB

L

OUTA OUTB OUTA OUTB OUTA OUTB

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

X

L

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

†}

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

Output current (OUTA, OUTB) DC, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 16 V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 A

OUT_DC

Pulsed, (0.5 µs), I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 A

OUT_PULSED

Input voltage (INA, INB), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 V to 6 V or V +0.3 (whichever is larger)

Enable voltage (ENBA, ENBB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V or V +0.3 (whichever is larger)

IN

DD

Power dissipation at T = 25°C (DGN package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W

A

(D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW

(P package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 mW

Junction operating temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

J

Storage temperature, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature (soldering, 10 sec.), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

ELECTRICAL CHARACTERISTICS

V

= 4.5 V to 15 V, TA = −40°C to 105°C,T = T , (unless otherwise noted)

A J

DD

PARAMETER

TEST CONDITION

MIN

2

TYP

MAX

UNITS

Input (INA, INB)

VIN_H, logic 1 input threshold

VIN_L, logic 0 input threshold

Input current

V

1

0 V <= VIN <= VDD

−10

0

10

µA

Output (OUTA, OUTB)

Output current

V

DD

= 14 V,

See Note 1,

See Note 2

4

A

V

, high-level output voltage

VOH = VDD – VOUT,

IOUT = 10 mA

IOUT = −10 mA

330

22

450

40

mV

Ω

OH

, low-level output level

OL

Output resistance high

Output resistance low

Latch-up protection

T

= 25°C,

IOUT = −10 mA,

IOUT = 10 mA,

VDD = 14 V,

25

18

30

35

A

See Note 3

T

= full range,

45

2.5

4.0

Ω

A

See Note 3

T

= 25°C,

1.9

1.2

500

2.2

A

See Note 3

T

= full range

Ω

A

See Note 3

See Note 1

mA

NOTES: 1. Ensured by design. Not tested in production.

2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the

combined current from the bipolar and MOSFET transistors.

3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of

the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

ELECTRICAL CHARACTERISTICS

V

= 4.5 V to 15 V, TA = −40°C to 105°C,T = T , (unless otherwise noted)

A J

DD

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNITS

Switching Time

(1)

t_R, rise time (OUTA, OUTB)

t_F, fall time (OUTA, OUTB)

t_D1, delay, IN rising (IN to OUT)

t_D2, delay, IN falling (IN to OUT)

Enable (ENBA, ENBB)

CLOAD = 1.8 nF,

20

15

25

35

40

50

ns

V

, high-level input voltage

LO to HI transition

HI to LO transition

1.7

1.1

0.15

75

2.4

1.8

2.9

2.2

IN_H

, low-level input voltage

IN_L

V

Hysteresis

, enable impedance

0.55

100

30

0.90

140

60

R

V

DD

= 14 V,

ENBL = GND

kΩ

ENBL

(4)

(1)

t

, propagation delay time

CLOAD = 1.8 nF

D3

ns

, propagation delay time

D4

100

150

Overall

INA = 0 V,

INB = 0 V

900

750

600

300

750

1200

600

1050

450

900

300

450

600

1350

1100

900

INA = 0 V,

INB = HIGH

INB = 0 V

UCC27423

UCC27424

UCC27425

All

INA = HIGH,

INA = 0 V,

INB = HIGH

INB = 0 V

450

I

V

, static operating current,

DD

INA = 0 V,

INB = HIGH

INB = 0 V

1100

1800

900

= 15 V,

DD

INA = HIGH,

INA = 0 V,

ENBA = ENBB = 15 V

INB = HIGH

INB = 0 V

µA

INA = 0 V,

INB = HIGH

INB = 0 V

1600

700

INA = HIGH,

INA = 0 V,

INB = HIGH

INB = 0 V

1350

450

INA = 0 V,

INB = HIGH

INB = 0 V

700

I

, disabled, V

= 15 V,

DD

ENBA = ENBB = 0 V

INA = HIGH,

700

INB = HIGH

900

NOTES: 1. Ensured by design. Not production.

2. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The peak output current rating is the

combined current from the bipolar and MOSFET transistors.

3. The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of

the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

4. See Figure 2.

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

(a)

(b)

+5V

90%

INPUT

10%

0V

t

f

D1

D2

F

t

F

16V

90%

t

D1

t

OUTPUT

D2

10%

0V

Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver

5V

ENBx

0V

V

IN_L

V

IN_H

t

D3

D4

V

DD

90%

t

F

OUTx

R

10%

0V

Figure 2. Switching Waveform for Enable to Output

NOTE:

The 10% and 90% thresholds depict the dynamics of the BiPolar output devices that dominate the

power MOSFET transition through the Miller regions of operation.

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

Terminal Functions

TERMINAL

FUNCTION

NO.

NAME

I/O

1

ENBA

I

Enable input for the driver A with logic compatible threshold and hysteresis. The driver

output can be enabled and disabled with this pin. It is internally pulled up to V with

100-kΩ resistor for active high operation. The output state when the device is disabled

will be low regardless of the input state.

DD

2

3

4

5

INA

GND

INB

I

−

I

Input A. Input signal of the A driver which has logic compatible threshold and hysteresis.

If not used, this input should be tied to either VDD or GND. It should not be left floating.

Common ground. This ground should be connected very closely to the source of the

power MOSFET which the driver is driving.

Input B. Input signal of the A driver which has logic compatible threshold and hysteresis.

If not used, this input should be tied to either VDD or GND. It should not be left floating.

OUTB

O

Driver output B. The output stage is capable of providing 4-A drive current to the gate of

a power MOSFET.

6

7

VDD

I

Supply. Supply voltage and the power input connection for this device.

OUTA

O

Driver output A. The output stage is capable of providing 4-A drive current to the gate of

a power MOSFET.

8

ENBB

I

Enable input for the driver B with logic compatible threshold and hysteresis. The driver

output can be enabled and disabled with this pin. It is internally pulled up to V

100-kΩ resistor for active high operation. The output state when the device is disabled

will be low regardless of the input state.

with

DD

APPLICATION INFORMATION

General Information

High frequency power supplies often require high-speed, high-current drivers such as the UCC27423/4/5 family.

A leading application is the need to provide a high power buffer stage between the PWM output of the control

IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is

utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also

have the need to simultaneously drive multiple devices which can present an extremely large load to the control

circuitry.

Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching

devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended

switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire

to minimize the effect of high frequency switching noise by placing the high current driver physically close to

the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers

at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the

UCC27423/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external

driver can help by moving the heat from the controller to an external package.

6

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

Input Stage

The input thresholds have a 3.3-V logic sensitivity over the full range of V

voltages; yet it is equally compatible

DD

with 0 to V

signals. The inputs of UCC27423/4/5 family of drivers are designed to withstand 500-mA reverse

DD

current without either damage to the IC for logic upset. The input stage of each driver should be driven by a signal

with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input

signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages

to the drivers function as a digital gate, and they are not intended for applications where a slow changing input

voltage is used to generate a switching output when the logic threshold of the input section is reached. While

this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.

Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal

at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power

device, then an external resistance can be added between the output of the driver and the load device, which

is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the

devoce package, as discussed in the section on Thermal Considerations.

Output Stage

Inverting outputs of the UCC27423 and OUTA of the UCC27425 are intended to drive external P-channel

MOSFETs. Noninverting outputs of the UCC27424 and OUTB of the UCC27425 are intended to drive external

N-channel MOSFETs.

Each output stage is capable of supplying 4-A peak current pulses and swings to both VDD and GND. The

pullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak

output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance

is the R

of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage

DS(on)

of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot

due to the body diode of the external MOSFET. This means that in many cases, external-schottky-clamp diodes

are not required.

The UCC27423 family delivers 4-A of gate drive where it is most needed during the MOSFET switching

transition – at the Miller plateau region – providing improved efficiency gains. A unique BiPolar and MOSFET

hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

Source/Sink Capabilities During Miller Plateau

Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable

operation. The UCC27423/4/5 drivers have been optimized to provide maximum drive to a power MOSFET

during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging

between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate

[1]

capacitance with current supplied or removed by the driver device.

Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry is

added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied

at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where

the current peaked up and then settled down to a steady-state value. The noted current measurements are

made at a time of 200 ns after the input pulse is applied, after the initial transient.

The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped

around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found to

sink 4.5 A at V

= 15 V and 4.28 A at V

= 12 V.

DD

VDD

UCC27423

ENBA

1

2

3

4

ENBB

8

7

6

5

INPUT

D

SCHOTTKY

Ω

10

INA

OUTA

V

SUPPLY

5.5 V

C2

C3

+

µ

1

F

100

F

GND

INB

VDD

OUTB

V

SNS

µ

100

F

R

0.1

SNS

µ

CER

1

F

AL EL

Ω

UDG−01065

Figure 3.

8

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V

with a string of Zener diodes. The UCC27423 is found to source 4.8 A at V

= 15 V and 3.7 A at V

= 12 V.

DD

VDD

UCC27423

ENBA

1

2

3

4

ENBB

8

7

INPUT

D

SCHOTTKY

10

Ω

INA

OUTA

D

ADJ

5.5 V

C2

µ

C3

100 F

µ

+

1 F

GND

INB

VDD 6

OUTB

5

V

SNS

100 F

AL EL

µ

R

0.1

SNS

1 F

µ

Ω

CER

UDG−01066

Figure 4.

It should be noted that the current sink capability is slightly stronger than the current source capability at lower

VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the

current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.

In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the

turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients

which may turn the device back ON.

Parallel Outputs

The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the

OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in

Figure 4.

VDD

UCC27423

ENBA

1

2

3

4

ENBB

8

7

INPUT

INA

OUTA

GND

INB

VDD 6

OUTB

5

C

LOAD

2.2 F

µ

1 F

CER

µ

UDG−01067

Figure 5.

9

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

Operational Waveforms and Circuit Layout

Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load.

The input pulsewidth (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear

rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the

driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.

Figure 6.

In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much

overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high

di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout.

It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground

on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load

with copper trace as wide as possible. These connections should also be made with a small enclosed loop area

to minimize the inductance.

VDD

Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB

current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and

the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT

current can be calculated from:

I

= Qg x f, where f is frequency

OUT

For the best high-speed circuit performance, two V

bypass capacitors are recommended tp prevent noise

DD

problems. The use of surface mount components is highly recommended. A 0.1-µF ceramic capacitor should

be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-µF) with relatively

low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel

combination of capacitors should present a low impedance characteristic for the expected current levels in the

driver application.

10

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

Drive Current and Power Requirements

The UCC27423/4/5 family of drivers are capable of delivering 4-A of current to a MOSFET gate for a period of

several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the

device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating

frequency of the power device. A MOSFET is used in this discussion because it is the most common type of

switching device used in high frequency power conversion equipment.

References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching

devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.

When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that

is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor

is given by:

1

2

E + CV , where C is the load capacitor and V is the bias voltage feeding the driver.

There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a

power loss given by the following:

1

2

P + 2 CV f, where f is the switching frequency.

This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver

and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is

charged, and the other half is dissipated when the capacitor is discharged. An actual example using the

conditions of the previous gate drive waveform should help clarify this.

With V

= 12 V, C

= 10 nF, and f = 300 kHz, the power loss can be calculated as:

DD

LOAD

2

P = 10 nF x (12) x (300 kHz) = 0.432 W

With a 12-V supply, this would equate to a current of:

0.432 W

12 V

P

V

I +

+

+ 0.036 A

The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the

current that is due to the IC internal consumption should be considered. With no load the IC current draw

I

DD

is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to an

almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,

these small current differences are buried in the high frequency switching spikes, and are beyond the

measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to

that expected.

11

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

APPLICATION INFORMATION

The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining

the gate charge required to switch the device. This gate charge includes the effects of the input capacitance

plus the added charge needed to swing the drain of the device between the ON and OFF states. Most

manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the

device under specified conditions. Using the gate charge Qg, one can determine the power that must be

dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following

equation for power:

2

P + C V f + Q f

g

This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate

at a specific bias voltage.

Enable

UCC27423/4/5 provides dual Enable inputs for improved control of each driver channel operation. The inputs

incorporate logic compatible thresholds with hysteresis. They are internally pulled up to V with 100-kΩ

DD

resistor for active high operation. When ENBA and ENBB are driven high, the drivers are enabled and when

ENBA and ENBB are low, the drivers are disabled. The default state of the Enable pin is to enable the driver

and therefore can be left open for standard operation. The output states when the drivers are disabled is low

regardless of the input state. See the truth table of Table 1 for the operation using enable logic.

Enable input are compatible with both logic signals and slow changing analog signals. They can be directly

driven or a power−up delay can be programmed with a capacitor between ENBA, ENBB and AGND. ENBA and

ENBB control input A and input B respectively.

12

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SLUS545B − NOVEMBER 2002 − REVISED NOVEMBER 2004

THERMAL INFORMATION

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal

characteristics of the IC package. In order for a power driver to be useful over a particular temperature range

the package must allow for the efficient removal of the heat produced while keeping the junction temperature

within rated limits. The UCC27423/4/5 family of drivers is available in three different packages to cover a range

of application requirements.

As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power

rating of around 0.5 W with T = 70°C. This limit is imposed in conjunction with the power derating factor also

A

given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD,

switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package, even if the two

onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.

The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of

removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer

a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC

board directly underneath the IC package, reducing the Θjc down to 4.7°C/W. Data is presented in Reference 3

to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the

standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat

removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking over

that available in the D or P packages, and is shown to more than double the power capability of the D and P

packages. Note that the PowerPAD is not directly connected to any leads of the package. However, it is

electrically and thermally connected to the substrate which is the ground of the device.

References

1. Power Supply Seminar SEM−1400 Topic 2: Design And Application Guide For High Speed MOSFET

Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.

2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive

Circuits, by Bill Andreycak, Texas Instruments Literature No. SLUA105

3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002

4. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	16
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.65
高边驱动器：	NO	接口集成电路类型：	BUFFER OR INVERTER BASED MOSFET DRIVER
JESD-30 代码：	R-PDSO-G16	长度：	9.89 mm
功能数量：	2	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
标称输出峰值电流：	3 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大供电电压：	18 V
最小供电电压：	4.5 V	标称供电电压：	12 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
断开时间：	0.1 µs	接通时间：	0.1 µs
宽度：	3.9 mm	Base Number Matches：	1

型号	制造商	描述	价格	文档
UCC27425DR	TI	Dual 4-A High Speed Low-Side MOSFET Drivers With Enable	获取价格
UCC27425DRG4	TI	Dual 4-A High Speed Low-Side MOSFET Drivers With Enable	获取价格
UCC27425P	TI	DUAL 4-A HIGH SPEED LOW SIDE MOSFET DRIVERS WITH ENABLE	获取价格
UCC27425PE4	TI	Dual 4-A High Speed Low-Side MOSFET Drivers With Enable	获取价格
UCC27425QDRQ1	TI	DUAL 4-A HIGH-SPEED LOW-SIDE MOSFET DRIVERS WITH ENABLE	获取价格
UCC27444	TI	具有 -5V 输入能力的 4A 双通道低侧栅极驱动器	获取价格
UCC27444-Q1	TI	具有 -5V 输入能力的汽车类 4A 双通道低侧栅极驱动器	获取价格
UCC27444DGNR	TI	具有 -5V 输入能力的 4A 双通道低侧栅极驱动器 \| DGN \| 8 \| -40 to 125	获取价格
UCC27444DR	TI	具有 -5V 输入能力的 4A 双通道低侧栅极驱动器 \| D \| 8 \| -40 to 125	获取价格
UCC27444QDGNRQ1	TI	具有 -5V 输入能力的汽车类 4A 双通道低侧栅极驱动器 \| DGN \| 8 \| -40 to 125	获取价格

UCC27425DP

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UCC27425DP 规格参数

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