UCC1776
UCC2776
UCC3776
APPLICATION INFORMATION (cont.)
The UCC3776 specifies peak source and sink currents gate drive energy (WGD) is computed as:
for a driver output voltage of 5V. This output voltage
QG
V
WGD = 2 • 0.5 • CG • V2 =
• V = QG • V
2
1)
approximately coincides with the average gate plateau
voltage of a power MOSFET. Outside of the plateau
region the gate drive waveform is primarily limited by the
slew rate capability of the driver.Through proper analysis
of the MOSFET’s gate drive requirements and the speci-
fications for the UCC3776, an accurate model of AC per-
formance can be created. For a detailed description of
MOSFET AC gate drive requirements please see
Unitrode Application Notes U-118 and U-137. Although
the Unitrode power drivers referenced in these applica-
tion notes are bipolar devices, the information relating to
MOSFET gate drive characteristics is applicable.
Where QG is the MOSFET’s total gate charge, and V is
the gate voltage. The factor of two results from the fact
that the gate drive circuit must charge and discharge the
gate every electrical cycle. Each time the gate is charged
or discharged, the gate drive dissipates an amount of
energy equal to the energy supplied to the gate. Power
lost due to driving the gate is:
WGD
Q • V
T
2)
PLGD =
=
= QG • V • F
T
Where F is the operating frequency of the MOSFET.This
is a worst case assumption since the power loss is
shared by the output driver and the gate resistor. If a rel-
atively large value series gate resistor is used, the power
loss in the gate driver is reduced. The penalty for this is
slower switching speed, and therefore more loss in the
MOSFET. For high power MOSFETs this power loss can
be significant.
Power Supply Decoupling/Grounding
The high peak currents required to charge high capaci-
tance MOSFET gates make proper power supply decou-
pling and grounding essential. The UCC3776 provides
two power supply inputs (VDD1 and VDD2) to allow for
optimum internal circuit layout and minimum resistive
voltage drop with high peak current loads. VDD1 pro-
vides the drive current for outputs 1 and 4, while VDD2
provides drive current for outputs 2 and 3. Both of these
pins must be externally connected to the source power
supply, and the DC potential difference between these
two points should be limited to 100mV. Under no circum-
stances should an output driver be used with only one
supply input connected.
To illustrate a typical example of driver loss, consider a
MOSFET with 70nC of gate charge and a 15V gate volt-
age.The power loss at 200kHz is:
3)
PLGD = 70nC • 15V • 200kHz = 210mW
This analysis applies to one of the four drivers on the
UCC3776. Four drivers operating under the same condi-
tions results in a total power loss of 840mW. At higher
frequencies the dissipation will be proportionally greater.
This example demonstrates the need for power packag-
ing which is available on the UCC3776, and not available
on many other FET drivers.
To guarantee a low impedance current path over a wide
frequency range, each supply input should be separately
bypassed to ground with both a high value tantalum or
electrolytic capacitor in parallel with a 0.1µF ceramic
capacitor. The exact value of the tantalum or electrolytic
capacitor will depend on the charge requirements of the
MOSFET gate. For most applications a value between
1µF and 10µF should suffice. Connections for ground
leads should be kept as short as possible. The driver
chip and support electronics should be located over a
large copper ground plane if layout conditions allow it.
After device power dissipation has been estimated, prop-
er heat sinking must be provided to ensure that the
device junction temperature does not exceed the speci-
fied maximum. Refer to the packaging section of the
databook for package thermal impedance information.
Application Circuits
Power Dissipation/Thermal Considerations
Figure 1 depicts a typical gate drive application circuit.
Four independent, noninverting low side FET drivers are
shown. Although series gate drive resistors are not
required because all FET drivers have a finite peak current
capability, it is good practice to include some series resis-
tance to limit peak current and to prevent oscillations due
to parasitic inductance and capacitance.The parallel diode
and resistor allow for a faster gate turn off than turn on.
This characteristic is often desirable for bridge driver appli-
cations to prevent MOSFET cross conduction in the power
stage.
Being a CMOS device, the standby power dissipation of
the UCC3776 is quite low. For a 15V supply, the maxi-
mum quiescent current of 2mA results in a maximum
power loss of only 30mW. However, driving high frequen-
cy MOSFETs at high peak currents results in additional
power dissipation. This is because each time the MOS-
FET gate is charged or discharged, the energy transfer is
only 50% efficient. The same amount of energy that is
transferred to the gate is lost in the drive stage.
In order to determine the average output stage loss, the
5
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