概述
规格参数
数据手册
替代型号SI9978DW 概述
Configurable H-Bridge Driver 可配置的H桥驱动器 MOSFET 驱动器
SI9978DW 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Transferred |
| 零件包装代码： | SOIC | 包装说明： | SOP, |
| 针数： | 24 | Reach Compliance Code： | compliant |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.58 | Is Samacsys： | N |
| 高边驱动器： | YES | 输入特性： | SCHMITT TRIGGER |
| 接口集成电路类型： | HALF BRIDGE BASED MOSFET DRIVER | JESD-30 代码： | R-PDSO-G24 |
| JESD-609代码： | e0 | 长度： | 15.3924 mm |
| 功能数量： | 1 | 端子数量： | 24 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | OPEN-DRAIN | 标称输出峰值电流： | 0.5 A |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 240 |
| 认证状态： | Not Qualified | 座面最大高度： | 2.54 mm |
| 最大供电电压： | 17.5 V | 最小供电电压： | 14.5 V |
| 标称供电电压： | 16 V | 电源电压1-最大： | 40 V |
| 电源电压1-分钟： | 20 V | 表面贴装： | YES |
| 技术： | MOS | 温度等级： | INDUSTRIAL |
| 端子面层： | TIN LEAD | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | 30 | 宽度： | 7.49 mm |
| Base Number Matches： | 1 |
SI9978DW 数据手册
通过下载SI9978DW数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Si9978
Vishay Siliconix
Configurable H-Bridge Driver
FEATURES
D H-Bridge or Dual Half-Bridge Operation
D 20- to 40-V Supply
D Cross-Conduction Protected
D Current Limit
D ESD Protected
D Fault Output
D Static (dc) Operation
D Undervoltage Lockout
DESCRIPTION
The Si9978 is an integrated driver for an n-channel MOSFET
H-bridge. The mode control allows operation as either a full
H-bridge driver or as two independent half-bridges. The
DIR/PWM input configuration allows easy implementation of
either sign/magnitude or anti-phase PWM drive schemes for
full H-bridges. Schmitt triggers on the inputs provide logic
signal compatibility and hysteresis for increased noise
immunity. An internal low-voltage regulator allows the device
to be powered directly from a system supply of 20 to 40 volts.
All n-channel gates are driven directly from low-impedance
outputs. The addition of one external capacitor per half-bridge
allows internal circuitry to level shift both the power supply and
logic signal for the high-side n-channel gate drives. Internal
charge pumps replace leakage current lost in the high-side
driver circuits to provide “static” (dc) operation in any output
condition. Protection features include an undervoltage
lockout, cross-conduction prevention logic, and overcurrent
monitors.
The Si9978 is available in both standard and lead (Pb)-free,
24-pin wide-body SOIC (surface mount) packages, specified
to operate over the industrial (−40 to +85_C) temperature
range.
FUNCTIONAL BLOCK DIAGRAM
Bootstrap Reg.
23
24
V+
CAP
A
Charge Pump
Low-Voltage
Regulator
CAP
CAP
B
21
22
A
GT
A
1
High-Side
U.V. Lockout
V
DD
S
A
V
DD
Low-Side
U.V. Lockout
Bootstrap Reg.
Charge Pump
19
17
18
CAP
B
V
V
V
V
V
GT
B
DD
3
DIR/IN
QS/IN
A
DD
5
4
6
7
2
S
B
B
V
DD
V
DD
DD
DD
Input
Logic
PWM/EN
B
20
MODE
BRK
GB
GB
A
DD
DD
V
16
15
B
EN/EN
A
8
9
CL/FAULT
GND
B
FAULT/FAULT
A
−
11
12
One Shot
R /C
A
+
A
13
14
IL +
A
−
R /C
B
One Shot
+
B
IL +
B
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
www.vishay.com
1
Si9978
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltage on pins 2−7 with respect to ground . . . . . . . . . . . −0.3 to V + 0.3 V
Operating Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to +85_C
DD
A
Voltage on pin 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 50 V
Voltage on pins 17, 19, 21, 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to +60 V
Voltage on pins 18, 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 to 50 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150_C
Maximum Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C
J
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
RECOMMENDED OPERATING CONDITIONS
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 to 40 V
DC
R , R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 kW
A
B
SPECIFICATIONS
Limits
Test Conditions
Unless Otherwise Specified
−40 to 85_C
Typb
Mina
Maxa
V+ = 20 to 40 V
Parameter
Power
Symbol
Unit
Supply Voltage Range
Logic Voltage
V+
20
40
17.5
5
V
V
DD
14.5
16
3
Supply Current
I+
I
= 0 mA
mA
DD
Inputs (DIR, PWM, EN, QS, MODE, BRK)
High-State
V
4.0
IH
V
Low-State
V
1.0
10
IL
High-State Input Current
Low-State Input Current
I
IH
V
= V
IH DD
mA
I
IL
V
= 0 V
−100
−50
−25
IL
Outputs
Low-Side Gate Drive, High State
Low-Side Gate Drive, Low State
High-Side Gate Drive, High State
High-Side Gate Drive, Low State
Low-Side Switching, Rise Time
Low-Side Switching, Fall Time
High-Side Switching, Rise Time
High-Side Switching, Fall Time
Break-Before-Make Time
V
14
14
16
16
17.5
1
GBH
V
GBL
GTH
V
V
18
1
S
= 0 V
A, B
V
GTL
t
rL
fL
110
50
Rise Time = 1 to 10 V
Fall Time = 10 to 1 V
t
t
110
50
ns
rH
fH
C
L
= 600 pF
t
250
FAULT, CL
V
I
= 1 mA
0.4
10
V
OL
OL
FAULT, CL Leakage Current
I
FAULT, CL = V
0.2
mA
OH
DD
Protection
Low-Side Undervoltage Lockout
Low-Side Hysteresis
UVLL
0.8 V
DD
V
H
0.8
V −3.3 V
DD
V
High-Side Undervoltage Lockout
UVLH
S
A, B
= 0 V
Current Limit
Comparator Input Bias Current
I
−5
90
85
8
−0.2
5
mA
IB
T
= 25_C
100
110
115
12
A
Comparator Threshold Voltage
One Shot Pulse Width
V
mV
TH
R , R = 100 kW, C , C = 100 pF
10
A
B
A
B
t
ms
p
R , R = 100 kW, C , C = 0.001 mF
80
100
600
120
A
B
A
B
Propagation Delay
Notes:
t
pd
C
L
= 600 pF
ns
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
www.vishay.com
2
Si9978
Vishay Siliconix
TRUTH TABLEꢀH-BRIDGE MODE
DIR/
EN/ QS/
PWM/
CL/
FAULT
FAULT/
IN
A
EN
IN
B
EN
FAULT
MODE
BRK
IL +
IL +
GT
GB
L
GT
L
GB
B
Condition
A
B
B
A
A
B
A
A
B
1
1
1
1
1
0
1
1
0
1
0
0
0
L
L
L
X
X
X
H
1
1
1
1
1
1
1
L
L
Normal
Operation
1
L
H
L
1
1
1
1
0
X
X
X
1
1
0
1
0
X
X
X
0
1
X
0
L
L
L
X
X
X
X
L
L
L
L
L
H
L
1
1
1
1
1
1
X
X
X
H
L
L
L
L
L
Brake
Disable
L
Overcurrent
Undervoltage
1
X
X
X
X
X
X
X
L
L
L
L
1
0
on V
DD
TRUTH TABLEꢀHALF-BRIDGE MODE
DIR/
EN/
EN
QS/
PWM/
CL/
FAULT
FAULT/
IN
A
IN
B
EN
FAULT
MODE
BRK
IL +
IL +
GT
GB
L
GT
L
GB
L
Condition
A
B
B
A
A
B
A
A
B
B
0
0
0
0
1
0
1
1
0
0
X
X
1
0
0
0
1
1
X
X
X
X
L
L
L
L
L
L
L
L
H
L
L
L
1
1
1
1
1
1
1
1
H
L
L
Normal
Operation
X
X
L
H
L
L
L
H
Overcurrent on
A
0
0
0
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
L
X
L
L
X
L
X
L
L
X
L
L
1
Overcurrent on
B
X
X
1
0
Undervoltage
X
X
0
on V
DD
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
www.vishay.com
3
Si9978
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
SO-24
(Wide Body)
V
V+
1
2
24
23
22
21
20
19
18
17
16
15
14
13
DD
EN/EN
CAP
A
A
DIR/IN
S
A
3
A
PWM/EN
GT
A
4
B
ORDERING INFORMATION
QS/IN
GB
A
5
B
Lead (Pb)-Free Temperature
MODE
BRK
CAP
B
6
Part Number
Range
Part Number
Package
S
B
7
Si9978DW
CL/FAULT
B
GT
B
8
SOIC-24
(Wide Body)
−40 to 85_C
Si9978DW-T1
Si9978DW-T1—E3
GB
B
FAULT/FAULT
A
9
NC
GND
10
11
12
R /C
A
IL +
B
A
B
R /C
B
IL +
A
Top View
PIN DESCRIPTION
Pin 1: VDD
As the INA pin, it is the input that controls the “A” half-bridge.
When at logic “1”, the high-side MOSFET is turned on, and
when at logic “0”, the low-side MOSFET is turned on.
VDD is an internally generated voltage. It is connected to this
pin to allow connection of a decoupling capacitor. A minimum
of 1 mF is recommended.
Pin 4: PWM/ENB
With the mode pin at logic “1”, this pin is the PWM input. It
controls the switching of the active diagonal pair. A logic “1”
turns the active MOSFETs on, while a logic “0” turns it off. The
QS input determines whether the bottom or both bottom and
top MOSFETs are switched. When implementing an
anti-phase PWM control, the PWM input is connected to a logic
“1”. When the mode pin is at logic “0”, this pin becomes the
ENABLE pin for half-bridge B.
Pin 2: EN/ENA
The EN input allows normal operation when at logic “1”, and
turns all gate drive outputs off when at logic “0”. When the
mode pin is at logic “1”, EN controls the entire H-bridge. When
the mode pin is at logic “0”, this pin becomes the ENABLE pin
for half-bridge A.
Pin 5: QS/INB
Pin 3: DIR/INA
With the mode pin at logic “1”, this input determines whether
the bottom MOSFETs of the H-bridge or both bottom and top
MOSFETs switch in response to the PWM signal. A logic “1” on
this input enables only the bottom MOSFETs. This is the
default condition as this pin is pulled up internally. When this
pin is pulled to ground, both the bottom and top MOSFETs are
enabled.
The function of this pin is determined by the MODE pin. When
the MODE pin is at logic “1”, it is the DIR pin, and when MODE
is at logic “0”, it is the INA pin.
As the DIR input, it is the direction control for the H-bridge, and
determines which diagonal pair of power MOSFETs is active.
A logic “1” turns on GTA and enables GBB, while a logic “0”
turns on GTB and enables GBA. When implementing an
anti-phase PWM control, the DIR input serves as the PWM
input.
This input controls the B half-bridge when the MODE pin is at
logic “0”. When at logic “1”, the high-side MOSFET is turned on,
and when at logic “0”, the low-side MOSFET is turned on.
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
www.vishay.com
4
Si9978
Vishay Siliconix
PIN DESCRIPTION (CONT’D)
Pin 6: MODE
one-shot is triggered when the current limit comparator detects
an overcurrent condition.
This input determines whether the Si9978 functions as an
H-bridge or as two independent half-bridges. When the MODE
pin is at logic “1”, the Si9978 functions as an H-bridge, and
when MODE is at logic “0”, it functions as two independent
half-bridges.
Pin 13: ILA+ and Pin 14, ILB+
These are the overcurrent sense inputs. Internally, they are
connected to the noninverting inputs of the current limit
comparators. Externally they are connected to the source(s) of
the low-side MOSFET(s) and the current sense resistor.
Pin 7: BRK
When this input and MODE are at logic “1”, both bottom gate
drives are switched high, turning on the bottom MOSFETs.
When this input is at logic “0”, the Si9978 operates normally.
Pin 15: GND
The GND pin is the ground return for V+ and the ground
reference for the logic. Also, this is the ground reference input
for the current limit comparators and is connected to the
ground side of the internal 100-mV references. This pin should
be connected directly to the ground side of the current sensing
resistors.
Pin 8: CL/FAULTB
This is an open drain output which is active low. When the
MODE pin is at logic “1”, this pin functions as CL and indicates
that the H-bridge is in current limit. It stays low for the duration
of the current limit one-shot. With the MODE pin at logic “0”, it
serves as the FAULT output for half-bridge B to indicate when
an undervoltage or overcurrent condition is detected. When
indicating an overcurrent condition, the output stays low for the
duration of the current limit one-shot. The FAULT output resets
automatically when the condition clears.
Pin 16: GBB and Pin 20, GBA
These pins drive the gates of the low-side power MOSFETs.
Pin 17: GTB and Pin 21, GTA
These pins drive the gates of the high-side power MOSFETs.
Pin 9: FAULT/FAULTA
Pin 18: SB and Pin 22, SA
This is an open drain output which is switched low when an
undervoltage or overcurrent condition is detected. When
indicating an overcurrent condition, the output stays low for the
duration of the current limit one-shot. When the MODE pin is
at logic “1”, this pin is the H-bridge FAULT output. With the
MODE pin at logic “0”, it serves as the FAULT output for
half-bridge A. The FAULT output resets automatically when the
condition clears.
These are the source connections of the high-side power
MOSFETs, the drain of the external low-side power MOSFET,
the negative terminal of the bootstrap capacitor, and the output
for each half-bridge.
Pin 19: CAPB and Pin 23, CAPA
These are the connections for the positive terminals of the
bootstrap capacitors CBAand CBB. A 0.01-mF capacitor can be
used for most applications.
Pin 10: NC
No internal connection.
Pin 24: V+
Pin 11: RA/CA
This is the only external power supply required for the Si9978,
and must be the same supply used to power the H-bridge it is
driving. The Si9978 powers the low-voltage logic, low-side
gate driver, and bootstrap/ charge pump circuits from
self-contained voltage regulators which require only a
bootstrap capacitor on the CAP pins.
The timing resistor and capacitor for the current limit one-shot
are connected to this pin. The values of the resistor and
capacitor determine the off time set by the one-shot. The
one-shot is triggered when the current limit comparator detects
an overcurrent condition.
Pin 12: RB/CB
No voltage sensing circuitry monitors V+ directly; however, the
low-voltage, internally generated supply and the bootstrap
voltage (which are derived from V+) are directly protected by
undervoltage monitors.
The timing resistor and capacitor for the current limit one-shot
are connected to this pin. The values of the resistor and
capacitor determine the off time set by the one-shot. The
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
www.vishay.com
5
Si9978
Vishay Siliconix
APPLICATION CIRCUIT
LITTLE FOOTr
V+
Q
3
Q
1
C
2
C
3
C
1
C
6
C
7
U1
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
V
V+
CAP
DD
C
C
4
A
OUT
B
OUT
EN
DIR
EN/EN
A
A
DIR/IN
S
A
A
PWM
QS
PWM/EN
GT
A
B
QS/IN
GB
A
B
5
MODE
BRK
CAP
B
BRK
CL
S
GT
GB
B
B
B
Q
Q
4
2
CL/F
B
FAULT
F/F
A
10
11
12
NC
R /C
GND
IL +
R
4
R
3
A
A
B
B
R /C
IL +
A
B
V
CC
R
2
Si9978
100 kW
R
1
C
8
GND
FIGURE 1. Basic H-Bridge Circuit
Document Number: 70011
S-40804—Rev. E, 26-Apr-04
www.vishay.com
6
SI9978DW 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| SI9978DW-T1 | VISHAY | Configurable H-Bridge Driver | 功能相似 |
|
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