概述
数据手册Si8902AEDB 概述
N-Channel 24 V (D-S) MOSFET
Si8902AEDB 数据手册
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N-Channel 24 V (D-S) MOSFET, Common Drain
FEATURES
• TrenchFET® power MOSFET
MICRO FOOT® 2.4 x 1.6
S1
2
G1
• Small 2.4 mm x 1.6 mm outline
• Thin 0.6 mm max. height
3
S2
4
8902AE
xxx
• Typical ESD protection 5000 V (HBM)
1
S1
• Material categorization: for definitions of
compliance please see www.vishay.com/doc?99912
6
G2
5
S2
1
Backside View
Bump Side View
S
1
APPLICATIONS
Marking code: 8902AE
• Battery protection switch
• Bi-directional switch
PRODUCT SUMMARY
G
G
1
2
VS1S2 (V)
24
R
R
RS1S2 max. () at VGS = 4.5 V
RS1S2 max. () at VGS = 3.7 V
RS1S2 max. () at VGS = 2.5 V
RS1S2 max. () at VGS = 1.8 V
0.0280
0.0290
0.0310
0.0370
5.9
I
S1S2 (A) a
Configuration
Common drain
N-Channel
S
2
ORDERING INFORMATION
Package
MICRO FOOT
Lead (Pb)-free and halogen-free
Si8902AEDB-T2-E1
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
24
UNIT
Source 1-to-source 2 voltage
Gate-source voltage
VS1S2
V
VGS
12
TC = 25 °C
11 b
TC = 85 °C
TA = 25 °C
TA = 85 °C
7.9 b
5.9 a
4.3 a
40
5.7 b
3 b
Continuous source 1-to-source 2 current
IS1S2
(TJ = 150 °C)
A
Pulsed source 1-to-source 2 current (t = 100 μs)
Maximum power dissipation
ISM
TC = 25 °C
TC = 85 °C
PD
W
TA = 25 °C
TA = 85 °C
1.7 a
0.9 a
-55 to +150
260
Operating junction and storage temperature range
Soldering recommendations (peak temperature) c
TJ, Tstg
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYPICAL
MAXIMUM
UNIT
Maximum junction-to-ambient a, d
Maximum junction-to-case b
t 5 s
RthJA
RthJC
60
18
75
22
°C/W
Steady state
Notes
a. Surface mounted on 1" x 1" FR4 board with full copper, t = 5 s
b. The case is defined as the top surface of the package
c. Refer to IPC/JEDEC® (J-STD-020), no manual or hand soldering
d. Maximum under steady state conditions is 120 °C/W
S15-1171-Rev. B, 25-May-15
Document Number: 62948
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8902AEDB
Vishay Siliconix
www.vishay.com
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Source 1-to-source 2 breakdown voltage
VS1S2
VGS(th)/TJ
VGS(th)
VGS = 0 V, IS = 250 μA
IS = 250 μA
24
-
-
3
-
-
-
-
-
-
-
-
V
mV/°C
V
VGS(th) temperature coefficient
Gate-source threshold voltage
VSS = VGS, IS = 250 μA
0.4
-
0.9
0.2
10
1
VSS = 0 V, VGS
SS = 0 V, VGS
=
=
4.5 V
12 V
μA
Gate-source leakage
IGSS
V
-
mA
VSS = 24 V, VGS = 0 V
VSS = 24 V, VGS = 0 V, TJ = 85 °C
VSS 5 V, VGS = 4.5 V
-
Zero gate voltage source current
On-state source current a
IS1S2
IS(on)
μA
A
-
10
-
5
-
VGS = 4.5 V, ISS = 1 A
0.0215 0.0280
0.0222 0.0290
0.0240 0.0310
0.0260 0.0370
VGS = 3.7 V, ISS = 1 A
VGS = 2.5 V, ISS = 1 A
VGS = 1.8 V, ISS = 1 A
-
Source1-to-source 2 on-state resistance a
RS1S2
-
-
Forward transconductance a
Dynamic b
gfs
VSS = 10 V, ISS = 1 A
-
15
-
S
Gate resistance
Turn-on delay time
Rise time
Rg
td(on)
tr
f = 1 MHz
-
-
-
-
-
-
-
-
-
5300
1.5
3.5
25
-
3
7
VSS = 12.5 V, RL = 12.5
ISS 1 A, VGEN = 4.5 V, Rg = 1
Turn-off delay time
Fall time
td(off)
tf
td(on)
tr
td(off)
tf
50
25
1.4
2.6
70
25
12
μs
Turn-on delay time
Rise time
0.7
1.3
35
VSS = 12.5 V, RL = 12.5
ISS 1 A, VGEN = 10 V, Rg = 1
Turn-off delay time
Fall time
12
Notes
a. Pulse test; pulse width 300 μs, duty cycle 2 %
b. Guaranteed by design, not subject to production testing
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S15-1171-Rev. B, 25-May-15
Document Number: 62948
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8902AEDB
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
10-2
1.5
10-3
10-4
10-5
10-6
10-7
10-8
10-9
1.2
0.9
0.6
0.3
0
TJ = 150 °C
TJ = 25 °C
TJ = 25 °C
0
3
6
9
12
3.0
30
0
3
6
9
12
VGS - Gate-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Gate Current vs. Gate-Source Voltage
Gate Current vs. Gate-Source Voltage
40
V
10
8
GS = 5 V thru 3 V
VGS = 2.5 V
30
20
10
0
6
V
GS = 1.5 V
TC = 25 °C
4
TC = 125 °C
2
VGS = 1 V
2.5
TC = - 55 °C
1.0 1.2
0
0.0
0.5
1.0
1.5
2.0
0.0
0.2
0.4
0.6
0.8
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.05
0.04
0.03
0.02
0.01
0
VGS = 4.5 V, 3.7 V, 2.5 V, 1.8V; ID = 1A
VGS = 1.8 V
VGS = 3.7 V
VGS = 2.5 V
VGS = 4.5 V
- 50 - 25
0
25
50
75
100 125 150
0
5
10
15
20
25
ID - Drain Current (A)
TJ - Junction Temperature (°C)
On-Resistance vs. Drain Current
On-Resistance vs. Junction Temperature
S15-1171-Rev. B, 25-May-15
Document Number: 62948
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For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8902AEDB
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.06
0.05
0.04
0.03
0.02
0.01
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
ID = 1 A
TJ = 125 °C
ID = 250 μA
TJ = 25 °C
- 50 - 25
0
25
50
75
100 125 150
0
1
2
3
4
5
TJ - Temperature (°C)
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Threshold Voltage
100
10
1
30
25
20
15
10
5
TJ = 150 °C
TJ = 25 °C
0.1
0
0.0
0.3
0.6
0.9
1.2
1.5
0.01
0.1
1
10
100
1000
VSD - Source-to-Drain Voltage (V)
Time (s)
Source-Drain Diode Forward Voltage
Single Pulse Power (Junction-to-Ambient)
S15-1171-Rev. B, 25-May-15
Document Number: 62948
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For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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Si8902AEDB
Vishay Siliconix
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
Limited by RDS(on)
*
I
DM Limited
100 µs
I
D(on)Limited
10
1 ms
10 ms
1
0.1
100 ms
10 s
1 s
DC
TA = 25 °C
BVDSS Limited
0.01
0.1
1
10
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
100
Safe Operating Area, Junction-to-Ambient
6
5
4
3
2
1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TA - Case Temperature (°C)
TA - Ambient Temperature (°C)
Current Derating a
Power Derating
Notes
When mounted on 1" x 1" FR4 with full copper
•
a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-ambient thermal resistance, and is more useful in settling the
upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below
the package limit
S15-1171-Rev. B, 25-May-15
Document Number: 62948
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8902AEDB
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
P
DM
0.05
t
1
t
2
t
t
1
2
0.02
1. Duty Cycle, D =
2.
P
ER
U
NIT
B
ASE = RTHJA
(t)
= 120°C/W
3. TJM - T = P
Z
DM thJA
A
Single Pulse
0.01
4. Surface Mounted
-4
-3
10
-2
10
-1
10
10
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient (On 1" x 1" FR4 board with maximum copper)
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
10
-3
10
-2
-1
10
10
Square Wave Pulse Duration (s)
1
Normalized Thermal Transient Impedance, Junction-to-Case (on 1" x 1" FR4 board with minimum copper)
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62948.
S15-1171-Rev. B, 25-May-15
Document Number: 62948
6
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
MICRO FOOT®: 6-Bumps
(1.6 mm x 2.4 mm, 0.8 mm Pitch, 0.290 mm Bump Height)
E
6x Ø b1
S
e
e
Mark on backside of die
S2
S1
S1
G1
G2
XXXXXX
XXX
S2
b1
Note 5
6x 0.30 to 0.31
(Note 3)
Solder mask-0.4
Note 2
b
K
b Diameter bump
(Note 1)
e
e
Recommended land pattern
Notes
1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
MILLIMETERS
NOM.
0.575
INCHES
NOM.
DIM.
MIN.
0.550
0.260
0.290
0.370
MAX.
0.600
0.290
0.310
0.410
MIN.
MAX.
0.0236
0.0114
0.0122
0.0161
A
A1
A2
b
0.0217
0.0102
0.0114
0.0146
0.0226
0.0108
0.0118
0.0153
0.0118
0.0314
0.0150
0.0614
0.0929
0.0072
0.275
0.300
0.390
b1
e
0.300
0.800
s
0.360
1.520
2.320
0.155
0.380
0.400
1.600
2.400
0.215
0.0141
0.0598
0.0913
0.0061
0.0157
0.0630
0.0945
0.0084
D
1.560
E
2.360
K
0.185
Note
•
Use millimeters as the primary measurement.
ECN: T15-0143-Rev. A, 27-Apr-15
DWG: 6036
Revision: 27-Apr-15
Document Number: 69350
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN824
Vishay Siliconix
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
Si8900EDB
3
2
1
0.18 ~ 0.25
A
B
1.08
0.5
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
0.285
0.5
0.285
1.58
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
Document Number: 71990
06-Jan-03
www.vishay.com
1
AN824
Vishay Siliconix
TABLE 1
Main Parameters of Solder Bumps in MICRO FOOT Designs
MICRO FOOT CSP
Bump Material
Bump Pitch*
Bump Diameter*
Bump Height*
MICRO FOOT CSP MOSFET
0.8
0.5
0.5
0.37-0.41
0.18-0.25
0.32-0.34
0.26-0.29
0.14-0.19
0.21-0.24
Eutectic Solder:
63Sm/37Pb
MICRO FOOT CSP Analog Switch
MICRO FOOT UCSP Analog Switch
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
BOARD LAYOUT GUIDELINES
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
TABLE 2
MICRO FOOT Reliability Results
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Test Condition C: −65_ to 150_C
Test condition B: −40_ to 125_C
121_C @ 15PSI 100% Humidity Test
>500 Cycles
>1000 Cycles
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
Copper pads should be finished with an organic solderability
preservative
(OSP)
coating.
For
electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
Solder Mask
Copper
Solder Mask
Copper
FIGURE 3. SMD
FIGURE 4. NSMD
Document Number: 71990
06-Jan-03
www.vishay.com
2
AN824
Vishay Siliconix
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
Solder Mask
Opening
Stencil
Aperture
Pitch Copper Pad
0.33 " 0.01 mm
Thermal Profile
0.80 mm 0.30 " 0.01 mm 0.41 " 0.01 mm
0.50 mm 0.17 " 0.01 mm 0.27 " 0.01 mm
in ciircle aperture
250
0.30 " 0.01 mm
in square aperture
200
150
100
50
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
Stencil Design
IIncoming Tape and Reel Inspection
Solder Paste Printing
Chip Placement
0
0
100
200
300
400
Time (Seconds
FIGURE 6. Reflow Profile
Reflow
Solder Joint Inspection
Pack and Ship
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
FIGURE 5. SMT Assembly Process Flow
1. Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
2. Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3. Resurface the pads using a temperature-controlled
soldering iron.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
4. Apply gel flux to the pad.
5. Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
6. Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Document Number: 71990
06-Jan-03
www.vishay.com
3
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Revision: 01-Jan-2023
Document Number: 91000
1
Si8902AEDB 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SI8902AEDB-T2-E1 | VISHAY | Small Signal Field-Effect Transistor, | 获取价格 |
|
| Si8902B-A01-GS | SILICON | ISOLATED MONITORING ADC | 获取价格 |
|
| SI8902B-A01-GSR | SILICON | ADC, Successive Approximation, 10-Bit, 1 Func, 3 Channel, Serial Access, CMOS, PDSO16, SOIC-16 | 获取价格 |
|
| Si8902D-A01-GS | SILICON | ISOLATED MONITORING ADC | 获取价格 |
|
| SI8902D-A01-GSR | SILICON | ADC, Successive Approximation, 10-Bit, 1 Func, 3 Channel, Serial Access, CMOS, PDSO16, SOIC-16 | 获取价格 |
|
| SI8902EDB | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
| SI8902EDB-T1 | VISHAY | TRANSISTOR 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MICRO FOOT, CSP-6, FET General Purpose Small Signal | 获取价格 |
|
| SI8902EDB-T2-E1 | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
| SI8902EDB_06 | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
| SI8902EDB_08 | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
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