29F400B-90PC

更新时间:2024-12-03 18:28:26
品牌:WINBOND
描述:Flash, 512KX8, 90ns, PDSO44, PLASTIC, SOP-44

29F400B-90PC 概述

Flash, 512KX8, 90ns, PDSO44, PLASTIC, SOP-44 闪存

29F400B-90PC 规格参数

生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, SOP-44针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.47
Is Samacsys:N最长访问时间:90 ns
备用内存宽度:16启动块:BOTTOM
JESD-30 代码:R-PDSO-G44长度:28.2 mm
内存密度:4194304 bit内存集成电路类型:FLASH
内存宽度:8功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
编程电压:5 V认证状态:Not Qualified
座面最大高度:2.8 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
类型:NOR TYPE宽度:13.3 mm
最长写入周期时间 (tWC):0.09 msBase Number Matches:1

29F400B-90PC 数据手册

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BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
4MEGABIT (512K x 8/ 256K x 16)  
5VOLT SECTOR ERASE CMOS FLASH MEMORY  
GENERAL DESCRIPTION  
The BM29F400 is an 4 Megabit, 5.0 volt-only CMOS Flash memory device organized as a 512  
Kbytes of 8-bits each, or 256 Kbytes of 16 bits each. The device is offered in standard 44-pin SOP  
and 48-pin TSOP packages. It is designed to be programmed and erased in-system with a 5.0 volt  
power-supply and can also be reprogrammed in standard EPROM programmers.  
With access times of 90 nS, 120 nS, and 150 nS, the BM29F400 has separate chip enable CE, write  
enable WE , and output enable OE controls. BMI's memory devices reliably store memory data even  
after 100,000 program and erase cycles.  
The BM29F400 is entirely pin and command set compatible with the JEDEC standard for 4 Megabit  
Flash memory devices. Commands are written to the command register using standard  
microprocessor write timings. Register contents serve as input to an internal state-machine which  
controls the erase and programming circuitry. Write cycles also internally latch addresses and data  
needed for the programming and erase operations.  
The BM29F400 is programmed by executing the program command sequence. This will start the  
internal byte/word programming algorithm that automatically times the program pulse width and also  
verifies the proper cell margin. Erase is accomplished by executing either the sector erase or chip  
erase command sequence. This will start the internal erasing algorithm that automatically times the  
erase pulse width and also verifies the proper cell margin. No preprogramming is required prior to  
execution of the internal erase algorithm. Sectors of the BM29F400 Flash memory array are  
electrically erased via Fowler-Nordheim tunneling. Bytes/words are programmed one byte/word at a  
time using a hot electron injection mechanism.  
The BM29F400 features a sector erase architecture. The device memory array is divided into one 16  
Kbytes, two 8 Kbytes, one 32 Kbytes, and seven 64 Kbytes. Sectors can be erased individually or in  
groups without affecting the data in other sectors. Multiple sector erase and full chip erase capabilities  
add flexibility to altering the data in the device. To protect this data from accidental program and  
erase, the device also has a sector protect function. This function hardware write protects the  
selected sector(s). The sector protect and sector unprotect features can be enabled in a PROM  
programmer.  
For read, program and erase operation, the BM29F400 needs a single 5.0 volt power-supply.  
Internally generated and well regulated voltages are provided for the program and erase operation. A  
low Vcc detector inhibits write operations on loss of power. End of program or erase is detected by the  
Ready/Busy status pin, Data Polling of DQ7, or by the Toggle Bit I feature on DQ6. Once the program  
or erase cycle has been successfully completed, the device internally resets to the Read mode.  
The BM29F400 also has a hardware RESET pin. Driving the RESET pin low during execution of an  
Internal Programming or Erase command will terminate the operation and reset the device to the  
Read mode. The RESET pin may be tied to the system reset circuitry, so that the system will have  
access to boot code upon completion of system reset, even if the Flash device is in the process of an  
Internal Programming or Erase operation. If the device is reset using the RESET pin during an  
Internal Programming or Erase operation, data in the address locations on which the internal state  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 1 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
machine is operating will be erroneous. Thus, these address locations will need rewriting after the  
device is reset.  
FEATURES  
· 5.0 V +/- 10% Program and Erase  
- Minimizes system-level power requirements  
High performance  
· RESET  
- Hardware pin resets the internal state  
machine to the read mode  
- 90 nS access time  
· Internal Erase Algorithms  
- Automatically erases a sector, any  
combination of sectors, or the entire  
chip  
· Compatible with JEDEC-standard Commands  
- Uses software commands, pinouts, and  
packages following industry standards for  
single power supply Flash memory  
· Internal Programming Algorithms  
- Automatically programs and verifies data at a  
specified address  
· Typically 100,000 Program/Erase Cycles  
· Sector Erase Architecture  
- One 16 Kbytes, two 8 Kbytes, one 32 Kbytes,  
and seven 64 Kbytes  
· Low Power Consumption  
- 20 mA typical active read current for Byte  
Mode  
- Any combination of sectors can be erased  
concurrently; also supports full chip erase  
- 28 mA typical active read current for Word  
Mode  
- 30 mA typical write/erase current  
· Erase Suspend/Resume  
- Suspend a sector erase operation to allow a  
data read in a sector not being erased within  
the same device  
· Sector Protection  
- Hardware method disables any combination  
of sectors from a program or erase operation  
· Ready/Busy  
- RY/BY output pin for detection of  
programming or erase cycle completion  
· Boot Code Sector Architecture  
-90  
-120  
120  
120  
-150  
150  
150  
FAMILY PART NO.  
Maximum Access Time (nS)  
90  
90  
CE (E) Access time (nS)  
OE (G) Access time (nS)  
35  
50  
60  
*This speed is available with Vcc = 5V +/- 5% variation  
- 2 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
PIN CONFIGURATIONS  
1
NC  
RY/BY  
A17  
A7  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
/RESET  
/WE  
2
3
A8  
4
A9  
5
A6  
A10  
6
A5  
A11  
7
A4  
A12  
8
A3  
A13  
9
A2  
A14  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
A1  
A15  
A0  
A16  
/CE  
Vss  
/OE  
DQ0  
DQ8  
DQ1  
DQ9  
DQ2  
DQ10  
DQ3  
DQ11  
/BYTE  
Vss  
DQ15/A-1  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
Vcc  
PSOP  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A16  
1
A15  
A14  
A13  
A12  
A11  
A10  
A9  
/BYTE  
Vss  
2
3
DQ15/A-1  
DQ7  
DQ14  
DQ6  
DQ13  
DQ5  
DQ12  
DQ4  
Vcc  
4
5
6
7
8
A8  
9
NC  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
/WE  
/RESET  
NC  
DQ11  
DQ3  
DQ10  
DQ2  
DQ9  
DQ1  
DQ8  
DQ0  
/OE  
NC  
RY/BY  
NC  
A17  
A7  
A6  
A5  
A4  
Vss  
A3  
/CE  
A2  
A0  
A1  
Standard TSOP  
PIN DESCRIPTION  
A0 - A17  
Address Inputs  
DQ0 - DQ14  
DQ15 /A-1  
Data Input/Output  
Data Input/Output, Address Mux.  
Chip Enable  
Output Enable  
Write Enable  
CE  
OE  
WE  
Vss  
Device Ground  
Hardware RESET Pin, Active Low  
Ready/Busy Status Output  
Device Power Supply  
Selects 8-bit or 16-bit Mode  
Not Internally Connected  
RESET  
RY/BY  
Vcc  
BYTE  
NC  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 3 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
BLOCK DIAGRAM  
DQ0-DQ15  
Vcc  
Vss  
RY/BY  
Buffer  
Erase Boltage  
Generator  
Input/Output  
Buffers  
State  
Control  
/WE  
/BYTE  
/RESET  
Command  
Register  
PGM Voltage  
Generator  
STB  
Chip Enable  
/CE  
/OE  
Output Enable  
Data Latch  
Logic  
STB  
Y-Gating  
Y-Decodor  
Cell Matrix  
Vcc Detector  
Address  
Latch  
Timer  
X-Decoder  
A0-A16  
A-1  
BUS OPERATION  
(1)  
Table 1. Bus Operations (BYTE = VIH)  
OPERATION  
A0  
A1  
A6  
A9  
DQ0-DQ15  
CE  
WE  
RESET  
OE  
(2)  
Electronic ID Manufacturer  
L
L
H
H
H
X
X
H
L
L
L
L
VID  
VID  
A9  
X
Code  
Code  
DOUT  
H
H
H
H
L
(2)  
Electronic ID Device  
L
L
H
X
L
L
L
X
L
H
A0  
X
L
L
(3)  
Read  
L
A1  
X
A6  
X
Standby  
X
X
H
H
L
High Z  
High Z  
Hardware Reset  
Output Disable  
Write  
X
X
X
X
X
X
X
X
High Z  
DIN(4)  
X
A0  
L
A1  
H
X
A6  
L
A9  
VID  
X
H
H
VID  
(2)  
Verify Sector Protect  
H
X
Code  
X
Temporary Sector Unprotect  
X
X
X
Notes:  
1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels.  
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.  
3. WE can be VIL if is VIL, OE at VIH initiates the write operations.  
CE  
4. Refer to Table 6 for valid D during a write operation.  
IN  
- 4 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
(1)  
Table 2. Bus Operations (BYTE = VIL)  
OPERATION  
A0  
A1  
A6  
A9  
DQ0-DQ7  
DQ8-DQ15  
WE  
CE  
OE  
RESET  
(2)  
Electronic ID Manufacturer  
L
L
H
L
L
L
VID  
VID  
A9  
X
Code  
Code  
DOUT  
High Z  
High Z  
High Z  
High Z  
High Z  
High Z  
High Z  
High Z  
High Z  
H
H
H
H
L
(2)  
Electronic ID Device  
L
L
H
X
L
L
L
X
L
H
H
X
X
H
L
H
A0  
X
L
L
(3)  
Read  
L
A1  
X
A6  
X
Standby  
X
X
H
H
L
High Z  
High Z  
Hardware Reset  
Output Disable  
Write  
X
X
X
X
X
X
X
X
High Z  
DIN(4)  
H
H
H
VID  
A0  
L
A1  
H
X
A6  
L
A9  
VID  
X
(2)  
Verify Sector Protect  
H
X
Code  
X
Temporary Sector Unprotect  
X
X
X
Notes:  
1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels.  
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 6.  
3. WE can be VIL if is VIL, OE at VIH initiates the write operations.  
CE  
4. Refer to Table 6 for valid D during a write operation.  
IN  
Table 3. Sector Protection Verify Electronic ID Codes  
TYPE  
Manufacturer Code  
29F400T  
A17-A12  
A6  
VIL  
VIL  
A1  
VIL  
VIL  
A0  
VIL  
VIH  
Code (Hex)  
ADH  
X
X
Byte  
Word  
Byte  
23H  
29F400  
22,23H  
ABH  
29F400B  
X
VIL  
VIL  
VIH  
VIL  
Word  
22 ABH  
01H(1)  
Sector Protection  
Sector Address  
VIL  
VIH  
Note: Outputs 01H at protected sector addresses, and outputs 00H at unprotected addresses.  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 5 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Table 4. Sector Address Tables (BM29F400T)  
A17  
0
A16  
0
A15  
0
A14  
X
A13  
X
A12  
X
(x8) Address Range  
00000H-0FFFFH  
10000H-1FFFFH  
20000H-2FFFFH  
30000H-3FFFFH  
40000H-4FFFFH  
50000H-5FFFFH  
60000H-6FFFFH  
70000H-77FFFH  
78000H-79FFFH  
7A000H-7BFFFH  
7C000H-7FFFFH  
(x16) Address Range  
00000H-07FFFH  
08000H-0FFFFH  
10000H-17FFFH  
18000H-1FFFFH  
20000H-27FFFH  
28000H-2FFFFH  
30000H-37FFFH  
38000H-3BFFFH  
3C000H-3CFFFH  
3D000H-3DFFFH  
3E000H-3FFFFH  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
0
0
1
X
X
X
0
1
0
X
X
X
0
1
1
X
X
X
1
0
0
X
X
X
1
0
1
X
X
X
1
1
0
X
X
X
1
1
1
0
X
X
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
X
Notes:  
1. The address range is A17:A-1 if in byte mode ( BYTE = VIL).  
2. The address range is A17:A0, if in word mode ( BYTE = VIH).  
Table 5. Sector Address Tables (BM29F400B)  
A17  
0
A16  
0
A15  
0
A14  
0
A13  
0
A12  
X
(x8) Address Range  
00000H-03FFFH  
04000H-05FFFH  
06000H-07FFFH  
08000H-0FFFFH  
10000H-1FFFFH  
20000H-2FFFFH  
30000H-3FFFFH  
40000H-4FFFFH  
50000H-5FFFFH  
60000H-6FFFFH  
70000H-7FFFFH  
x16) Address Range  
00000H-01FFFH  
02000H-02FFFH  
03000H-03FFFH  
04000H-07FFFH  
08000H-0FFFFH  
10000H-17FFFH  
18000H-1FFFFH  
20000H-27FFFH  
28000H-2FFFFH  
30000H-37FFFH  
38000H-3FFFFH  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
SA10  
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
X
X
0
0
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
Notes:  
1. The address range is A17:A-1 if in byte mode ( BYTE = VIL).  
2. The address range is A17:A0, if in word mode ( BYTE = VIH).  
- 6 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Electronic ID Mode  
The Electronic ID mode allows the reading out of a binary code from the device and will identify its  
manufacturer and device type. This mode is intended for use by programming equipment for the  
purpose of automatically matching the device to be programmed with its corresponding programming  
algorithm. This mode is functional over the entire temperature range of the device.  
To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin  
A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from  
VIL to VIH. All addresses are don't cares except A0, A1, and A6 (see Table 3).  
Manufacturer and device codes may also be read via the command register; for instance, when the  
BM29F400 is erased or programmed in a system without access to high voltage on the A9 pin. The  
command sequence is illustrated in Table 6 (refer to Electronic ID Command section).  
Byte 0 (A0 = VIL) represents the manufacturer's code (Bright Microelectronics = ADH) and byte 1 (A0  
= VIH) the device identifier code (BM29F400T = 23H and BM29F400B = ABH for 8-bit mode;  
BM29F400T = 2223H and BM29F400B = 22ABH for 16-bit mode). These two byte words are given in  
Table 3. To read the proper device codes when executing the Electronic ID, all identifiers for  
manufacturer and device will exhibit odd parity with the MSB (DQ7) defined as the parity bit. A1 must  
be VIL (see Table 3).  
Read Mode  
The BM29F400 has three control functions which must be satisfied in order to obtain data at the  
outputs. CE is the power control and should be used for device selection. OE is the output control  
and should be used to gate data to the output pins if a device is selected. As shown in Table 1, WE  
should be held at VIH, except in Write mode and Enable Sector Protect mode.  
Address access time (t ) is equal to the delay from stable addresses to valid output data. Chip  
ACC  
enable access time (t ) is the delay from stable addresses and stable CE to valid data at the output  
CE  
pins. Output enable access time is the delay from the falling edge of OE to valid data at the output  
pins (assuming the addresses have been stable for at least t -t time).  
ACC OE  
Standby Mode and Hardware RESET Standby Mode  
The BM29F400 has two methods for implementing standby mode. The first method requires use of  
both the CE pin and the RESET pin. The second method only requires use of the RESET pin.  
When using both pins, a CMOS standby mode is achieved when both CE and RESET are held at  
Vcc ±0.5V. In this condition, the current consumed is typically less than 100 uA. A TTL standby mode  
is achieved with both CE and RESET held at V . In this condition, the typical current required is  
IH  
reduced to 200 uA. The device can be read with standard access time (t ) from either of these two  
CE  
standby modes.  
When using the RESET pin only, a CMOS standby mode is achieved with RESET held at Vss  
±0.5V. In this condition, the current consumed is typically less than 100 uA. A TTL standby mode is  
achieved with RESET held at VIL. In this condition, the typical current required is reduced to 1mA.  
Once the RESET pin is taken high, the device requires 500 nS of wake-up time before outputs are  
valid for a read access.  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 7 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
If the device is deselected during programming or erase, the device will draw active current until the  
programming or erase operation is completed. In the standby mode the outputs are in a high  
impedance state, independent of the OE input.  
Output Disable Mode  
With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the  
output pins to be in a high impedance state. It is shown in Table 1 that CE = VIL and WE = VIH for  
Output Disable. This is to differentiate Output Disable mode from Write mode and to prevent  
inadvertent writes during Output Disable.  
Program and Erase Modes  
Device programming and erase are accomplished via the command register. Contents of the register  
serve as inputs to the internal state machine. Outputs of the state machine dictate the function of the  
device.  
The command register itself does not occupy any addressable memory locations. The register is a  
latch used to store the commands along with the addresses and data information needed to execute  
the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is  
at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later, while data  
is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write  
timings are used. Refer to AC Characteristics for Programming/Erase and their respective Timing  
Waveforms for specific timing parameters.  
Enable Sector Protect and Verify Sector Protect Modes  
The BM29F400 has a hardware Sector Protect mode that disables both Programming and Erase  
operation to the protected sector(s). There are total of 11 sectors in this device. The sector protect  
feature is enabled using the programming equipment at the user's site. The device is shipped from  
the BMI factory with all sectors unprotected.  
To verify programming of the protection circuitry, the programming equipment must force VID on the  
address pin A9 with CE and OE at VIL and WE at VIH. As shown in Table 2, scanning the sector  
addresses while (A6, A1 and A0) = (0, 1, 0) will produce a 01H code at the device output pins for a  
protected sector. In the Verify Sector Protect mode, the device will read 00H for an unprotected  
sector. In this mode, the lower order addresses, except for A0, A1 and A6, are don't care. Address  
locations with A1 = VIL are reserved for Electronic ID manufacturer and device codes. It is also  
possible to determine if a sector is protected in-system by writing the Electronic ID command  
(described in the Electronic ID command section below.)  
Temporary Sector Unprotect Mode  
The BM29F400 has a Temporary Sector Unprotect feature that allows the protect feature to be  
temporarily suspended to change data in a protected sector in-system. The Temporary Sector  
Unprotect mode is activated by setting the RESET pin to VID (11.5V - 12.5V).  
In this mode, protected sectors can be programmed or erased by selecting the sector addresses.  
Once VID is removed from the RESET pin, all previously protected sectors will be protected. Refer to  
the Temporary Sector Unprotect algorithm and timing waveforms.  
- 8 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Read RESET Command  
The read or RESET operation is initiated by writing the Read/Reset command sequence in to the  
command register. Microprocessor read cycles retrieve the data from the memory. The device  
remains enable for reads until the command register contents are changed.  
The device will automatically power-up in the Read/Reset mode. In this case, a command sequence  
is not needed to read the memory data. This default power-up to Read mode ensures that no spurious  
changes of the data can take place during the power transitions. Refer to the AC Characteristics for  
Read-Only Operation and the respective Timing Waveforms for the specific timing parameters.  
Electronic ID Command  
The BM29F400 contains an Electronic ID command to supplement the traditional PROM  
programming method described in the Electronic ID Mode section. The operation is initiated by writing  
the Electronic ID command sequence into the command register. Following command write, a read  
cycle from address XX00H retrieves manufacturer code of ADH. A read cycle from address XX01H  
returns the device code (BM29F400T = 23H and BM29F400B = ABH for 8-bit mode; BM29F400T =  
2223H and BM29F400B = 22ABH for 16-bit mode) (see Table 3). All manufacturer and device codes  
exhibit odd parity with the MSB (DQ7) defined as the parity bit.  
The Electronic ID command can also be used to identify protected sectors. After writing the Electronic  
ID command sequence, the CPU can scan the sector addresses (see Table 4 and Table 5) while (A6,  
A1, A0) = (0, 1, 0). Protected sectors will return 01H on the data outputs and unprotected sectors will  
return 00H. To terminate the operation, it is necessary to write the Read/Reset command sequence  
into the command register.  
Byte/Word Programming Command  
The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus  
cycle operation (see Table 6). There are two "unlock" write cycles. These are followed by the program  
set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE ,  
whichever happens later, and program data (PD) is latched on the rising edge of CE or WE ,  
whichever happens first. The rising edge of CE or WE , whichever happens first, begins  
programming using the Embedded Program Algorithm.  
Upon executing the algorithm, the system is not required to provide further controls or timings. The  
device will automatically provide adequate internally generated program pulses and verify the  
programmed cell margin.  
The automatic programming operation is completed when the data on DQ7 (also used as Data  
Polling) is equivalent to the data written to this bit at which time the device returns to the read mode  
and addresses are no longer latched (see Table 7, Write Operation Status Flags). Therefore, the  
device requires that a valid address to the device be supplied by the system at this particular instance  
of time for Data Polling operations. Data Polling must be performed at the memory location which is  
being programmed.  
Any commands written to the chip during the Internal Program Algorithm will be ignored. If a  
hardware RESET occurs during the programming operation, the data at that particular location will  
be corrupted.  
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Byte/Word programming is allowed in any sequence, and across sector boundaries. However,  
remember that a data "0" cannot be programmed to a data "1". Only erase operations can convert a  
logical "0" to a logical "1". Attempting to program data from "0" to "1" may cause the device to exceed  
time limits, or even worse, result in an apparent success according to the Data Polling algorithm. In  
the later case, however, a subsequent read of this bit will show that the data is still a logical "0".  
Figure 1 illustrates the Byte/Word Programming Algorithm using typical command strings and bus  
operations.  
The device will ignore any commands written to the chip during execution of the internal Byte/Word  
Programming Algorithm. If a hardware RESET occurs during the Byte/Word Programming operation,  
the data at that particular address location will be corrupted.  
Chip Erase Command  
Chip erase is a six bus cycle operation (see Table 6). The chip erase begins on the rising edge of the  
last WE pulse in the command sequence.  
Upon executing the Chip Erase command sequence, the device's internal state machine executes an  
internal erase algorithm. The system is not required to provide further controls or timings. The device  
will automatically provide adequate internally generated erase pulses and verify chip erase within the  
proper cell margins. During chip erase, all sectors of the device are erased except protected sectors.  
During Chip Erase, data bit DQ7 shows a logical "0". This operation is known as Data Polling. The  
erase operation is completed when the data on DQ7 is a logical "1" (see Write Operation Status  
section). Upon completion of the Chip Erase operation, the device returns to read mode. At this time,  
the address pins are no longer latched. Note that Data Polling must be performed at a sector address  
within any of the sectors being erased and not a protected sector to ensure that DQ7 returns a logical  
"1" upon completion of the Chip Erase operation.  
Figure 2 illustrates the Chip Erase Algorithm using typical command strings and bus operations.  
The device will ignore any commands written to the chip during execution of the internal Chip Erase  
algorithm. If a hardware RESET occurs during the Chip Erase operation, the data in the device will  
be corrupted.  
Sector Erase Command  
Sector erase is a six bus cycle operation (see Table 6). The sector address (any address location  
within the desired sector) is latched on the falling edge of WE , while the command data is latched on  
the rising edge of WE . An internal device timer will initiate the Sector Erase operation 100 mS ±20%  
(80 uS to 120 uS) from the rising edge of the WE pulse for the last Sector Erase command entered  
on the device.  
Upon executing the Sector Erase command sequence, the device's internal state machine executes  
an internal erase algorithm. The system is not required to provide further controls or timings. The  
device automatically provides adequate internally generated erase pulses and verify sector erase  
within the proper cell margins. Protected sectors of the device will not be erased, even if they are  
selected with the Sector Erase command.  
Multiple sectors can be erased simultaneously by writing the sixth bus cycle command of the Sector  
Erase command for each sector to be erased. The time between initiation of the next Sector Erase  
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Preliminary BM29F400T/BM29F400B  
command must be less than 80 mS to guarantee acceptance of the command by the internal state  
machine. The time-out window can be monitored via the write operation status pin DQ3 (refer to the  
Write Operation Status section for Sector Erase Timer operation). It is recommended that CPU  
interrupts be disabled during this time to ensure that the subsequent Sector Erase commands can be  
initiated within the 100 uS window. The interrupts can be re-enabled after the last Sector Erase  
command is written. As mentioned above, an internal device timer will initiate the Sector Erase  
operation 100 uS ±20% (80 uS to 120 uS) from the rising edge of the last WE pulse. Sector Erase  
Timer Write Operation Status pin (DQ3) can be used to monitor time out window. If another falling  
edge of the WE occurs within the 100 mS time-out window, the internal device timer is reset.  
Loading the sector erase buffer may be done in any sequence and with any number of sectors.  
Any command other than Sector Erase or Erase Suspend during this period and afterwards will  
RESET the device to read mode, ignoring the previous command string. Resetting the device with a  
hardware RESET after it has begun execution of a Sector Erase operation will result in the data in  
the operated sectors being undefined and may be unrecoverable. In this case, restart the Sector  
Erase operation on those sectors and attempt to allow them to complete the Erase operation.  
Command Definitions  
Device operations are selected by writing specific address and data sequences in to the Command  
register. Writing incorrect addresses and data values or writing them in the improper sequence will  
RESET the device to Read mode. Table 5 defines the valid register command sequences. Either of  
the two Read/Reset commands will RESET the device (when applicable).  
During Sector Erase operation, data bit DQ7 shows a logical "0". This operation is known as Data  
Polling. Sector Erase operation is complete when data on DQ7 is a logical "1" (see Write Operation  
Status section) at which time the device returns to read mode. At this time, the address pins are no  
longer latched. Note that Data Polling must be performed at a sector address within any of the  
sectors being erased and not a protected sector to ensure that DQ7 returns a logical "1" upon  
completion of the Sector Erase operation.  
Figure 2 illustrates the Sector Erase Algorithm using typical command strings and bus operations.  
During execution of the Sector Erase command, only the Erase Suspend and Erase Resume  
commands are allowed. All other commands will RESET the device to read mode.  
Note: Do not attempt to write an invalid command sequence during the sector erase operation. Doing so will terminate the sector  
erase operation and the device will /RESET to the read mode.  
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Preliminary BM29F400T/BM29F400B  
Table 6. Command Definitions  
Command  
Sequence  
Bus Write  
Cycles  
First Bus Write  
Cycle  
Second Bus  
Write Cycle  
Third Bus Write  
Cycle  
Fourth Bus Write  
Cycle  
Fifth Bus Write  
Cycle  
Sixth Bus Write  
Cycle  
Reset/Read  
Reset/Read  
Required  
addr  
XXXXH  
5555H  
AAAAH  
5555H  
Data  
F0H  
AAH  
addr  
Data  
addr  
Data  
addr  
Data  
addr  
Data  
addr  
Data  
1
4
Reset  
Word  
Byte  
2AAAH  
5555H  
2AAAH  
55H  
55H  
5555H  
AAAAH  
5555H  
F0H  
RA  
RD  
/Read  
Word  
4
AAH  
90H  
01H(7)  
2223H  
(T Device ID)  
22ABH  
Electronic  
ID  
(B Device ID)  
Byte  
AAAAH  
5555H  
AAAAH  
23H  
(T Device ID)  
ABH  
(B Device ID)  
Program  
Word  
Byte  
4
6
6
1
1
5555H  
AAAAH  
5555H  
AAH  
AAH  
AAH  
B0H  
30H  
2AAAH  
5555H  
2AAAH  
5555H  
2AAAH  
5555H  
55H  
55H  
55H  
5555H  
AAAAH  
5555H  
AAAAH  
5555H  
AAAAH  
A0H  
80H  
80H  
PA  
PD  
Chip  
Erase  
Word  
Byte  
5555H  
AAAAH  
5555H  
AAH  
AAH  
2AAAH  
5555H  
2AAAH  
5555H  
55H  
5555H  
AAAAH  
SA  
10H  
AAAAH  
5555H  
Sector  
Erase  
Word  
Byte  
55H  
30H  
AAAAH  
XXXXH  
AAAAH  
Erase  
Word  
Byte  
Suspend  
Erase  
Word  
Byte  
XXXXH  
Resume  
Notes:  
1. Bus operations are defined in Tables 1 and 2.  
2. For a Command Sequence, address bit A15 = X = Don't Care for all address commands except for Program Address (PA) and  
Sector Address (SA).  
3. RA = Address of the memory location to be read.  
RD = Data read from location RA during read operation.  
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.  
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE .  
SA = Address of sector to be erased. (See Table 4 for top boot and Table 5 for bottom boot.)  
4. The Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in  
progress.  
5. Reading from, and programming to, non-erasing sectors is allowed in the Erase Suspend mode.  
6. The System should generate the following address patterns:  
Word Mode: 5555H or 2AAAH to addresses A0 - A14.  
Byte Mode: AAAAH or 5555H to addresses A-1 - A14.  
7. Address 00H returns the manufacturer's ID code (Bright Microelectronics - ADH), address 01H returns the device ID code.  
Erase Suspend/Erase Resume Commands  
The Erase Suspend command allows the user to interrupt a Sector Erase operation and read data  
from or to a sector that is not being erased. The Erase Suspend command is applicable only during  
Sector Erase operation, including, but not limited to, sector erase time-out period after any Sector  
Erase commands (30H) have been initiated.  
Writing the Erase Suspend command during the time-out will result in immediate termination of the  
time-out period. Any subsequent writes of the Sector Erase command will be taken as the Erase  
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Resume command (30H). Note that any other commands during the time-out will RESET the device  
to the Read mode. The address pins are "don't cares" when writing the Erase Suspend or Erase  
Resume commands.  
When the Erase Suspend command is written during a Sector Erase operation, the chip will take  
between 1 uS and 230 uS to suspend the erase operation and go into Erase Suspended mode. During  
this time, the system can monitor the Data Polling or Toggle Bit write operation status flags to  
determine when the device has entered erase suspend mode (see Write Operation Status section.)  
The system must use an address of an erasing sector to monitor Data Polling or Toggle Bit to  
determine if the Sector Erase operation has been suspended.  
In Erase Suspend mode, the system can read data from any sector that is not being erased. A read  
from a sector being erased will result in write operation status data. After the system writes the Erase  
Suspend command and waits until the Toggle Bit stops toggling, data reads from the device may then  
be performed (see Write Operation Status section). Any further writes of the Erase Suspend  
command at this time will be ignored.  
To resume operation of Sector Erase, the Erase Resume command (30H) should be written. Any  
further writes of the Erase Resume command at this point will be ignored. Another Erase Suspend  
command can be written after the chip has resumed Sector Erase operation.  
DQ7  
Data Polling  
The BM29F400 device features Data Polling as a method to indicate to the host the status of the  
Byte/Word Programming, Chip Erase, and Sector Erase operations. When the Byte/Word  
Programming operation is in progress, an attempt to read the device will produce the compliment of  
the data last written to DQ7. Upon completion of the Byte/Word Programming operation, an attempt  
to read the device will produce the true data last written to DQ7. When the Chip Erase or Sector  
Erase operation is in progress, an attempt to read the device will produce a logical "0" at the DQ7  
output. Upon completion of the Chip Erase or Sector Erase operation, an attempt to read the device  
will produce a logical "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in Figure  
3.  
For Chip Erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write  
pulse sequence. For Sector Erase, the Data Polling is valid after the last rising edge of the sector  
erase WE pulse. For both Chip Erase and Sector Erase, Data Polling must be performed at sector  
address within any of the sectors being erased and not a protected sector. Otherwise, the Data  
Polling status may not be valid. Once the Internal Algorithm operation is close to being completed,  
the BM29F400 data pins (DQ7) may change asynchronously while the output enable (OE ) is  
asserted low. This means that the device is driving status information on DQ7 at one instant and valid  
data at the next instant of time. Depending on when the system samples the DQ7 output, it may read  
status or valid data. Even if the device has completed the Internal Algorithm operation and DQ7 has a  
valid data, data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will be read on the  
successive read attempts.  
The Data Polling feature is only active during the Byte/Word Programming operation, Chip Erase  
operation, Sector Erase Operation, or Sector Erase time-out window (see Table 7).  
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DQ6  
Toggle Bit  
The BM29F400 also features the "Toggle Bit" as a method to indicate to the host system the status of  
the Internal Programming and Erase Algorithms (see Figure 4 for Toggle Bit (DQ6) flowchart.  
During an Internal Programming or Erase Algorithm cycle, successive attempts to read (OE toggling)  
data from the device will result in DQ6 toggling between one and zero. Once Internal Programming or  
Erase operation is completed, DQ6 will stop toggling and valid data will be read on the next  
successive attempts. During BYTE Programming, Toggle Bit is valid after the rising edge of the  
fourth WE pulse in the four write pulse sequence. For Chip Erase, Toggle Bit is valid after the rising  
edge of the sixth WE pulse in the six write pulse sequence. For Sector Erase, Toggle Bit is valid after  
the last rising edge of the sector erase WE pulse. Toggle Bit is also active during sector erase time-  
out window.  
In Byte/Word Programming, if the sector being written to is protected, the Toggle Bit will toggle for  
about 300 nS and then stop toggling without the data having changed. In Chip Erase or Sector Erase,  
the device will erase all the selected sectors except for the ones that are protected. If all selected  
sectors are protected, the chip will toggle the Toggle Bit for about 300ns and then drop back into read  
mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 Toggle Bit I to  
toggle.  
DQ5  
Exceeded Timing Limits  
DQ5 will indicate if the Byte/Word Programming, Chip Erase, or Sector Erase time has exceeded the  
specified limits (internal pulse count) of the device. Under these conditions DQ5 will produce a logical  
"1". This is a failure condition which indicates that the program or erase cycle was not successfully  
completed. Data Polling is the only operating function of the device under this condition. The OE  
and WE pins will control the output disable functions as described in Table 1.  
If this failure condition occurs during Sector Erase operation, it specifies that particular sector is bad  
and it may not be reused. However, other sectors are still functional and may continue to be used for  
the program or erase operation. The device must be RESET to the Read mode to use other sectors  
of the device. Write the Read/Reset command sequence to the device, and then execute the  
Byte/Word Programming or Sector Erase command sequence. This allows the system to continue to  
use the other active sectors in the device.  
If this failure condition occurs during Chip Erase operation, it specifies that the entire chip is bad or  
combination of sectors are bad. In so, the chip should not be reused.  
If this failure condition occurs during Byte/Word Programming operation, it indicates the entire sector  
containing that BYTE is bad and this sector may not be reused (other sectors are still functional and  
can be reused.)  
The DQ5 failure condition may also appear if a user tries to program a non blank location without  
erasing. In this case, the device may exceed time limits and not complete the Internal Algorithm  
operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling.  
Once the device has exceeded timing limits, the DQ5 bit will indicate a "1".  
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DQ3  
Sector Erase Timer  
After the completion of the initial Sector Erase command sequence, the sector erase time-out window  
will begin. DQ3 will remain low until the time-out window is closed. Data Polling and Toggle Bit are  
valid after the initial Sector Erase command sequence.  
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command,  
DQ3 maybe used to determine if the Sector Erase time-out window is still open. If DQ3 is a logical  
"1", the internally controlled erase cycle has begun. Attempts to write subsequent command to the  
device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle  
Bit. If DQ3 is a logical "0", the device will accept additional Sector Erase commands. To ensure the  
command has been accepted, the system software should check the status of DQ3 prior to and  
following each subsequent Sector Erase command. If DQ3 were high on the second status check, the  
command may not have been accepted. Refer to Table 7: Write Operation Status Flags.  
Write Operations Status  
Table 7. Write Operation Status Flags(1)  
Status  
DQ7  
/DQ7  
0
DQ6  
Toggle  
Toggle  
Data  
DQ5  
0
DQ3  
N/A  
1
In  
Byte/Word Programming Operation  
Chip or Sector Erase Operation  
Progress  
0
Erase Suspend Mode  
Data  
Data  
Data  
(Non-Erase Suspended Sector)  
Exceeded  
Byte/Word Programming Operation  
/DQ7  
0
Toggle  
Toggle  
1
1
0
1
Time Limits  
Chip or Sector Erase Operation  
Notes: DQ0, DQ1, DQ4 are reserve pins for future use.  
RY/BY  
Ready/Busy Status  
The BM29F400 provides a RY/BY open-drain output pin as a way to indicate to the host system that  
an Internal Programming or Erase operation is either in progress or has been completed. If the RY/BY  
output is low, the device is busy with either a Programming or Erase operation. If the RY/BY output is  
high, the device is ready to accept a Read, Programming, or Erase command. When the RY/BY pin  
is low, the device will not accept any additional Programming or Erase commands with the exception  
of the Erase Suspend command. If the BM29F400 is placed in an Erase Suspend mode, the RY/BY  
output will be high.  
During a programming operation, the RY/BY pin is driven low after the rising edge of the fourth WE  
pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE  
pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to the timing  
waveforms for the RY/BY status pin for further clarification. The RY/BY pin is high in the Standby  
mode.  
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Since this is an open-drain output, several RY/BY pins can be tied together with a pull-up resistor to  
Vcc.  
RESET Hardware Reset  
The BM29F400 device may be RESET by driving the RESET pin to VIL. The RESET pin must be  
kept low (VIL) for at least 500 nS. Pulling the RESET pin low will terminate any operation in progress.  
The internal state machine will be RESET to the read mode 1 mS to 230 mS after the RESET pin is  
driven low. If a hardware RESET occurs during a Programming or Erase operation, the data at that  
particular location will be indeterminate.  
When the RESET pin is low and the internal RESET is complete, the device goes to Standby mode  
and cannot be accessed. Also, note that all the data output pins are tri-stated for the duration of the  
RESET pulse. Once the RESET pin is taken high, the device requires 500 nS of wake up time until  
outputs are valid for a read access.  
The RESET pin may be tied to the system RESET input. Therefore, if a system RESET occurs  
during an Internal Programming or Erase operation, the device will be automatically RESET to read  
mode. This will enable the system's microprocessor to read the boot-up firmware from the Flag's  
memory.  
Data Protection  
The BM29F400 is designed to offer protection against accidental erasure or programming caused by  
spurious system level signals that may exist during power transitions. During power-up the device  
automatically resets the internal state machine in the Read mode. Also, with its control register  
architecture, alteration of the memory contents only occurs after successful completion of specific  
multi-bus cycle command sequences. The device also incorporates several features to prevent  
inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise.  
Low Vcc Write Inhibit  
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out  
for Vcc less than 3.2V (typically 3.7V). If Vcc < VLKO, the command register is disabled and all  
internal programming/erase circuits are disabled. Under this condition the device will RESET to the  
Read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the users  
responsibility to ensure that the control pins are logically correct to prevent unintentional writes when  
Vcc is above 3.2V.  
Write Pulse "Glitch" Protection  
Noise pulses of less than 5 nS (typical) on OE , CE or WE will not initiate a write cycle.  
Logical Inhibit  
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle  
CE and WE must be a logical "0" while OE is a logical "1".  
Power-Up Write Inhibit  
Power-up of the device with WE = CE = VIL and OE = V will not accept commands on the rising  
IH  
edge of WE . The internal state machine is automatically RESET to the Read mode on power-up.  
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Sector Unprotect  
The BM29F400 also features a sector unprotect mode, so that protected sectors may be unprotected  
to incorporate any changes in the code. Protecting all sectors is necessary before unprotecting any  
sector(s). Sector unprotection is accomplished in a PROM programmer.  
START  
Write Program Command Sequence  
(see below)  
/Data Polling Device  
NO  
Increment Address  
Last Address  
?
YES  
Programming Completed  
Program Command Sequence (Address/Command)  
5555H/AAH  
2AAAH/55H  
5555H/A0H  
Program Address/ Program Data  
Figure 1. Internal Programming Algorithm  
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START  
Write Erase Command Sequence  
(see below)  
/Data Polling or Toggle Bit  
Successfully Completed  
Erase Completed  
Individual Sector/Multiple Sector  
Erase Command Sequence  
Chip Erase Command Sequence  
(Address/Command)  
(Address/Command)  
5555H/AAH  
5555H/AAH  
2AAAH/55H  
5555H/80H  
5555H/AAH  
2AAAH/55H  
5555H/10H  
2AAAH/55H  
5555H/80H  
5555H/AAH  
2AAAH/55H  
Sector Address/30H  
Sector Address/30H  
Additional sector  
erase commands  
are optional  
Sector Address/30H  
Figure 2. Internal Erase Algorithm  
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START  
Read Byte  
(DQ0-DQ7), Addr=VA  
VA = Byte address for programming  
= Any of the sector addresses  
within the secotr being erased  
during sector erase operation.  
= XXXXH during Chip Erase  
YES  
DQ7=Data  
NO  
NO  
DQ5=1  
YES  
Read Byte  
(DQ0-DQ7), Addr=VA  
YES  
DQ7=Data  
Fail  
Pass  
Figure 3. Data Polling Algorithm  
Notes: DQ7 is rechecked even if DQ5 = logical "1" because DQ7 may change simultaneously with DQ5.  
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START  
Read Byte(DQ0-DQ7)  
Addr=Don't care  
NO  
DQ6=Toggle  
YES  
NO  
DQ5=1  
?
YES  
Read Byte(DQ0-DQ7)  
Addr=Don't care  
NO  
DQ6=Toggle  
?
YES  
Pass  
Fail  
Figure 4. Toggle Bit Algorithm  
Note: DQ6 is rechecked even if DQ5 = logical "1" because DQ6 may stop toggling at the same time as DQ5 changing to a logical  
"1".  
Absolute Maximum Ratings  
PARAMETER  
Storage Temperature  
RATING  
-65 to +125  
-55 to +125  
UNIT  
°C  
Plastic Packages  
Ambient Temperature  
With Power Applied  
°C  
Voltages with Respect to Ground  
All pins except A9 (Note 1)  
Vcc (Note 1)  
-2 to +7  
-2 to +7  
-2 to +14  
200  
V
A9 (Note 2)  
Output Short Circuit Current (Note 4)  
mA  
Notes :  
1. Minimum DC voltage on input or I/O pins is -0.5V.  
During voltage transitions, inputs may overshoot Vss to -2.0V for periods of up to 20 nS. Maximum DC voltage on output and  
I/O pins is Vcc +0.5V. During Voltage transitions, outputs may overshoot to Vcc + 2.0V for periods up to 20 nS.  
2. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2.0V for periods of up to  
20 nS. Maximum DC input voltage on A9 is + 12.5V which may overshoot to 14.0V for periods of up to 20 nS.  
3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.  
Operating Ranges  
- 20 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
PARAMETER  
RATING  
0 to +70  
UNIT  
°C  
Commercial (C) Devices  
Industrial (I) Devices  
Extended (I) Devices  
Vcc Supply Voltage  
-40 to +85  
-55 to +125  
+4.5 to 5.5  
°C  
°C  
V
Vcc for BM29F400-90  
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.  
*Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a  
stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may  
affect device reliability.  
Maximum Negative Overshoot Waveform  
20 nS  
20 nS  
+0.8 V  
20 nS  
-0.5 V  
-2.0 V  
Figure 5.  
Maximum positive Overshoot Waveform  
Vcc + 2.0 V  
Vcc + 0.5 V  
20 nS  
2.0 V  
20 nS  
20 nS  
Figure 6.  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 21 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
DC CHARACTERISTICS  
TTL/NMOS Compatible  
PARAMETER  
SYM.  
TEST CONDITIONS  
MIN.  
MAX.  
UNIT  
Input Load Current  
ILI  
ILIT  
ILO  
VIN = Vss to VCC,  
VCC = VCC Max.  
uA  
±1.0  
A9 Input Load Current  
Output Leakage Current  
VCC Active Current(1)  
VCC = VCC Max.,  
A9 = 12.5 V  
uA  
uA  
±1.0  
±1.0  
40  
VOUT = Vss to VCC,  
VCC = VCC Max.  
ICC1  
mA  
Byte  
CE = VIL, OE = VIH  
Word  
50  
60  
mA  
mA  
VCC Active Current(2,3)  
VCC Standby Current  
ICC2  
ICC3  
CE = VIL, OE = VIH  
VCC = VCC Max.,  
1.0  
mA  
CE = RESET = VIH  
VCC Standby Current  
(RESET )  
ICC4  
VCC = VCC Max.,  
RESET = VIL  
1.0  
mA  
Input Low Level  
Input High Level  
Voltage for Electronic  
Output Low Voltage  
Output High Voltage  
Notes:  
VIL  
VIH  
-0.5  
2.0  
0.8  
VCC +0.5  
12.5  
V
V
V
V
V
VID  
VCC = 5.0V  
11.5  
VOL  
VOH  
IOL = 5.8 mA, VCC = VCC Min.  
IOH = -2.5 mA, VCC = VCC Min.  
0.45  
2.4  
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The  
frequency component typically is less than 2 mA/MHz, with OE at VIH.  
2. ICC active while Internal Algorithm (program or erase) is in progress.  
3. Not 100% tested.  
- 22 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
DC Characteristics, continued  
CMOS Compatible  
PARAMETER  
Input Load Current  
SYM.  
ILI  
TEST CONDITIONS  
MIN.  
MAX.  
±1.0  
±1.0  
±1.0  
40  
UNIT  
uA  
VIN = VSS to VCC, VCC = VCC Max.  
VCC = VCC Max., A9 = 12.5 V  
VOUT = VSS to VCC, VCC = VCC Max.  
A9 Input Load Current  
Output Leakage Current  
ILIT  
uA  
ILO  
uA  
(1)  
VCC Active Current  
ICC1  
mA  
Byte  
= VIL,  
= VIH  
CE  
OE  
Word  
50  
60  
mA  
mA  
(2,3)  
VCC Active Current  
ICC2  
ICC3  
CE = VIL,  
= VIH  
OE  
VCC Standby Current  
100  
uA  
VCC = VCC Max.,  
= VCC ±0.5V,  
CE  
RESET = VCC ±0.5V  
Vcc Standby Current  
VCC = VCC Max.,  
ICC4  
100  
0.8  
uA  
(
)
= VSS ±0.5V  
RESET  
RESET  
Input Low Level  
Input High Level  
VIL  
-0.5  
V
V
V
VIH  
0.7 x VCC VCC + 0.3  
Voltage for Electronic ID  
and Sector Protect  
VCC = 5.0 V  
VID  
11.5  
12.5  
Output Low Voltage  
Output High Voltage  
VOL  
VOH1  
VOH2  
IOL = 5.8 mA, VCC = VCC Min.  
IOH = -2.5 mA, VCC = VCC Min.  
IOH = -100 mA, VCC = VCC Min.  
0.45  
V
V
0.85 x VIH  
VCC -0.4  
3.2  
V
Low VCC Lock-out Voltage  
Notes:  
VLKO  
4.2  
V
1.The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 Mhz). The frequency  
component typically is less than 2 mA/MHz, with OE at VIH.  
2. ICC active while Internal Algorithm (program or erase) is in progress.  
3. Not 100% tested.  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 23 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
AC CHARACTERISTICS  
Read-Only Operations  
DESCRIPTION  
-90  
-120 -150 UNIT  
PARAMETER SYM.  
TEST SETUP  
JEDEC  
Standard  
(2)  
Read Cycle Time  
Min.  
90  
90  
120  
120  
150  
150  
nS  
nS  
t
t
t
t
AVAV  
AVQV  
RC  
Address to Output Delay  
Max.  
ACC  
CE = VIL  
= VIL  
OE  
Chip Enable to Output Delay  
Max.  
Max.  
90  
35  
120  
50  
150  
55  
nS  
nS  
t
t
t
t
ELQV  
GLQV  
CE  
OE  
= VIL  
OE  
Output Enable to Output  
Delay  
Chip Enable to Output High  
Z(3,4)  
Max.  
20  
20  
0
30  
30  
0
35  
35  
0
nS  
nS  
nS  
t
t
t
t
t
t
EHQZ  
GHQZ  
AXQX  
HZ  
DF  
OH  
Output Enable to Output High  
Z(2,3)  
Output Hold Time from  
Min.  
Addresses,  
or  
,
OE  
CE  
Whichever Occurs First  
t
Max.  
Max.  
20  
5
20  
5
20  
5
mS  
nS  
READY  
Pin Low to Read  
RESET  
(4)  
Mode  
t
t
ELFL  
ELFH  
CE to BYTE Switching  
Low or High  
Notes:  
1. Test Conditions: Output Load: 1 TTL gate and 100 pF  
Input rise and fall times: 20 nS; Input pulse levels: 0.45 V to 2.4 V  
2. Timing measurement reference level  
Input: 0.8 and 2.0 V; Output: 0.8 and 2.0 V  
3. Output driver disable time.  
4. Not 100% tested.  
5.0 V  
2.7 KOhm  
IN3064 or  
Equivalent  
DEVICE  
UNDER  
TEST  
CL  
6.2 KOhm  
Diodes = IN3064  
or Equivalent  
Figure 7. Test Condition  
Note: CL = 100 pF including jig capacitance.  
- 24 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
AC CHARACTERISTICS  
Programming/Erase Operations  
PARAMETER  
SYM.  
DESCRIPTION  
-90  
-120  
-150  
UNIT  
JEDEC  
Standard  
(1)  
t
t
Write Cycle Time  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
90  
0
120  
0
150  
0
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
AVAV  
WC  
t
t
t
Address Setup Time  
Address Hold Time  
Data Setup Time  
AVWL  
WLAX  
AS  
AH  
DS  
DH  
t
t
45  
45  
0
50  
50  
0
50  
50  
0
t
DVWH  
WHDX  
t
t
Data Hold Time  
t
Output Enable Setup Time  
0
0
0
OES  
OEH  
(1)  
Read  
t
Output Enable  
Hold Time  
0
0
0
10  
10  
10  
(1)  
Polling  
Toggle &  
Data  
t
t
t
Read Recover Time Before Write  
CE Setup Time  
Min.  
Min.  
0
0
0
0
0
0
nS  
nS  
GHWL  
GHWL  
t
t
ELWL  
CS  
t
Min.  
0
0
0
nS  
WHEH  
CH  
CE Hold Time  
t
t
t
Write Pulse Width  
Min.  
Min.  
45  
20  
50  
20  
50  
20  
nS  
nS  
WLWH  
WP  
t
Write Pulse Width High  
Byte Programming Operation  
WHWL  
WPH  
t
t
t
t
t
t
Typ.  
Max.  
16  
400  
16  
400  
16  
400  
uS  
uS  
WHWH1  
WHWH2  
WHWH3  
WHWH1  
WHWH2  
WHWH3  
(2)  
Sector Erase Operation  
Typ. Max.  
0.26  
12  
0.26  
12  
0.26  
12  
sec  
(2)  
Chip Erase Operation  
(1)  
Typ.  
Max.  
2.0  
90  
2.0  
90  
2.0  
90  
sec  
t
Vcc Setup Time  
Min.  
Min.  
Min.  
50  
500  
4
50  
500  
4
50  
500  
4
mS  
nS  
VCS  
(1,3)  
Rise Time to VID  
t
VIDR  
t
mS  
OESP  
(1, 3, 4)  
OE Setup Time to WE Active  
t
Min.  
Min.  
500  
4
500  
4
500  
4
nS  
uS  
RP  
RESET Pulse Width  
t
RSP  
( 3)  
RESET Setup Time  
(1)  
t
Programming/Erase Valid to RY/BY Delay  
Min.  
Min.  
Min.  
Min.  
Min.  
40  
4
50  
4
60  
4
nS  
mS  
mS  
mS  
nS  
BUSY  
(1, 4)  
t
Voltage Transition Time  
Sector Protect Write Pulse Width  
Sector Unprotect Write Pulse Width  
VLHT  
(4)  
(4)  
t
t
100  
350  
4
100  
350  
4
100  
350  
4
WPP1  
WPP2  
t
CSP  
(1, 4)  
CE Setup Time to WE Active  
Notes:  
1. Not 100% tested.  
2. Does not include pre-programming time.  
3. This timing is for Temporary Sector Unprotect operation.  
These timings are for Sector Protect and/or Sector Unprotect operations.  
A Winbond Company  
- 25 -  
Publication Release Date: May 1999  
Revision A1  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
SWITCHING WAVEFORMS  
WAVEFORM  
INPUT  
OUTPUT  
Must Be Steady  
Will Be Steady  
Will Be Change  
from H to L  
May Change  
from H to L  
May Change  
from L to H  
Will Be Change  
from L to H  
Don't Care,  
Any Change  
Permitted  
Change,  
State Unknown  
Center Line is  
High impedance  
Off State  
Does Not  
Apply  
RC  
t
Address Stable  
Address  
ACC  
t
CE  
HZ  
t
OE  
t
OE  
DF  
t
OEH  
t
OH  
t
CE  
t
WE  
High Z  
High Z  
Output Vaild  
Outputs  
Figure 8. AC Waveforms for Read Operations  
- 26 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Switching Waveforms, continued  
/Data Polling  
PA  
5555H  
Address  
CE  
PA  
AH  
t
WC  
t
AS  
t
GHWL  
t
OE  
WP  
t
WHWH1  
t
WPH  
t
WE  
tCS  
DH  
t
A0H  
OUT  
D
DQ7  
PD  
Data  
DS  
t
5.0V  
VCC  
GND  
Figure 9. AC Waveforms Program Operations  
Notes:  
1. PA is address of the memory location to be programmed.  
2. PD is data to be programmed at BYTE address.  
3. /DQ7 is the output of the complement of the data written to the device.  
4. DOUT is the output of the data written to the device.  
5. Figure indicates last two bus cycles of four bus cycle sequence.  
6. These waveforms are for 16-bit mode.  
AS  
t
AH  
t
Address  
CE  
5555H  
2AAAH  
5555H  
SA  
5555H  
2AAAH  
GHWL  
t
OE  
WP  
t
WE  
WPH  
t
CS  
DH  
t
t
10H/30H  
Data  
5.0V  
80H  
55H  
AAH  
55H  
AAH  
DS  
t
VCS  
t
V
GND  
CC  
Figure 10. AC Waveforms Chip/Sector Erase Operations  
Notes:  
1. SA is the sector address for Sector Erase. Address = X = Don't Care for Chip Erase.  
2. These waveforms are for 16-bit mode.  
A Winbond Company  
- 27 -  
Publication Release Date: May 1999  
Revision A1  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Switching Waveforms, continued  
CH  
t
CE  
OE  
DF  
OE  
t
t
OEH  
t
WE  
CE  
t
OH  
t
DQ7  
DQ7  
DQ7=Valid Data  
WHWH  
1 or 2  
t
Data  
High  
Z
DQ0-DQ7  
Valid Data  
DQ0-DQ6  
DQ0-DQ6=Invalid  
OE  
t
5.0V  
CC  
V
GND  
Figure 11. AC Waveforms for  
Polling during Internal Algorithm Operations  
Data  
Note: DQ7 = Valid Data (The device has completed the internal program or erase operation.)  
CE  
OEH  
t
OE  
OES  
t
WE  
DQ6=  
Stop Toggling  
Data  
(DQ0-DQ7)  
DQ0-DQ7  
Valid  
DQ6=Toggle  
DQ6=Toggle  
Data  
OE  
t
5.0V  
CC  
V
GND  
Figure 12 AC Waveforms for Toggle Bit during Internal Algorithm Operation  
Note: DQ6 stops toggling (The device has completed the internal program or erase operation.)  
- 28 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Switching Waveforms, continued  
CE  
The rising edge of the last WE signal  
WE  
Entire programming  
or erase operations  
BY/RY  
tBUSY  
5.0V  
Vcc  
GND  
Figure 13. RY/BY Timing Diagram During Program/Erase Operation  
RY/BY  
RESET  
PWH  
t
RP  
Ready  
Vaild Data  
Data  
5.0V  
Vcc  
GND  
Figure 14. /RESET Timing Diagram  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 29 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Switching Waveforms, continued  
WC  
t
Address Stable  
Address  
CE  
AVFL  
t
ELFL  
t
DF  
t
OE  
OE  
t
BYTE  
CE  
t
OH  
t
Data  
High Z  
High Z  
High Z  
Data Output  
on DQ0-DQ7  
Data Output  
on DQ0-DQ7  
(DQ0-DQ7)  
ACC  
t
Data  
(DQ8-DQ14)  
Data  
Outputon  
DQ8-DQ14  
ACC  
t
FLQZ  
t
Data  
Outputon  
DQ15  
High Z  
Address  
Input  
DQ15/A-1  
Figure 15. BYTE Timing Diagram for Read Operation  
CE  
The falling edge of the last WE signal  
WE  
BYTE  
tSET  
(
)
tHOLD  
tAH  
tAS  
(
)
Figure 16. BYTE Timing Diagram for Write Operation  
- 30 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Start  
RESET = VID  
(Note 1)  
Perform Erase or  
Program Operations  
RESET = VIH  
Temporary Sector  
Unprotect Completed  
(Note 2)  
Figure 17. Temporary Sector Unprotect Algorithm  
Notes:  
1. All protected sector groups unprotected.  
2. All previously protected sector groups are protected again.  
12V  
5V  
RESET  
tVIDR  
CE  
WE  
tRSP  
Program or Erase Command Sequence  
RY/BY  
Figure 18. Temporary Unprotect Timing Diagram  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 31 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
AC CHARACTERISTICS  
Programming/Erase Operations  
PARAMETER  
JEDEC  
SYM.  
DESCRIPTION  
Standard  
-90  
90  
0
-120  
120  
0
-150  
150  
0
Unit  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
(1)  
Write Cycle Time  
t
t
t
t
t
t
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
AVAV  
AVEL  
ELAX  
DVEH  
EHDX  
WC  
t
t
t
Address Setup Time  
Address Hold Time  
Data Setup Time  
AS  
AH  
DS  
45  
45  
0
50  
50  
0
50  
50  
0
t
Data Hold Time  
DH  
(1)  
t
t
Output Enable Setup Time  
0
0
0
OES  
OEH  
(1)  
Read  
Output Enable  
Hold Time  
0
0
0
10  
10  
10  
(1)  
Polling  
Toggle and  
Data  
t
t
t
Read Recover Time Before Write  
WE Setup Time  
Min.  
Min.  
0
0
0
0
0
0
nS  
nS  
GHWL  
GHWL  
t
WLEL  
WS  
t
t
t
t
t
t
t
t
Min.  
Min.  
Min.  
0
0
0
nS  
nS  
nS  
EHWH  
WH  
WE Hold Time  
45  
20  
50  
20  
50  
20  
ELEH  
CP  
Pulse Width  
CE  
CE  
EHEL  
CPH  
WHWH1  
Pulse Width High  
Byte Programming Operation  
Typ.  
Max.  
Typ.  
Max.  
Typ.  
Max.  
Min.  
Min.  
Min.  
Min.  
Min.  
Min.  
16  
400  
0.26  
12  
16  
400  
0.26  
12  
16  
400  
0.26  
12  
mS  
mS  
sec  
sec  
sec  
sec  
mS  
nS  
WHWH1  
(2)  
Sector Erase Operation  
t
t
t
WHWH2  
WHWH3  
WHWH2  
WHWH3  
(2)  
Chip Erase Operation  
t
2.0  
90  
2.0  
90  
2.0  
90  
(1,3)  
Vcc Setup Time  
t
t
t
t
t
t
50  
50  
50  
VCS  
Rise Time to VID(1,3)  
500  
4
500  
4
500  
4
VIDR  
VLHT  
WPP1  
WPP2  
OESP  
(1,3)  
Voltage Transition Time  
mS  
mS  
mS  
mS  
(4)  
Sector Protect Write Pulse Width  
100  
10  
100  
10  
100  
10  
(4)  
Sector Unprotect Write Pulse Width  
4
4
4
(1, 3)  
OE Setup Time to WE Active  
OE Setup Time to WE Active  
t
Min.  
4
4
4
nS  
CSP  
(1, 4)  
Notes:  
1. Not 100% tested.  
2. Does not include pre-programming time.  
3. This timing is for Sector Unprotect operation.  
4. Output Driver Disable Time.  
- 32 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Switching Waveforms, continued  
Data Polling  
PA  
PA  
5555H  
Address  
CE  
t
WC  
t
AH  
t
AS  
t
GHWL  
OE  
WP  
t
t
WHWH1  
WE  
t
WPH  
CS  
t
t
D
OUT  
Data  
A0H  
PD  
DQ7  
D
DS  
t
5.0V  
Vcc  
GND  
Figure 19. Alternate  
Controlled Program Operation Timings  
CE  
Notes:  
1. PA is address of the memory location to be programmed.  
2. PD is data to be programmed at BYTE address.  
3. /DQ7 is the output of the complement of the data written to the device.  
4. D is the output of the data written to the device.  
OUT  
5. Figure indicates last two bus cycles of four bus cycle sequence.  
6. These waveforms are for the x16 mode.  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 33 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
Erase and Programming Performance  
PARAMETER  
MIN.  
LIMITS  
TYP.  
0.33  
2.4  
MAX.  
15  
UNIT  
sec  
Sector Erase Time  
Chip Erase Time  
Byte Programming Time  
Chip Programming Time  
120  
400  
200  
sec  
16  
us  
8
sec  
Erase/Program Cycles  
10,000  
100,000  
cycles  
Latch Up Characteristics  
PARAMETER  
MIN.  
MAX.  
Input Voltage with respect to Vss on all I/O  
pins  
-1.0V  
Vcc + 1.0V  
Vcc Current  
-100 mA  
+ 100 mA  
Note: Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.  
CAPACITANCE  
TSOP Pin  
PARAMETER  
Input Capacitance  
SYMBOL  
CIN  
TEST SETUP  
VIN = 0  
TYP.  
MAX.  
UNIT  
6
8.5  
8
7.5  
12  
10  
pF  
pF  
pF  
Output Capacitance  
Control Pin Capacitance  
VOUT = 0  
VIN = 0  
COUT  
CIN2  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions TA = 25°, f = 1.0 MHz.  
SOP Pin  
PARAMETER  
Input Capacitance  
SYMBOL  
CIN  
TEST SETUP  
VIN = 0  
TYP.  
6
MAX.  
7.5  
12  
UNIT  
pF  
Output Capacitance  
Control Pin Capacitance  
COUT  
CIN2  
VOUT = 0  
VIN = 0  
8.5  
8
pF  
10  
pF  
Notes:  
1. Sampled, not 100% tested.  
2. Test conditions TA = 25°, f = 1.0 MHz.  
Data Retention  
PARAMETER  
TEST CONDITIONS  
MIN.  
10  
UNIT  
Minimum Pattern Data Retention Time  
Minimum Pattern Data Retention Time  
Years  
Years  
150°  
125°  
20  
- 34 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
ORDERING INFORMATION  
PART NO.  
ACCESS  
TIME  
POWER  
SUPPLY  
CURRENT  
MAX. (mA)  
BOOT PACKAGE CYCLING  
TEMPERATURE  
RANGE  
BLOCK  
(MIN.)  
(nS)  
29F400T-90PC  
29F400T-12PC  
29F400T-90TC  
29F400T-12TC  
29F400B-90PC  
29F400B-12PC  
29F400B-90TC  
29F400B-12TC  
29F400T-90PI  
29F400T-12PI  
29F400T-90TI  
29F400T-12TI  
29F400B-90PI  
29F400B-12PI  
29F400B-90TI  
29F400B-12TI  
90  
120  
90  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
Top  
Top  
44SOP  
44SOP  
48TSOP  
48TSOP  
44SOP  
44SOP  
48TSOP  
48TSOP  
44SOP  
44SOP  
48TSOP  
48TSOP  
44SOP  
44SOP  
48TSOP  
48TSOP  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
10,000  
0°C - 70°C  
0°C - 70°C  
0°C - 70°C  
Top  
0°C - 70°C  
120  
90  
Top  
0°C - 70°C  
Bottom  
Bottom  
Bottom  
Bottom  
Top  
0°C - 70°C  
120  
90  
0°C - 70°C  
0°C - 70°C  
120  
90  
-40°C - 85°C  
-40°C - 85°C  
-40°C - 85°C  
-40°C - 85°C  
-40°C - 85°C  
-40°C - 85°C  
-40°C - 85°C  
-40°C - 85°C  
120  
90  
Top  
Top  
120  
90  
Top  
Bottom  
Bottom  
Bottom  
Bottom  
120  
90  
120  
Notes:  
1. Winbond reserves the right to make changes to its products without prior notice.  
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in  
applications where personal injury might occur as a consequence of product failure.  
3. Typical Program/Erase Cycle is 100,000.  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 35 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
APPENDIX A:  
Compatibility to AMD's AMD29F400B:  
The device is essentially fully functional compatible to the AMD29F400B except for three issues:  
1. During Erase Suspend  
2. DQ2 Status Flag  
3. Command Address Subset  
During Erase Suspend, the device can only read data in the memory-- not Program or execute an  
Auto Command like the AMD29400B. Also, the DQ2 Flag is not available. This flag is used to  
determine during multiple or single sector erase whether a sector has been selected for erase. DQ2  
can only be used during and embedded sector erase operation or during erase suspend.  
In the AMD device, commands do not require address pin A15, A14, A13, A12, A11 to be forced  
during the command sequence. This makes their device slighly easier to inadvertently create a  
command and cause a program, erase or malfunction. The advantage of reducing the address to a  
subset is to simplify the hardware interface in systems where control signals are limited in number.  
The 29F400B reduces the interface requirement by 4 signals. However if the full address is supplied  
(i.e.2AAAH and 5555H) by the host system, there will be no incompatibility using either device.  
- 36 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
PACKAGE DIMENSIONS  
PSOP44  
44-pin Small Outline Package (measured in millimeters)  
23  
44  
0.10  
0.21  
.060  
1.00  
15.70  
16.30  
13.10  
13.50  
1
22  
1.27 NOM.  
0
8
28.00  
28.40  
2.17  
2.45  
2.80  
MAX.  
Seating Plane  
0.10  
0.35  
0.35  
0.50  
TSOP48  
48-Pin Standard Thin Small Outline Package (measured in millimeters)  
0.95  
1.05  
Pin 1 I.D.  
1
48  
11.90  
12.10  
0.50 BSC  
24  
25  
0.05  
0.15  
18.30  
18.50  
19.80  
20.20  
0.08  
0.20  
0.10  
0.21  
1.20  
MAX  
0
5
0.25MM(0.0098)BSC  
.050  
.070  
A Winbond Company  
Publication Release Date: May 1999  
Revision A1  
- 37 -  
BRIGHT  
Microelectronics  
Inc.  
Preliminary BM29F400T/BM29F400B  
VERSION HISTORY  
VERSION  
DATE  
May. 1999  
PAGE  
DESCRIPTION  
A1  
-
Initial Issued  
Winbond Electronics (H.K.) Ltd.  
Headquarters  
Winbond Electronics Corporation America  
2727 N. First Street, San Jose,  
CA 95134, U.S.A.  
TEL: 408-9436666  
FAX: 408-5441798  
Rm. 803, World Trade Square, Tower II,  
123 Hoi Bun Rd., Kwun Tong,  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5796096  
http://www.winbond.com.tw/  
Voice & Fax-on-demand: 886-2-27197006  
Taipei Office  
11F, No. 115, Sec. 3, Min-Sheng East Rd.,  
Taipei, Taiwan  
TEL: 886-2-27190505  
FAX: 886-2-27197502  
Note: All data and specifications are subject to change without notice.  
- 38 -  

29F400B-90PC 相关器件

型号 制造商 描述 价格 文档
29F400B-90PI WINBOND Flash, 512KX8, 90ns, PDSO44, PLASTIC, SOP-44 获取价格
29F400B-90TC ETC 4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY 获取价格
29F400B-90TI WINBOND Flash, 512KX8, 90ns, PDSO48, TSOP-48 获取价格
29F400C-55 Macronix 4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE 5V ONLY BOOT SECTOR FLASH MEMORY 获取价格
29F400C-70 Macronix 4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE 5V ONLY BOOT SECTOR FLASH MEMORY 获取价格
29F400C-90 Macronix 4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE 5V ONLY BOOT SECTOR FLASH MEMORY 获取价格
29F400T-12PC ETC 4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY 获取价格
29F400T-12PI WINBOND Flash, 512KX8, 120ns, PDSO44, PLASTIC, SOP-44 获取价格
29F400T-12TC ETC 4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY 获取价格
29F400T-12TI WINBOND Flash, 512KX8, 120ns, PDSO48, TSOP-48 获取价格

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