ADS6616A4A-5 [ADATA]
Synchronous DRAM(1M X 16 Bit X 4 Banks); 同步DRAM （ 1M ×16位×4银行）
| 型号： | ADS6616A4A-5 |
| 厂家： | 
ADATA Technology Co., Ltd. |
| 描述： | Synchronous DRAM(1M X 16 Bit X 4 Banks) |
| 文件： | 总8页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A-Data
ADS6616A4A
1M x 16 Bit x 4 Banks
Synchronous DRAM
General Description
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
The ADS6616A4A are four-bank Synchronous
DRAMs organized as 1,048,576 words x 16 bits x 4
banks,
-CAS Latency (2 & 3)
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:54-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
200Mhz
166Mhz
143Mhz
133Mhz
Interface
Package
ADS6616A4A-5
ADS6616A4A-6
ADS6616A4A-7
ADS6616A4A-7.5
LVTTL
LVTTL
LVTTL
LVTTL
400mil 54pin TSOPII
400mil 54pin TSOPII
400mil 54pin TSOPII
400mil 54pin TSOPII
Pin Assignment
V
DD
1
2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ0
DQ15
V
DDQ
3
VssQ
DQ1
DQ2
4
DQ14
DQ13
5
V
SS
6
VDDQ
DQ3
DQ4
7
DQ12
DQ11
8
V
DDQ
9
VSSQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ10
DQ9
V
SSQ
VDDQ
DQ7
DQ8
V
DD
VSS
LDQM
/WE
/CAS
/RAS
/CS
NC
UDQM
CLK
CKE
NC
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
V
DD
VSS
54-pin plastic TSOP II 400 mil
Rev 1.1 April, 2001
1
A-Data
ADS6616A4A
Pin Description
PIN
NAME
FUNCTION
CLK
CKE
System Clock
Active on the positive edge to sample all inputs.
Clock Enable
Chip Select
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and L(U)DQM
A0~A11 Address
Row / Column address are multiplexed on the same pins.
Row address : RA0~RA11
Column address : CA0~CA7
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Makes data output Hi-Z,
DQ0~DQ15 Data
L(U)DQM Data Mask
/RAS
/CAS
/WE
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Column Address Strobe
Write Enable
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
Clock
Generator
Bank3
Bank2
CKE
Bank1
Address
Address
Buffer
&
Bank0
Mode
Register
Refresh
Counter
Amplifier
L(U)DQM
/CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
/RAS
/CAS
Data Control Circuit
DQ
/WE
Rev 1.1 April, 2001
2
A-Data
ADS6616A4A
Absolute Maximum Ratings
Parameter
Symbol
VIN, Vout
VDD, VDDQ
TSTG
Value
-0.3 ~ VDD+0.3
-0.3 ~ 4.6
-55 ~ +150
1
Unit
V
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
V
℃
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
3.0
VDD+0.3
V
1
VIL
0
-
0.8
-
V
2
VOH
V
IOH=-2mA
VOL
-
0.4
5
V
IOL=2mA
IIL
-5
-
uA
uA
3
4
IOL
-5
-
5
Note : 1. VIH (max)=4.6V AC for pulse width ≦ 10ns acceptable.
2.VIL(min)=-1.5V AC for pulse width ≦ 10ns acceptable.
3.Any input 0V ≦ VIN ≦ VDD + 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V ≦ VOUT ≦ VDD.
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
AC input high / low level voltage
Symbol
VIH / VIL
Vtrip
Value
2.4 / 0.4
1.4
Unit
V
Note
Input timing measurement reference level voltage
Input rise / fall time
V
TR / tF
Voutfef
CL
1
Ns
V
Output timing measurement reference level
Output load capacitance for access time measurement
Note: 1. 3.15V ≦ VDD ≦ 3.6V is applied for ADS6616A4A5.
1.4
50
pF
2
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1.1 April, 2001
3
A-Data
ADS6616A4A
Capacitance
TA=25℃, f-=1Mhz, VDD=3.3V
Parameter
Pin
Symbol
Cl1
Min
2.5
2.5
Max
4
Unit
pF
Input capacitance
CLK
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2
5
pF
Data input / output capacitance DQM
CI/O
4
6.5
pF
Output load circuit
3.3 V
1200 ohms
V
OH(DC) = 2.4V,IOH= -2mA
Output
V
OL(DC) = 0.4V,IOL= 2mA
50 pF
870 ohms
DC Characteristics I
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Symbol
Min
Max
5
Unit
uA
Note
I
I
LI
-5
-5
2.4
-
1
LO
5
uA
2
V
V
OH
OL
-
V
V
I
OH = -4mA
0.4
IOL = 4mA
Note : 1.VIN = 0 TO 3.6V, All other pins are not tested under VIN = 0V.
2.DOUT is disabled, VOUT = 0 to 3.6.
Rev 1.1 April, 2001
4
A-Data
ADS6616A4A
DC Characteristics II
Speed
Parameter
Symbol
Test condition
Unit
mA
Note
1
-5
-6
-7
-7.5
80
Burst length=1, One bank active
Operating Current
IDD1
105
90
80
tRC≧tRC(min),IOL=0mA
Precharge standby
current in power
down mode
CKE≦VIL(max), tCK=min
CKE≦VIL(max), tCK=∞
IDD2P
1
1
mA
mA
mA
IDD2PS
CKE≧VIH(min), /CS≧VIH(min),
tCK=min input signals are
Precharge standby
current in Non power
down mode
IDD2N changed one time during 2clks.
All other pins ≧VDD-0.2V or ≦
0.2V
35
CKE≧VIH(min), tCK=∞
IDD2NS
8
5
5
Input signals are stable.
Active standby
current in power
down mode
CKE≦VIL(max), tCK=min
IDD3P
CKE≦VIL(max), tCK=∞
IDD3PS
CKE≧VIH(min), /CS≧VIH(min),
tCK=min input signals are
Active standby
current in Non power
down mode
IDD3N changed one time during 2clks.
All other pins ≧VDD-0.2V or ≦
0.2V
30
20
mA
mA
CKE≧VIH(min), tCK=∞
IDD3NS
Input signals are stable.
tCK≧tCK(min),IOL=0 mA
IDD4
Burst mode operating
current
185
165
145
145
1
2
All banks active
tRRC≧tRRC(min), All banks
Auto refresh current IDD5
120
1
mA
mA
active
CKE≦0.2V
Self refresh current IDD6
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 1.1 April, 2001
5
A-Data
ADS6616A4A
AC Characteristics
-5
-6
-7
-7.5
Parameter
Symbol
Unit Note
Min Max Min Max Min Max Min Max
System clock /CAS Latency = 3 tCK3
Cycle time
5
7
6
7.5
2
7
8
7
8
1000
1000
1000
1000 ns
/CAS Latency = 2 tCK2
Clock high pulse width
Clock low pulse width
tCHW
tCLW
1.5
1.5
-
-
-
-
2
-
-
2
-
-
ns
ns
1
1
-
4.5
5.5
-
2
2
2
Access time /CAS Latency = 3 tAC3
5
5.5
-
-
5.5
6
-
-
5.5
6
-
ns
2
form clock
/RAS cycle
time
/CAS Latency = 2 tAC2
-
-
-
Operation
tRC
54
54
14
60
60
18
65
65
20
65
65
20
ns
ns
Auto Refresh
tRRC
tRCD
tRAS
tRP
-
-
-
-
/RAS to /CAS delay
/RAS active time
-
-
-
-
40 100K 42 100K 42 120K 42 120K ns
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
Data – out hold time
Data – input setup time
Data – input hold time
Address setup time
Address hold time
CKE setup time
14
10
1
-
-
-
-
-
-
-
-
-
-
-
-
-
18
12
1
-
-
-
-
-
-
-
-
-
-
-
-
-
20
14
1
-
-
-
-
-
-
-
-
-
-
-
-
-
20
14
1
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
tRRD
tCCD
tOH
CLK
ns
1.5
1.5
1
2
2
2
tDS
1.5
1
1.5
1
1.5
1
ns
1
1
1
1
1
1
1
1
tDH
ns
tAS
1.5
1
1.5
1
1.5
1
1.5
1
ns
tAH
ns
tCKS
tCKH
tCS
1.5
1
1.5
1
1.5
1
1.5
1
ns
CKE hold time
ns
Command setup time
Command hold time
Refresh time
1.5
1
1.5
1
1.5
1
1.5
1
ns
tCH
ns
tREF
64
64
64
64
ms
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.1 April, 2001
6
A-Data
ADS6616A4A
Command Truth-Table
Command
CKEn-1 CKEn
/CS
L
/RAS
/CAS
/WE
L
DQM ADDR A10/AP
BA
Mode Register Set
H
H
H
H
X
X
X
X
L
X
H
L
L
X
H
H
X
X
X
X
OP code
H
X
No Operation
X
L
H
Bank Active
Read
L
H
RA
V
V
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Auto Precharge
Write
H
L
H
H
X
X
X
V
Write with Auto Precharge
Precharge All Bank
H
H
X
V
X
X
L
L
H
H
L
L
Precharge select Bank
Burst Stop
DQM
L
X
X
X
H
H
H
H
H
X
L
X
V
X
X
Auto Refresh
Entry
H
L
L
L
L
L
H
H
X
H
X
H
X
L
Self Refresh
Exit
X
X
X
H
L
X
H
X
H
X
X
H
X
H
X
L
H
L
X
X
H
L
Entry
H
Precharge
H
Power down
Exit
L
H
X
L
H
H
H
H
L
X
V
X
V
X
V
Entry
H
L
L
X
X
Clock Suspend
Exit
H
X
Rev 1.1 April, 2001
7
A-Data
ADS6616A4A
Package Information
MILLIMETER
NOM.
INCH
NOM.
SYMBOL
MIN.
MAX.
1.20
0.15
1.05
0.45
0.21
MIN.
MAX.
0.047
0.006
0.041
0.018
0.008
A
A1
A2
B
0.05
0.95
0.30
0.12
0.10
1.00
0.35
0.002
0.037
0.012
0.005
0.004
0.039
0.014
c
D
HE
E
e
L
22.22 BSC
11.76
10.16
0.875 BSC
0.463
0.400
11.56
10.03
0.80 BSC
0.40
11.96
10.29
0.460
0.390
0.031
0.016
0.470
0.410
0.50
0.60
0.020
0.024
L1
S
0.80 REF
0.71 REF
0.031 REF
0.028 REF
0 °
-
8 °
0 °
-
8 °
θ
400mil 54pin TSOP II Package
Rev 1.1 April, 2001
8
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