AD1852JRSZ [ADI]
Stereo, 24-Bit, 192 kHz, Multibit, Sigma-Delta DAC; 立体声， 24位， 192千赫，多位， Σ-Δ DAC
| 型号： | AD1852JRSZ |
| 厂家： | 
ADI |
| 描述： | Stereo, 24-Bit, 192 kHz, Multibit, Sigma-Delta DAC |
| 文件： | 总20页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stereo, 24-Bit, 192 kHz,
Multibit, Sigma-Delta DAC
AD1852
FEATURES
APPLICATIONS
5 V stereo audio DAC system
High end
DVDs, CDs, home theater systems, automotive, audio
Accepts 16-bit/18-bit/20-bit/24-bit data
Supports 24 bits, 192 kHz sample rate
Accepts a wide range of sample rates including
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Σ-Δ modulator with perfect differential linearity
restoration for reduced idle tones and noise floor
Data-directed scrambling DAC—least sensitive to jitter
Differential output for optimum performance
117 dB signal-to-noise (not muted) at 48 kHz sample rate
(A-weighted mono)
114 dB signal-to-noise (not muted) at 48 kHz sample rate
(A-weighted stereo)
117 dB dynamic range (not muted) at 48 kHz sample rate
(A-weighted mono)
114 dB dynamic range (not muted) at 48 kHz sample rate
(A-weighted stereo)
−105 dB THD+N (mono application circuit)
−102 dB THD+N (stereo)
systems, sampling musical keyboards, digital mixing
consoles, and digital audio effects processors
GENERAL DESCRIPTION
The AD1852 is a complete, high performance, single-chip, stereo
digital, audio playback system. It is comprised of a multibit, Σ-Δ
modulator, digital interpolation filters, and analog output drive
circuitry. Other features include an on-chip, stereo attenuator
and mute, programmed through an SPI-compatible serial control
port. The AD1852 is fully compatible with all known DVD
formats, including 192 kHz, as well as 96 kHz sample frequencies
and 24 bits. It is also backwards compatible by supporting
50 μs/15 μs digital de-emphasis intended for Red Book compact
discs, as well as de-emphasis at 32 kHz and 48 kHz sample rate.
The AD1852 has a very simple, but very flexible, serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers, and sample rate converters. The
AD1852 can be configured in left-justified, I2S, right-justified,
or DSP serial port compatible modes. It can support 16, 18, 20,
and 24 bits in all modes. The AD1852 accepts serial audio data
in MSB first, twos-complement format. The AD1852 operates
from a single 5 V power supply. It is fabricated on a single,
monolithic integrated circuit and is housed in a 28-lead SSOP
for operation over the 0°C to 70°C temperature range.
115 dB stop-band attenuation
On-chip clickless volume control
Hardware and software controllable clickless mute
Serial (SPI) control for: serial mode, number of bits, sample
rate, volume, mute, de-emp
Digital de-emphasis processing for 32 kHz, 44.1 kHz, 48 kHz
sample rates
Clock autodivide circuit supports five master-clock frequencies
Flexible serial data port with right-justified, left-justified,
I2S-compatible and DSP serial port modes
28-Lead SSOP plastic package
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
SUPPLY
CLOCK
IN
CONTROL DATA
INPUT
VOLUME
MUTE
2
3
VOLTAGE
REFERENCE
AUTO-CLOCK
DIVIDE CIRCUIT
SERIAL CONTROL
INTERFACE
AD1852
16-/18-/20-/24-BIT
DIGITAL
8 × fS
ATTEN/
MUTE
MULTIBIT SIGMA-
DAC
DELTA MODULATOR
INTERPOLATOR
SERIAL
DATA
INTERFACE
DATA INPUT
ANALOG
OUTPUTS
2
8 × fS
INTERPOLATOR
SERIAL
MODE
ATTEN/
MUTE
MULTIBIT SIGMA-
DELTA MODULATOR
DAC
2
ANALOG
2
MUTE
DE-EMPHASIS
ZERO
FLAG
RESET
SUPPLY
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
AD1852
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Theory of Operation ...................................................................... 12
Serial Data Input Port................................................................ 12
Serial Data Input Mode ............................................................. 12
Master Clock Autodivide Feature ............................................ 13
SPI Register Definitions ............................................................ 13
Register Addresses...................................................................... 14
Volume Left and Volume Right Registers............................... 14
SPI Timing................................................................................... 14
Mute ............................................................................................. 14
Control Register ......................................................................... 15
De-Emphasis............................................................................... 15
Output Impedance ..................................................................... 15
Reset............................................................................................. 15
Control Signals ........................................................................... 15
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Performance .................................................................... 3
Digital I/O (0°C to 70°C)............................................................. 4
Temperature Range ...................................................................... 4
Power.............................................................................................. 4
Digital Filter Characteristics ....................................................... 4
Group Delay .................................................................................. 4
Digital Timing............................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
REVISION HISTORY
11/09—Rev. 0 to Rev. A
Changes to Format .............................................................Universal
Changes to Note 1............................................................................. 1
Changes to Table 2............................................................................ 3
Changes to Table 11.......................................................................... 7
Changes to Register Addresses Section and Mute Section ....... 14
Changes to Figure 29...................................................................... 16
1/00—Revision 0: Initial Version
Rev. A | Page 2 of 20
AD1852
SPECIFICATIONS
Test conditions, unless otherwise noted.
Table 1.
Parameter
Rating
Supply Voltages (AVDD, DVDD)
Ambient Temperature
Input Clock
5.0 V
25°C
24.576 MHz (512 × fS Mode)
Input Signal
996.11 Hz
−0.5 dB full scale
48 kHz
20 Hz to 20 kHz
20 bits
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
Input Voltage High
Input Voltage Low
100 pF
47 kΩ
2.4 V
0.8 V
ANALOG PERFORMANCE
Table 2.
Parameter1
Min
Typ
Max
Unit
RESOLUTION
24
Bits
SIGNAL-TO-NOISE RATIO (20 Hz TO 20 kHz)
No Filter (Stereo)
112
115
114
117
dB
dB
dB
dB
No Filter (Mono, See Figure 19)
With A-Weighted Filter (Stereo)
With A-Weighted Filter (Mono)
DYNAMIC RANGE (20 Hz To 20 kHz, −60 dB INPUT)
No Filter (Stereo)
No Filter (Mono, See Figure 24)
With A-Weighted Filter (Stereo)
With A-Weighted Filter (Mono)
TOTAL HARMONIC DISTORTION + NOISE (STEREO)
107
110
−94
112
115
114
117
dB
dB
dB
dB
dB
%
−102
0.00079
−105
0.00056
−92
TOTAL HARMONIC DISTORTION + NOISE (MONO, SEE Figure 20)
dB
%
TOTAL HARMONIC DISTORTION + NOISE (STEREO) VO = −20 dB
TOTAL HARMONIC DISTORTION + NOISE (STEREO) VO = −60 dB
ANALOG OUTPUTS
dB
dB
−52
Differential Output Range ( Full Scale)
Output Capacitance at Each Output Pin
OUT-OF-BAND ENERGY (0.5 × fS TO 100 kHz)
CMOUT
5.6
V p-p
pF
2
−90
dB
2.37
V
DC ACCURACY
Gain Error
Interchannel Gain Mismatch
Gain Drift
−10
−0.15
2.0
0.015
150
+10
+0.15
250
%
dB
ppm/°C
mV
DC Offset
−50
INTERCHANNEL CROSSTALK (EIAJ METHOD)
INTERCHANNEL PHASE DEVIATION
MUTE ATTENUATION
−120
0.1
dB
Degrees
dB
−100
DE-EMPHASIS GAIN ERROR
0.1
dB
1 Performance of right and left channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Rev. A | Page 3 of 20
AD1852
DIGITAL I/O (0°C TO 70°C)
Table 3.
Parameter
Min
Typ
Max
Unit
V
V
μA
μA
V
Input Voltage High (VIH)
Input Voltage Low (VIL)
2.2
0.8
10
10
Input Leakage (IIH at VIH = 2.4 V)
Input Leakage (IIL at VIL = 0.8 V)
High Level Output Voltage (VOH), IOH = 1 mA
Low Level Output Voltage (VOL), IOL = 1 mA
Input Capacitance
2.0
0.4
20
V
pF
TEMPERATURE RANGE
Table 4.
Parameter
Min
Typ
Max
Unit
°C
°C
Specifications Guaranteed
Functionality Guaranteed
Storage
25
0
−55
70
+150
°C
POWER
Table 5.
Parameter
Min
Typ
Max
Unit
SUPPLIES
Voltage, Analog and Digital
Analog Current
Analog Current—RESET
Digital Current
4.50
5
5.50
40
V
33
32
20
27
mA
mA
mA
mA
46
30
37
Digital Current—RESET
DISSIPATION
Operation—Both Supplies
Operation—Analog Supply
Operation—Digital Supply
265
165
100
mW
mW
mW
POWER SUPPLY REJECTION RATIO
1 kHz, 300 mV p-p Signal at Analog Supply Pins
20 kHz, 300 mV p-p Signal at Analog Supply Pins
−60
−50
dB
dB
DIGITAL FILTER CHARACTERISTICS
Table 6.
Sample Rate (kHz)
Pass Band (kHz)
DC − 20
DC − 21.8
DC − 39.95
DC − 87.2
Stop Band (kHz)
24.1 − 328.7
26.23 − 358.28
56.9 − 327.65
117 − 327.65
Stop-Band Attenuation (dB)
Pass-Band Ripple (dB)
0.0002
0.0002
44.1
48
96
110
110
115
95
0.0005
192
+0/−0.04 (DC − 21.8 kHz)
+0/−0.5 (DC − 65.4 kHz)
+0/−1.5 (DC − 87.2 kHz)
GROUP DELAY
Table 7.
Chip Mode
INT8× Mode
INT4× Mode
INT2× Mode
Group Delay Calculation
5553/(128 × fS)
5601/(64 × fS)
fS (kHz)
48
96
Group Delay (μs)
903.8
911.6
921
5659/(32 × fS)
192
Rev. A | Page 4 of 20
AD1852
DIGITAL TIMING
Guaranteed over 0°C to 70°C, AVDD = DVDD = 5.0 V × 10%.
Table 8.
Parameter
Description
Min
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tDMP
tDML
tDMH
tDBH
tDBL
tDBP
tDLS
tDLH
tDDS
MCLK period (fMCLK = 256 × fLRCLK
)
54
0.4 × tDMP
0.4 × tDMP
MCLK low pulse width (all modes)
MCLK high pulse width (all modes)
BCLK high pulse width (see Figure 26)
BCLK low pulse width (see Figure 26)
BCLK period (see Figure 26)
LRCLK setup (see Figure 26)
LRCLK hold (DSP serial port mode only)
SDATA setup (see Figure 26)
20
20
60
20
5
5
10
15
tDDH
SDATA hold (see Figure 26)
RESET low pulse width
tRSTL
1 Higher MCLK frequencies are allowable when using the on-chip master clock autodivide feature.
Rev. A | Page 5 of 20
AD1852
ABSOLUTE MAXIMUM RATINGS
Table 9.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
DVDD to DGND
AVDD to AGND
Digital Inputs
Analog Outputs
AGND to DGND
ReferenceVoltage
Soldering
−0.3 V to +6 V
−0.3 V to +6 V
Table 10.
Package Type
DGND − 0.3 V to DVDD + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V (see Figure 26)
−0.3 V to +0.3 V
(AVDD + 0.3 V)/2 V
300°C
θJA
θJC
Unit
Thermal Resistance
Junction-to-Ambient
Junction-to-Case
109
°C/W
°C/W
39
ESD CAUTION
10 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 6 of 20
AD1852
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND
1
2
3
4
5
6
7
8
9
28 DVDD
27 SDATA
26 BCLK
25 LRCLK
24 RESET
23 MUTE
22 ZEROL
21 IDPM0
20 IDPM1
19 FILTB
18 AVDD
17 OUTL+
16 OUTL–
15 AGND
MCLK
CLATCH
CCLK
CDATA
NC
AD1852
TOP VIEW
192/48
ZEROR
DEEMP
(Not to Scale)
96/48 10
AGND 11
OUTR+ 12
OUTR– 13
FILTER 14
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Input/Output Description
1
2
DGND
MCLK
I
I
Digital Ground.
Master Clock Input. Connect to an external clock source running at either 256 fS, 384 fS, 512 fS,
768 fS, or 1024 fS.
3
4
CLATCH
CCLK
I
I
Latch Input for SPI Control Data Port. This input is rising-edge sensitive.
SPI Control Clock Input for Control Data. Control input data must be valid on the rising edge of
CCLK. CCLK may be continuous or gated.
5
6
CDATA
I
SPI Control Data Input, MSB First. SPI data port for controlling AD1852 functions as described in
the SPI Register Definitions section.
NC
No Connect.
192 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 192 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 11 of the control register.
Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input
for more than 1024 LR clock cycles.
192/48
ZEROR
7
8
I
O
9
DEEMP
I
De-Emphasis. Digital de-emphasis is enabled when this input signal is high. This is used to
impose a 50 μs/15 μs response characteristic on the output audio spectrum at an assumed
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via the SPI
control register.
96 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 96 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 10 of the control register.
96/48
10
I
11, 15
12
13
AGND
OUTR+
OUTR−
FILTR
I
Analog Ground.
Right Channel Positive Line Level Analog Output.
Right Channel Negative Line Level Analog Output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference
with parallel 10 μF and 0.1 μF capacitors to the AGND.
O
O
O
14
16
17
18
19
20
21
22
OUTL−
OUTL+
AVDD
FILTB
IDPM1
IDPM0
ZEROL
O
O
I
Left Channel Negative Line Level Analog Output.
Left Channel Positive Line Level Analog Output.
Analog Power Supply. Connect this pin to the analog 5 V supply.
Filter Capacitor Connection. Connect 10 μF||10 nF capacitor to AGND (Pin 15).
Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input
for more than 1024 LR clock cycles.
I
I
O
23
24
MUTE
RESET
I
I
Mute. Assert this pin high to mute both stereo analog outputs. De-assert low for normal operation.
Reset. The AD1852 is reset on the rising edge of this signal. The serial control port registers are
reset to the default values. For normal operation, assert this pin high.
Rev. A | Page 7 of 20
AD1852
Pin No. Mnemonic Input/Output Description
Left/Right Clock Input for Serial Audio Data Input Port. This pin must run continuously.
25
26
LRCLK
BCLK
I
I
Bit Clock Input for Serial Audio Data Input Port. This pin need not run continuously; may be
gated or used in a burst fashion.
27
28
SDATA
DVDD
I
I
Serial Audio Data Input, MSB First. Input for the serial audio data stream is as described the
in Serial Data Input Port section.
Digital Power Supply. Connect this pin to the digital 5 V supply.
Table 12. Serial Data Input Mode
IDPM1 (Pin 20)
IDPM0 (Pin 21)
Serial Data Input Format
Right justified
I2S compatible
Left justified
0
0
1
1
0
1
0
1
DSP
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1
LSB
MSB–1
LSB+1
LSB+2
MSB
MSB–2
LSB
Figure 3. Right-Justified Mode
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
MSB–1
LSB+1
MSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB
MSB–2
LSB+2
LSB
SDATA
INPUT
Figure 4. I2S-Justified Mode
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB–1
LSB+1
MSB
MSB–1
MSB
MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB
MSB–2
LSB+2
LSB
Figure 5. Left-Justified Mode
LRCLK
INPUT
RIGHT CHANNEL
LEFT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB–1
LSB+1
MSB MSB–1
MSB
MSB–1
LSB+2 LSB+1 LSB
MSB
LSB+2
LSB
Figure 6. Left-Justified DSP Mode
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LSB+2
LSB+1
LSB
MSB
MSB–1
LSB
MSB
MSB–1 MSB–2
LSB+2
LSB+1
LSB
MSB
MSB–1 MSB–2
Figure 7. 32 × fS Packed Mode
Rev. A | Page 8 of 20
AD1852
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8 to Figure 13 show the calculated frequency response of the digital interpolation filters. Figure 14 to Figure 25 show the performance of
the AD1852 as measured by an Audio Precision System 2 Cascade. For the wideband plots, the noise floor shown in the plots is higher
than the actual noise floor of the AD1852. This is caused by the higher noise floor of the high bandwidth ADC used in the Audio Precision
measurement system. The two-tone test shown in Figure 16 is per the SMPTE standard for measuring intermodulation distortion.
0.0010
0.0008
0.0006
0.0004
0.0002
0
0
–20
–40
–60
–80
–0.0002
–0.0004
–0.0006
–0.0008
–0.0010
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
22
0
50
100
150
200
250
300
350
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. Pass-Band Response 8× Mode, 48 kHz Sample Rate
Figure 11. Complete Response, 8× Mode, 48 kHz Sample Rate
0.5
0.4
0.3
0.2
0.1
0
0
–20
–40
–60
–80
–0.1
–100
–120
–140
–160
–0.2
–0.3
–0.4
–0.5
–10
5
10
15
20
25
30
35
40
45
0
50
100
150
200
250
300
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 9. 44 kHz Pass-Band Response 4× Mode, 96 kHz Sample Rate
Figure 12. Complete Response, 4× Mode, 96 kHz Sample Rate
2.0
1.5
0
–20
1.0
–40
0.5
–60
0
–80
–0.5
–1.0
–1.5
–2.0
–100
–120
–140
–160
0
10
20
30
40
50
60
70
80
90
0
50
100
150
200
250
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 10. 88 kHz Pass-Band Response 2× Mode, 192 kHz Sample Rate
Figure 13. Complete Response, 2× Mode, 192 kHz Sample Rate
Rev. A | Page 9 of 20
AD1852
–50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–60
–70
–80
–90
–100
–110
–120
10
100
1k
10k 20k
–120
–100
–80
–60
–40
–20
0
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 14. THD vs. Frequency Input @ −3 dBFS, SR 48 kHz
Figure 17. THD + N Ratio vs. Amplitude Input 1 kHz, SR 48 kS/s, 24-Bit
2
0
–90
–100
–110
–120
–130
–140
–150
–160
–2
–4
–6
–8
–10
–12
10
100
1k
10k 20k
0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 15. Normal De-Emphasis Frequency Response Input @
−10 dBFS, SR 48 kHz
Figure 18. Noise Floor for Zero Input, SR 48 kHz
–10
0
–10
–20
–30
–30
–40
–50
–50
–60
–70
–70
–80
–90
–90
–100
–110
–120
–130
–140
–150
–110
–130
–150
0
2
4
6
8
10
12
14
16
18
20
22
0
2
4
6
8
10
12
14
16
18
20
22
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 16. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS
Figure 19. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz, SR 48 kHz
Rev. A | Page 10 of 20
AD1852
0
–20
–50
–60
–70
–80
–40
–90
–60
–100
–110
–120
–130
–140
–150
–160
–80
–100
–120
–140
–140
–120
–100
–80
–60
–40
–20
0
0
2
4
6
8
10
12
14
16
18
20
22
(dBFS)
FREQUENCY (kHz)
Figure 20. Linearity vs. Amplitude Input 200 Hz, SR 48 kS/s, 24-Bit Word
Figure 23. Dynamic Range for 1 kHz @ −60 dBFS, Triangular Dithered Input
–64
–66
–68
–70
–72
–74
–76
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
10
100
1k
10k 20k
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 21. Power Supply Rejection vs. Frequency, AVDD 5 V DC + 100 mV p-p AC
Figure 24. Wideband Plot, 75 kHz Input, 2× Interpolation, SR 192 kHz
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–100
–110
–120
–130
–140
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 22. Wideband Plot, 15 kHz Input, 8× Interpolation, SR 48 kHz
Figure 25. Wideband Plot, 37 kHz Input, 4× Interpolation, SR 96 kHz
Rev. A | Page 11 of 20
AD1852
THEORY OF OPERATION
Figure 4 shows the I2S mode. LRCLK is low for the left channel
and high for the right channel. Data is valid on the rising edge
of BCLK. The MSB is left justified to an LRCLK transition but
with a single BCLK period delay. The I2S mode can be used to
accept any number of bits up to 24.
SERIAL DATA INPUT PORT
The flexible, serial data input port of the AD1852 accepts data
in twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The serial mode is
set by either using the external mode pins (IDPM0, Pin 21 and
IDPM1, Pin 20) or the mode select bits (Bit 4 and Bit 5) in the
SPI control register. To control the serial mode using the
external mode pins, the SPI mode select bits should be set to
zero (the default mode at power-up). To control the serial mode
using the SPI mode select bits, the external mode control pins
should be grounded.
Figure 5 shows the left-justified mode. LRCLK is high for the
left channel, and low for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an LRCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits, and any number of bit
clocks from two times the word length to 64-bit clocks per
frame.
In all modes, except for right-justified mode, the serial port
accepts an arbitrary number of bits up to 24. Extra bits do not
cause an error, but they are truncated internally. In right-
justified mode, use Bit 8 and Bit 9 of the SPI control register to
set the word length to 16 bits, 20 bits, or 24 bits. The default
mode at power-up is 24-bit mode. When the SPI control port is
not being used, the SPI pins (CLATCH, CCLK, and CDATA
[Pin 3, Pin 4, and Pin 5]) should be tied low.
Figure 6 shows the DSP serial port mode. LRCLK must pulse
high for at least one bit clock period before the MSB of the left
channel is valid, and LRCLK must pulse high again for at least
one bit clock period before the MSB of the right channel is
valid. Data is valid on the falling edge of BCLK. The DSP serial
port mode can be used with any word length up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse and that
synchronism is maintained from that point forward.
SERIAL DATA INPUT MODE
The AD1852 uses two multiplexed input pins to control the
mode configuration of the input data port mode (see Table 12).
Note that the AD1852 is capable of a 32 × fS BCLK frequency
packed mode, where the MSB is left justified to an LRCLK
transition, and the LSB is right justified to the opposite LRCLK
transition. LRCLK is high for the left channel and low for the
right channel. Data is valid on the rising edge of BLCK. Packed
mode can be used when the AD1852 is programmed in right-
justified or left-justified mode. Packed mode is shown is Figure 7.
Figure 3 shows the right-justified mode (16 bits shown). LRCLK is
high for the left channel and low for the right channel. Data is
valid on the rising edge of BCLK.
In normal operation, there are 64-bit clocks per frame (or 32 per
half frame). When the SPI word length control bits (Bit 8 and
Bit 9 in the SPI control register) are set to 24 bits (0:0), the serial
port begins to accept data starting at the eighth bit clock pulse
after the LRCLK transition. When the word length control bits
are set to 20-bit mode, data is accepted starting at the 12th bit
clock position. In 16-bit mode, data is accepted starting at the
16th bit clock position. These delays are independent of the
number of bit clocks per frame, and therefore, other data formats
are possible using the delay values previously described. For
detailed timing, see Figure 26.
Rev. A | Page 12 of 20
AD1852
tDBH
tDBP
BCLK
tDBL
tDLS
LRCLK
tDDS
SDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB – 1
tDDS
SDATA
2
I C-JUSTIFIED
MSB
tDDH
MODE
tDDS
MSB
tDDS
LSB
tDDH
SDATA
RIGHT-JUSTIFIED
MODE
tDDH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 26. Serial Data Port Timing
Table 13. Allowable MCLK Frequencies and Internal Delta Clock Rates
Chip Mode
Allowable Master Clock Frequencies
Nominal Input Sample Rate (kHz)
Internal Sigma-Delta Clock Rate
INT 8× Mode 256 × fS, 384 × fS, 512 × fS, 768 × fS, 1024 × fS
INT 4× Mode 128 × fS, 192 × fS, 256 × fS, 384 × fS, 512 × fS
INT 2× Mode 64 × fS, 96 × fS, 128 × fS, 192 × fS, 256 × fS
tCHD
48
96
192
128 × fS
64 × fS
32 × fS
CDATA
D15
D14
D0
tCCH
CCLK
tCLH
tCCL
tCSU
tCLL
CLATCH
tCLSU
Figure 27. Serial Control Port Timing
The SPI CCLK signal is used to clock in the data. The incoming
data should change on the falling edge of this signal. At the end
of the 16 CCLK periods, the CLATCH signal should rise to
clock the data internally into the AD1852.
MASTER CLOCK AUTODIVIDE FEATURE
The AD1852 has a circuit that autodetects the relationship between
the master clock and the incoming serial data and internally sets
the correct divide ratio to run the interpolator and modulator. The
allowable frequencies for each mode are shown in Table 13.
Master clock should be synchronized with LRCLK; however,
phase relation between master clock and LRCLK is not critical.
The serial control port timing is shown in Figure 27, and the
SPI digital timing values are listed in Table 14.
Table 14. SPI Digital Timing
SPI REGISTER DEFINITIONS
Parameter
Description
Value
40 ns
40 ns
10 ns
10 ns
10 ns
10 ns
4 × tMCLK
The SPI port allows flexible control of many chip parameters. It
is organized around three registers: a left-channel volume register, a
right-channel volume register, and a control register. Each write
operation to the AD1852 SPI control port requires 16 bits of
serial data in MSB-first format. The bottom two bits are used to
select one of three registers, and the top 14 bits are then written
to that register. This allows a write to one of the three registers
in a single 16-bit transaction.
tCCH
tCCL
tCSU
tCHD
tCLL
tCLH
tCLSU
CCLK high pulse width
CCLK low pulse width
CDATA setup time
CDATA hold time
CLATCH low pulse width
CLATCH high pulse width
CLATCH setup time
Rev. A | Page 13 of 20
AD1852
REGISTER ADDRESSES
SPI TIMING
The lowest two bits of the 16-bit serial control data word are
decoded as the address of the register into which the upper
14 bits are written. These bits are defined in Table 15.
The SPI port is a 3-wire interface with serial data (CDATA),
serial bit clock (CCLK), and data latch (CLATCH). The data
is clocked into an internal shift register on the rising edge of
CCLK. The serial data should change on the falling edge of
CCLK and be stable on the rising edge of CCLK. The rising
edge of CLATCH is used internally to latch the parallel data
from the serial-to-parallel converter. This rising edge should be
aligned with the falling edge of the last CCLK pulse in the 16-bit
frame. The CCLK can run continuously between transactions.
Table 15. AD1852 Registers
Bit 1
Bit 0
Register
0
1
0
0
0
1
Volume left
Volume right
Control register
Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
update on the next edge of the LRCLK after the CLATCH write
pulse, as shown in Figure 27.
VOLUME LEFT AND VOLUME RIGHT REGISTERS
A write operation to the left or right volume registers activates
the autoramp, clickless volume control feature of the AD1852.
The upper 10 bits of the volume control word increment or
decrement by 1 at a rate equal to the input sample rate. The
bottom four bits are not fed into the autoramp circuit and thus
take effect immediately. This arrangement gives a worst-case
ramp time of about 20 ms for step changes of more than 60 dB,
which was determined by listening tests to be optimal in terms of
preventing the perception of a click sound on large volume
changes. See Figure 28 for a graphical description of how the
volume changes as a function of time.
MUTE
The AD1852 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal high, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Bit 6) high. The
AD1852 was designed to minimize pops and clicks when muting
and unmuting the device by automatically ramping the gain up
or down. When the device is unmuted, the volume returns to
the value set in the volume register.
The 14-bit volume control word is used to multiply the signal,
and therefore, the control characteristic is linear, not dB. A
constant dB/step characteristic can be obtained by using a
lookup table in the microprocessor that is writing to the SPI
port. The volume word is unsigned (that is, 0 dB is 11 1111
1111 1111).
0
VOLUME REQUEST REGISTER
–60
0
ACTUAL VOLUME REGISTER
–60
TIME
20ms
Figure 28. Smooth Volume Control
Rev. A | Page 14 of 20
AD1852
RESET
default values, when the
Using the
pin, the internal registers are set to their
RESET RESET
CONTROL REGISTER
pin is active low. When
Table 16 shows the functions of the control register. The control
register is addressed by having a 01 in the bottom two bits of the
16-bit SPI word. The top 14 bits are then used for the control register.
rises, the default operation is enabled. Alternatively, the internal
registers can be reset to their default values by setting Bit 7 of
the internal control register high. When Bit 7 is reset low,
default operation continues. The software reset differs from the
hardware reset because the soft reset does not affect the values
stored in the SPI registers.
DE-EMPHASIS
The AD1852 has a built-in, de-emphasis filter that can be used
to decode CDs that have been encoded with the standard Red
Book 50 μs/15 μs emphasis response curve. Three curves are
available; one each for the 32 kHz, 44.1 kHz, and 48 kHz
sampling rates. The external DEEMP pin (Pin 9) turns on the
44.1 kHz de-emphasis filter. The other filters may be selected by
writing to Control Bit 2 and Control Bit 3 in the control register.
If the SPI port is used to control the de-emphasis filter, the
external DEEMP pin should be tied low.
CONTROL SIGNALS
The IDPM0 and IDPM1 control inputs are normally connected
high or low to establish the operating state of the AD1852, as
described in Table 12. They can be changed dynamically (and
asynchronously to LRCLK and the master clock), but it is
possible that a click or pop sound will result during the
transition from one serial mode to another. If possible, the
AD1852 should be placed in mute before such a change is
made.
OUTPUT IMPEDANCE
The output impedance of the AD1852 is 65 Ω 30%.
RESET
The AD1852 may be reset either by a dedicated hardware pin
RESET
(
, Pin 24) or by software via the SPI control port. When
reset is active, normal operation of the AD1852 is suspended,
and the outputs assume midscale values. The AD1852 should
RESET
always be reset at power up. The
active for a minimum of 64 master clock periods. When the
RESET
function should be
function becomes inactive, normal operation continues
after a delay equal to the group delay, plus three MCLK periods.
Table 16. Control Register Functions
Bit Number
Function
Bit 11
INT 2× mode OR’d with Pin 7 (192/48); default = 0
INT 4× mode OR’d with Pin 10 (96/48); default = 0
Bit 10
Bit 9:8
Number of bits in right-justified serial mode
0:0 = 24
0:1 = 20
1:0 = 16
Default = 0:0
Bit 7
Reset; default = 0
Soft mute OR’d with pin; default = 0
Serial mode OR’d with mode pins; IDPM1:IDPM0
0:0 = right-justified
0:1 = I2S
Bit 6
Bit 5:4
1:0 = left-justified
1:1 = DSP mode
Default = 0:0
Bit 3:2
De-emphasis filter select
0:0 = no filter
0:1 = 44.1 kHz filter
1:0 = 32 kHz filter
1:1 = 48 kHz filter
Default = 0:0
Rev. A | Page 15 of 20
AD1852
MCLK/SR SELECT
RATE 192/48 96/48
SELECT
SPDIF
DIRECT
DIRECT
DVDD
44.1kHz TO 48kHz
88.2kHz TO 96kHz
176.4kHz TO 192kHz
0
0
1
0
1
0
R3
R2
R1
OUTPUT BUFFERS AND LP FILTERS
C9
10kΩ
10kΩ 10kΩ
JP11
AD1852 STEREO DAC
DVDD AVDD
R9
220pF
NP0
U3B
SSM2135
1.96kΩ
R8
1.96kΩ
MCLK/SR SEL
C3
C2
100nF
R16
1.87kΩ
C14
1nF
NP0
100nF
R20
200Ω
J11
LEFT
OUT
DVDD
C15
10nF
NP0
C13
1nF
NP0
DVDD
AVDD
96/48
192/48
NC
R17
1.87kΩ
I/F MODE IDPM1 IDPM0
R4
10kΩ
R5
R10
1.96kΩ
C10
220pF
NP0
OUTL+
OUTL–
OUTR+
10kΩ
RJ, 16-BIT
0
0
1
1
0
1
0
1
R11
1.96kΩ
2
I S
3RD ORDER LP BESSEL FILTER
CORNER FREQUENCY: 75kHz
GROUP DELAY: ~3.5µs
SDATA
LRCLK
SDATA
LRCLK
BCLK
RJ, 20-BIT
RJ, 24-BIT
U1
AD1852JRS
BCLK
MCLK
JP21
+AV
CC
C11
220pF
NP0
MCLK
R13
1.96kΩ
I/F
MODE
U3A
SSM2135
R12
1.96kΩ
C5
100nF
IDPM0
IDPM1
R18
1.87kΩ
C17
1nF
NP0
R21
200Ω
OUTR–
DEEMP
DEEMP
MUTE
J21
RIGHT
OUT
MUTE
C18
10nF
NP0
C16
1nF
NP0
C6
100nF
R19
1.87kΩ
CLATCH
CCLK
CLATCH
CCLK
R14
1.96kΩ
C12
220pF
NP0
R15
1.96kΩ
CDATA
CDATA
ZR
ZL
–AV
ZEROR
ZEROL
CC
FILTR
FILTB
AGND
C1
100nF
C7
10µF
RESET
DGND
RESET
AGND
DGND
C8
10µF
FB1
600Z
C4
100nF
CR1
ZERO
CR2
ZERO
LEFT
R6
221Ω
RIGHT
R7
221Ω
1
2
4
ZL
U2A
HC04
3
ZR
U2B
HC04
Figure 29. DAC, Output Buffers, and LP Filters
Rev. A | Page 16 of 20
AD1852
R5
3.01kΩ
R1
3.01kΩ
C2
270pF
L+
L–
SDATA
BCLK
SDATA
LRCLK
BCLK
R13
1.00kΩ
R2
3.01kΩ
L
L
2
0°
I S LEFT/RIGHT
DATA SEPARATOR
AND INVERTER
R17
549Ω
1
C8
1.5nF
C7
1.5nF
LRCLK
AD797
AD1852
0
R+
R3
3.01kΩ
R14
1.00kΩ
180°
R19
53.6kΩ
C5
2.2nF
R–
C2
270pF
R4
3.01kΩ
R6
3.01kΩ
R11
3.01kΩ
R7
3.01kΩ
C3
270pF
L+
L–
SDATA
LRCLK
BCLK
R
R
R8
3.01kΩ
R15
1.00kΩ
0°
R18
549Ω
MCLK
1
C9
1.5nF
C10
1.5nF
AD797
AD1852
0
R+
R9
3.01kΩ
R16
1.00kΩ
180°
R20
53.6kΩ
C6
2.2nF
R–
C4
270pF
R10
3.01kΩ
R12
3.01kΩ
LRCLK
2
I S INPUT TO
DATA SEPARATOR
Ln+1
Ln+2
Ln
Rn
Rn+1
Rn+2
SDATA
LRCLK
DATA SEPARATOR
OUTPUT
Ln
Rn
Ln+1
Rn+1
Ln+2
Rn+2
Ln
Rn
LSDATA
Ln+1
Rn+1
Ln+2
Rn+2
RDATA
Figure 30. Mono Application Circuit
Rev. A | Page 17 of 20
AD1852
OUTLINE DIMENSIONS
10.50
10.20
9.90
15
28
5.60
5.30
5.00
8.20
7.80
7.40
1
14
0.25
0.09
1.85
1.75
1.65
2.00 MAX
0.05 MIN
8°
4°
0°
0.95
0.75
0.55
0.38
0.22
SEATING
PLANE
COPLANARITY
0.10
0.65 BSC
COMPLIANT TO JEDEC STANDARDS MO-150-AH
Figure 31. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD1852JRSZ1
AD1852JRSZRL1
EVAL-AD1852EBZ1
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
Package Option
RS-28
RS-28
28-Lead Shrink Small Outline Package [SSOP]
28-Lead Shrink Small Outline Package [SSOP], 13" Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 18 of 20
AD1852
NOTES
Rev. A | Page 19 of 20
AD1852
NOTES
©2000–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08457-0-11/09(A)
Rev. A | Page 20 of 20
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