AD1862N [ADI]
Ultralow Noise 20-Bit Audio DAC; 超低噪声， 20位音频DAC
| 型号： | AD1862N |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise 20-Bit Audio DAC |
| 文件： | 总12页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise
20-Bit Audio DAC
a
AD1862*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
120 dB Signal-to-Noise Ratio
102 dB D-Range Perform ance
؎1 dB Gain Linearity
؎1 m A Output Current
16-Pin DIP Package
VOLTAGE
REFERENCE
+V
–V
–V
1
2
3
4
5
6
7
8
16
S
S
15 NR
S
2
0.0012% THD + N
TRIM
14
ADJ
APPLICATIONS
High Perform ance Com pact Disc Players
Digital Audio Am plifiers
Synthesizer Keyboards
Digital Mixing Consoles
+V
L
13 NR
1
CLK
LE
12
11
10
9
AGND
INPUT
&
DIGITAL
OFFSET
20-BIT
DAC
I
OUT
DATA
R
F
High Resolution Signal Processing
–V
L
DGND
AD1862
P RO D UCT D ESCRIP TIO N
register to the DAC input register. T he data clock can function
at 17 MHz, allowing 16 × FS operation. T he serial input port is
compatible with second-generation digital filter chips for con-
sumer audio products such as the NPC SM5813 and SM5818.
T he AD1862 is a monolithic 20-bit digital audio DAC. Each
device provides a 20-bit DAC, 20-bit serial-to-parallel input
register and voltage reference. T he digital portion of the
AD1862 is fabricated with CMOS logic elements that are pro-
vided by Analog Devices’ BiMOS II process. T he analog por-
tion of the AD1862 is fabricated with bipolar and MOS devices
as well as thin-film resistors.
T he AD1862 operates with ±5 V to ±12 V supplies for the dig-
ital power supplies and ±12 V supplies for the analog supplies.
T he digital and analog supplies can be separated for reduced
digital crosstalk. Separate analog and digital common pins are
also provided. T he AD1862 typically dissipates less than
300 mW.
New design, layout and packaging techniques all combine to
produce extremely high performance audio playback. T he de-
sign of the AD1862 incorporates a digital offset circuit which
improves low-level distortion performance. Low stress packag-
ing techniques are used to minimize stress-induced parametric
shifts. Stress-sensitive circuit elements are located in die areas
which are least affected by packaging stress. Laser-trimming of
initial linearity error affords extremely low total harmonic
distortion. Output glitch is also small, contributing to the over-
all high level of performance.
T he AD1862 is packaged in a 16-pin plastic DIP. T he operating
range is guaranteed to be –25°C to +70°C.
P RO D UCT H IGH LIGH TS
1. 120 dB signal-to-noise ratio. (typical)
2. 102 dB D-Range performance. (minimum)
3. ±1 dB gain linearity @ –90 dB amplitude.
4. 20-bit resolution provides 120 dB of dynamic range.
5. 16 × FS operation.
T he noise performance of the AD1862 is excellent. When used
with the recommended two external noise-reduction capacitors,
it achieves 120 dB signal-to-noise ratio.
6. 0.0016% T HD+N @ 0 dB signal amplitude. (typical)
7. Space saving 16-pin DIP package.
T he serial input port consists of the clock, data and latch enable
pins. A serial 20-bit, 2s complement data word is clocked into
the DAC, MSB first, by the external data clock. A latch-enable
signal transfers the input word from the internal serial input
8. ±1 mA output current.
*P r otected by U.S. P atent Num ber s: 4,349,811; 4,857,862; 4,855,618;
3,961,326; 4,141,004; 4,902,959.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(T at +25؇C and ؎12 V supplies, see Figure 10 for test circuit schematic)
AD1862–SPECIFICATIONS
A
Min
20
Typ
Max
Units
RESOLUT ION
Bits
DIGIT AL INPUT S VIH
VIL
IIH @ VIH = 4.0 V
IIL @ VIL = 0.4 V
Maximum Clock Input Frequency
2.0
4.0
0.4
V
V
µA
µA
MHz
0.8
1.0
–10
17
ACCURACY
Gain Error
Midscale Output Error
±
±
2
5
%
µA
±2
T OT AL HARMONIC DIST ORT ION + NOISE (EIAJ)1
0 dB, 990.5 Hz
AD1862N-J
AD1862N
–98 (0.0012)
–94 (0.0019)
–84 (0.0063)
–45 (0.56)
–96 (0.0016)
–92 (0.0025)
–80 (0.01)
–42 (0.8)
dB (%)
dB (%)
dB (%)
dB (%)
dB
–20 dB, 990.5 Hz AD1862N, N-J
–60 dB, 990.5 Hz AD1862N, N-J
D-Range, –60 dB, A-Weight Filter
102
SIGNAL-T O-NOISE RAT IO2: (EIAJ)1
A-Weight Filter
AD1862N-J
AD1862N
113
110
119
119
dB
dB
GAIN LINEARIT Y
@ –90 dB
AD1862N-J
AD1862N
±1
±1
dB
dB
OUT PUT CURRENT
Bipolar Range
T olerance
Output Impedance (±30%)
Settling T ime
±1
±1
2.1
350
mA
%
kΩ
ns
؎2
؎2
FEEDBACK RESIST OR
Value
T olerance
3
±1
kΩ
%
POWER SUPPLY
Voltage
Voltage
Current
VL and –VL
VS and –VS
+I, VL and VS = 12 V, 17 MHz Clock
–I, –VL and –VS = –12 V, 17 MHz Clock
4.75
10.8
12.0
12.0
11
13.2
13.2
15
±V
±V
mA
mA
13
16
POWER DISSIPAT ION
VL and VS = 12 V, –VL and –VS = –12 V, 17 MHz Clock
288
372
mW
T EMPERAT URE RANGE
Specification
Operation
+25
°C
°C
°C
–25
–60
+70
+100
Storage
NOT ES
1T est Method complies with EIAJ Standard CP-307.
2T he signal-to-noise measurement includes noise contributed by the SE5534A op amp used in the test fixture but does not include the noise contributed by the low
pass filter used in the test fixture.
Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
–2–
REV. A
AD1862
2
AD1862N-J
GAIN LINEARITY
–30
–40
–50
–60
–70
–80
–90
1
–60dB
–
1
–20dB
0dB
–
2
–
–
–
–
–
20
100
80
60
40
0
1
10
20
DIGITAL INPUT – dB
FREQUENCY – kHz
Figure 4. Gain Linearity
Figure 1. THD+N vs. Frequency
400
–30
–40
–50
–60
–70
–80
–90
350
300
–60dB
250
200
150
100
FULLSCALE
–20dB
0dB
MIDSCALE
–FULLSCALE
50
0
–25
0
25
50
75
TEMPERATURE – °C
1
10
100
1k
10k
100k
Hz
Figure 5. THD+N vs. Tem perature (1 kHz)
Figure 2. Noise Density
Figure 6. Midscale Differential Linearity
Figure 3. Broadband Noise (20 kHz Bandwidth, Midscale)
REV. A
–3–
AD1862
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ABSO LUTE MAXIMUM RATINGS*
VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +13.2 V
–VL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS to 0 V
VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +13.2 V
–VS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –13.2 to 0 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 to +0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 to VL
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage T emperature . . . . . . . . . . . . . . . . . . –60°C to +100°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1862 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO N
P IN D ESIGNATIO NS
P in
Function
D escription
+VS
16
–VS
–VS
1
2
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
10
11
12
13
14
15
16
–VS
–VS
T RIM
+VL
CLK
LE
D
–VL
DGND
RF
IOUT
AGND
NR1
ADJ
NR2
+VS
Bias Capacitor
15 NR2
14 ADJ
13 NR1
12 AGND
11 IOUT
Analog Negative Supply
T rim Pot Connection
Positive Logic Supply
External Clock Input
Latch Enable Input
Data Input
Negative Logic Supply
Digital Ground
Feedback Resistor
Output Current
Analog Ground
Reference Capacitor
Midscale Adjust
Bias Capacitor
Positive Analog Supply
TRIM
+VL
AD1862
TOP VIEW
(Not to Scale)
CLK
LE
10
9
RF
DATA
–VL
DGND
O RD ERING GUID E
O perating
Tem perature
Range
P ackage
O ption*
Model
TH D +N @ FS
SNR
AD1862N
AD1862N-J
–25°C to +70°C –92 dB, 0.0025% 110 dB
–25°C to +70°C –96 dB, 0.0016% 113 dB
N-16
N-16
*N = Plastic DIP.
–4–
REV. A
AD1862
TRIM
ADJ
TO TAL H ARMO NIC D ISTO RTIO N + NO ISE
T otal Harmonic Distortion plus Noise (T HD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the harmonics and noise to the value of the fundamental
input frequency. It is usually expressed in percent (%) or deci-
bels (dB).
NR1
FEEDBACK
REGISTER
VS
CURRENT
OUTPUT
VREF
20-BIT DAC
LATCH
NR2
AGND
+
V
L
LATCH
ENABLE
D -RANGE D ISTO RTIO N
D-Range Distortion is the ratio of the signal amplitude to the
distortion plus noise at –60 dB. In this case, an A-Weight filter
is used. T he value specified for D-Range performance is the ra-
tio measured plus 60 dB.
–
V
L
DECODER AND
DIGITAL OFFSET
CLOCK
DATA
SERIAL INPUT
REGISTER
SETTLING TIME
Settling T ime is the time required for the output to reach and
remain within ±1/2 LSB about its final value, measured from
the digital input transition. It is a primary measure of dynamic
performance and is usually expressed in nanoseconds (ns).
DGND
AD1862 Block Diagram
FUNCTIO NAL D ESCRIP TIO N
T he AD1862 is a high performance, monolithic 20-bit audio
DAC. Each device includes a voltage reference, a 20-bit DAC,
20-bit input latch and a 20-bit serial-to-parallel input register. A
special digital offset circuit, combined with segmentation cir-
cuitry, produces excellent T HD+N and D-range performance.
SIGNAL-TO -NO ISE RATIO
T he Signal-to-Noise Ratio is defined as the ratio of the ampli-
tude of the output with full-scale present to the amplitude of the
output when no signal is present. It is expressed in decibels (dB)
and measured using an A-Weight filter.
Extensive noise-reduction features are utilized to make the noise
performance of the AD1862 as high as possible. For example,
the voltage reference circuit is a low-noise, 9 volt bandgap cell.
T his cell supplies the reference voltage to the bipolar offset cir-
cuit and the DAC. An external noise-reduction capacitor is con-
nected to NR1 to form a low-pass filter network.
GAIN LINEARITY
Gain Linearity is a measure of the deviation of the actual output
amplitude from the ideal output amplitude. It is determined by
measuring the amplitude of the output signal as the amplitude
of that output signal is digitally reduced to a low level. A perfect
D/A converter exhibits no difference between the ideal and ac-
tual amplitudes. Gain linearity is expressed in decibels (dB).
Additional noise-reduction techniques are used in the control
amplifier of the DAC. By connecting an external noise-reduction
capacitor to NR2 output noise contributions from the control
portion of the DAC are similarly reduced. T he noise-reduction
efforts result in a signal-to-noise ratio of 120 dB.
MID SCALE ERRO R
Midscale Error, or bipolar zero error, is the deviation of the ac-
tual analog output from the ideal output when the 2s comple-
ment input code representing midscale is loaded in the input
register. T he AD1862 is a current output D/A converter. T here-
fore, this error is expressed in µA.
T he design of the AD1862 uses a combination of segmented de-
coder, R-2R topology and digital offset to produce low distor-
tion at all signal amplitudes. T he digital offset technique shifts
the midscale output voltage (0 V) away from the MSB transition
of the device. T herefore, small amplitude signals are not af-
fected by an MSB change. An extra DAC cell is included to
avoid clipping the output at full scale.
T he DAC supplies a ±1 mA output current to an external
I-to-V converter. An on-board 3 kΩ feedback resistor is also
supplied. Both the output current and feedback resistor are
laser-trimmed to ±2% tolerance, simplifying the selection of
external filter and/or deemphasis network components. T he in-
put register and serial-to-parallel converter are fabricated with
CMOS logic gates. T hese gates allow the achievement of fast
switching speeds and low power consumption. Internal T T L-
to-CMOS converters are used to insure T T L and 5 V CMOS
compatibility.
REV. A
–5–
AD1862
tributed by the voltage reference circuitry. The proper choice for
this capacitor is a tantalum type with value of 10 µF or more. This
capacitor should be connected to the package pins as closely as
possible. This will minimize the effects of parasitic inductance of
the leads and connections circuit connections.
Analog Circuit Considerations
GRO UND ING RECO MMEND ATIO NS
T he AD1862 has two ground pins, designated analog ground
(AGND) and digital ground (DGND). T he analog ground pin
is the “high-quality” ground reference for the device. T he ana-
log ground pin should be connected to the analog common
point in the system. T he reference bypass capacitor, the nonin-
verting terminal of the current-to-voltage conversion op amp,
and any output loads should be connected to this point. T he
digital ground pin returns ground current from the digital logic
portions of the AD1862 circuitry. T his pin should be connected
to the digital common point in the system.
16
15
14
1
2
3
C2
C1
–12V
ANALOG
SUPPLY
+
AD1862
+
13
12
11
10
9
4
5
6
TOP VIEW
(Not to
Scale)
As illustrated in Figure 7, AGND and DGND should be con-
nected together at one point in the system.
7
8
NOTE:
PIN 1 IS "HIGH QUALITY" RETURN
FOR BIAS CAP.
1
2
3
4
5
6
7
8
16
15
14
13
Figure 8. Noise Reduction Capacitors
AD1862
TOP VIEW
Capacitor C2 is connected between the pin labeled NR2 and the
negative analog supply, –VS. T his capacitor reduces the portion
of output noise contributed by the control amplifier circuitry.
C2 should be chosen to be a tantalum capacitor with a value of
about 1 µF. Again, the connections between the AD1862 and
C2 should be made as short as possible.
(Not to Scale) 12
11
10
9
AGND
DGND
T he recommended values for C1 and C2 are 10 µF and 1 µF,
respectively. T he ratio between C1 and C2 should be approxi-
mately 10. Additional noise reduction can be gained by choos-
ing slightly higher values for C1 and C2 such as 22 µF and
2.2 µF. Figure 2 illustrates the noise performance of the
AD1862 with 10 µF and 1 µF.
Figure 7. Grounding and Bypassing Recom m endations
P O WER SUP P LIES AND D ECO UP LING
T he AD1862 has four power supply input pins. ±VS provide the
supply voltages which operate the linear portions of the DAC in-
cluding the voltage reference and control amplifier. T he ±VS
supplies are designed to operate with ±12 volts.
EXTERNAL AMP LIFIER CO NNECTIO NS
T he AD1862 is a current-output D/A converter. T herefore, an
external amplifier, in combination with the on-board feedback
resistor, is required to derive an output voltage. Figure 9 illus-
trates the proper connections for an external operational ampli-
fier. T he output of the AD1862 is intended to drive the
summing junction of an external current-to-voltage conversion
op amp. T herefore, the voltage on the output current pin of the
AD1862 should be approximately the same as that on the
AGND pin of the device.
T he ±VL supplies operate the digital portions of the chip includ-
ing the input shift register, the input latching circuitry and the
T T L-to-CMOS level shifters. T he ±VL supplies are designed to
be operated from ±5 V to ±12 V supplies subject only to the
limitation that –VL may not be more negative than –VS.
Decoupling capacitors should be used on all power supply input
pins. Good engineering practice suggests that these capacitors
be placed as close as possible to the package pins and the com-
mon points. T he logic supplies, ±VL, should be decoupled to
DGND and the analog supplies, ±VS, should be decoupled to
AGND.
T he on-board 3 kΩ feedback resistor and the ±1 mA output
current typically have ±1% tolerance or less. T his makes the
choice of external components very simple and eliminates addi-
tional trimming. For example, if a user wishes to derive an out-
put voltage higher than the ±3 V swing offered by the output
current and feedback resistor combination, all that is required is
to combine a standard value resistor with the feedback resistor
to achieve the appropriate output voltage swing. T his technique
can be extended to include the choice of elements in the
deemphasis network, etc.
EXTERNAL NO ISE RED UCTIO N CO MP O NENTS
Two external capacitors are required to achieve low-noise opera-
tion. Their correct connection is illustrated in Figure 8. Capacitor
C1 is connected between the pin labeled NR1 and analog com-
mon. C1 forms a low-pass filter element which reduces noise con-
–6–
REV. A
Testing the AD1862
TO TAL H ARMO NIC D ISTO RTIO N + NO ISE
1
2
3
4
5
6
7
8
16
15
14
13
T he T HD figure of an audio DAC represents the amount of un-
desirable signal produced during reconstruction and playback of
an audio waveform. T he T HD specification, therefore, provides
a direct method to classify and choose an audio DAC for a de-
sired level of performance.
AD1862
TOP VIEW
(Not to Scale) 12
11
10
9
By combining noise measurement with the T HD measurement,
a T HD+N specification is realized. T his specification indicates
all of the undesirable signal produced by the DAC, including
harmonic products of the test tone as well as noise.
VOUT
Figure 9. External Am plifier Connections
Analog Devices tests all AD1862s on the basis of T HD+N per-
formance. In this test procedure, a digital data stream represent-
ing a 0 dB, –20 dB or –60 dB sine wave is sent to the device
under test. T he frequency of the waveform is 990.5 Hz. Input
data is sent to the AD1862 at an 8 × FS rate (352.8 kHz). T he
AD1862 under test produces an output current which is con-
verted to an output voltage by an external amplifier. Figure 10
illustrates the recommended test circuit. Deglitchers and trims
are not used during this test procedure. T he automatic test
equipment digitizes 4096 samples of the output test waveform,
incorporating 23 complete cycles of the sine wave. A 4096 point
FFT is performed on the test data.
Based upon the harmonics of the fundamental 990.5 Hz test
tone, and the noise components in the audio band, the total har-
monic distortion + noise of the device is calculated. T he
AD1862 is available in two performance grades. T he AD1862N
produces a maximum of 0.0025% T HD+N at 0 dB signal lev-
els. T he higher performance AD1862N-J produces a maximum
of 0.0016% T HD+N at 0 dB signal levels.
SIGNAL-TO -NO ISE RATIO
T he Signal-to-Noise Ratio (SNR) of the AD1862 is tested in the
following manner. T he amplitude of a 0 dB signal is measured.
T he device under test is then set to midscale output voltage (0
volts). T he amplitude of all noise present to 30 kHz is mea-
sured. T he SNR is the ratio of these two measurements. T he
SNR figure for the AD1862 includes the output noise contrib-
uted by the NE5534 op amp used in the test fixture but does
not include the noise contributed by the low-pass filter used in
the test fixture.
T he AD1862N has a minimum SNR of 110 dB. T he higher
performance AD1862N-J has a minimum SNR of 113 dB.
12V
0.1µF
1
16
1µF
0.1µF
+
–12V
12V
2
3
4
5
6
7
8
15
14
13
10µF
+
AD1862
TOP VIEW
ANALOG
COMMON
0.1µF
0.1µF
SE5534A
17MHz
(Not to Scale) 12
352.8kHz
11
10
9
3-POLE
LOW PASS
FILTER
360pF
OUTPUT
VOLTAGE
DIGITAL
COMMON
–
12V
Figure 10. Recom m ended Test Circuit
REV. A
–7–
AD1862
O P TIO NAL TRIM AD JUSTMENT
–
12V
T he AD1862 includes an external midscale adjust feature.
Should an application require improved distortion performance
under small and very small signal amplitudes (–60 dB and
lower), an adjustment is possible. T wo resistors and one poten-
tiometer form the adjustment network. Figure 11 illustrates the
correct configuration of the external components. Analog
Devices recommends that this adjustment be performed with
–60 dB signal amplitudes or lower. Minor performance im-
provement is achieved with larger signal amplitudes such as
–20 dB. Almost no improvement is possible when this adjust-
ment is performed with 0 dB signal amplitudes.
1
2
3
4
5
6
7
8
16
15
14
13
470kΩ
100kΩ
470kΩ
AD1862
TOP VIEW
(Not to Scale) 12
11
10
9
Figure 11. External Midscale Adjust
D IGITAL CIRCUIT CO NSID ERATIO NS
INP UT D ATA
clocked into the input register on the rising edge of the clock
signal (CLK). T he LSB is clocked in on the 20th clock pulse.
When all data bits are loaded, a low going latch enable (LE)
pulse updates the DAC input. Figure 12a illustrates the general
signal requirements for data transfer for the AD1862.
Data is transmitted to the AD1862 in a bit stream composed of
20-bit words with a serial, 2s complement, MSB first format.
T hree signals must be present to achieve proper operation. T hey
are the data, clock and latch enable signals. Input data bits are
MSB
LSB
WORD n+1
MSB
WORD n
DATA
CLOCK
LATCH
ENABLE
Figure 12a. Input Data
12b are compatible with the data outputs provided by popular
digital interpolation filter chips used in digital audio playback
systems. T he AD1862 input clock will run at 17 MHz allowing
data to be transferred at a rate of 16 × FS. Of course, it will also
function at slower rates such as 2 ×, 4 × or 8 × FS.
TIMING
Figure 12b illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished success-
fully. T he input pins of the AD1862 are both T T L and 5 V
CMOS compatible, independent of the power supplies used in
the application. T he input requirements illustrated in Figure
> 60ns
>25ns
>25ns
CLK
>15ns
>40ns
>60ns
>40ns
LATCH ENABLE (LE)
>40ns
INTERNAL DAC INPUT REGISTER
>15ns >15ns
UPDATED WITH 20 MOST RECENT BITS
WORD
NEXT
MSB
1st BIT
LSB
(20th BIT)
DATA
2nd BIT
BITS CLOCKED
TO SHIFT REGISTER
Figure 12b. Tim ing Requirem ents
–8–
REV. A
AD1862
T he AD1862 is an extremely high performance DAC designed
for high-end consumer and professional digital audio applica-
tions. Compact disc players, digital preamplifiers, digital musi-
cal instruments and sound processors benefit from the extended
dynamic range, low T HD+Noise and high signal-to-noise ratio.
For the first time, the D/A converter is no longer the basic limi-
tation in the performance of a CD player.
Furthermore, high-resolution signal processing and waveform
generation applications are equally well served by the AD1862.
H IGH P ERFO RMANCE CD P LAYER
Figure 13 illustrates the application of AD1862s in a high per-
formance CD player. T wo AD1862s are used, one for the left
channel and one for the right channel. T he CXD11XX chip de-
codes the digital data coming from the read electronics and
sends it to the SM5813. Input data is sent to each AD1862 by
the SM5813 digital interpolating filter. T his device operates at
8 times oversampling. T he NE5534 op amps are chosen for
current-to-voltage converters due to their low distortion and low
noise. The output filters are 5-pole designs. For the purpose of
clarity, all bypass capacitors have been omitted from the schematic.
T he performance of professional audio gear, such as mixing
consoles, digital tape recorders and multivoice synthesizers can
utilize the wide dynamic range and signal-to-noise ratio to
achieve greater performance. And, the AD1862’s space saving
16-pin package contributes to compact system design. T his per-
mits a system designer to incorporate more voices in multivoice
synthesizers, more tracks in multitrack tape recorders and more
channels in multichannel mixing consoles.
1µF
+
12V ANALOG
SUPPLY
–
–
+
V
1
2
3
4
5
6
7
8
VS 16
S
VS
NR2 15
TRIM
14
13
ADJ
NR1
10µF
+
+
V
L
LEFT
CHANNEL
OUTPUT
AGND 12
CLK
LE
LOW PASS
FILTER
11
10
9
IOUT
RF
NE5534
DATA
–
5V DIGITAL
SUPPLY
–
V
DGND
L
AD1862
–
12V ANALOG
SUPPLY
1µF
+
5V DIGITAL
SUPPLY
12V ANALOG
SUPPLY
+
1
2
3
4
5
6
7
8
–
VS 16
VS
–
V
NR2 15
ADJ 14
NR1 13
S
16.9344MHz
TRIM
10µF
CKO XTI XTO DOL
+
V
L
XTAI
SONY
+
CXD1125
LRCK
LRCI
DIN
BCKO
WCKO
DOR
RIGHT
CHANNEL
OUTPUT
AGND 12
IOUT 11
CLK
LE
1130
1135
LOW PASS
FILTER
SM5813
DATA
NE5534
BCKI
C210
10
9
DATA
RF
PSSL SLOB
OW20 CKDV
–
VL
DGND
AD1862
Figure 13. High Perform ance 20-Bit 8 × Oversam pling CD Player Application
REV. A
–9–
AD1862
H IGH -RESO LUTIO N SIGNAL P RO CESSING
Figure 14 illustrates the AD1862 combined with the DSP56000.
In high-resolution applications, the combination of the 24-bit
architecture of the DSP56000 and the low noise and high reso-
lution of the AD1862 can produce a high-resolution, low-noise
system.
depends on the sample rate of the output data. In general, the
higher the oversampling rate, the fewer number of filter poles
are required to prevent aliasing.
T he 20-bit resolution is particularly suitable for professional au-
dio, mixing or equalization equipment. Its resolution allows
24 dB of equalization to be performed on 16-bit input words
without signal truncation. Furthermore, up to sixteen 16-bit in-
put words can be mixed and output directly to the AD1862. In
this case, no loss of signal information would be encountered.
As shown in Figure 14, the clock signal supplied by the DSP
processor must be inverted to be compatible with the input of
the AD1862. T he exact architecture of the output low-pass filter
–
12V
12V
ANALOG
SUPPLY
ANALOG
SUPPLY
5V
DIGITAL
SUPPLY
0.1µF
–
–
+
1
2
3
4
5
6
7
8
VS
VS
VS 16
1µF
0.1µF
10µF
15
14
13
12
11
10
9
NR2
ADJ
TRIM
+
VL
NR1
AD846
0.1µF
VCC
SCK
SC2
CLK
LE
AGND
IOUT
LOW PASS
FILTER
OUTPUT
VOLTAGE
STD
DATA
RF
DSP56001
–
VL
DGND
–
5V
0.1µF
DIGITAL
SUPPLY
AD1862
VDD
ANALOG
COMMON
DIGITAL
COMMON
Figure 14. DSP56001 and AD1862 Produce High Resolution Signal Processing System
–10–
REV. A
AD1862
O TH ER D IGITAL AUD IO CO MP O NENTS AVAILABLE
FRO M ANALO G D EVICES
16-BIT
LATCH
16-BIT
DAC
–
+
VS
1
2
3
4
5
6
7
8
16 VS
DGND
15 TRIM
AD 1856 16-Bit Audio D AC
Complete, No External Components Required
0.0025% T HD
Low Cost
16-Pin DIP or SOIC Package
Standard Pinout
SERIAL
INPUT
REGISTER
+V
14 MSB ADJ
L
NC
CLK
LE
IOUT
13 IOUT
12 AGND
CONTROL
LOGIC
11 SJ
10 RF
DATA
–
V
9
AD1856
VOUT
L
=
NC NO CONNECT
18-BIT
LATCH
18-BIT
DAC
–
+
VS
1
2
3
4
5
6
7
8
16 VS
DGND
+VL
15 TRIM
SERIAL
INPUT
REGISTER
AD 1860 18-Bit Audio D AC
Complete, No External Components Required
0.002% T HD+N
108 dB Signal-to-Noise Ratio
16-Pin DIP or SOIC Package
14 MSB ADJ
NC
IOUT
13 IOUT
12 AGND
CLK
LE
CONTROL
LOGIC
11 SJ
10 RF
DATA
–
9
V
AD1860
VOUT
L
=
NC NO CONNECT
–
+
VS
1
2
3
4
5
6
7
8
9
24 VS
AD1864
TRIM
MSB
IOUT
23 TRIM
22 MSB
REFERENCE
REFERENCE
AD 1864 D ual 18-Bit Audio D AC
Complete, No External Components
0.002% T HD+N
115 dB Channel Separation
24-Pin DIP
IOUT
AGND
SJ
21
20
19
18
AGND
SJ
RF
RF
VOUT
17 VOUT
–
V
L
+
16
15
14
13
V
L
18-BIT
DAC
18-BIT
DAC
10
11
DR
LR
DL
18-BIT
LATCH
18-BIT
LATCH
LL
CK 12
DGND
REV. A
–11–
AD1862
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic D IP
(N-16)
–12–
REV. A
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