AD5063BRMZ1_技术文档

Fully Accurate 16-Bit V_OUTnanoDAC

SPI Interface 2.7 V to 5.5 V in an MSOP

AD5063

FUNCTIONAL BLOCK DIAGRAM

FEATURES

V

DD

Single 16-bit DAC, 1 LSB INL

REF

Power-on reset to midscale

Guaranteed monotonic by design

3 power-down functions

AD5063

POWER-ON

RESET

BUF

R

FB

INV

Low power serial interface with Schmitt-triggered inputs

10-lead MSOP, low power

REF(+)

DAC

REGISTER

V

OUT

Fast settling time of 1 μs maximum (AD5063-1 model)

2.7 V to 5.5 V power supply

Low glitch on power-up

Unbuffered voltage capable of driving 60 kΩ load

SYNC interrupt facility

AGND

INPUT

CONTROL

LOGIC

POWER-DOWN

CONTROL LOGIC

RESISTOR

NETWORK

APPLICATIONS

SYNC SCLK DIN

DACGND

Process control

Figure 1.

Data acquisition systems

Table 1. Related Devices

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

Part No.

Description

AD5061

2.7 V to 5.5 V, 16-bit nanoDAC D/A,

4 LSBs INL, SOT-23.

AD5062

2.7 V to 5.5 V, 16-bit nanoDAC D/A,

1 LSB INL, SOT-23.

AD5040/AD5060 2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A,

1 LSB INL, SOT-23.

GENERAL DESCRIPTION

that reduces the current consumption of the device to typically

300 nA at 5 V and provides software-selectable output loads

while in power-down mode. The part is put into power-down

mode via the serial interface. Total unadjusted error for the part

is <1 mV.

The AD5063, a member of ADI’s nanoDAC™ family, is a low

power, single 16-bit, unbuffered voltage-output DAC that operates

from a single 2.7 V to 5 V supply. The part offers a relative

accuracy specification of 1 ꢀLB, and operation is guaranteed

monotonic with a 1 ꢀLB DNꢀ specification. The AD5063

comes with on-board resistors in a 10-lead MLOP, allowing

bipolar signals to be generated with an output amplifier. The

part uses a versatile 3-wire serial interface that operates at

clock rates up to 30 MHz and that is compatible with standard

LPI®, QLPI™, MICROWIRE™, and DLP interface standards. The

reference for the AD5063 is supplied from an external V_REFpin.

A reference buffer is also provided on-chip. The part incor-

porates a power-on reset circuit that ensures the DAC output

powers up to midscale and remains there until a valid write to

the device takes place. The part contains a power-down feature

This part exhibits very low glitch on power-up.

PRODUCT HIGHLIGHTS

Available in 10-lead MLOP.

16-bit accurate, 1 ꢀLB INꢀ.

ꢀow glitch on power-up.

High speed serial interface with clock speeds up to 30 MHz.

Three power-down modes available to the user.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD5063

TABLE OF CONTENTS

Features .............................................................................................. 1

Lerial Interface............................................................................ 13

Input Lhift Register .................................................................... 13

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Lpecifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ELD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

DAC Architecture....................................................................... 13

Reference Buffer ......................................................................... 13

LYNC

Interrupt .......................................................................... 13

Power-On to Midscale............................................................... 14

Loftware Reset............................................................................. 14

Power-Down Modes .................................................................. 14

Microprocessor Interfacing....................................................... 14

Applications..................................................................................... 16

Choosing a Reference for the AD5063.................................... 16

Bipolar Operation Using the AD5063..................................... 16

Using the AD5063

with a Galvanically Isolated Interface Chip............................ 17

Power Lupply Bypassing and Grounding................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

8/09—Rev. B to Rev. C

Changes to Features Lection............................................................ 1

Changes to Output Voltage Lettling Time Parameter, Table 2 ... 3

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide .......................................................... 18

3/06—Rev. A to Rev. B

Updated Format..................................................................Universal

Change to Features ........................................................................... 1

Change to Figure 1 ........................................................................... 1

Changes to Lpecifications................................................................ 3

Change to Absolute Maximum Ratings......................................... 6

Change to Reference Buffer Lection ............................................ 13

Change to Lerial Interface Lection ............................................... 13

Change to Table 6 ........................................................................... 14

Change to Bipolar Operation Using the AD5063 Lection ........ 16

7/05—Rev. 0 to Rev. A

Changes to Galvanically Isolated Chip Lection.......................... 17

Changes to Figure 38...................................................................... 17

4/05—Revision 0: Initial Version

Rev. C | Page 2 of 20

AD5063

SPECIFICATIONS

V_DD= 2.7 V to 5.5 V, V_REF= 4.096 V @ V_DD= 5.0 V, R_ꢀ= unloaded, C_ꢀ= unloaded to GND; T_MINto T_MAX, unless otherwise noted.

Table 2.

B Version¹

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

16

Bits

Relative Accuracy (INL)

Total Unadjusted Error (TUE)

Differential Nonlinearity (DNL)

Gain Error

Gain Error Temperature Coefficient

Zero-Code Error

0.5

500

0.5

0.01

1

800

1

LSB

μV

LSB

% FSR

ppm FSR/°C

mV

−40°C to + 85°C, B grade over all codes

Guaranteed monotonic

T_A= −40°C to +85°C

0.02

0.05

0.1

All 0s loaded to DAC register,

T_A= −40°C to +85°C

Zero-Code Error Temperature Coefficient

Offset Error

Offset Error Temperature Coefficient

Full-Scale Error

0.05

0.5

μV/°C

mV

μV/°C

μV

0.1

T_A= −40°C to +85°C

500

800

All 1s loaded to DAC register,

T_A= −40°C to +85°C

Bipolar Resistor Matching

Bipolar Zero Offset Error

Bipolar Zero Temperature Coefficient

Bipolar Gain Error

1

Ω/Ω

LSB

ppm FSR/°C

LSB

R_FB/R_INV, R_FB= R_INV= 30 kΩ typically

8

0.5

16

32

OUTPUT CHARACTERISTICS²

Output Voltage Range

0

V_REF

V

Unipolar operation

Bipolar operation

−V_REF

Output Voltage Settling Time³

AD5063BRMZ

¼ scale to ¾ scale code transition to 1 LSB

4

μs

AD5063BRMZ-1

1

μs

V_DD= 4.5 V to 5.5 V

4

μs

V_DD= 2.7 V to 5.5 V

Output Noise Spectral Density

Output Voltage Noise

64

6

nV/√Hz

μV p-p

DAC code = midscale, 1 kHz

DAC code = midscale, 0.1 Hz to 10 Hz

bandwidth

Digital-to-Analog Glitch Impulse

Digital Feedthrough

2

nV-s

kΩ

1 LSB change around major carry

0.002

8

DC Output Impedance (Normal)

DC Output Impedance (Power-Down)

(Output Connected to 1 kΩ Network)

(Output Connected to 10 kΩ Network)

REFERENCE INPUT/OUPUT

V_REFInput Range

Input Current (Power-Down)

Input Current (Normal)

DC Input Impedance

Output impedance tolerance 10%

1

100

kΩ

Output impedance tolerance 400 Ω

Output impedance tolerance 20 kΩ

2

V_DD− 50 mV

1

μA

MΩ

Zero-scale loaded

Bipolar/unipolar operation

LOGIC INPUTS

Input Current⁴

Input Low Voltage, V_IL

1

2

0.8

μA

V

V_DD= 4.5 V to 5.5 V

V_DD= 2.7 V to 3.6 V

V_DD= 2.7 V to 5.5 V

V_DD= 2.7 V to 3.6 V

Input High Voltage, V_IH

Pin Capacitance

2.0

1.8

V

4

pF

Rev. C | Page 3 of 20

AD5063

B Version¹

Typ Max

Parameter

Min

Unit

Test Conditions/Comments

POWER REQUIREMENTS

V_DD

I_DD(Normal Mode)

V_DD= 4.5 V to 5.5 V

2.7

5.5

0.7

V

All digital inputs at 0 V or V_DD

DAC active and excluding load current

V_IN= V_DDand V_IL= GND, V_DD= 5 V,

V_REF= 4.096 V, code = midscale

V_IH= V_DDand V_IL= GND, V_DD= 3 V

0.65

0.5

mA

V_DD= 2.7 V to 3.6 V

I_DD(All Power-Down Modes)

V_DD= 4.5 V to 5.5 V

V_DD= 2.7 V to 3.6 V

1

μA

V_IH= V_DDand V_IL= GND

Power Supply Rejection Ratio (PSRR)

0.5

LSB

∆V_DD10%, V_DD= 5 V, unloaded

¹Temperature ranges for the B version: −40°C to +85°C, typical at +25°C, functional to +125°C.

²Guaranteed by design and characterization, not production tested.

³See the Ordering Guide.

⁴Total current flowing into all pins.

Rev. C | Page 4 of 20

AD5063

TIMING CHARACTERISTICS

V_DD= 2.7 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

Limit¹

Unit

Test Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge setup time

Data setup time

2

t₁

33

5

3

10

3

2

ns min

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

Data hold time

0

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to next SCLK fall ignore

12

9

¹All input signals are specified with t_R= t_F= 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

²Maximum SCLK frequency is 30 MHz.

t₄

t₂

t₁

t₉

SCLK

SYNC

t₈

t₃

t₇

t₆

t₅

DIN

D23

D22

D2

D1

D0

D23

D22

Figure 2. Timing Diagram

Rev. C | Page 5 of 20

AD5063

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

Ltresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

V_DDto GND

Digital Input Voltage to GND

V_OUTto GND

V_REFto GND

INV to GND

−0.3 V to +7.0 V

−0.3 V to V_DD+ 0.3 V

+7 V to −7 V

R_FBto GND

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Maximum Junction Temperature

MSOP Package

This device is a high performance integrated circuit with an

ELD rating of <2 kV, and it is ELD sensitive. Proper precautions

should be taken for handling and assembly.

−40°C to + 85°C¹

−65°C to +150°C

150°C

Power Dissipation

θ_JAThermal Impedance

θ_JcThermal Impedance

Reflow Soldering (Pb-Free)

Peak Temperature

Time at Peak Temperature

ESD

(T_Jmax − T_A)/θ_JA

206°C/W

44°C/W

260(0/−5)°C

10 sec to 40 sec

1.5 kV

¹Temperature range for this device is −40°C to +85°C; however, the device is

still operational at 125°C.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page 6 of 20

AD5063

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

10

DIN

SCLK

V

9

DD

SYNC

AD5063

DACGND

8

V

TOP VIEW

REF

OUT

INV

(Not to Scale)

V

7

AGND

6

R

FB

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input.

2

3

4

5

V_DD

V_REF

V_OUT

INV

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and V_DDshould be decoupled to GND.

Reference Voltage Input.

Analog Output Voltage from DAC.

Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amp’s inverting

input in bipolar mode.

6

7

8

9

R_FB

Feedback Resistor. In bipolar mode, connect this pin to the external op amp circuit.

Ground Reference Point for Analog Circuitry.

Ground Input to the DAC.

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When

SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the

following clocks. The DAC is updated following the 24^thclock cycle unless SYNC is taken high before this edge, in

which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.

AGND

DACGND

SYNC

10

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at rates of up to 30 MHz.

Rev. C | Page 7 of 20

AD5063

TYPICAL PERFORMANCE CHARACTERISTICS

1.4

1.0

0.8

0.6

0.4

0.2

0

T

= 25°C

T = 25°C

A

1.2

V

= 5V V

= 4.096V

V

= 5V V = 4.096V

DD

REF

DD

REF

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

–0.8

–1.0

–0.8

–1.0

0

10000

20000

30000

40000

50000

60000

70000

0

10000

20000

30000

40000

50000

60000

70000

DAC CODE

Figure 4. INL Error vs. DAC Code

Figure 7. DNL Error vs. DAC Code

0.10

0.08

0.06

0.04

0.02

0

1.0

0.8

T

V

= 25°C

V

= 5.5V V

= 2.7V V

= 4.096V

= 2.0V

A

DD

REF

= 5V V = 4.096V

DD

REF

0.6

MAX DNL @ V = 5.5V

DD

0.4

0.2

0

MAX DNL @ V = 2.7V

DD

–0.02

–0.04

–0.06

–0.08

–0.10

–0.2

–0.4

–0.6

–0.8

–1.0

MIN DNL @ V = 2.7V

DD

MIN DNL @ V = 5.5V

DD

0

10000

20000

30000

40000

50000

60000

70000

–40

–20

0

20

40

60

80

100

120

140

DAC CODE

TEMPERATURE (°C)

Figure 5. TUE Error vs. DAC Code

Figure 8. DNL Error vs. Temperature

1.0

1.2

1.0

V

= 5.5V V

= 2.7V V

= 4.096V

= 2.0V

DD

REF

V

= 5.5V V

= 2.7V V

= 4.096V

= 2.0V

MAX INL @ V = 2.7V

DD

REF

0.8

0.6

DD

0.8

MAX INL @ V = 5.5V

DD

MAX TUE @ 2.7V

MAX TUE @ 5.5V

0.6

0.4

0.2

MIN TUE @ 5.5V

0

MIN INL @ V = 5.5V

DD

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

MIN TUE @ 2.7V

MIN INL @ V = 2.7V

DD

–40

–20

0

20

40

60

80

100

120

140

–40

–20

0

20

40

60

80

100

120

140

TEMPERATURE (°C)

Figure 6. INL Error vs. Temperature

Figure 9. TUE Error vs. Temperature

Rev. C | Page 8 of 20

AD5063

3

2

0.25

0.20

0.15

0.10

0.05

0

V

= 5.5V V

= 2.7V V

= 4.096V

= 2.0V

T

= 25°C

DD

REF

A

1

MAX INL @ V = 5.5V

DD

MAX OFFSET @ V = 5.5V

DD

0

MAX OFFSET @ V = 2.7V

DD

–0.05

–0.10

–0.15

–0.20

–0.25

MIN INL @ V = 5.5V

DD

–1

–2

–3

–40

–20

0

20

40

60

80

100

120

140

1

2

3

4

5

6

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

Figure 13. Offset vs. Temperature

Figure 10. INL Error vs. Reference Input Voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.0

T

= 25°C

A

0.8

0.6

V

= 5.5V V = 4.096V

REF

0.4

DD

MAX DNL V = 5.5V

DD

0.2

0

= 3V V

REF

= 2.7V

–0.2

–0.4

–0.6

–0.8

–1.0

MIN DNL V = 5.5V

DD

–40

–20

0

20

40

60

80

100

120

140

1

2

3

4

5

6

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

Figure 14. Supply Current vs. Temperature

Figure 11. DNL Error vs. Reference Input Voltage

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.10

0.08

0.06

0.04

0.02

0

T

= 25°C

A

T

= 25°C

A

V

= 5.5V V

= 4.096V

= 2.5V

MAX TUE @ V = 5.5V

DD

REF

V

= 3V V

DD

REF

–0.02

–0.04

–0.06

–0.08

–0.10

MIN TUE @ V = 5.5V

DD

0

10000

20000

30000

40000

50000

60000

70000

1

2

3

4

5

6

DIGITAL INPUT CODE

REFERENCE VOLTAGE (V)

Figure 15. Supply Current vs. Digital Input Code

Figure 12. TUE Error vs. Reference Input Voltage

Rev. C | Page 9 of 20

AD5063

1.0

T

= 25°C

A

V

= 2.7V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

REF

CH3 = SCLK

CH2 = V

OUT

CH1 = TRIGGER

2.7

3.2

3.7

4.2

4.7

5.2

5.7

CH1 2V/DIV CH2 2V/DIV CH3 2V TIME BASE = 5.00μs

SUPPLY VOLTAGE (V)

Figure 16. Supply Current vs. Supply Voltage

Figure 19. Exiting Power-Down Time to Midscale

24TH CLOCK FALLING

V

= 3V

DD

DAC = FULL SCALE

= 2.7V

V

REF

= 25°C

T

A

CH1 = SCLK

CH2 = V

OUT

Y-AXIS = 2µV/DIV

X-AXIS = 4sec/DIV

CH2 50mV/DIV CH1 2V/DIV

TIME BASE 400ns/DIV

Figure 20. 0.1 Hz to 10 Hz Noise Plot

Figure 17. Digital-to-Analog Glitch Impulse (See Figure 21)

300

250

200

150

100

50

V

= 5V

DD

= 25°C

V

= 5V

DD

= 4.096V

T

A

V

REF

V

= 4.096V

REF

T

= 25°C

A

10ns/SAMPLE

FULL SCALE

MIDSCALE

ZERO SCALE

0

100

1000

10000

FREQUENCY (Hz)

100000

1000000

0

50 100 150 200 250 300 350 400 450 500

SAMPLES

Figure 18. Output Noise Spectral Density

Figure 21. Glitch Energy

Rev. C | Page 10 of 20

AD5063

0.010

0.008

0.006

0.004

0.002

0

V

= 5.5V

= 2.7V

V

= 4.096V

= 2.0V

DD

REF

V

REF

CH1 = V

DD

GAIN ERROR @ V

= 5.5V

= 2.7V

DD

–0.002

–0.004

–0.006

–0.008

–0.010

CH2 = V

OUT

GAIN ERROR @ V

DD

V

= 5V V

= 4.096V

DD

REF

RAMP RATE = 200µs

°

T

= 25 C

A

–40

–20

0

20

40

60

80

100

120

140

TEMPERATURE (°C)

CH1 2V/DIV CH2 1V/DIV TIME BASE = 100µs

Figure 22. Gain Error vs. Temperature

Figure 25. Hardware Power-Down Glitch

20

18

16

14

12

10

8

CH1 = SCLK

CH2 = SYNC

6

CH3 = V

OUT

4

2

V

T

= 5V V

= 25°C

= 4.096V

DD

REF

0

CH4 = TRIGGER

A

CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV

TIME BASE 1µs/DIV

BIN

Figure 26. Exiting Software Power-Down Glitch

Figure 23. I_DDHistogram @ V_DD= 5 V

35

30

25

20

15

10

5

0

BIN

Figure 24. I_DDHistogram @ V_DD= 3 V

Rev. C | Page 11 of 20

AD5063

TERMINOLOGY

Relative Accuracy

Total Unadjusted Error (TUE)

For the DAC, relative accuracy, or integral nonlinearity (INꢀ), is

a measure of the maximum deviation, in ꢀLB, from a straight

line passing through the endpoints of the DAC transfer

function. A typical INꢀ error vs. code plot is shown in Figure 4.

Total unadjusted error is a measure of the output error, taking

all the various errors into account. A typical TUE vs. code plot

is shown in Figure 5.

Zero-Code Error Drift

Differential Nonlinearity (DNL)

Zero-code error drift is a measure of the change in zero-code

error with a change in temperature. It is expressed in μV/°C.

Differential nonlinearity is the difference between the measured

change and the ideal 1 ꢀLB change between any two adjacent

codes. A specified differential nonlinearity of 1 ꢀLB maximum

ensures monotonicity. This DAC is guaranteed monotonic by

design. A typical DNꢀ error vs. code plot is shown in Figure 7.

Gain Error Drift

Gain error drift is a measure of the change in gain error with a

change in temperature. It is expressed in (ppm of full-scale

range)/°C.

Zero-Code Error

Digital-to-Analog Glitch Impulse

Zero-code error is a measure of the output error when zero

code (0x0000) is loaded to the DAC register. Ideally, the output

should be 0 V. The zero-code error is always positive in the

AD5063 because the output of the DAC cannot go below 0 V.

This is due to a combination of the offset errors in the DAC

and output amplifier. Zero-code error is expressed in mV.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-s

and is measured when the digital input code is changed by

1 ꢀLB at the major carry transition. Lee Figure 17 and Figure 21.

Figure 17 shows the glitch generated following completion of

the calibration routine; Figure 21 zooms in on this glitch.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded to the DAC register. Ideally, the output

should be V_DD− 1 ꢀLB. Full-scale error is expressed as a percentage

of the full-scale range.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC, but is measured when the DAC output is not updated. It

is specified in nV-s and measured with a full-scale code change

on the data bus, that is, from all 0s to all 1s, and vice versa.

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from ideal,

expressed as a percentage of the full-scale range.

Rev. C | Page 12 of 20

AD5063

THEORY OF OPERATION

The AD5063 is a single 16-bit, serial input, voltage-output DAC.

It operates from supply voltages of 2.7 V to 5.5 V. Data is

written to the AD5063 in a 24-bit word format via a 3-wire serial

interface.

The write sequence begins by bringing the

line low. Data

LYNC

from the DIN line is clocked into the 24-bit shift register on the

falling edge of LCꢀK. The serial clock frequency can be as high

as 30 MHz, making these parts compatible with high speed

DLPs. On the 24^thfalling clock edge, the last data bit is clocked

in and the programmed function is executed (that is, a change

in the DAC register contents and/or a change in the mode of

operation).

The AD5063 incorporates a power-on reset circuit that ensures

the DAC output powers up to midscale. The device also has a

software power-down mode pin that reduces the typical current

consumption to less than 1 μA.

At this stage, the

high. In either case, it must be brought high for a minimum of

12 ns before the next write sequence, so that a falling edge of

line can be kept low or be brought

LYNC

DAC ARCHITECTURE

The DAC architecture of the AD5063 consists of two matched

DAC sections. A simplified circuit diagram is shown in

Figure 27. The four MLBs of the 16-bit data-word are decoded

to drive 15 switches, E1 to E15. Each of these switches connects

one of 15 matched resistors to either the DACGND or V_REF

buffer output. The remaining 12 bits of the data-word drive

Lwitches L0 to L11 of a 12-bit voltage mode R-2R ladder

network.

can initiate the next write sequence. Because the

LYNC

buffer draws more current when V_IH= 1.8 V than it does when

_IH= 0.8 V, should be idled low between write sequences

LYNC

V

LYNC

for even lower power operation of the part. As previously indi-

cated, however, it must be brought high again just before the

next write sequence.

INPUT SHIFT REGISTER

V

OUT

2R

S1

2R

E1

2R

E2

2R

S0

The input shift register is 24 bits wide (see Figure 28). PD1

and PD0 are bits that control the operating mode of the part

(normal mode or any one of the three power-down modes).

There is a more complete description of the various modes in

the Power-Down Modes section. The next 16 bits are the data

bits. These are transferred to the DAC register on the 24^thfalling

edge of LCꢀK.

E15

S11

V

REF

12-BIT R-2R LADDER

FOUR MSBs DECODED INTO

15 EQUAL SEGMENTS

Figure 27. DAC Ladder Structure

SYNC INTERRUPT

REFERENCE BUFFER

The AD5063 operates with an external reference. The reference

input (V_REF) has an input range of 2 V to AV_DD− 50 mV. This

input voltage is used to provide a buffered reference for the

DAC core.

In a normal write sequence, the

line is kept low for at

LYNC

least 24 falling edges of LCꢀK, and the DAC is updated on the

24^thfalling edge. However, if

is brought high before the

LYNC

24^thfalling edge, it acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 31).

SERIAL INTERFACE

The AD5063 has a 3-wire serial interface (

, LCꢀK, and

LYNC

DIN) that is compatible with LPI, QLPI, and MICROWIRE

interface standards, as well as most DLPs. (Lee Figure 2 for a

timing diagram of a typical write sequence.)

DB15 (MSB)

DB0 (LSB)

0

PD1

PD0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DATA BITS

NORMAL OPERATION

THREE-STATE

0

1

0

1

0

1

100kΩ TO GND

1kΩ TO GND

POWER-DOWN MODES

Figure 28. Input Register Contents

Rev. C | Page 13 of 20

AD5063

POWER-ON TO MIDSCALE

AD5063

DAC

V

OUT

The AD5063 contains a power-on reset circuit that controls the

output voltage during power-up. The DAC register is filled with

the midscale code, and the output voltage is midscale until a

valid write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the DAC

output while it is in the process of powering up.

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Figure 29. Output Stage During Power-Down

SOFTWARE RESET

The bias generator, DAC core, and other associated linear

circuitry are all shut down when the power-down mode is

activated. However, the contents of the DAC register are unaffected

when in power-down. The time to exit power-down is typically

2.5 μs for V_DD= 5 V, and 5 μs for V_DD= 3 V (see Figure 19).

The device can be put into software reset by setting all bits in

the DAC register to 1; this includes writing 1s to Bits D23 to

D16, which is not the normal mode of operation. Note that the

interrupt command cannot be performed if a software

LYNC

reset command is started.

MICROPROCESSOR INTERFACING

AD5063 to ADSP-2101/ADSP-2103 Interface

POWER-DOWN MODES

The AD5063 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB17

and DB16) in the control register. Table 6 shows how the state

of the bits corresponds to the operating mode of the device.

Figure 30 shows a serial interface between the AD5063 and the

ADLP-2101/ADLP-2103. The ADLP-2101/ADLP-2103 should

be set up to operate in the LPORT transmit alternate framing

mode. The ADLP-2101/ADLP-2103 LPORT are programmed

through the LPORT control register and should be configured

as follows: internal clock operation, active low framing, and

16-bit word length. Transmission is initiated by writing a word

to the Tx register after the LPORT has been enabled.

Table 6. Modes of Operation for the AD5063

DB17

DB16

Operating Mode

Normal operation

Power-down mode:

Three-state

100 kΩ to GND

1 kΩ to GND

0

1

0

1

ADSP-2101/

AD5063

ADSP-2103¹

When both bits are set to 0, the part has normal power con-

sumption. However, for the three power-down modes, the

supply current falls to 200 nA at 5 V (50 nA at 3 V). Not

only does the supply current fall, but the output stage is

also internally switched from the output of the amplifier to

a resistor network of known values. This has the advantage

that the output impedance of the part is known while the part

is in power-down mode. There are three options: The output

can be connected internally to GND through either a 1 kΩ

resistor or a 100 kΩ resistor, or it can be left open-circuited

(three-stated). The output stage is illustrated in Figure 29.

TFS

DT

SYNC

DIN

SCLK

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 30. AD5063 to ADSP-2101/ADSP-2103 Interface

SCLK

SYNC

DIN

DB23

DB0

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24^THFALLING EDGE

VALID WRITE SEQUENCE:

OUTPUT UPDATES ON THE 24^THFALLING EDGE

SYNC

Figure 31.

Interrupt Facility

Rev. C | Page 14 of 20

AD5063

AD5063 to 80C51/80L51 Interface

AD5063 to 68HC11/68L11 Interface

Figure 34 shows a serial interface between the AD5063 and the

80C51/80ꢀ51 microcontroller. The setup for the interface is as

follows: TxD of the 80C51/80ꢀ51 drives LCꢀK of the AD5063,

Figure 32 shows a serial interface between the AD5063 and the

68HC11/68ꢀ11 microcontroller. LCK of the 68HC11/68ꢀ11

drives the LCꢀK pin of the AD5063, and the MOLI output

and RxD drives the serial data line of the part. The

signal

LYNC

drives the serial data line of the DAC. The

signal is

LYNC

is again derived from a bit-programmable pin on the port. In

this case, Port ꢀine P3.3 is used. When data is to be transmitted

to the AD5063, P3.3 is taken low. The 80C51/80ꢀ51 transmits

data only in 8-bit bytes; therefore, only eight falling clock edges

occur in the transmit cycle. To load data to the DAC, P3.3 is left

low after the first eight bits are transmitted, and a second write

cycle is initiated to transmit the second byte of data. P3.3 is taken

high following the completion of this cycle. The 80C51/80ꢀ51

output the serial data in a format that has the ꢀLB first. The

AD5063 requires its data with the MLB as the first bit received.

The 80C51/80ꢀ51 transmit routine should take this into

account.

derived from a port line (PC7). The setup conditions for correct

operation of this interface require that the 68HC11/68ꢀ11 be

configured so that its CPOꢀ bit is 0 and its CPHA bit is 1. When

data is being transmitted to the DAC, the

line is taken

LYNC

low (PC7). When the 68HC11/68ꢀ11 are configured with their

CPOꢀ bit set to 0 and their CPHA bit set to 1, data appearing

on the MOLI output is valid on the falling edge of LCK. Lerial

data from the 68HC11/68ꢀ11 is transmitted in 8-bit bytes with

only eight falling clock edges occurring in the transmit cycle.

Data is transmitted MLB first. To load data to the AD5063, PC7

is left low after the first eight bits are transferred, and then a

second serial write operation is performed to the DAC, with

PC7 taken high at the end of this procedure.

AD5063¹

80C51/80L51¹

68HC11/

68L11¹

AD5063¹

P3.3

SYNC

TxD

RxD

SCLK

DIN

PC7

SCK

SYNC

SCLK

DIN

MOSI

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 34. AD5063 to 80C51/80L51 Interface

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 32. AD5063 to 68HC11/68L11 Interface

AD5063 to MICROWIRE Interface

Figure 35 shows an interface between the AD5063 and any

MICROWIRE-compatible device. Lerial data is shifted out on

the falling edge of the serial clock and clocked into the AD5063

on the rising edge of the LK.

AD5063 to Blackfin® ADSP-BF53x Interface

Figure 33 shows a serial interface between the AD5063 and

the Blackfin® ADLP-BF53x microprocessor. The ADLP-BF53x

processor family incorporates two dual-channel synchronous

serial ports, LPORT1 and LPORT0, for serial and multiprocessor

communications. Using LPORT0 to connect to the AD5063, the

setup for the interface is as follows: DT0PRI drives the DIN pin

of the AD5063, TLCꢀK0 drives the LCꢀK of the part, and TFL0

AD5063¹

MICROWIRE¹

CS

SK

SO

SYNC

SCLK

DIN

drives

.

LYNC

AD5063¹

ADSP-BF53x¹

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 35. AD5063 to MICROWIRE Interface

DT0PRI

DIN

TSCLK0

TFS0

SCLK

SYNC

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 33. AD5063 to Blackfin ADSP-BF53x Interface

Rev. C | Page 15 of 20

AD5063

APPLICATIONS

Table 7. Recommended Precision References for the AD5063

CHOOSING A REFERENCE FOR THE AD5063

Initial

To achieve optimum performance of the AD5063, thought

should be given to the choice of a precision voltage reference.

The AD5063 has one reference input, V_REF. The voltage on the

reference input is used to supply the positive input to the DAC;

therefore, any error in the reference is reflected in the DAC.

Accuracy Temperature Drift 0.1 Hz to 10 Hz

Part No. (mV max) (ppm/°C max)

Noise (μV p-p typ)

ADR435

ADR425

ADR02

ADR395

2

3

5

3 (R-8)

3 (SC-70)

9 (TSOT-23)

8

3.4

10

8

There are four possible sources of error when choosing a voltage

reference for high accuracy applications: initial accuracy, ppm

drift, long-term drift, and output voltage noise. Initial accuracy

on the output voltage of the DAC leads to a full-scale error in the

DAC. To minimize these errors, a reference with high initial

accuracy is preferred. Also, choosing a reference with an output

trim adjustment, such as the ADR423, allows a system designer to

trim out system errors by setting a reference voltage to a voltage

other than the nominal. The trim adjustment can also be used at

any point within the operating temperature range to trim out error.

BIPOLAR OPERATION USING THE AD5063

The AD5063 has been designed for single-supply operation, but

a bipolar output range is also possible by using the circuit shown

in Figure 37. This circuit yields an output voltage range of 4.096 V.

Rail-to-rail operation at the amplifier output is achievable using

AD8675/AD8031/AD8032 or an OP196.

The output voltage for any input code can be calculated as

Because the supply current required by the AD5063 is extremely

low, the parts are ideal for low supply applications. The ADR395

voltage reference is recommended; it requires less than 100 μA of

quiescent current and can, therefore, drive multiple DACs in one

system, if required. It also provides very good noise performance

at 8 μV p-p in the 0.1 Hz to 10 Hz range.

⎡

⎤

⎥

⎦

D

65,536

R1+ R2

R1

R2

R1

⎛

⎜

⎞

⎟

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎜

⎝

⎞

⎟

⎠

V_O= V

×

−V

×

DD

⎢

DD

⎝

⎠

⎣

where D represents the input code in decimal (0 to 65,536).

With V_REF= 5 V, R1 = R2 = 30 kΩ

7V

10×D

65536

⎛

⎜

⎝

⎞

⎟

⎠

5V

V_O

=

−5 V

ADR395

This is an output voltage range of 5 V, with 0x0000 corresponding

to a −5 V output and 0xFFFF corresponding to a +5 V output.

SYNC

3-WIRE

SERIAL

INTERFACE

V

= 0V TO 5V

OUT

AD5063

SCLK

DIN

+4.096V

10µ

F

+5V

+

0.1

µF

0.1µF

Figure 36. ADR395 as a Reference to AD5063

R

FB

+5V

SERIAL

INTERFACE

ꢀong-term drift is a measure of how much the reference drifts

over time. A reference with a tight long-term drift specification

ensures that the overall solution remains relatively stable during

its entire lifetime. The temperature coefficient of a reference’s

output voltage affects INꢀ, DNꢀ, and TUE. A reference with a

tight temperature coefficient specification should be chosen to

reduce the temperature dependence of the DAC output voltage

on ambient conditions.

V

DD

V

REF

R

FB

INV

OUT

SYNC

DIN

R

INV

BIPOLAR

OUTPUT

SCLK

AD5063

–5V

EXTERNAL

OP AMP

AGND

DACGND

Figure 37. Bipolar Operation

In high accuracy applications, which have a relatively low

tolerance for noise, reference output voltage noise needs to be

considered. It is important to choose a reference with as low an

output noise voltage as practical for the system noise resolution

required. Precision voltage references, such as the ADR435,

produce low output noise in the 0.1 Hz to 10 Hz region. Exam-

ples of some recommended precision references for use as the

supply to the AD5063 are shown in Table 7.

Rev. C | Page 16 of 20

AD5063

POWER SUPPLY BYPASSING AND GROUNDING

USING THE AD5063 WITH A GALVANICALLY

ISOLATED INTERFACE CHIP

When accuracy is important in a circuit, it is helpful to consider

carefully the power supply and ground return layout on the

board. The printed circuit board containing the AD5063 should

have separate analog and digital sections, each on its own area

of the board. If the AD5063 is in a system where other devices

require an AGND-to-DGND connection, the connection

should be made at one point only. This ground point should be

as close as possible to the AD5063.

In process-control applications in industrial environments, it is

often necessary to use a galvanically isolated interface to protect

and isolate the controlling circuitry from hazardous common-

mode voltages that may occur in the area where the DAC is

functioning. iCoupler® provides isolation in excess of 2.5 kV.

Because the AD5063 uses a 3-wire serial logic interface, the

ADuM130x family provides an ideal digital solution for the

DAC interface.

The power supply to the AD5063 should be bypassed with

10 μF and 0.1 μF capacitors. The capacitors should physically be

as close as possible to the device, with the 0.1 μF capacitor

ideally right up against the device. The 10 μF capacitors are the

tantalum bead type. It is important that the 0.1 μF capacitor has

low effective series resistance (ELR) and low effective series

inductance (ELI), as do common ceramic types of capacitors.

This 0.1 μF capacitor provides a low impedance path to ground

for high frequencies caused by transient currents from internal

logic switching.

The ADuM130x isolators provide three independent isolation

channels in a variety of channel configurations and data rates.

They operate across the full range of 2.7 V to 5.5 V, providing

compatibility with lower voltage systems as well as enabling a

voltage translation functionality across the isolation barrier.

Figure 38 shows a typical galvanically isolated configuration

using the AD5063. The power supply to the part also needs to

be isolated; this is accomplished by using a transformer. On the

DAC side of the transformer, a 5 V regulator provides the 5 V

supply required for the AD5063.

The power supply line itself should have as large a trace as

possible to provide a low impedance path and to reduce glitch

effects on the supply line. Clocks and other fast switching

digital signals should be shielded from other parts of the board

by a digital ground. Avoid crossover of digital and analog

signals, if possible. When traces cross on opposite sides of the

board, ensure that they run at right angles to each other to

reduce feedthrough effects on the board. The best board layout

technique is the microstrip technique where the component

side of the board is dedicated to the ground plane only, and the

signal traces are placed on the solder side. However, this is not

always possible with a 2-layer board.

5V

REGULATOR

POWER

10µF

0.1µF

V

DD

SCLK

V1A

V0A

SCLK

ADMu1300

AD5063

V

OUT

SDI

V1B

V1C

V0B

V0C

SYNC

DIN

DATA

GND

Figure 38. AD5063 with a Galvanically Isolated Interface

Rev. C | Page 17 of 20

AD5063

OUTLINE DIMENSIONS

3.10

3.00

2.90

6

10

5.15

4.90

4.65

3.10

3.00

2.90

1

5

PIN 1

0.50 BSC

0.95

0.85

0.75

1.10 MAX

0.80

0.60

0.40

8°

0°

0.15

0.05

0.33

0.17

SEATING

PLANE

0.23

0.08

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 39. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD5063BRMZ¹

AD5063BRMZ-REEL7¹

AD5063BRMZ-1¹

AD5063BRMZ-1-REEL7¹

EVAL-AD5063EB

Temperature Range

−40°C to +85°C

INL

Settling Time

Package Description

10-Lead MSOP

Package Option

RM-10

Branding

D49

DCG

1 LSB 4 μs typ

1 LSB 1 μs max

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. C | Page 18 of 20

AD5063

NOTES

Rev. C | Page 19 of 20

AD5063

NOTES

registered trademarks are the property of their respective owners.

D04766-0-8/09(C)

Rev. C | Page 20 of 20


型号：	AD5063BRMZ1
厂家：	ADI
描述：	Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V in an MSOP 完全准确的16位VOUT属于nanoDAC SPI接口， 2.7 V至5.5 V采用MSOP
文件：	总20页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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