AD5065BRUZ-1REEL7 [ADI]
Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP; 完全准确的12位/ 14位/ 16位DAC VOUT SPI接口的2.7 V至5.5 V采用TSSOP
| 型号： | AD5065BRUZ-1REEL7 |
| 厂家： | 
ADI |
| 描述： | Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP |
| 文件： | 总33页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fully Accurate 12-/14-/16-Bit VOUT DAC SPI Interface
2.7 V to 5.5 V in a TSSOP
Preliminary Technical Data
AD5025/45/65
Functional Block Diagrams
FEATURES
V
V
V
DD
REFA
REFB
Low power Dual 12-/14-/16 bit DAC, 1LSB INL
Individual Voltage reference pins
Rail-to-rail operation
LDAC
INPUT
DAC
DAC A
DAC B
V
A
SCLK
SYNC
DIN
BUFFER
BUFFER
OUT
OUT
REGISTER
REGISTER
INTERFACE
LOGIC
2.7 V to 5.5 V power supply
Power-on reset to zero scale or midscale
Power down to 400 nA @ 5 V, 200 nA @ 3 V
3 power-down functions
INPUT
REGISTER
DAC
REGISTER
V
B
PDL
SDO
AD5025/AD5045R/AD5065
POWER-ON
RESET
POWER-DOWN
LOGIC
Per channel power-down
Low glitch upon power up
LDAC CLR
GND
POR
Hardware Power Down lock Out Capability
Hardware LDAC with LDAC override function
CLR Function to programmable code
SDO daisy-chaining option
Figure 1.AD5025/45/65
Table 1. Related Devices
14 lead TSSOP
Part No.
AD5666
AD5066
Description
Quad,16-bit buffered D/A,16 LSB INL, TSSOP
Quad,16-bit unbuffered D/A,1 LSB INL, TSSOP
APPLICATIONS
AD5064/44/24 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP
Process control
AD5063/62
AD5061
AD5060/40
16-bit nanoDAC, 1 LSB INL, MSOP
16-/14bit nanoDAC, 4 LSB INL, SOT-23
16-/14bit nanoDAC, 1 LSB INL, SOT-23
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
all DACs can be updated simultaneously using the
function, with the added functionality of user-selectable DAC
channels to simultaneously update. There is also an
LDAC
The AD5025/45/65 are low power, dual 12-/14-/16-bit buffered
voltage-out DACs offering relative accuracy specs of 1 LSB INL
with individual reference pins and can operate from a single 2.7
V to 5.5 V supply. The AD5025/45/65 64 parts also offer a
differential accuracy specification of 1 LSB. The parts use a
versatile 3-wire, low power Schmitt trigger serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards. The reference for the AD5025/45 and AD5065 are
supplied from an external pin. A reference buffer is also
provided on-chip. The AD5025/45/64 incorporates a power-on
reset circuit that ensures the DAC output powers up zero scale
or midscale and remains there until a valid write takes place to
the device. The AD5025/45/65 contain a power-down feature
that reduces the current consumption of the device to typically
330 nA at 5 V and provides software selectable output loads
while in power-down mode. The parts are put into power-down
mode over the serial interface. Total unadjusted error for the
parts is <2 mV.
asynchronous
that clears all DACs to a software-selectable
CLR
code—0 V, midscale, or full scale. The Part also features a power
down lockout pin , which can be used to prevent the DAC
PDL
from entering power down under any circumstances over the
serial interface.
PRODUCT HIGHLIGHTS
1. Dual channel available in 14-lead TSSOP package with
individual Voltage reference pins.
2. 12-/14-/-16 bit accurate, 1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 50 MHz.
5. Three power-down modes available to the user.
6. Reset to known output voltage (zero scale or midscale).
7. Power Down lockout capability.
Both parts exhibit very low glitch on power-up. The outputs of
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2007 Analog Devices, Inc. All rights reserved.
AD5025/45/65
Preliminary Technical Data
TABLE OF CONTENTS
REVISION HISTORY
Rev. PrB | Page 2 of 33
Preliminary Technical Data
SPECIFICATIONS
AD5025/45/65
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 2.2V ≤VREFIN ≤. VDD unless otherwise specified. All specifications TMIN to
TMAX, unless otherwise noted.
Table 2.
B Grade1
Typ
Parameter
STATIC PERFORMANCE2
Min
Max
Unit
Conditions/Comments
Resolution
16
14
12
Bits
AD5065
AD5045
AD5025
Relative Accuracy
0.5
0.5
0.5
0.5
0.5
0.5
1
1.5
1
1.5
1
1.5
1
2
LSB
LSB
LSB
AD5065 TA = -40°C to +105°C
AD5065 TA = -40°C to +125°C
AD5045 TA = -40°C to +105°C
AD5045 TA = -40°C to +125°C
AD5025 TA = -40°C to +105°C
AD5025 TA = -40°C to +125°C
AD5065/45/25: Guaranteed monotonic by design
AD5065/45/25 TA = -40°C to +105°C
AD5065/45/25 TA = -40°C to +125°C
All 0s loaded to DAC register
Differential Nonlinearity
Total Unadjusted Error Tue
LSB
mV
mV
mV
0.2
0.2
1
2
Offset Error
9
Offset Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
DC Power Supply Rejection
Ratio
2
−0.2
μV/°C
% FSR
% FSR
ppm
dB
−1
1
All 1s loaded to DAC register
2.5
–80
Of FSR/°C
VDD 10%
DC Crosstalk
0.5
0.5
0.5
LSB
Due to single-channel full-scale output change,
RL = 2 kΩ to GND or VDD
Due to load current change
LSB/m
A
LSB
Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range
0
VDD
V
Capacitive Load Stability
DC Output Impedance
(Normal mode)
1
0.5
pF
Ω
RL = 2 kΩ, RL = 100 kΩ and RL = ∞
DC Output Impedance
DAC in Power Down mode
(output connected to 100kΩ
network)
(output connected to 1kΩ
network)
100
1
kΩ
kΩ
Output impedance tolerance 20Ω
Output impedance tolerance 400Ω
Short-Circuit Current
60
45
4.5
-92
-67
mA
mA
μs
dB
dB
DAC = full scale, o/p shorted to Gnd
DAC = zero scale, o/p shorted to VDD
Coming out of power-down mode VDD = 5 V
VDD 10%, DAC = full scale
Power-Up Time
DC PSRR
Wideband SFDR
REFERENCE INPUTS
Reference Input Range
Reference Current
Reference Input Impedance
LOGIC INPUTS3
Output frequency = 10Khz
2.2
VDD
50
V
μA
KΩ
30
120
Per DAC channel VREF = VDD = 5.5 V
Per DAC channel
Input Current4
3
μA
All digital inputs
Rev. PrB | Page 3 of 33
AD5025/45/65
Preliminary Technical Data
B Grade1
Typ
Parameter
Min
Max
Unit
V
V
Conditions/Comments
VDD = 5 V
VDD = 5 V
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance
0.8
2
4
pF
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
0.4
V
ISINK = 2 mA
ISOURCE = 2 mA
VDD
1
−
High Impedance Leakage
Current
0.25 ꢀA
High Impedance Output
Capacitance
2
pF
POWER REQUIREMENTS
VDD
2.7
5.5
V
All digital inputs at 0 or VDD
DAC active, excludes load current
VIH = VDD and VIL = GND
IDD (Normal Mode)5
VDD = 4.5 V to 5.5 V
3.2
0.4
4
1
mA
μA
IDD (All Power-Down Modes)6
VDD = 4.5 V to 5.5 V
VIH = VDD and VIL = GND
1 1 Temperature range is −40°C to +105°C, typical at 25°C.
2 Linearity calculated using a reduced code range of 512 to 65,024. Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Total current flowing into all pins.
5. Interface inactive. All DACs active. DAC outputs unloaded
6. All four DACs powered down
Rev. PrB | Page 4 of 33
Preliminary Technical Data
AD5025/45/65
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREFIN =4.096V unless otherwise specified . All specifications TMIN to TMAX
,
unless otherwise noted.
Table 3.
Parameter1, 2
Min Typ
Max
Unit
Conditions/Comments3
Output Voltage Settling Time
5
μs
¼ to ¾ scale settling to 1 LSB,RL = 5kΩ single channel update
including DAC calibration sequence
Output Voltage Settling Time
14
μs
¼ to ¾ scale settling to 1 LSB,RL = 5kΩ all channel update including
DAC calibration sequence
Slew Rate
1.5
4
−90
3
0.1
0.5
6
6.5
6
V/μs
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
nV-s
Digital-to-Analog Glitch Impulse
Reference Feedthrough
SDO Feedthrough
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
AC Crosstalk
1 LSB change around major carry
VREF = 2 V 0.1 V p-p, frequency = 10 Hz to 20 MHz
Daisy-chain mode; SDO load is 10 pF
AC PSRR
TBD
340
−80
64
60
6
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
kHz
VREF = 2 V 0.2 V p-p
dB
VREF = 2 V 0.1 V p-p, frequency = 10 kHz
DAC code = 0x8400, 1 kHz
DAC code = 0x8400, 10 kHz
0.1 Hz to 10 Hz
nV/√Hz
nV/√Hz
ꢀV p-p
Output Noise
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to + 105°C, typical at 25°C.
Rev. PrB | Page 5 of 33
AD5025/45/65
Preliminary Technical Data
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 3 and
Figure 5. VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
1
t1
t2
t3
t4
20
10
10
16.5
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
us min
us min
ns min
ns min
ns min
ns min
ns min
ns min
us min
ns max
ns min
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
t5
t6
t7
5
0
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (single channel update)
Minimum SYNC high time ( all channel update)
SYNC rising edge to SCLK fall ignore
SCLK falling edge to SYNC fall ignore
LDAC pulse width low
t8
1.9
10.5
16.5
0
t8
t9
t10
t11
t12
t13
t14
t15
20
20
10
10
10.6
22
5
SCLK falling edge to LDAC rising edge
CLR pulse width low
SCLK falling edge to LDAC falling edge
CLR pulse activation time
2, 3
t16
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
PDL pulse width activation time
3
t17
3
t18
8
3
t19
0
t20
20
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2 Measured with the load circuit of Figure 16. t16 determines the maximum SCLK frequency in daisy-chain mode.
3 Daisy-chain mode only.
2mA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
50pF
2mA
I
OH
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. PrB | Page 6 of 33
Preliminary Technical Data
AD5025/45/65
Figure 3. Serial Write Operation
t1
SCLK
32
64
t18
t3
t2
t7
t4
t17
SYNC
DIN
t8
t9
DB0
DB31
DB0
DB31
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N + 1
INPUT WORD FOR DAC N
t16
DB31
DB0
SDO
UNDEFINED
t19
t11
LDAC
Figure 4. Daisy-Chain Timing Diagram
Rev. PrB | Page 7 of 33
AD5025/45/65
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
VOUT to GND
VREF to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
−40°C to +125°C
−65°C to +150°C
+150°C
Junction Temperature (TJ MAX
)
TSSOP Package
Power Dissipation
θJA Thermal Impedance
(TJ MAX − TA)/θJA
150.4°C/W
Reflow Soldering Peak Temperature
SnPb
Pb Free
240°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 8 of 33
Preliminary Technical Data
AD5025/45/65
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
14
13
12
1
2
3
4
5
6
7
LDAC
SCLK
DIN
SYNC
V
PDL
DD
AD5065/45/35
11
10
VrefA
GND
TOP VIEW
(Not to Scale)
V
B
V
A
OUT
OUT
9
8
VrefB
CLR
POR
SDO
Figure 5. 14-Lead TSSOP (RU-14)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively, this
pin can be tied permanently low.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input
shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is
taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt
and the write sequence is ignored by the device.
3
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply
should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to
GND.
4
5
6
VREFA
Dac A reference input .This is the reference voltage input pin for Dac A.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to
VDD powers up the part to midscale.
VOUT
A
POR
7
SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices
together or for reading back the data in the shift register for diagnostic purposes. The
serial data is transferred on the rising edge of SCLK and is valid on the falling edge of
the clock.
8
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low,
all LDAC pulses are ignored. When CLR is activated, the input register and the DAC
register are updated with the data contained in the CLR code register—zero,
midscale, or full scale. Default setting clears the output to 0 V.
9
VREFB
Dac B reference input .This is the reference voltage input pin for Dac B.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
The PDL pin is used to ensure hardware shutdown lockout of the device under any
circumstance. A Logic 1 at the PLO pin will cause the device to behave as normal.
The user may successfully enter software power down over the serial interface while
logic 1 is applied to the PDL pin.
10
11
12
VOUT
GND
PDL
B
If a logic 0 is applied to this pin, it will ensure that the device cannot enter software
power down under any circumstances. If the device had previously been placed in
software power down mode, a high to low transition at the PDL pin will cause the
DAC(s) to exit power down and the output the last code in the dac register before
the device entered software power down.
13
14
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the
register on the falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. Data can be transferred at rates of up to 50 MHz.
SCLK
Rev. PrB | Page 9 of 33
AD5025/45/65
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
TBD
Figure 6. INL
TBD
Figure 7. DNL
TBD
Figure 8. TUE
Rev. PrB | Page 10 of 33
Preliminary Technical Data
AD5025/45/65
TBD
Figure 9. INL vs. Reference Input Voltag
TBD
Figure 10. DNL vs. Reference Input Voltage
TBD
Figure 11. TUE vs. Reference Input Voltage
Rev. PrB | Page 11 of 33
AD5025/45/65
Preliminary Technical Data
TBD
Figure 12. Gain Error and Full-Scale Error vs. Temperature
TBD
Figure 13. Offset Error vs. Temperature
TBD
Figure 14. Gain Error and Full-Scale Error vs. Supply Voltage
Rev. PrB | Page 12 of 33
Preliminary Technical Data
AD5025/45/65
TBD
Figure 15. Zero-Scale Error and Offset Error vs. Supply Voltage
TBD
Figure 16. IDD Histogram VDD = 3.0 V
TBD
Figure 17. IDD Histogram VDD = 5.0 V
Rev. PrB | Page 13 of 33
AD5025/45/65
Preliminary Technical Data
Figure 18. Headroom at Rails vs. Source and Sink
TBD
Figure 19. Source and Sink Current Capability with VDD = 3 V
TBD
Figure 20. Source and Sink Current Capability with VDD = 5 V
Rev. PrB | Page 14 of 33
Preliminary Technical Data
AD5025/45/65
TBD
Figure 21. Supply Current vs. Code
TBD
Figure 22. Supply Current vs. Temperature
TBD
Figure 23. Supply Current vs. Supply Voltage
Rev. PrB | Page 15 of 33
AD5025/45/65
Preliminary Technical Data
Figure 24. Supply Current vs. Logic Input Voltage
Figure 25. Full-Scale Settling Time
TBD
Figure 26. Power-On Reset to 0 V
Rev. PrB | Page 16 of 33
Preliminary Technical Data
AD5025/45/65
TBD
Figure 27. Power-On Reset to Midscale
TBD
Figure 28. Exiting Power-Down to Midscale
TBD
Figure 29. Digital-to-Analog Glitch Impulse (See Figure 34)
Rev. PrB | Page 17 of 33
AD5025/45/65
Preliminary Technical Data
TBD
Figure 30. Analog Crosstalk
TBD
Figure 31. DAC-to-DAC Crosstalk
TBD
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot
Rev. PrB | Page 18 of 33
Preliminary Technical Data
AD5025/45/65
TBD
Figure 33. Typical Supply Current vs. Frequency @ 5.5 V1
TBD
Figure 34. Digital-to-Analog Glitch Energy
TBD
Figure 35. Noise Spectral Density, Internal Reference
Rev. PrB | Page 19 of 33
AD5025/45/65
Preliminary Technical Data
TBD
Figure 36. Total Harmonic Distortion
TBD
Figure 37. Settling Time vs. Capacitive Load
TBD
CLR
Figure 38. Hardware
TBD
Figure 39. Multiplying Bandwidth
Rev. PrB | Page 20 of 33
Preliminary Technical Data
AD5025/45/65
TBD
Figure 40.Typical output slew rate
Rev. PrB | Page 21 of 33
AD5025/45/65
Preliminary Technical Data
THEORY OF OPERATION
D/A SECTION
OUTPUT AMPLIFIER
The AD5025/45/65 are single 12-/14 and 16-bit, serial input,
voltage output DACs. The parts operate from supply voltages of
2.7 V to 5.5 V. Data is written to the AD5025/45/65 in a 32-bit
word format via a 3-wire serial interface. The AD5025/45 and
AD5065 incorporate a power-on reset circuit that ensures the
DAC output powers up to a known out-put state (midscale or
zero-scale, see the Ordering Guide). The devices also have a
software power-down mode that reduces the typical current
consumption to less than 1 μa.
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1,000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in (TBD) and (TBD). The slew rate is 1.5
V/μs with a ¼ to ¾ scale settling time of 10 μs.
SERIAL INTERFACE
The AD5025/45/65 has a 3-wire serial interface (
, SCLK,
SYNC
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
and DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 3 for a
timing diagram of a typical write sequence.
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT =VREFIN
×
2N
STANDALONE MODE
The ideal output voltage when using and internal reference is
given by
The write sequence begins by bringing the
line low. Data
SYNC
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5025/45/65 compatible with high
speed DSPs. On the 32nd falling clock edge, the last data bit is
clocked in and the programmed function is executed, that is, a
change in DAC register contents and/or a change in the mode
D
⎛
⎜
⎝
⎞
⎟
⎠
VOUT = 2×VREFOUT
×
2N
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register. 0 to 65,535 for AD5065 (16 bits).N = the DAC
resolution.
of operation. At this stage, the
line can be kept low or be
SYNC
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
DAC ARCHITECTURE
falling edge of
can initiate the next write sequence.
buffer draws more current when VIN = 2 V
The DAC architecture of the AD5065 consists of two matched
DAC sections. A simplified circuit diagram is shown in Figure
41. The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
15 matched resistors to either GND or VREF buffer output. The
remaining 12 bits of the data word drive switches S0 to S11 of a
12-bit voltage mode R-2R ladder network.
SYNC
Because the
SYNC
than it does when VIN = 0.8 V,
should be idled low
SYNC
between write sequences for even lower power operation of the
part. As is mentioned previously, however, must be
SYNC
brought high again just before the next write sequence.
V
OUT
2R
S1
2R
2R
E1
2R
E2
2R
2R
2R
S0
Table 7. Command Definitions
Command
E15
S11
V
REF
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
0
1
0
1
0
Write to Input Register n
Update DAC Register n
Write to Input Register n, update all
(software LDAC)
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 42. Dac Ladder Structure
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
Write to and update DAC Channel n
Power down/power up DAC
Load clear code register
REFERENCE BUFFER
The AD5025/45 and AD5065 operate with an external
reference. Each of the two onboard dac’s will have a dedicated
voltage reference pin. In either case the reference input pin has
an input range of 2 V to VDD. This input voltage is then used to
provide a buffered reference for the DAC core.
Load LDAC register
Reset (power-on reset)
Set up DCEN register (Daisy chain enable)
Set up DIO direction and Value
Reserved
Rev. PrB | Page 22 of 33
Preliminary Technical Data
AD5025/45/65
Table 8. Address Commands
Address (n)
Selected DAC
Channel
A3
0
A2
0
A1
0
A0
0
DAC A
0
0
0
1
DAC B
0
0
1
0
0
1
1
1
1
0
1
1
Reserved
Reserved
All DACs
Rev. PrB | Page 23 of 33
AD5025/45/65
Preliminary Technical Data
INTERRUPT
SYNC
INPUT SHIFT REGISTER
In a normal write sequence, the
line is kept low for at
SYNC
least 32 falling edges of SCLK, and the DAC is updated on the
32nd falling edge. However, if
is brought high before the
The AD5025/45/65 input shift register is 32 bits wide (see
Figure 43). The first four bits are don’t cares. The next four bits
are the command bits, C3 to C0 (see Table 8), followed by the 4-
bit DAC address bits, A3 to A0 (see Table 9) and finally the bit
data-word. The data-word comprises either 12-/14 or 16-bit
input code followed by 8-/6 or 4 don’t care bits for the
SYNC
32nd falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 46).
AD5025/45/65 (see Figure 43). These data bits are transferred to
the DAC register on the 32nd falling edge of SCLK.
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 43. AD5065 Input Register Content
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 44. AD5045 Input Register Content
DB31 (MSB)
DB0 (LSB)
X
X
X
X
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6
D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
DATA BITS
COMMAND BITS
ADDRESS BITS
Figure 45. AD5025 Input Register Content
SCLK
SYNC
DIN
DB31
DB0
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
SYNC
Figure 46.
Interrupt Facility
Rev. PrB | Page 24 of 33
Preliminary Technical Data
AD5025/45/65
2. If a
is generated, whilst the DAC(s) are in
PDL
DAISY-CHAINING
power down mode, then the DAC (s) will come out of
power down ( i.e. all power down registers get reset to
0000 ) to the last valid stored DAC value. As long, as
For systems that contain several DACs, or where the user
wishes to read back the DAC contents for diagnostic purposes,
the SDO pin can be used to daisy-chain several devices together
and provide serial read-back.
remains active software power down is disabled.
PDL
3. After the
is taken from a low to a high state, then
PDL
The daisy-chain mode is enabled through a software executable
DCEN (Daisy Chain Enable) command. Command 1000 is
reserved for this DCEN function (see Table 7). The daisy-chain
mode is enabled by setting a bit (DB1) in the DCEN register.
The default setting is standalone mode, where Bit DCEN = 0.
Table 9 shows how the state of the bits corresponds to the mode
of operation of the device.
all DAC channels will remain in normal mode and
the user will have to re-issue a software power down
command to the control register in order to power
down the required channels..
4. Transitioning the
from a low to a high will
PDL
disable the feature immediately.
5. if and are generated at the same time, then
PLO
CLR
The SCLK is continuously applied to the input shift register
signal will cause the dac register to change as
CLR
when
is low. If more than 32 clock pulses are applied, the
SYNC
per the Clear Content Register and then DACs will
come out of Power Down.
data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next DAC in the chain, a multi-DAC interface is
constructed. Each DAC in the system requires 32 clock pulses;
therefore, the total number of clock cycles must equal 32N,
where N is the total number of devices in the chain.
6. if
,
and
are generated at same time
PLO CLR
LDAC
then
will have higher precedence over
LDAC
this case will be same as case 2 mentioned
CLR
and
PLO
above.
7. The user is recommended to hardwire the pin to a
logic high or low thereby either enabling or disabling
the feature.
When the serial transfer to all devices is complete,
is
SYNC
taken high. This prevents any further data from being clocked
into the input shift register.
POWER-ON RESET
The AD5025/45/65 contains a power-on reset circuit that
controls the output voltage during power-up. By connecting the
POR pin low, the AD5025/45/65 output powers up to 0 V; by
connecting the POR pin high, the AD5025/45/65 output powers
up to mid-scale. The output remains powered up at this level
until a valid write sequence is made to the DAC. This is useful
in applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
There is also a software executable reset function that resets the
DAC to the power-on reset code. Command 0111 is reserved
If
is taken high before 32 clocks are clocked into the part,
SYNC
it is considered an invalid frame and the data is discarded.
The serial clock can be continuous or a gated clock. A
continuous SCLK source can be used only if the
held low for the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and
can be
SYNC
must be taken high after the final
SYNC
clock to latch the data.
for this reset function (see Table 7). Any events on
or
LDAC
POWER DOWN LOCKOUT
The AD5025/45/65 contains a 1-bit digital input pin
during power-on reset are ignored.
CLR
.
PDL
When activated, the power down lock out pin (
) disables
PDL
software shutdown under any circumstances The user should
hardwire the pin to a logic low ( thus preventing
POWER-DOWN MODES
The AD5025/45/65 contains four separate modes of operation.
Command 0100 is reserved for the power-down function (see
Table 7). These modes are software-programmable by setting
two bits, Bit DB9 and Bit DB8, in the control register (refer to
Table 12). Table 11 shows how the state of the bits corresponds
to the mode of operation of the device. Any or all DACs (DAC
A and DAC B) can be powered down to the selected mode by
setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1.
See Table 12 for the contents of the input shift register during
power-down/power-up operation.
PDL
subsequent software power down) or logic high (the part can be
placed in power down mode over the serial interface). Should
the user decide to transition the
pin from logic high to a
PDL
logic low during a valid write sequence, the device will respond
immediately and the current write sequence will be aborted.
Points to note about the
feature is that
PDL
1. if a
is generated ( i.e. a high to low transition)
PDL
while a valid write sequence is ongoing then the write
will be aborted. The user will need to re write the
current write command again.
Rev. PrB | Page 25 of 33
AD5025/45/65
Preliminary Technical Data
When both Bit DB9 and Bit DB8, in the control register are set to
0, the part works normally with its normal power consumption
of TBD at 5 V. However, for the three power-down modes, the
supply current falls to TBD at 5 V (TBD at 3 V). Not only does
the supply current fall, but the output stage is also internally
switched from the output of the amplifier to a resistor network
of known values. This has the advantage that the output
impedance of the part is known while the part is in power-
down mode. There are three different options. The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output
stage is illustrated in Figure 47.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 2.5 μs for VDD = 5 V and VDD = 3 V (see Figure 28).
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (
Low) or to the value in the
LDAC
DAC register before powering down (
high).
LDAC
Rev. PrB | Page 26 of 33
Preliminary Technical Data
AD5025/45/65
Table 9. DCEN (Daisy-Chain Enable) Register
(DB1)
(DB0)
Action
0
1
0
0
Standalone mode (default)
DCEN mode
Table 10. 32-Bit Input Shift Register Contents for Daisy-Chain Enable and Reference Set-Up Function
MSB
LSB
DB0
1/0
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
X
DB1
1
0
0
0
X
X
X
X
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
DCEN
register
Table 11. Modes of Operation
DB9
DB8
Operating Mode
Normal operation
Power-down modes
1 kΩ to GND
100 kΩ to GND
Three-state
0
0
0
1
1
1
0
1
Table 12. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function
MSB
LSB
DB31 to
DB28
DB10 to
DB19
DB4 to
DB7
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB9
DB8
DB3
DB2
DB1
DAC B
DB0
X
0
1
0
0
X
X
X
X
X
PD1
PD0
X
DAC A
X
X
Don’t
cares
Command bits (C2 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Power-down
mode
Don’t
cares
Power-down/power-up channel selection—
set bit to 1 to select
Figure 47. Output Stage During Power-Down
Rev. PrB | Page 27 of 33
AD5025/45/65
Preliminary Technical Data
updates synchronously; that is, the DAC register is updated
CLEAR CODE REGISTER
after new data is read, regardless of the state of the
pin.
LDAC
The AD5025/45/65 has a hardware
asynchronous clear input. The
pin that is an
input is falling edge
CLR
It effectively sees the
pin as being tied low. (See Table 15
LDAC
CLR
for the
register mode of operation.) This flexibility is
LDAC
sensitive. Bringing the
line low clears the contents of the
CLR
input register and the DAC registers to the data contained in the
user-configurable register and sets the analog outputs
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
CLR
accordingly. (see Table 13) This function can be used in system
calibration to load zero scale, midscale, or full scale to all
channels together. These clear code values are user-
programmable by setting two bits, Bit DB1 and Bit DB0, in the
control register (see Table 13). The default setting clears the
outputs to 0 V. Command 0101 is reserved for loading the clear
code register (see Table 7).
Writing to the DAC using command 0110 loads the 4-bit
LDAC
register (DB3 to DB0). The default for each channel is 0; that is,
the pin works normally. Setting the bits to 1 means the
LDAC
DAC channel is updated regardless of the state of the
LDAC
pin. See Table 16 for the contents of the input shift register
during the load register mode of operation.
LDAC
The part exits clear code mode on the 32nd falling edge of the
POWER SUPPLY BYPASSING AND GROUNDING
next write to the part. If
is activated during a write
CLR
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5666 should
have separate analog and digital sections. If the AD5666 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5025/45/65.
sequence, the write is aborted.
The pulse activation time—the falling edge of
to when
CLR
CLR
the output starts to change—is typically TBD ns. However, if
outside the DAC linear region, it typically takes TBD ns after
executing
for the output to start changing (see Figure 38).
CLR
See Table 14 for contents of the input shift register during the
loading clear code register operation
The power supply to the AD5025/45/65 should be bypassed with
10 μF and 0.1 μF capacitors. The capacitors should physically be
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and low effective series
inductance (ESI), such as is typical of common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
FUNCTION
LDAC
The outputs of all DACs can be updated simultaneously using
the hardware
pin.
LDAC
Synchronous
: After new data is read, the DAC registers
LDAC
are updated on the falling edge of the 32nd SCLK pulse.
can be permanently low or pulsed as in Figure 3
LDAC
Asynchronous
: The outputs are not updated at the same
LDAC
time that the input registers are written to. When
low, the DAC registers are updated with the contents of the
input register.
goes
LDAC
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique, where the component side of the
board is dedicated to the ground plane only and the signal
traces are placed on the solder side. However, this is not always
possible with a 2-layer board.
Alternatively, the outputs of all DACs can be updated
simultaneously using the software
function by writing to
LDAC
Input Register n and updating all DAC registers. Command
0010 is reserved for this software function.
LDAC
register gives the user extra flexibility and control
An
LDAC
over the hardware
pin. This register allows the user to
LDAC
select which combination of channels to simultaneously update
when the hardware pin is executed. Setting the bit
LDAC
register to 0 for a DAC channel means that this channel’s update
is controlled by the pin. If this bit is set to 1, this channel
LDAC
LDAC
Rev. PrB | Page 28 of 33
Preliminary Technical Data
AD5025/45/65
Table 13. Clear Code Register
Clear Code Register
DB1
CR1
0
DB0
CR0
0
Clears to Code
0x0000
0
1
0x8000
1
0
0xFFFF
1
1
No operation
Table 14. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
LSB
DB31 to DB28
X
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB2 to DB19
X
DB1
DB0
0
1
0
1
X
X
X
X
1/0
1/0
Don’t cares
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t cares
Clear code register
(CR1 to CR0)
Table 15.
Overwrite Definition
LDAC
Load DAC Register
LDAC Bits (DB3 to DB0)
LDAC Pin
1/0
LDAC Operation
0
1
Determined by LDAC pin
DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0.
X—don’t care
Table 16. 32-Bit Input Shift Register Contents for
Overwrite Function
LDAC
MSB
LSB
DB31
to
DB4
to
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB3
DB2
X
DB1
DAC B
DB0
X
0
1
1
0
X
X
X
X
X
X
DAC A
Don’t
cares
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
LDAC
LDAC
bit to 1 override pin
Setting
Rev. PrB | Page 29 of 33
AD5025/45/65
Preliminary Technical Data
serial write operation is performed to the DAC. PC7 is taken
high at the end of this procedure.
MICROPROCESSOR INTERFACING
AD5025/45/65 to Blackfin® ADSP-BF53X Interface
AD5024/44/64 to 80C51/80L51 Interface
Figure 48 shows a serial interface between the AD5025/45/65
and the Blackfin ADSP-BF53X microprocessor. The ADSP-
BF53X processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5025/45/65, the setup for the interface is as follows:
DT0PRI drives the DIN pin of the AD5025/45/65, while
Figure 50 shows a serial interface between the AD5024/44/64
and the 80C51/80L51 microcontroller. The setup for the
interface is as follows: TxD of the 80C51/ 80L51 drives SCLK of
the AD5025/45/65, and RxD drives the serial data line of the
SYNC
part. The
signal is again derived from a bit-programmable
pin on the port. In this case, Port Line P3.3 is used. When data is
to be transmitted to the AD5025/45/65, P3.3 is taken low. The
80C51/80L51 transmit data in 8-bit bytes only; thus, only eight
falling clock edges occur in the transmit cycle. To load data to
the DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this
cycle. The 80C51/80L51 output the serial data in a format that
has the LSB first. The AD5025/45/65 must receive data with the
MSB first. The 80C51/80L51 transmit routine should take this
into account.
SYNC
TSCLK0 drives the SCLK of the parts. The
TFS0.
is driven from
AD5065/
AD5045/
AD5025
1
ADSP-BF53x
1
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AD5065/
1
80C51/80L51
AD5045/
AD5025
SYNC
Figure 48. AD5025/45/65 to Blackfin ADSP-BF53X Interface
1
P3.3
TxD
RxD
AD5025/45/65 to 68HC11/68L11 Interface
Figure 49 shows a serial interface between the AD5025/45/65
and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5025/45/65, and the
MOSI output drives the serial data line of the DAC.
SCLK
DIN
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 50. AD5025/45/65 to 80C512/80L51 Interface
AD5065/
AD5045/
AD5025/
1
68HC11/68L11
1
AD5025/45/65 to MICROWIRE Interface
PC7
SCK
SYNC
SCLK
DIN
Figure 51 shows an interface between the AD5025/45/65 and any
MICROWIRE-compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the
MOSI
AD5025/45/65 on the rising edge of the SCLK.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 49. AD5025/45/65 to 68HC11/68L11 Interface
AD5065/
1
MICROWIRE
AD5045/
1
AD5025
SYNC
CS
SK
SO
SYNC
The
signal is derived from a port line (PC7). The setup
DIN
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SCLK
SYNC
line is taken low (PC7). When the 68HC11/ 68L11 is
1
ADDITIONAL PINS OMITTED FOR CLARITY.
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5025/45/65, PC7
is left low after the first eight bits are transferred, and a second
Figure 51. AD5025/45/654 to MICROWIRE Interface
Rev. PrB | Page 30 of 33
Preliminary Technical Data
APPLICATIONS
AD5025/45/65
This is an output voltage range of 5 V, with 0x0000 corre-
sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD5025/45/65
Because the supply current required by the AD5025/45/65 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the parts (see Figure 52). This is
especially useful if the power supply is quite noisy or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5025, AD5045 and AD5065. If the low
dropout REF195 is used, it must supply 500 μA of current to the
AD5025/ AD5045 / AD5065, with no load on the output of the
DAC. When the DAC output is loaded, the REF195 also needs
to supply the current to the load. The total current required
(with a 5 kΩ load on the DAC output) is
R2 = 10kΩ
+5V
+5V
R1 = 10kΩ
AD820/
OP295
±5V
V
V
OUT
DD
10µF
0.1µF
AD5025/45/65
–5V
THREE-WIRE
SERIAL
INTERFACE
500 μA + (5 V/5 kΩ) = 1.5 mA
Figure 53. Bipolar Operation with the AD5025/45/65
The load regulation of the REF195 is typically 2 ppm/mA,
which results in a 3 ppm (15 μV) error for the 1.5 mA current
drawn from it. This corresponds to a 0.196 LSB error.
USING THE AD5025/45/65 WITH A
GALVANICALLY ISOLATED INTERFACE
In process control applications in industrial environments,
it is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that can occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5025/45/65 uses a 3-wire serial logic interface,
so the ADuM1300 three-channel digital isolator provides the
required isolation (see Figure 54). The power supply to the part
also needs to be isolated, which is done by using a transformer.
On the DAC side of the transformer, a 5 V regulator provides
the 5 V supply required for the AD5025/45/65.
15V
5V
REF195
V
DD
SYNC
SCLK
DIN
THREE-WIRE
SERIAL
INTERFACE
AD5065/
AD5045/
AD5025
V
= 0V TO 5V
OUT
Figure 52. REF195 as Power Supply to the AD5025/45/65
5V
REGULATOR
BIPOLAR OPERATION USING THE AD5025/45/65
10µF
0.1µF
POWER
The AD5025/45/65 has been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 53. The circuit gives an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
V
DD
SCLK
V
V
V
V
OA
SCLK
IA
ADuM1300
AD5025/45/65
The output voltage for any input code can be calculated as
follows:
V
SDI
OUT
SYNC
V
IB
OB
OC
⎡
⎤
⎥
⎦
D
65,536
R1+ R2
R1
R2
R1
⎛
⎜
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
V = V
×
×
− V
×
⎢
O
DD
DD
⎝
⎠
V
⎣
DATA
DIN
IC
GND
where D represents the input code in decimal (0 to 65,535).
With VDD = 5 V, R1 = R2 = 10 kΩ,
Figure 54. AD5025/45/65 with a Galvanically Isolated Interface
10 × D
65,536
⎛
⎜
⎞
⎟
V =
− 5 V
O
⎝
⎠
Rev. PrB | Page 31 of 33
AD5025/45/65
Preliminary Technical Data
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65
BSC
1.05
1.00
0.80
0.20
0.09
1.20
MAX
0.75
0.60
0.45
8°
0°
0.15
0.05
0.30
0.19
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 55. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. PrB | Page 32 of 33
Preliminary Technical Data
AD5025/45/65
ORDERING GUIDE
Package
Option
Power-On
Reset to Code
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
14-Lead TSSOP
14-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation board
Evaluation board
Evaluation board
Accuracy
Resolution
16 bits
16 bits
14 bits
14 bits
12 bits
12 bits
AD5065BRUZ-11
AD5065BRUZ-1REEL71
AD5045BRUZ1
RU-14
RU-14
RU-16
RU-16
RU-16
RU-16
Zero
Zero
Zero
Zero
Zero
Zero
1 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
1 LSB INL
AD5045BRUZ-REEL71
AD5025BRUZ1
AD5025BRUZ-REEL71
Eval-AD5065 EBZ1
Eval-AD5045 EBZ1
Eval-AD5025 EBZ1
1 Z = Pb-free part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06844-0-6/07(PrB)
Rev. PrB | Page 33 of 33
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