AD5162BRM50-R2 [ADI]
IC DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer;
| 型号： | AD5162BRM50-R2 |
| 厂家： | 
ADI |
| 描述： | IC DUAL 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10, 3 X 4.90 MM, MO-187BA, MSOP-10, Digital Potentiometer 光电二极管 转换器 电阻器 |
| 文件： | 总20页 (文件大小：783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 256-Position SPI
Digital Potentiometer
AD5162
FEATURES
2-channel, 256-position
FUNCTIONAL BLOCK DIAGRAM
A1
W1
B1
W2
B2
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Fast settling time: tS = 5 µs typical on power-up
Full read/write of wiper register
Power-on preset to midscale
V
DD
WIPER
REGISTER 1
WIPER
REGISTER 2
Extra package address decode pin AD0
GND
Computer software replaces µC in factory programming
applications
A = 0
A = 1
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 µA max
AD5162
CLK
SDI
CS
SPI INTERFACE
Wide operating temperature: −40°C to +125°C
Evaluation board available
Figure 1.
APPLICATIONS
Systems calibrations
Electronics level settings
Mechanical Trimmers® replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5162 provides a compact 3 mm × 4.9 mm packaged
solution for dual 256-position adjustment applications. This
device performs the same electronic adjustment function as a
3-terminal mechanical potentiometer. Available in four different
end-to-end resistance values (2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ),
this low temperature coefficient device is ideal for high accu-
racy and stability variable resistance adjustments. The wiper
settings are controllable through an SPI digital interface. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code
transferred into the RDAC1 latch.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 µA allows the AD5162 to be used in portable
battery-operated applications.
For applications that program the AD5162 at the factory,
Analog Devices offers device programming software running
on Windows® NT/2000/XP operating systems. This software
effectively replaces any external SPI controllers, which in turn
enhances users’ systems time-to-market. An AD5162 evaluation
kit and software are available. The kit includes a cable and
instruction manual.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD5162
TABLE OF CONTENTS
Electrical Characteristics—2.5 kΩ Version................................... 3
Programming the Potentiometer Divider............................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 15
Constant Bias to Retain Resistance Setting............................. 15
Evaluation Board........................................................................ 15
SPI Interface .................................................................................... 16
SPI Compatible 3-Wire Serial Bus ........................................... 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics—All Versions ........................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Pin Configuration......................................................................... 7
Pin Function Descriptions .......................................................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor and Voltage.................... 13
REVISION HISTORY
11/03 Changed from REV. 0 to REV. A:
Changes to Electrical Characteristics.................................... Page 3
11/03 Revision 0: Initial Version
Rev. A | Page 2 of 20
AD5162
ELECTRICAL CHARACTERISTICS—2.5 kΩ VERSION
Table 1. VDD = 5 V 10ꢀ, or 3 V 10ꢀ% VA = +VDD% VB = 0 V% −40°C < TA < +125°C% unless otherwise noted
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
R-DNL
R-INL
∆RAB
RWB, VA = no connect
RWB, VA = no connect
TA = 27°C
−2
−6
−20
0.1
0.ꢀ7
+2
+6
+77
LSB
LSB
%
(∆RAB/RAB )/∆T VAB = VDD, wiper = no connect
RWB Code = 0x00, VDD = 7 V
37
160
ppm/°C
Ω
200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4
Integral Nonlinearity
DNL
INL
−1.7
−2
0.1
0.6
+1.7
+2
LSB
LSB
Voltage Divider Temperature
Coefficient
(∆VW/VW)/∆T
Code = 0x80
17
ppm/°C
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range7
VWFSE
VWZSE
Code = 0xFF
Code = 0x00
−10
0
−2.7
2
0
10
LSB
LSB
VA, B, W
CA, B
GND
VDD
V
pF
Capacitance6 A, B
f = 1 MHz, measured to GND, Code =
0x80
f = 1 MHz, measured to GND, Code =
0x80
47
60
1
Capacitance6 W
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance6
VA = VB = VDD/2
nA
VIH
VIL
VIH
VIL
IIL
VDD = 7 V
VDD = 7 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
1
VIN = 0 V or 7 V
CIL
7
POWER SUPPLIES
Power Supply Range
Supply Current
VDD RANGE
IDD
PDISS
2.ꢀ
7.7
6
30
V
VIH = 7 V or VIL = 0 V
VIH = 7 V or VIL = 0 V, VDD = 7 V
VDD = 7 V 10%, Code = midscale
3.7
µA
µW
%/%
Power Dissipationꢀ
Power Supply Sensitivity
PSS
0.02
0.08
DYNAMIC CHARACTERISTICS8
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
BW_2.7 K
THDW
tS
Code = 0x80
4.8
0.1
1
MHz
%
µs
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 7 V, VB = 0 V, 1 LSB error band
RWB = 1.27 kΩ, RS = 0
Resistor Noise Voltage Density
See notes at end of section.
eN_WB
3.2
nV/√Hz
Rev. A | Page 3 of 20
AD5162
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
Table 2. VDD = 5 V 10ꢀ, or 3 V 10ꢀ% VA = VDD% VB = 0 V% −40°C < TA < 125°C% unless otherwise noted
Parameter
Symbol
Conditions
Min Typ1
Max
Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2
Resistor Integral Nonlinearity2
Nominal Resistor Tolerance3
Resistance Temperature Coefficient
RWB (Wiper Resistance)
R-DNL
R-INL
RWB, VA = no connect
RWB, VA = no connect
TA = 27°C
−1
−2.7
−20
0.1
0.27
+1
+2.7
+20
LSB
LSB
%
∆RAB
(∆RAB/RAB )/∆T
RWB
VAB = VDD, wiper = no connect
Code = 0x00, VDD = 7 V
37
160
ppm/°C
Ω
200
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity4
Integral Nonlinearity4
Voltage Divider Temperature Coefficient
Full-Scale Error
DNL
INL
(∆VW/VW)/∆T
VWFSE
VWZSE
−1
−1
0.1
0.3
17
+1
+1
LSB
LSB
ppm/°C
LSB
LSB
Code = 0x80
Code = 0xFF
Code = 0x00
−2.7 −1
0
0
2.7
Zero-Scale Error
1
RESISTOR TERMINALS
Voltage Range7
VA,B,W
CA,B
GND
VDD
V
pF
Capacitance6 A, B
f = 1 MHz, measured to GND,
Code = 0x80
f = 1 MHz, measured to GND,
Code = 0x80
47
60
1
Capacitance6 W
CW
ICM
pF
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
POWER SUPPLIES
VA = VB = VDD/2
nA
VIH
VIL
VIH
VIL
IIL
VDD = 7 V
VDD = 7 V
VDD = 3 V
VDD = 3 V
2.4
2.1
V
V
V
V
µA
pF
0.8
0.6
1
VIN = 0 V or 7 V
CIL
7
Power Supply Range
Supply Current
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD
PDISS
2.ꢀ
7.7
6
30
V
µA
µW
VIH = 7 V or VIL = 0 V
VIH = 7 V or VIL = 0 V, VDD = 7 V
VDD = 7 V 10%, Code =
midscale
3.7
PSS
0.02
0.08 %/%
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB
BW
RAB = 10 kΩ/70 kΩ/100 kΩ,
Code = 0x80
VA = 1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kΩ
VA = 7 V, VB = 0 V,
1 LSB error band
600/100/40
kHz
%
Total Harmonic Distortion
THDW
tS
0.1
2
VW Settling Time (10 kΩ/70 kΩ/100 kΩ)
µs
Resistor Noise Voltage Density
eN_WB
RWB = 7 kΩ, RS = 0
9
nV/√Hz
See notes at end of section.
Rev. A | Page 4 of 20
AD5162
TIMING CHARACTERISTICS—ALL VERSIONS
Table 3. VDD = +5 V 10ꢀ, or +3 V 10ꢀ% VA = VDD% VB = 0 V% −40°C < TA < +125°C% unless otherwise noted
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
SPI INTERFACE TIMING CHARACTERISTICS9 (Specifications Apply to All Parts)
Clock Frequency
Input Clock Pulse Width
Data Setup Time
fCLK
tCH, tCL
tDS
27
MHz
ns
ns
Clock level high or low
20
7
Data Hold Time
tDH
7
ns
CS Setup Time
tCSS
17
40
0
ns
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
tCSW
tCSH0
tCSH1
tCS1
ns
ns
0
ns
CS Rise to Clock Rise Setup
10
ns
See notes at end of section.
NOTES
1 Typical specifications represent average readings at 27°C and VDD = 7 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC converter. VA = VDD and VB = 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
7 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
ꢀPDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8All dynamic characteristics use VDD = 7 V.
9See timing diagrams for locations of measured values.
Rev. A | Page 7 of 20
AD5162
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Value
VDD to GND
VA, VB, VW to GND
–0.3 V to +ꢀ V
VDD
Terminal Current, Ax to Bx, Ax to Wx,
Bx to Wx1
Pulsed
Continuous
20 mA
7 mA
Digital Inputs and Output Voltage to GND 0 V to ꢀ V
Operating Temperature Range
Maximum Junction Temperature (TJMAX
Storage Temperature
Lead Temperature (Soldering, 10 s)
Thermal Resistance2 θJA: MSOP-10
–40°C to +127°C
170°C
–67°C to +170°C
300°C
230°C/W
)
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX − TA)/θJA
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 20
AD5162
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Table 5.
1
10
9
W1
B2
B1
Pin
No.
2
A1
Mnemonic Description
3
8
W2
AD5162
CS
1
2
3
4
7
6
B1
A1
W2
GND
VDD
CLK
B1 Terminal.
A1 Terminal.
W2 Terminal.
Digital Ground.
Positive Power Supply.
TOP VIEW
7
4
5
GND
SDI
CLK
6
V
DD
Figure 2.
Serial Clock Input. Positive edge
triggered.
ꢀ
8
SDI
CS
Serial Data Input.
Chip Select Input, Active Low. When CS
returns high, data is loaded into the DAC
register.
9
10
B2
W1
B2 Terminal.
W1 Terminal.
Rev. A | Page ꢀ of 20
AD5162
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
0.5
0.4
T
R
= 25°C
R
= 10kΩ
A
AB
= 10kΩ
AB
1.5
1.0
0.3
V
= 2.7V
DD
0.2
0.5
0.1
V
= 2.7V; T = –40°C, +25°C, +85°C, +125°C
A
DD
0
0
V
= 5.5V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
–1.0
–1.5
–2.0
0
0
0
32
64
96
128
160
192
224
256
0
0
0
32
32
32
64
96
128
160
192
224
256
256
256
CODE (DECIMAL)
CODE (DECIMAL)
Figure 3. R-INL vs. Code vs. Supply Voltages
Figure 6. DNL vs. Code vs. Temperature
0.5
0.4
1.0
0.8
T
R
= 25°C
T
R
= 25°C
= 10kΩ
A
A
= 10kΩ
AB
AB
0.3
0.6
0.2
0.4
V
= 2.7V
DD
V
= 5.5V
0.1
0.2
DD
0
0
V
= 2.7V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 5.5V
DD
32
64
96
128
160
192
224
256
64
96
128
160
192
224
CODE (DECIMAL)
CODE (DECIMAL)
Figure 4. R-DNL vs. Code vs. Supply Voltages
Figure 7. INL vs. Code vs. Supply Voltages
0.5
0.4
0.5
0.4
R
= 10kΩ
T
R
= 25°C
= 10kΩ
AB
A
AB
0.3
0.3
V
= 5.5V
DD
T
= –40°C, +25°C, +85°C, +125°C
A
0.2
0.2
0.1
0.1
V
= 2.7V
DD
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
V
= 5.5V
DD
V
= 2.7V
DD
T
= –40°C, +25°C, +85°C, +125°C
A
32
64
96
128
160
192
224
256
64
96
128
160
192
224
CODE (DECIMAL)
CODE (DECIMAL)
Figure 5. INL vs. Code vs. Temperature
Figure 8. DNL vs. Code vs. Supply Voltages
Rev. A | Page 8 of 20
AD5162
2.0
1.5
4.50
3.75
3.00
2.25
1.50
0.75
0
R
= 10kΩ
R
= 10kΩ
AB
AB
V
= 2.7V
DD
= –40°C, +25°C, +85°C, +125°C
T
A
1.0
0.5
0
V
= 2.7V, V = 2.7V
A
DD
V
= 5.5V
DD
= –40°C, +25°C, +85°C, +125°C
–0.5
–1.0
–1.5
–2.0
T
A
V
= 5.5V, V = 5.0V
A
DD
0
32
64
96
128
160
192
224
256
–40 –25 –10
5
20
35
50
65
80
95 110 125
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 9. R-INL vs. Code vs. Temperature
Figure 12. Zero-Scale Error vs. Temperature
0.5
0.4
10
R
= 10kΩ
AB
0.3
V
V
= 5V
DD
0.2
V
= 2.7V, 5.5V; T = –40°C, +25°C, +85°C, +125°C
A
DD
0.1
0
1
–0.1
–0.2
–0.3
–0.4
–0.5
= 3V
DD
0.1
–40
0
32
64
96
128
160
192
224
256
–7
26
59
92
125
TEMPERATURE (°C)
CODE (DECIMAL)
Figure 10. R-DNL vs. Code vs. Temperature
Figure 13. Supply Current vs. Temperature
120
100
80
2.0
1.5
R
= 10kΩ
R
= 10kΩ
AB
AB
1.0
0.5
60
V
= 2.7V
DD
= –40°C TO +85°C, –40°C TO +125°C
T
A
0
V
= 5.5V, V = 5.0V
A
DD
40
V
= 5.5V
DD
= –40°C TO +85°C, –40°C TO +125°C
–0.5
–1.0
–1.5
–2.0
T
A
20
V
= 2.7V, V = 2.7V
A
DD
0
–20
0
32
64
96
128
160
192
224
256
–40 –25 –10
5
20
35
50
65
80
95 110 125
CODE (DECIMAL)
TEMPERATURE (°C)
Figure 14. Rheostat Mode Tempco ∆RWB/∆T vs. Code
Figure 11. Full-Scale Error vs. Temperature
Rev. A | Page 9 of 20
AD5162
50
0
–6
R
= 10kΩ
AB
0x80
0x40
0x20
0x10
40
–12
–18
–24
–30
–36
–42
–48
–54
–60
30
V
T
= 2.7V
DD
= –40°C TO +85°C, –40°C TO +125°C
20
A
0x08
0x04
0x02
0x01
10
0
–10
–20
V
= 5.5V
DD
= –40°C TO +85°C, –40°C TO +125°C
T
A
–30
0
32
64
96
128
160
192
224
256
1k
10k
100k
1M
CODE (DECIMAL)
FREQUENCY (Hz)
Figure 15. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
–6
0
–6
0x80
0x80
0x40
0x20
0x40
0x20
0x10
–12
–18
–24
–30
–36
–42
–48
–54
–60
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x10
0x08
0x04
0x02
0x01
0x08
0x04
0x02 0x01
10k
100k
FREQUENCY (Hz)
1M
10M
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 16. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ
0
–6
0
–6
0x80
0x40
–12
–18
–24
–30
–36
–42
–48
–54
–60
–12
–18
–24
–30
–36
–42
–48
–54
–60
100kΩ
60kHz
50kΩ
0x20
0x10
0x08
0x04
120kHz
10kΩ
570kHz
2.5kΩ
2.2MHz
0x02
0x01
1k
10k
100k
FREQUENCY (Hz)
1M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ
Figure 20. –3 dB Bandwidth @ Code = 0x80
Rev. A | Page 10 of 20
AD5162
10
T
= 25°C
A
1
V
= 5.5V
DD
V
V
W2
0.1
0.01
V
= 2.7V
DD
W1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIGITAL INPUT VOLTAGE (V)
Figure 21. IDD vs. Input Voltage
Figure 24. Analog Crosstalk
Figure 25. Midscale Glitch, Code 0x80 to 0x7F
Figure 26. Large Signal Settling Time
V
W
V
W
CLK
Figure 22. Digital Feedthrough
V
V
W2
W
V
CS
W1
Figure 23. Digital Crosstalk
Rev. A | Page 11 of 20
AD5162
TEST CIRCUITS
Figure 27 through Figure 32 illustrate the test circuits that
define the test conditions used in the product specification
tables.
V
A
V+ = V ± 10%
DD
∆V
∆V
MS
DUT
W
PSRR (dB) = 20 LOG
(
)
DD
∆V
∆V
%
%
A
B
MS
DD
∆V
PSS (%/%) =
DD
V+ = V
1LSB = V+/2
DUT
W
DD
V+
N
A
B
V
MS
V+
V
MS
Figure 30. Test Circuit for Power Supply Sensitivity
(PSS, PSSR)
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
DUT
+15V
NO CONNECT
DUT
A
W
V
IN
I
W
A
AD8610
–15V
V
B
OUT
W
OFFSET
GND
B
2.5V
V
MS
Figure 31. Test Circuit for Gain vs. Frequency
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
NC
DUT
I
DUT
CM
A
B
V
DD
I
= V /R
DD NOMINAL
W
W
A
B
V
W
W
GND
V
MS2
V
CM
R
= [V
– V
]/I
MS2 W
W
MS1
V
MS1
NC NC = NO CONNECT
Figure 32. Test Circuit for Common-Mode Leakage Current
Figure 29. Test Circuit for Wiper Resistance
Rev. A | Page 12 of 20
AD5162
THEORY OF OPERATION
The AD5162 is a 256-position digitally controlled variable
resistor (VR) device.
The general equation determining the digitally programmed
output resistance between W and B is
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
D
256
R
WB (D) =
× RAB + 2× RW
(1)
where:
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
Rheostat Operation
R
R
AB is the end-to-end resistance.
W is the wiper resistance contributed by the ON resistance of
The nominal resistance of the RDAC between terminals A and
B is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance (RAB) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open
circuited, the following output resistance RWB is set for the
indicated RDAC latch codes.
Table 6. Codes and Corresponding RWB Resistance
A
A
A
D (Dec)
RWB (Ω)
9,961
7,060
139
Output State
277
128
1
Full scale (RAB − 1 LSB + RW)
Midscale
1 LSB
W
W
W
B
B
B
0
100
Zero scale (wiper contact resistance)
Figure 33. Rheostat Mode Configuration
Note that, in the zero-scale condition, a finite wiper resistance
of 100 Ω is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Assuming that a 10 kΩ part is used, the wiper’s first connection
starts at the B terminal for data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum
of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for data
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
A
R
S
256 − D
256
RWA(D) =
× RAB + 2× RW
(2)
R
R
D7
D6
D5
D4
D3
D2
D1
D0
S
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA is set for the indicated RDAC
latch codes.
S
W
Table 7. Codes and Corresponding RWA Resistance
D (Dec)
RWA (Ω)
Output State
Full scale
Midscale
1 LSB
277
128
1
139
7,060
9,961
10,060
R
RDAC
S
LATCH
AND
DECODER
B
0
Zero scale
Typical device-to-device matching is process lot dependent and
may vary by up to 30ꢀ. Because the resistance element is
processed in thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
Figure 34. AD5162 Equivalent RDAC Circuit
Rev. A | Page 13 of 20
AD5162
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures shown in Figure 36 and
Figure 37. This applies to the digital input pins SDI, CLK,
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
CS
and
.
340Ω
LOGIC
V
I
A
GND
W
V
O
Figure 36. ESD Protection of Digital Pins
B
A, B, W
Figure 35. Potentiometer Mode Configuration
GND
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-
age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on terminals A, B, and W that
exceed VDD or GND are clamped by the internal forward biased
diodes (see Figure 38).
D
256 − D
VW (D) =
VA +
VB
(3)
256
256
V
DD
A more accurate calculation, which includes the effect of wiper
resistance, VW, is
A
W
B
R
WB (D)
RAB
RWA(D)
RAB
(4)
VW (D) =
VA +
VB
GND
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
Figure 38. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 38), it is important to
power VDD/GND before applying any voltage to terminals A, B,
and W; otherwise, the diode is forward biased such that VDD is
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA, VB, VW. The relative order
of powering VA, VB, VW, and the digital inputs is not important
as long as they are powered after VDD/GND.
Rev. A | Page 14 of 20
AD5162
110%
108%
106%
104%
102%
100%
98%
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
T
= 25°C
A
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 39). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
96%
94%
92%
90%
0
5
10
15
20
25
30
DAYS
Figure 40. Battery Operating Life Depletion
V
V
DD
DD
+
EVALUATION BOARD
C3
C1
10µF
0.1µF
AD5162
An evaluation board, along with all necessary software, is
available to program the AD5162 from any PC running
Windows 98/2000/XP. The graphical user interface, as shown in
Figure 41, is straightforward and easy to use. More detailed
information is available in the user manual, which comes with
the board.
GND
Figure 39. Power Supply Bypassing
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the addi-
tional cost for the EEMEM, the AD5162 may be considered as a
low cost alternative by maintaining a constant bias to retain the
wiper setting. The AD5162 is designed specifically with low
power in mind, which allows low power consumption even in
battery-operated systems. The graph in Figure 40 demonstrates
the power consumption from a 3.4 V 450 mAhr Li-Ion cell
phone battery, which is connected to the AD5162. The measure-
ment over time shows that the device draws approximately
1.3 µA and consumes negligible power. Over a course of
30 days, the battery is depleted by less than 2ꢀ, the majority of
which is due to the intrinsic leakage current of the battery itself.
Figure 41. AD5162 Evaluation Board Software
The AD5162 starts at midscale upon power-up. To increment or
decrement the resistance, the user may simply move the scroll-
bars on the left. To write any specific value, the user should use
the bit pattern in the upper screen and press the Run button.
The format of writing data to the device is shown in Table 8.
This demonstrates that constantly biasing the potentiometer is
not an impractical approach. Most portable devices do not
require the removal of batteries for the purpose of charging.
Although the resistance setting of the AD5162 is lost when the
battery needs replacement, such events occur rather infre-
quently such that this inconvenience is justified by the lower
cost and smaller size offered by the AD5162. If and when total
power is lost, the user should be provided with a means to
adjust the setting accordingly.
Rev. A | Page 17 of 20
AD5162
SPI INTERFACE
Table 8. Serial Data-Word Format
SPI COMPATIBLE 3-WIRE SERIAL BUS
B8
B7
B6
B5
B4
B3
B2
B1
B0
D0
LSB
20
The AD5162 contains a 3-wire SPI compatible digital interface
(SDI, , and CLK). The 9-bit serial word must be loaded MSB
CS
first. The format of the word is shown in Table 8.
A0
Dꢀ
D6
D7
D4
D3
D2
D1
MSB
28
2ꢀ
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
1
A0 D7 D6 D5 D4 D3 D2 D1 D0
SDI
0
1
CLK
CS
flip-flop or other suitable means. When
is low, the clock
CS
0
1
loads data into the serial register on each positive clock edge
(see Figure 42).
RDAC REGISTER LOAD
0
1
V
OUT
0
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5162 uses a
9-bit serial input data register word that is transferred to the
Figure 42. SPI Interface Timing Diagram
(VA = 5 V, VB = 0 V, VW = VOUT
)
internal RDAC register when the
line returns to logic high.
CS
Extra MSB bits are ignored.
1
SDI
Dx
Dx
tDS
(DATA IN)
0
1
tCS1
tCH
tCH
CLK
CS
0
tCSH1
tCL
tCSHO
tCSS
1
0
tCSW
tS
V
DD
0
±1LSB
V
OUT
Figure 43. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT
)
Rev. A | Page 16 of 20
AD5162
OUTLINE DIMENSIONS
3.00 BSC
10
6
4.90 BSC
3.00 BSC
PIN 1
1
5
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.27
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 44. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
RAB (Ω)
Temperature
Package Description
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
MSOP-10
Package Option
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
Branding
AD7162BRM2.7
AD7162BRM2.7-RLꢀ
AD7162BRM10
AD7162BRM10-RLꢀ
AD7162BRM70
AD7162BRM70-RLꢀ
AD7162BRM100
AD7162BRM100-RLꢀ
AD7162EVAL
2.7 k
2.7 k
10 k
10 k
70 k
70 k
100 k
100 k
See Note 1
–40°C to +127°C
–40°C to +127°C
–40°C to +127°C
–40°C to +127°C
–40°C to +127°C
–40°C to +127°C
–40°C to +127°C
–40°C to +127°C
D0Q
D0Q
D0R
D0R
D0S
D0S
D0T
D0T
Evaluation Board
1The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
Rev. A | Page 1ꢀ of 20
AD5162
NOTES
Rev. A | Page 18 of 20
AD5162
NOTES
Rev. A | Page 19 of 20
AD5162
NOTES
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04108–0–11/03(A)
Rev. A | Page 20 of 20
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