AD5232BRU50-REEL7 [ADI]
8-Bit Dual Nonvolatile Memory Digital Potentiometer; 8位双非易失性存储器的数字电位器
| 型号： | AD5232BRU50-REEL7 |
| 厂家： | 
ADI |
| 描述： | 8-Bit Dual Nonvolatile Memory Digital Potentiometer |
| 文件： | 总20页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit Dual Nonvolatile Memory
Digital Potentiometer
a
AD5232*
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
Nonvolatile Memory Preset Maintains Wiper Settings
Dual Channel, 256-Position Resolution
Full Monotonic Operation DNL < 1 LSB
10 kꢀ, 50 kꢀ, 100 kꢀ Terminal Resistance
Linear or Log Taper Settings
Push-Button Increment/Decrement Compatible
SPI-Compatible Serial Data Input with Readback
Function
AD5232
CS
V
DD
RDAC1
REGISTER
ADDR
DECODE
RDAC1
CLK
SDI
A1
W1
B1
SDI
SERIAL
INTERFACE
GND
EEMEM1
3 V to 5 V Single Supply or ꢁ2.5 V Dual Supply
Operation
14 Bytes of User EEMEM Nonvolatile Memory for
Constant Storage
Permanent Memory Write Protection
100-Year Typical Data Retention TA = 55ꢂC
RDAC2
RDAC2
REGISTER
SDO
SDO
A2
W2
B2
WP
EEMEM
CONTROL
RDY
EEMEM2
14 BYTES
USER EEMEM
PR
V
SS
APPLICATIONS
T he basic mode of adjustment is the increment and decrement
command controlling the present setting of the Wiper position
setting (RDAC) register. An internal scratch pad RDAC register
can be moved UP or DOWN one step of the nominal terminal
resistance between terminals A and B. T his linearly changes the
wiper to B terminal resistance (RWB) by one position segment of
the devices’ end-to-end resistance (RAB). For exponential/loga-
rithmic changes in wiper setting, a left/right shift command
adjusts levels in ±6 dB steps, which can be useful for audio and
light alarm applications.
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
GENERAL D ESCRIP TIO N
T he AD5232 device provides a nonvolatile, dual-channel,
digitally controlled variable resistor (VR) with 256-position
resolution. T hese devices perform the same electronic adjust-
ment function as a potentiometer or variable resistor. T he
AD5232’s versatile programming via a microcontroller allows
multiple modes of operation and adjustment.
T he AD5232 is available in a thin T SSOP-16 package. All parts
are guaranteed to operate over the extended industrial tempera-
ture range of –40°C to +85°C. An evaluation board is available,
Part Number: AD5232EVAL.
In the direct program mode a predetermined setting of the RDAC
register can be loaded directly from the microcontroller.
Another key mode of operation allows the RDAC register to be
refreshed with the setting previously stored in the EEMEM
register. When changes are made to the RDAC register to estab-
lish a new wiper position, the value of the setting can be saved
into the EEMEM by executing an EEMEM save operation.
Once the settings are saved in the EEMEM register these values
will be automatically transferred to the RDAC register to set the
wiper position at system power ON. Such operation is enabled
by the internal preset strobe and the preset can also be accessed
externally.
100
75
50
25
R
R
WA
WB
All internal register contents can be read out of the serial data
output (SDO). T his includes the RDAC1 and RDAC2 registers,
the corresponding nonvolatile EEMEM1 and EEMEM2 regis-
ters, and the 14 spare USER EEMEM registers available for
constant storage.
0
0
64
128
192
256
CODE – Decimal
Figure 1. Symmetrical RDAC Operation
*P atent pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD5232–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, 10 kꢀ, 50 kꢀ, 100 kꢀ VERSIONS
( V = 3 V ꢁ 10% or 5 V ꢁ 10% and V = 0 V, V = +V , V = 0 V, –40ꢂC < T < +85ꢂC unless otherwise noted.)
DD
SS
A
DD
B
A
P aram eter
Sym bol
Conditions
Min
Typ1 Max Unit
DC CHARACT ERIST ICS
RHEOST AT MODE – Specifications Apply to All VRs
Resistor Differential Nonlinearity2
R-DNL
R-INL
⌬RAB
⌬RAB/⌬T
RW
RWB, VA = NC
RWB, VA = NC
–1
–0.4
–40
±1/2
+1
LSB
Resistor Nonlinearity2
+0.4 % FS
Nominal Resistor T olerance
Resistance T emperature Coefficient
Wiper Resistance
+20
100
%
600
5
200
ppm/°C
Ω
Ω
IW = 100 µA, VDD = 5.5 V, Code = 1EH
IW = 100 µA, VDD = 3 V, Code = 1EH
RW
POT ENT IOMET ER DIVIDER MODE — Specifications Apply to All VRs
Resolution
N
DNL
INL
8
–1
–0.4
Bits
LSB
+0.4 % FS
ppm/°C
% FS
Differential Nonlinearity3
±1/2
+1
Integral Nonlinearity3
Voltage Divider Temperature Coefficient ⌬VW/⌬T
Full-Scale Error
Zero-Scale Error
Code = Half-Scale
Code = Full-Scale
Code = Zero-Scale
15
VWFSE
VWZSE
–3
0
0
+3
% FS
RESIST OR T ERMINALS
T erminal Voltage Range4
Capacitance5 Ax, Bx
VA,B,W
CA,B
VSS
VDD
V
f = 1 MHz, Measured to GND,
Code = Half-Scale
f = 1 MHz, Measured to GND,
Code = Half-Scale
45
pF
Capacitance5 Wx
CW
ICM
60
0.01
pF
µA
Common-Mode Leakage Current5, 6
VW = VDD/2
1
DIGIT AL INPUT S AND OUT PUT S
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
VIH
VIL
VIH
VIL
VIH
With Respect to GND, VDD = 5 V
With Respect to GND, VDD = 5 V
With Respect to GND, VDD= 3 V
With Respect to GND, VDD = 3 V
With Respect to GND, VDD = +2.5 V, 2.0
VSS = –2.5 V
2.4
2.1
V
V
V
V
V
0.8
0.6
Input Logic High
Input Logic Low
VIL
With Respect to GND, VDD = +2.5 V,
0.5
4
V
VSS = –2.5 V
Output Logic High (SDO and RDY)
Output Logic Low
VOH
VOL
IIL
RPULL-UP = 2.2 kΩ to 5 V
IOL = 1.6 mA, VLOGIC = 5 V
VIN = 0 V or VDD
4.9
V
V
0.4
Input Current
±2.5 µA
Input Capacitance5
CIL
pF
POWER SUPPLIES
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Programming Mode Current
Read Mode Current7
VDD
VSS = 0 V
2.7
±2.25
5.5
±2.75
10
V
V
µA
mA
mA
VDD/VSS
IDD
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND
VIH = VDD or VIL = GND,
3.5
35
3
IDD(PG)
IDD(XFR)
ISS
0.9
9
Negative Supply Current
V
DD = +2.5 V, VSS = –2.5 V
3.5
10
µA
Power Dissipation8
PDISS
PSS
VIH = VDD or VIL = GND
⌬VDD = 5 V ±10%
0.018 0.05 mW
0.002 0.01 %/%
Power Supply Sensitivity5
–2–
REV. 0
AD5232
P aram eter
Sym bol
Conditions
Min
Typ1 Max Unit
DYNAMIC CHARACT ERIST ICS5, 9
Bandwidth
T otal Harmonic Distortion
–3 dB, BW_10 kΩ, R = 10 kΩ
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
VA =1 V rms, VB = 0 V, f = 1 kHz,
RAB = 50 kΩ, 100 kΩ
VDD = 5 V, VSS = 0 V, VA = VDD, VB = 0 V,
VW = 0.50% Error Band, Code 00H to 80H
For RAB = 10 kΩ/50 kΩ/100 kΩ
RWB = 5 kΩ, f = 1 kHz
500
kHz
%
T HDW
T HDW
tS
0.022
0.045
%
VW Settling T ime
0.65/3/6
9
µs
Resistor Noise Voltage
eN_WB
nV/√Hz
Crosstalk (CW1/CW2
)
CT
VA = VDD, VB = 0 V, Measure VW with
Adjacent VR Making Full-Scale Code Change
VA1 = VDD, VB1 = 0 V, Measure VW1
with VW2 = 5 V p-p @ f = 10 kHz,
Code1 = 80H; Code2 = FFH
–5
nV-s
dB
Analog Crosstalk (CW1/CW2
)
CT A
–70
INT ERFACE T IMING CHARACTERISTICS – Applies to All Parts5, 10
Clock Cycle T ime (tCYC
CS Setup T ime
CLK Shutdown T ime to CS Rise
Input Clock Pulsewidth
Data Setup T ime
)
t1
t2
t3
t 4 , t 5
t6
20
10
1
10
5
ns
ns
tCYC
ns
ns
Clock Level High or Low
From Positive CLK T ransition
From Positive CLK T ransition
Data Hold T ime
t7
5
ns
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay11
CLK to SDO Data Hold T ime
CS High Pulsewidth12
t8
t 9
40
50
50
ns
ns
ns
ns
ns
tCYC
ns
t10
t11
t12
t 13
t 14
t 15
RP = 2.2 kΩ, CL < 20 pF
RP = 2.2 kΩ, CL < 20 pF
0
10
4
CS High to CS High12
RDY Rise to CS Fall
0
CS Rise to RDY Fall T ime
0.1
0.15 ms
25
Read/Store to Nonvolatile EEMEM13 t 16
Applies to Command 2H, 3H, 9H
ms
ns
ns
CS Rise to Clock Rise/Fall Setup
Preset Pulsewidth (Asynchronous)
Preset Response T ime to RDY High tPRESP
t17
tPRW
10
50
Not Shown in T iming Diagram
PR Pulsed Low to Refreshed
Wiper Positions
70
µs
FLASH/EE MEMORY RELIABILIT Y CHARACT ERIST ICS
Endurance14
100
K Cycles
Years
Data Retention15
100
NOT ES
1T ypical parameters represent average readings at 25°C and VDD = 5 V.
2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I W ~ 50 µA @ VDD = 2.7 V and
IW ~ 400 µA @ VDD = 5 V for the RAB = 10 kΩ version, IW ~ 50 µA for the RAB = 50 kΩ and IW ~ 25 µA for the RAB = 100 kΩ version. See Figure 13.
3INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = VSS. DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14.
4Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment.
5Guaranteed by design and not subject to production test.
6Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of VDD/2.
7T ransfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See T PC 9.
8PDISS is calculated from (IDD ꢃ VDD ) + (ISS ꢃ VSS).
9All dynamic characteristics use VDD = +2.5 V and VSS = –2.5 V unless otherwise noted.
10See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using both VDD = 3 V or 5 V.
11Propagation delay depends on value of VDD, RPULL_UP, and C L. See applications text.
12Valid for commands that do not activate the RDY pin.
13RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the PR hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation
at T A = –40°C and VDD < 3 V extends the save time to 35 ms.
14Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at VDD = 2.7 V, T A = –40°C to +85°C, typical endurance at 25°C is
700,000 cycles.
15Retention lifetime equivalent at junction temperature (T J) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
will derate with junction temperature as shown in Figure 23 in the Flash/EE Memory description section of this data sheet. T he AD5232 contains 9,646
transistors. Die size: 69 mil ꢃ 115 mil, 7,993 sq. mil.
Specifications subject to change without notice
REV. 0
–3–
AD5232
CPHA = 1
CS
t12
t13
t3
t1
t2
CLK
CPOL = 1
t5
t17
t4
t10
t8
t11
t9
MSB
LSB OUT
SDO
SDI
*
t7
t6
MSB
LSB
t14
t15
t16
RDY
*
NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2a. CPHA = 1 Timing Diagram
CPHA = 0
CS
t12
t1
t3
t13
t2
t5
t17
CLK
CPOL = 0
t4
t8
t10
t11
t9
SDO
SDI
MSB OUT
LSB
*
t7
t6
LSB
MSB IN
t14
t15
t16
RDY
*
NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
Figure 2b. CPHA = 0 Timing Diagram
–4–
REV. 0
AD5232
ABSO LUTE MAXIMUM RATINGS1
(T A = 25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Package Power Dissipation . . . . . . . . . . . . . (T J Max – TA)/
T hermal Resistance Junction-to-Ambient JA,
T SSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
T hermal Resistance Junction-to-Case
JA
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VA, VB, VW to GND . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
AX – BX, AX – WX, BX – WX
,
JC
T SSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
NOT ES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Digital Inputs and Output Voltage to
2Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
3Includes programming of nonvolatile memory.
GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
Operating T emperature Range3 . . . . . . . . . . . –40°C to +85°C
Maximum Junction T emperature (TJ Max) . . . . . . . . 150°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5232 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. T herefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O RD ERING GUID E
Num ber of
P ackage D evices per Branding*
Num ber of
Channels
End-to-End Tem perature P ackage
Model
R AB (kꢀ)
Range (°C)
D escription O ption
Container
Inform ation
AD5232BRU10
AD5232BRU10-REEL7
AD5232BRU50
AD5232BRU50-REEL7
AD5232BRU100
AD5232BRU100-REEL7
2
2
2
2
2
2
10
10
50
50
100
100
–40 to +85
–40 to +85
–40 to +85
–40 to +85
–40 to +85
–40 to +85
T SSOP-16
T SSOP-16
T SSOP-16
T SSOP-16
T SSOP-16
T SSOP-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
96
1,000
96
1,000
96
1,000
5232B10
5232B10
5232B50
5232B50
5232BC
5232BC
*Line 1 contains ADI logo symbol and the data code YYWW, line 2 contains detail model number listed in this column.
–5–
REV. 0
AD5232
P IN CO NFIGURATIO N
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
RDY
CS
CLK
SDI
SDO
GND
PR
AD5232
TOP VIEW
(Not to Scale)
WP
V
V
DD
SS
A2
W2
B2
A1
W1
B1
P IN FUNCTIO N D ESCRIP TIO NS
P in
Num ber
Mnem onic
D escr iption
1
2
3
CLK
SDI
SDO
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
Serial Data Input Pin. MSB Loaded First.
Serial Data Output Pin. Open Drain Output requires external pull-up resistor. Commands 9 and 10
activate the SDO output. See T able II. Other commands shift out the previously loaded SDI bit
pattern delayed by 16 clock pulses. T his allows daisy-chain operation of multiple packages.
Ground Pin, Logic Ground Reference.
4
5
6
GND
VSS
A1
Negative Supply. Connect to zero volts for single supply applications.
A T erminal of RDAC1
7
8
W1
B1
Wiper T erminal of RDAC1, ADDR(RDAC1) = 0H
B T erminal of RDAC1
9
B2
B T erminal of RDAC2
10
11
12
13
W2
A2
VDD
WP
Wiper T erminal of RDAC2, ADDR(RDAC2) = 1H
A T erminal of RDAC2
Positive Power Supply Pin
Write Protect Pin. When active low, WP prevents any changes to the present register contents, except
PR and CMD 1 and 8 will refresh RDAC register from EEMEM. Execute a NOP instruction before
returning WP to logic high.
14
PR
Hardware Override Preset Pin. Refreshes the scratch pad register with current contents of the EEMEM
register. Factory default loads midscale 80H until EEMEM is loaded with a new value by the user
(PR is activated at the logic high transition).
15
16
CS
RDY
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
Ready. Active-high open drain output, requires pull-up resistor. Identifies completion of commands
2, 3, 8, 9, 10, and PR.
–6–
REV. 0
AD5232
O P ERATIO NAL O VERVIEW
Table I. Set Two D igital P O Ts to Independent D ata Values
th en Save Wiper P osition s in C or r espon din g Non volatile
EEMEM Register s
T he AD5232 digital potentiometer is designed to operate as a
true variable resistor replacement device for analog signals that
remain within the terminal voltage range of VSS < VT ERM < VDD
.
SD I
SD O
Action
T he basic voltage range is limited to a | VDD – VSS| < 5.5 V. T he
digital potentiometer wiper position is determined by the RDAC
register contents. T he RDAC register acts as a scratch pad,
register allowing as many value changes as necessary to place the
potentiometer wiper in the correct position. T he scratch pad
register can be programmed with any position value using the
standard SPI serial interface mode by loading the complete
representative data word. Once a desirable position is found,
this value can be saved into a corresponding EEMEM register.
T hereafter the wiper position will always be set at that position
for any future ON-OFF-ON power supply sequence. T he
EEMEM save process takes approximately 25 ms, during this
time the shift register is locked preventing any changes from
taking place. T he RDY pin indicates the completion of this
EEMEM save.
B040H
XXXXH Loads 40H data into RDAC1 register,
Wiper W1 moves to 1/4 full-scale position.
20xxH
B180H
21xxH
B040H
20xxH
B180H
Saves copy of RDAC1 register contents
into corresponding EEMEM0 register.
Loads 80H data into RDAC2 register,
Wiper W2 moves to 1/2 full-scale position.
Saves copy of RDAC2 register contents
into corresponding EEMEM1 register.
Be aware that the PR pulse first sets the wiper at midscale when
brought to logic zero, and then on the positive transition to logic
high, it reloads the DAC wiper register with the contents of
EEMEM. Many additional advanced programming commands
are available to simplify the variable resistor adjustment process.
SCRATCH P AD AND EEMEM P RO GRAMMING
For example, the wiper position can be changed one step at a
time by using the software-controlled Increment/Decrement
instruction or, by 6 dB at a time, with the Shift Left/Right
instruction command. Once an Increment, Decrement, or Shift
command has been loaded into the shift register, subsequent CS
strobes will repeat this command. T his is useful for push-button
control applications. See the Advanced Control Modes descrip-
tion following T able I. A serial data output SD O pin is
available for daisy chaining and for readout of the internal
register contents. T he serial input data register uses a 16-bit
[instruction/address/data] WORD.
T he scratch pad register (RDAC register) directly controls the
position of the digital potentiometer wiper. When the scratch
pad register is loaded with all zeros, the wiper will be connected
to the B-T erminal of the variable resistor. When the scratch pad
register is loaded with midscale code (1/2 of full-scale position),
the wiper will be connected to the middle of the variable resis-
tor. And when the scratch pad is loaded with full-scale code, all
1s, the wiper will connect to the A-T erminal. Since the scratch
pad register is a standard logic register, there is no restriction on
the number of changes allowed. T he EEMEM registers have a
program erase/write cycle limitation described in the Flash/
EEM EM Reliability section.
EEMEM P RO TECTIO N
Write protect (WP) disables any changes of the scratch pad
register contents regardless of the software commands, except
that the EEMEM setting can be refreshed using commands 8
and PR. T herefore, the write-protect (WP) pin provides a hard-
ware EEMEM protection feature. Execute a NOP command
before returning WP to logic high.
BASIC O P ERATIO N
T he basic mode of setting the variable resistor wiper position
(programming the scratch pad register) is accomplished by
loading the serial data input register with the command instruc-
tion # 11, which includes the desired wiper position data. When
the desired wiper position is found, the user loads the serial data
input register with the command instruction # 2, which copies
the desired wiper position data into the corresponding nonvola-
tile EEMEM register. After 25 ms the wiper position will be
permanently stored in the corresponding nonvolatile EEMEM
location. Table I provides an application-programming example
listing the sequence of serial data input (SDI) words and the
corresponding serial data output appearing at the SDO pin in
hexadecimal format.
D IGITAL INP UT/O UTP UT CO NFIGURATIO N
All digital inputs are ESD-protected high input impedance that
can be driven directly from most digital sources. PR and WP,
which are active at logic low, must be biased to VDD if they are
not being used. No internal pull-up resistors are present on any
digital input pins.
T he SDO and RDY pins are open-drain digital outputs where
pull-up resistors are needed only if using these functions. A
resistor value in the range of 1 kΩ to 10 kΩ optimizes the power
and switching speed trade-off.
At system power-on, the scratch pad register is refreshed with
the value last saved in the EEMEM register. T he factory preset
EEMEM value is midscale. T he scratch pad (wiper) register can
be refreshed with the current contents of the nonvolatile
EEMEM register under hardware control by pulsing the PR pin.
–7–
REV. 0
AD5232
V
SERIAL D ATA INTERFACE
DD
T he AD5232 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS, and CLK), and uses a 16-bit serial data word
loaded MSB first. T he format of the SPI-compatible word is
shown in T able II. T he chip select (CS) pin needs to be held
low until the complete data word is loaded into the SDI pin.
When CS returns high, the serial data word is decoded accord-
ing to the instructions in T able III. T he Command Bits (Cx)
control the operation of the digital potentiometer. T he Address
Bits (Ax) determine which register is activated. T he Data Bits
(Dx) are the values that are loaded into the decoded register.
T able IV provides an address map of the EEMEM locations.
T he last instruction executed prior to a period of no program-
ming activity should be the N o Operation (N OP) instruction.
T his will place the internal logic circuitry in a minimum power
dissipation state.
INPUT
300ꢀ
WP
AD5232
GND
Figure 4b. Equivalent WP Input Protection
D AISY CH AINING O P ERATIO N
T he serial data output pin (SDO) serves two purposes. It can
be used to read out the contents of the wiper setting and
EEMEM values using instruction 10 and 9 respectively. T he
remaining instructions (# 0–8, # 11–15) are valid for daisy-
chaining multiple devices in simultaneous operations.
D aisy-chaining minimizes the number of port pins required
from the controlling IC (see Figure 5). T he SDO pin contains
an open drain N-Channel FET that requires a pull-up resistor if
this function is used. As shown in Figure 5, users need to tie
the SDO pin of one package to the SD I pin of the next
package. Users may need to increase the clock period because
the pull-up resistor and the capacitive loading at the SDO-SDI
interface may require additional time delay between subsequent
packages. If two AD5232’s are daisy-chained, 32 bits of data
are required. T he first 16 bits go to U 2 and the second 16
bits with the same format go to U1. T he 16 bits are formatted
to contain the 4-bit instruction, followed by the 4-bit address,
then the 8 bits of data. T he CS should be kept low until all 32
bits are locked into their respective serial registers. T he CS
is then pulled high to complete the operation.
PR
WP
VALID
COMMAND
COMMAND
PROCESSOR
AND ADDRESS
DECODE
5V
COUNTER
R
PULLUP
CLK
SERIAL
REGISTER
SDO
GND
CS
SDI
AD5232
Figure 3. Equivalent Digital Input-Output Logic
The equivalent serial data input and output logic is shown in
Figure 3. The open-drain output SDO is disabled whenever chip
select CS is logic high. The SPI interface can be used in two slave
modes CPH A = 1, CPOL = 1 and CPH A = 0, CPOL = 0.
C PH A and C POL refer to the control bits, which dictate
SPI timing in these M icroConverters® and microprocessors:
ADuC812/ADuC824, M68HC11, and MC68HC16R1/916R1.
+V
AD5232
R
2kꢀ
AD5232
P
ꢄC
SDI
SDO
SDI
U1
SDO
U2
ESD protection of the digital inputs is shown in Figures 4a and 4b.
CLK
CLK
V
CS
CS
DD
INPUTS
300ꢀ
Figure 5. Daisy-Chain Configuration Using SDO
LOGIC
PINS
AD5232
GND
Figure 4a. Equivalent ESD Digital Input Protection
Table II. 16-Bit Serial D ata Word
MSB B14 B13 B12 B11 B10 B9
C3 C2 C1 C0 A3 A2 A1
B8
A0
B7
B6
B5
B4
B3
B2
B1
LSB
D0
AD 5232
D7
D6
D5
D4
D3
D2
D1
Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined
in T able III.
MicroConverter is a registered trademark of Analog Devices, Inc.
–8–
REV. 0
AD5232
Table III. Instruction/O peration Truth Table
D ata Byte 0
Instr uction Byte 1
B15
Inst
No.
B8
B7
B0
C3 C2 C1 C0 A3 A2 A1 A0
D 7 D 6 D5 D4 D3 D2 D1 D 0
O peration
0
1
0
0
0
0
0
0
0
1
X
0
X
0
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No Operation (NOP). Do nothing.
A0
Write contents of EEM EM (A0) to
RD AC(A0) Register. T his command
leaves device in the Read Program power
state. T o return part to the idle state,
perform NOP instruction # 0.
2
3
4
5
6
7
8
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
A0
X
X
X
X
X
X
X
X
SAVE WIPER SET T ING. Write con-
tents of RDAC(ADDR) to EEMEM(A0)
< < AD D R > >
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register D ata
Byte 0 to EEMEM(ADDR).
0
0
0
A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Decrement 6 dB right shift contents of
RDAC(A0), stops at all “Zeros.”
X
0
X
0
X
0
Decrement All 6 dB right shift contents
of all RDAC Registers, stops at all “Zeros.”
A0
X
Decrement contents of RDAC(A0) by
“One,” stops at all “Zeros.”
X
0
X
0
X
0
Decrement contents of all RDAC Regis-
ters by “One,” stops at all “Zeros.”
0
RESET . Load all RDACs with their cor-
responding EEMEM previously-saved
values.
9
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
< < AD D R > >
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Write contents of EEMEM(ADDR) to
Serial Register Data Byte 0.
10
0
0
0
A0
A0
A0
X
Write contents of RDAC(A0) to Serial
Register Data Byte 0.
11
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register Data
Byte 0 to RDAC(A0).
12
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Increment 6 dB left shift contents of
RDAC(A0), stops at all “Ones.”
13
X
0
X
0
X
0
Increment all 6 dB left shift contents
of all RDAC Registers, stops at all “Ones.”
14
A0
X
Increment contents of RDAC(A0) by
“One,” stops at all “Ones.”
15
X
X
X
Increment contents of all RDAC Regis-
ters “One,” stops at all “Ones.”
NOT ES
1. The SDO output shifts out the last eight bits of data clocked into the serial register for daisy-chain operation. Exception: following Instruction #9 or #10 the selected internal
register data will be present in data byte 0. Instructions following #9 and #10 must be a full 16-bit data word to completely clock out the contents of the serial register.
2. T he RDAC register is a volatile scratch pad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3. T he increment, decrement, and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the CS strobe returns to logic high.
5. Execution of a NOP instruction minimizes power dissipation.
–9–
REV. 0
AD5232
AD VANCED CO NTRO L MO D ES
Also the left shift commands were modified so that if the data in
the RDAC register is greater than or equal to midscale and the
data is left shifted then the data in the RDAC register is set to
full-scale. T his makes the left shift function as close to ideally
logarithmic as is possible.
The AD5232 digital potentiometer contains a set of user program-
ming features to address the wide applications available to these
universal adjustment devices. Key programming features include:
Independently Programmable Read and Write to all registers.
T he right shift # 4 and # 5 commands will be ideal only if the
LSB is zero (i.e., ideal logarithmic–no error). If the LSB is a
one then the right shift function generates a linear half LSB
error, which translates to a code dependent logarithmic error
for odd codes only as shown in the attached plots, (see Figure
5). T he plot shows the errors of the odd codes for the AD5232.
• Simultaneous refresh of all RDAC wiper registers from
corresponding internal EEMEM registers.
•
Increment and D ecrement instructions for each RD AC wiper
register.
• Left and right bit shift of all RDAC wiper registers to achieve
6 dB level changes.
LEFT SHIFT
RIGHT SHIFT
• Nonvolatile storage of the present scratch pad RDAC register
values into the corresponding EEMEM register.
0000 0000
0000 0001
0000 0010
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
1111 1111
1111 1111
1111 1111
0111 1111
0011 1111
0001 1111
0000 1111
0000 0111
0000 0011
0000 0001
0000 0000
0000 0000
0000 0000
LEFT
SHIFT
(+6 dB)
RIGHT
SHIFT
(–6 dB)
• Fourteen extra bytes of user-addressable electrical-erasable memory.
Incr em ent and D ecr em ent Com m ands
T he increment and decrement commands (# 14, # 15, # 6, # 7)
are useful for the basic servo adjustment application. T his com-
mand simplifies microcontroller software coding by eliminating
the need to perform a readback of the current wiper position,
then add one to the register contents using the microcontroller’s
adder. T he microcontroller simply sends an increment command
(# 14) to the digital POT , which will automatically move the
wiper to the next resistance segment position. T he master incre-
ment command (# 15) will move all POT wipers by one position
from their present position to the next resistor segment position.
T he direction of movement is referenced to T erminal B. T hus
each increment # 15 command will move the wiper tap position
farther away from T erminal B.
Figure 6. Detail Left and Right Shift Function for the
8-Bit AD5232
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right Shift # 4 and # 5 command execution contains an error
only for the odd codes. Even codes are ideal except zero right
shift or greater than half-scale left shift. T he graph in Figure 7
shows plots of Log_Error [i.e., 20 × log 10 (error/code)]. For
example, code 3 Log_Error = 20 × log 10 (0.5/3) = –15.56 dB,
which is the worst case. T he plot of Log_Error is more signifi-
cant at the lower codes.
Logar ithm ic Taper Mode Adjustm ent
Programming instructions allow a decrement and an increment
wiper position control by individual POT or in a ganged POT
arrangement where both wiper positions are changed at the
same time. T hese settings are activated by the 6 dB decrement
and 6 dB increment instructions # 4 and # 5 and # 12 and # 13
respectively. For example, starting with the wiper connected to
T erminal B executing nine increment instructions (# 12) would
move the wiper in +6 dB steps from the 0% of RBA (B terminal)
position to the 100% of RBA position of the AD 5232 8-Bit
potentiometer. T he 6 dB increment instruction doubles the
value of the RDAC register contents each time the command is
executed. When the wiper position is greater than midscale, the
last 6 dB increment instruction will cause the wiper to go to the
Full-Scale 255 code position. Any additional +6 dB instruction
will no longer change the wiper position from full scale (RDAC
register code = 255).
0
–10
LOG_ERROR (CODE) FOR 8-BIT
–20
–30
–40
–50
–60
Figure 6 illustrates the operation of the 6 dB shifting function
on the individual RDAC register data bits for the 8-bit AD5232
example. Each line going down the table represents a successive
shift operation. Very important: the left shift # 12 and # 13 com-
mands were modified so that if the data in the RDAC register is
equal to zero and the data is left shifted, it is then set to code 1.
0
20 40 60 80 100 120
160 180 200 220 240 260
140
CODE, FROM 1 TO 255 BY 2
Figure 7. Plot of Log_Error Conformance for Odd Codes
Only (Even Codes Are Ideal)
–10–
REV. 0
AD5232
V
USING AD D ITIO NAL INTERNAL NO NVO LATILE EEMEM
T he AD5232 contains additional internal user storage registers
(EEMEM) for saving constants and other 8-bit data. T able IV
provides an address map of the internal nonvolatile storage
registers shown in the functional block diagram as EEMEM1,
EEMEM2, and bytes of USER EEMEM.
DD
A
W
B
Table IV. EEMEM Addr ess Map
EEMEM
Addr ess
(AD D R)
EEMEM Contents of Each
D evice EEMEM (AD D R)
AD 5232 (8B)
0000
0001
0010
0011
0100
0101
***
RDAC1
RDAC2
USER 1
USER 2
USER 3
USER 4
***
V
SS
Figure 8. Maximum Terminal Voltages Set by VDD and VSS
DETAIL POTENTIOMETER OPERATION
T he actual structure of the RDAC is designed to emulate the
performance of a mechanical potentiometer. The patent-pending
RDAC contains multiple strings of connected resistor segments,
with an array of analog switches that act as the wiper connection
to several points along the resistor array. T he number of points
is the resolution of the device. For example, the AD5232 has
256 connection points allowing it to provide better than 0.5%
setability resolution. Figure 9 provides an equivalent dia-
gram of the connections between the three terminals that
make up one channel of the RDAC. T he SWA and SWB will
always be ON, while one of the switches SW(0) to SW(2N–1)
will be ON one at a time depending upon the resistance step
decoded from the Data Bits. T he resistance contributed by RW
must be accounted for in the output resistance. T he SWA and
SWB will always be ON while one of the switches SW(0) to
SW(2N–1) will be ON one at a time, depending upon the
resistance step decoded from the Data Bits. T he resistance
contributed by RW must be accounted for in the output resistance.
1111
USER 14
NOT ES
1RDAC data stored in EEMEM locations are transferred to their
corresponding RDAC REGIST ER at Power ON, or when
instructions Inst# 1 and Inst# 8 are executed.
2USER <data> is internal nonvolatile EEMEM registers available
to store and retrieve constants using Inst# 3 and Inst# 9 respectively.
3AD5232 EEMEM locations are 1 byte each (8 bits).
4Execution of instruction # 1 leaves the device in the Read Mode power con-
sumption state. After the last Instruction # 1 is executed, the user should
perform a NOP, Instruction # 0 com mand to return the device to the low
power idle state.
Table V. RD AC and D igital Register Address Map
Register Addr ess
(AD D R)
Nam e of Register*
AD 5232 (8B)
0000
0001
RDAC1
RDAC2
*RDACx registers contain data determining the
position of the variable resistor wiper.
SW
A
A
X
TERMINAL VO LTAGE O P ERATING RANGE
N
SW(2
– 1)
T he digital potentiometer’s positive VDD and negative VSS power
supply defines the boundary conditions for proper three-terminal
programmable resistance operation. Signals present on terminals
A, B, W that exceed VDD or VSS will be clamped by a forward
biased diode; see Figure 8.
RDAC
WIPER
REGISTER
AND
W
X
R
S
N
SW(2
– 2)
DECODER
T he ground pin of the AD5232 device is primarily used as a
digital ground reference, which needs to be tied to the PCBs’
common ground. T he digital input logic signals to the AD5232
must be referenced to the devices’ ground pin (GND), and
satisfy the logic minimum input high level and the maximum
low level defined in the specification table of this data sheet.
SW(1)
SW(0)
R
R
S
S
N
R
= R /2
AB
S
An internal level-shift circuit between the digital interface and
the wiper switch control ensures that the common-mode voltage
range of the three-terminals A, W, and B extends from VSS to VDD
DIGITAL
SW
B
CIRCUITRY
OMITTED FOR
CLARITY
B
X
.
Figure 9. Equivalent RDAC Structure (Patent Pending)
–11–
REV. 0
AD5232
100
75
50
25
0
Table VI. Nom inal Individual Segm ent Resistor Values (ꢀ)
Segment Resistor Size
for RAB End-to-End Values
Device
Resolution
10 kꢀ Ver sion 50 kꢀ Ver sion 100 kꢀ Ver sion
8-Bit
78.10
390.5
781.0
P RO GRAMMING TH E VARIABLE RESISTO R
Rheostat O per ation
The nominal resistances of the RDAC between terminals A and B
are available with values of 10 kΩ, 50 kΩ, and 100 kΩ. The final
digits of the part number determine the nominal resistance value,
e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance (RAB) of
the AD5232 VR has 256 contact points accessed by the wiper
terminal, plus the B terminal contact. The 8-bit data word in the
RDAC latch is decoded to select one of the 256 possible settings.
R
R
WA
WB
0
64
128
192
256
CODE – Decimal
Figure 10. Symmetrical RDAC Operation
T he general transfer equation, which determines the digitally
programmed output resistance between Wx and Bx, is:
Like the mechanical potentiometer the RDAC replaces, the
AD5232 parts are totally symmetrical. T he resistance between
the wiper W and terminal A also produces a digitally controlled
resistance RWA. Figure 10 shows the symmetrical programmabil-
ity of the various terminal connections. When these terminals
are used the B–terminal should be tied to the wiper. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch is increased in
value. T he general transfer equation for this operation is:
R
WB(Dx) = (Dx)/2N × RBA + RW
(1)
Where N is the resolution of the VR, Dx is the data contained in
the RDACx latch, and RBA is the nominal end-to-end resistance.
For example, the following output resistance values will be set
for the following RDAC latch codes (applies to the 8-bit, 10 kΩ
potentiometers):
WA(Dx) = (2N-Dx)/2N × RBA + RW
(2)
Table VII. Nom inal Resistance Value at Selected Codes for
RAB = 10 kꢀ
R
where N is the resolution of the VR, Dx is the data contained in
the RDACx latch, and RBA is the nominal end-to-end resistance.
For example, the following output resistance values will be set
for the following RDAC latch codes (applies to 8-bit, 10 kΩ
potentiometers).
D (D EC)
RWB (V) O utput State
255
128
1
10011
5050
89
Full-Scale
Midscale
1 LSB
0
50
Zero-Scale*(Wiper Contact Resistance)
*Note that in the zero-scale condition a finite wiper resistance of 50 Ω is present. Care
should be taken to limit the current flow between W and B in this state to a
maximum continuous value of 2 mA to avoid degradation or possible de struc-
tion of the internal switch metalization. Intermittent current operation to
20 mA is allowed.
Table VIII. Nom inal Resistance Value at Selected
Codes for RAB = 10 kꢀ
D (D EC) RWA (W)
O utput State
255
128
1
89
Full-Scale
Midscale
1 LSB
5050
10011
10050
0
Zero-Scale
T he multichannel AD5232 has a ±0.2% typical distribution of
internal channel-to-channel RBA match. D evice-to-device
matching is process-lot-dependent and exhibits a –40% to +20%
variation. The change in RBA with temperature has a 600 ppm/°C
temperature coefficient.
–12–
REV. 0
AD5232
P RO GRAMMING TH E P O TENTIO METER D IVID ER
Voltage O utput O per ation
The internal parasitic capacitances and the external capacitive loads
dominate the ac characteristics of the RDACs. Configured as a
potentiometer divider the –3 dB bandwidth of the AD5232BRU10
(10 kΩ resistor) measures 500 kHz at half scale. Figure TPC 10
provides the large signal BODE plot characteristics of the three
resistor versions 10 kΩ, 50 kΩ, and 100 kΩ. A parasitic simu-
lation model has been developed, and is shown in Figure 12.
Listing I provides a macro model net list for the 10 kΩ RDAC:
T he digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A-terminal to 5 V and B-terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 5 V. Each LSB of voltage is
equal to the voltage applied across terminal AB divided by the
2N position resolution of the potentiometer divider. T he general
equation defining the output voltage with respect to ground for
any given input voltage applied to terminals AB is:
Listing I. Macr o Model Net List for RD AC
.PARAM DW=255, RDAC=10E3
VW(Dx) = Dx/2N × VAB + VB
(3)
*
.SUBCKT DPOT (A,W,B)
*
Operation of the digital potentiometer in the divider mode results in
more accurate operation over temperature. Here the output voltage is
dependent on the ratio of the internal resistors, not the absolute
value; therefore, the drift improves to 15 ppm/°C. There is no
voltage polarity restriction between terminals A, B, and W, as long
CA
RAW
CW
RBW
CB
*
A
A
W
W
B
0
W
0
B
0
{45E-12}
{(1-DW/256)*RDAC+50}
60E-12
as the terminal voltage (VTERM) stays within VSS < VTERM < VDD
.
{DW/256*RDAC+50}
{45E-12}
O P ERATIO N FRO M D UAL SUP P LIES
T he AD5232 can be operated from dual supplies enabling con-
trol of ground-referenced ac signals. See Figure 11 for a typical
circuit connection.
.ENDS DPOT
+2.75V
AP P LICATIO N P RO GRAMMING EXAMP LES
The following command sequence examples have been developed
to illustrate a typical sequence of events for the various features
of the AD5232 nonvolatile digital potentiometer.
V
V
DD
SS
CS
DD
CLK
SDI
SCLK
MOSI
ꢄC
ꢁ2V p-p
~
ꢁ1V p-p
GND
[PCB = Printed Circuit Board containing the AD523x part].
Instruction numbers (Commands), addresses and data appear-
ing at SDI and SDO pins are listed in hexadecimal.
GND
V
SS
AD5232
Table IX. Set Two Digital P OTs to Independent Data Values
–2.5V
SD I
SD O
Action
Figure 11. Operation from Dual Supplies
B140H
XXXXH
Loads 40H data into RDAC2 register,
Wiper W2 moves to 1/4 full-scale
position.
RDAC
10kꢀ
A
B
B080H
B140H
Loads 80H data into RDAC1 register,
Wiper W1 moves to 1/2 Full-Scale
position.
C
C
B
A
C
W
60pF
C
= 45pF
C = 45pF
B
A
W
Figure 12. RDAC Circuit Simulation Model for RDAC = 10 kΩ
–13–
REV. 0
AD5232
Table X. Active Trim m ing of O ne P O T Followed by a Save to
Nonvolatile Mem ory (P CB Calibrate)
Analog D evices offers the AD 5232EVAL board for sale to
simplify evaluation of these programmable devices controlled by
a personal computer via the printer port.
SD I
SD O
Action
TEST CIRCUITS
Figures 13 to 22 define the test conditions used in the product
specification’s table.
B040H
XXXXH
Loads 40H data into RDAC1 register,
Wiper W1 moves to 1/4 full-scale
position.
E0XXH
E0XXH
B040H
Increments RDAC1 register by one to
41H , Wiper W1 moves one resistor
segment away from terminal B.
Increments RDAC1 register by one to
42H , Wiper W1 moves one more
resistor segment away from terminal B.
Continue until desired wiper position
reached.
NC
DUT
A
I
W
E0XXH
W
B
V
MS
NC = NO CONNECT
20XXH
E0XXH
Saves RD AC 1 register data into
corresponding nonvolatile EEMEM1
memory ADDR = 0H.
Figure 13. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
DUT
A
W
V+ =V
DD
1LSB =V+/2
EQ UIP MENT CUSTO MER STARTUP SEQ UENCE FO R A
P CB CALIBRATED UNIT WITH P RO TECTED SETTINGS
N
V+
B
PCB setting: T ie WP to GND [prevents changes in PCB
wiper set position]
V
MS
Power VDD and VSS with respect to GND
Optional: Strobe PR pin [ensures full power ON preset of
wiper register with EEMEM contents in unpredictable supply
sequencing environments]
Figure 14. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
Table XI. Using Left Shift by O ne to Change Circuit Gain in
6 dB Steps
DUT
A
I
W
V
W
W
V
MS2
SD I
SD O
Action
B
R
=
[
V
–V
]/I
MS2 W
V
W
MS1
MS1
C1XXH
XXXXH
Moves Wiper W2 to double the present
data value contained in RDAC2 regis-
ter, in the direction of the A terminal.
Moves Wiper W2 to double the present
data value contained in RDAC2 regis-
ter, in the direction of the A terminal.
Figure 15. Wiper Resistance Test Circuit
C1XXH
XXXXH
V
A
V+ =V
ꢁ 10%
DD
ꢅV
MS
V
A
B
PSRR (dB) = 20 LOG
DD
)
(
W
ꢅV
DD
Table XII. Storing Additional D ata in Nonvolatile Mem ory
V+ ~
ꢅV
ꢅV
%
MS
PSS (%/%) =
V
MS
%
SD I
SD O
Action
DD
3280H
XXXXH
Stores 80H data into spare EEMEM
location USER1.
Figure 16. Power Supply Sensitivity Test Circuit (PSS, PSRR)
3340H
XXXXH
Stores 40H data into spare EEMEM
location USER2.
A
DUT
B
5V
Table XIII. Reading Back Data from Various Mem ory Locations
W
V
~
IN
OP279
V
OUT
SD I
SD O
Action
OFFSET
GND
94XXH
XXXXH
Prepares data read from USER3 location.
Assumption: USER3 previously loaded
with 80H.
OFFSET BIAS
00XXH
XX80H
NOP instruction # 0 sends 16-bit word
out of SDO where the last 8 bits con-
tain the contents of USER3 location.
NOP command ensures device returns
to idle power dissipation state.
Figure 17. Inverting Gain Test Circuit
–14–
REV. 0
AD5232
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many Program, Read, and Erase cycles. In real
terms, a single endurance cycle is composed of four indepen-
dent, sequential events. T hese events are defined as:
5V
OP279
V
OUT
V
~
IN
W
a. Initial page erase sequence
b. Read/verify sequence
OFFSET
GND
A
DUT
B
OFFSET BIAS
c. Byte program sequence
d. Second read/verify sequence
Figure 18. Noninverting Gain Test Circuit
During reliability qualification Flash/EE memory is cycled from
00H to FFH until a first fail is recorded, signifying the endurance
limit of the on-chip Flash/EE memory.
+15V
A
W
~
V
IN
DUT
OP42
V
As indicated in the specification pages of this data sheet, the
AD5232 Flash/EE Memory Endurance qualification has been
carried out in accordance with JEDEC Specification A117 over
the industrial temperature range of –40°C to +85°C. T he results
allow the specification of a minimum endurance figure over supply
and temperature of 100,000 cycles, with an endurance figure of
700,000 cycles being typical of operation at 25°C.
OUT
B
OFFSET
GND
2.5V
–15V
Figure 19. Gain vs. Frequency Test Circuit
0.1V
R
=
SW
I
DUT
B
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the AD5232 has been
qualified in accordance with the formal JEDEC Retention Life-
time Specification (A117) at a specific junction temperature
(TJ = 55°C). As part of this qualification procedure, the Flash/EE
memory is cycled to its specified endurance limit described above,
before data retention is characterized. This means that the Flash/EE
memory is guaranteed to retain its data for its full-specified reten-
tion lifetime every time the Flash/EE memory is reprogrammed. It
should also be noted that retention lifetime, based on an activa-
tion energy of 0.6 eV, will derate with TJ as shown in Figure 23.
SW
CODE = OO
H
W
+
_
0.1V
I
SW
V
TO V
DD
SS
Figure 20. Incremental ON Resistance Test Circuit
NC
A
B
V
I
DD
CM
DUT
W
300
250
V
GND
SS
V
CM
NC
NC = NO CONNECT
ADI TYPICAL
200
PERFORMANCE
AT
T
= 55ꢂC
Figure 21. Common-Mode Leakage Current Test Circuit
J
150
100
50
A1
V
A2
RDAC
DD
RDAC
W1
1
2
W2
NC
V
OUT
V
~
IN
B2
V
B1
SS
C
= 20 log [V
/V
IN
]
TA
OUT
0
40
50
60
70
80
90
100
110
Figure 22. Analog Crosstalk Test Circuit
Flash/EEMEM Reliability
T he Flash/EE Memory array on the AD5232 is fully qualified
for two key Flash/EE memory characteristics, namely Flash/EE
M emory C ycling Endurance and Flash/EE M emory D ata
Retention.
T
JUNCTIONTEMPERATURE – ꢂC
J
Figure 23. Flash/EE Memory Data Retention
–15–
REV. 0
–Typical Performance Characteristics
AD5232
2.00
2000
1500
1000
500
0
V
= 2.7V
= 0V
1.75
1.50
1.25
1.00
0.75
0.50
0.25
DD
V
= 5V
DD
V
SS
T
= –40ꢂC/+85ꢂC
A
INL T = –40ꢂC
A
V
= NO CONNECT
A
R
MEASURED
WB
INL T = +25ꢂC
A
0
–0.25
–0.50
–0.75
INL T = +85ꢂC
A
–1.00
–1.25
–1.50
–1.75
–2.00
0
64
128
DIGITAL CODE
192
256
0
32
64
96
128
160
192
224
256
CODE – Decimal
TPC 1. INL vs. Code, TA = –40ЊC, +25ЊC, +85ЊC Overlay
TPC 4. ∆RWB/∆T vs. Code RAB = 10 kΩ, VDD = 5 V
2.00
70
V
= 2.7V
= 0V
1.75
1.50
1.25
1.00
0.75
0.50
0.25
DD
V
= 5V
DD
V
60
50
40
30
20
10
0
SS
T
= –40ꢂC/+85ꢂC
A
V
= 2.00V
A
DNL T = –40ꢂC
A
V
= 0V
B
DNL T = +25ꢂC
A
0
–0.25
–0.50
–0.75
DNL T = +85ꢂC
A
–1.00
–1.25
–1.50
–1.75
–2.00
–10
1
64
128
DIGITAL CODE
192
256
160
CODE – Decimal
192
224
256
0
32
64
96
128
TPC 2. DNL vs. Code, TA = –40ЊC, +25ЊC, +85ЊC Overlay
TPC 5. ∆VWB/∆T vs. Code RAB = 10 kΩ, VDD = 5 V
0.20
1
V
= 5.5V, V = 0V
SS
DD
V
= +2.5V
= –2.5V
= 0V
DD
T
= 25ꢂC
0.15
0.10
A
V
SS
V
CM
SEE FIGURE 21
0.1
0.05
0.00
–0.05
–0.10
–0.15
–0.20
0.01
0.001
0
32
64
96
128
160
192
224
256
25
40
55
70
85
–50
–35
–20 –5
10
CODE – Decimal
TEMPERATURE – ꢂC
TPC 3. R-DNL vs. Code RAB = 10 kΩ, 50 kΩ, 100 kΩ Overlay
TPC 6. ICM vs. Temperature
–16–
REV. 0
AD5232
4
12
6
f–3dB = 500kHz, R = 10kꢀ
V
= 5.5V
DD
0
–6
f–3dB = 45kHz, R = 100kꢀ
–12
–18
–24
–30
–36
–42
2
f
= 95kHz, R = 50kꢀ
3dB
–
V
= 2.7V
DD
V
= 100mV rms
IN
V
= +2.5V,V = –2.5V
DD
SS
R
T
= 1Mꢀ
= 25ꢂC
L
A
25
40
55
70
85
–50
–35
–20
–5
10
1k
10k
100k
1M
TEMPERATURE – ꢂC
FREQUENCY – Hz
TPC 7. IDD vs. Temperature
TPC 10. –3 dB Bandwidth vs. Resistance
10
V
= 5V
DD
FILTER = 22kHz
T
= 25ꢂC
A
1
0.1
R
= 10kꢀ
AB
0.01
R
= 50kꢀ, 100kꢀ
AB
0.001
10
100
1k
FREQUENCY – Hz
10k
100k
TPC 8. IDD vs. Time (Save) Program Mode
TPC 11. Total Harmonic Distortion vs. Frequency
110
100
T
= 25ꢂC
A
V
= 2.7V
90
80
70
60
DD
50
40
30
20
10
0
1
64
128
192
256
CODE
TPC 12. Wiper On-Resistance vs. Code
TPC 9. IDD vs. Time Read Mode
–17–
REV. 0
AD5232
0
80
60
40
20
0
DATA = 80
H
R
= 100kꢀ
AB
–6
–12
–18
–24
–30
DATA = 40
DATA = 20
DATA = 10
R
= 50kꢀ
H
H
H
AB
R
= 10kꢀ
AB
DATA = 08
DATA = 04
H
H
–36
–42
DATA = 02
DATA = 01
H
H
V
= 5.5V 100mV ac
V
V
V
T
= +2.7V
= –2.7V
= 100mV rms
= 25ꢂC
DD
–48
–54
–60
DD
V
A
V
= 0V,V = 5V,V = 0V
SS
B
A
SS
MEASURE atV WITH CODE = 80
R
= 10kꢀ
W
H
AB
A
A
T
= 25ꢂC
A
1k
10k
100k
FREQUENCY– Hz
1M
1k
10k
100k
1M
FREQUENCY – Hz
TPC 16. PSRR vs. Frequency
TPC 13. Gain vs. Frequency vs. Code, RAB = 10 kΩ
120
100
80
0
DATA = 80
H
–6
–12
–18
–24
–30
DATA = 40
DATA = 20
DATA = 10
H
H
H
R
= 10kꢀ
R
= 50kꢀ
AB
AB
R
= 100kꢀ
DATA = 08
DATA = 04
AB
H
H
60
–36
–42
–48
–54
–60
DATA = 02
DATA = 01
H
H
V
V
V
T
=V = +2.75V
A2
DD
V
= +2.7V
= –2.7V
= 100mV rms
= 25ꢂC
40
DD
V
A
=V = –2.75V
SS
B2
V
V
T
SS
= +2.5V
IN
P
R
= 50kꢀ
AB
A
= 25ꢂC
A
SEE TEST CIRCUIT, FIGURE 22
A
20
1
10
FREQUENCY – kHz
100
1k
10k
100k
1M
FREQUENCY – Hz
TPC 17. Analog Crosstalk vs. Frequency
TPC 14. Gain vs. Frequency vs. Code, RAB = 50 kΩ
0
DATA = 80
H
–6
–12
–18
–24
–30
DATA = 40
DATA = 20
DATA = 10
H
H
H
DATA = 08
DATA = 04
H
H
–36
–42
–48
–54
–60
DATA = 02
DATA = 01
H
H
V
= +2.7V
= –2.7V
= 100mV rms
= 25ꢂC
DD
V
A
V
V
T
SS
R
= 100kꢀ
AB
A
A
1k
10k
100k
1M
FREQUENCY – Hz
TPC 15. Gain vs. Frequency vs. Code, RAB = 100 kΩ
–18–
REV. 0
AD5232
D IGITAL P O TENTIO METER FAMILY SELECTIO N GUID E
Resolution P ower
Num ber
of VRs
per
Ter m inal
Voltage
Inter face Nom inal
D ata Resistance
Contr ol (kꢀ)
(Num ber
of Wiper
Supply
P ar t
Cur r ent
Num ber P ackage Range (V)
P ositions) (ID D )(ꢄA) P ackages
Com m ents
AD 5201
1
±3, +5.5
3-wire
10, 50
33
40
µSOIC-10
Full ac Specs, Dual
Supply, Pwr-On-Reset,
Low Cost
AD 5220
AD 7376
1
1
5.5
UP/
10, 50, 100
128
40
PDIP, SO-8,
No Rollover,
DOWN
µSOIC-8
Pwr-On-Reset
±15 , +28
3-wire
10, 50, 100, 1000 128
100
PDIP-14,
SOL-16,
T SSOP-14
Single 28 V
or Dual ±15 V
Supply Operation
AD 5200
1
±3 , +5.5
3-wire
10, 50
256
40
µSOIC-10
Full ac Specs,
Dual Supply,
Pwr-On-Reset
AD 8400
AD 5260
1
1
5.5
3-wire
3-wire
1, 10, 50, 100
20, 50, 200
256
256
5
SO-8
Full ac Specs
±5, +15
60
T SSOP-14
+5 V to +15 V or ±5 V
Operation,
T C < 50 ppm/°C
AD 5241
AD 5231
1
1
±3, +5.5
2-wire
3-wire
10, 100, 1000
10, 50, 100
256
50
10
SO-14,
I2C Compatible,
T SSOP-14
T C < 50 ppm/°C
±2.75, +5.5
1024
T SSOP-16
Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD 5222
2
±3, +5.5
UP/
DOWN
10, 50, 100, 1000 128
80
SO-14,
T SSOP-14
No Rollover, Stereo,
Pwr-On-Reset,
T C < 50 ppm/°C
AD 8402
AD 5207
2
2
5.5
3-wire
3-wire
1, 10, 50, 100
10, 50, 100
256
256
5
PDIP, SO-14, Full ac Specs, nA
TSSOP-14
Shutdown Current
±3, +5.5
40
T SSOP-14
Full ac Specs, Dual
Supply, Pwr-On-
Reset, SDO
AD 5232
2
±2.75, +5.5
±2.75, +5.5
3-wire
3-wire
10, 50, 100
25, 250
256
10
20
T SSOP-16
T SSOP-16
Nonvolatile Memory,
Direct Program, I/D,
±6 dB Settability
AD 5235* 2
1024
Nonvolatile Memory,
Direct Program,
T C < 50 ppm/°C
AD 5242
2
±3, +5.5
±5, +15
2-wire
3-wire
10, 100, 1000
20, 50, 200
256
256
50
60
SO-16,
I2C Compatible,
T SSOP-16
T C < 50 ppm/°C
AD 5262* 2
T SSOP-16
+5 V to +15 V or ±5 V
Operation,
T C < 50 ppm/°C
AD 5203
AD 5233
4
4
5.5
3-wire
3-wire
10, 100
64
64
5
PDIP, SOL-24, Full ac Specs, nA
T SSOP-24
Shutdown Current
±2.75, +5.5
10, 50, 100
10
T SSOP-16
Nonvolatile Memory,
Direct Program,
I/D, ±6 dB Settability
AD 5204
4
±3, +5.5
3-wire
10, 50, 100
256
60
PDIP, SOL-24, Full ac Specs,
T SSOP-24
Dual Supply,
Pwr-On-Reset
AD 8403
AD 5206
4
6
5.5
3-wire
3-wire
1, 10, 50, 100
10, 50, 100
256
256
5
PDIP, SOL-24, Full ac Specs, nA
T SSOP-24 Shutdown Current
±3, +5.5
60
PDIP, SOL-24, Full ac Specs,
T SSOP-24
Dual Supply,
Pwr-On-Reset
*Future Product, consult factory for latest status.
Latest Digital Potentiometer Information located at: www.analog.com/DigitalPotentiometers
–19–
REV. 0
AD5232
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-Lead TSSO P
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
8
1
PIN 1
0.0433 (1.10)
MAX
0.006 (0.15)
0.002 (0.05)
8ꢂ
0ꢂ
0.028 (0.70)
0.020 (0.50)
0.0256 (0.65) 0.0118 (0.30)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
0.0075 (0.19)
–20–
REV. 0
相关型号：
AD5232BRUZ100-REEL7
IC DUAL 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16, Digital Potentiometer
ADI
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