AD53040KRP [ADI]
Ultrahigh Speed Pin Driver with Inhibit Mode; 超高速引脚驱动器，具有抑制模式
| 型号： | AD53040KRP |
| 厂家： | 
ADI |
| 描述： | Ultrahigh Speed Pin Driver with Inhibit Mode |
| 文件： | 总7页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrahigh Speed Pin Driver
with Inhibit Mode
a
AD53040
FUNCTIONAL BLOCK DIAGRAM
FEATURES
500 MHz Driver Operation
Driver Inhibit Function
V
V
V
EE
V
CC
CC
EE
100 ps Edge Matching
Guaranteed Industry Specifications
50 ⍀ Output Impedance
39nF
39nF
V
H
V
V
V
DATA
DATA
INH
HDCPL
>1.5 V/ns Slew Rate
50⍀
Variable Output Voltages for ECL, TTL and CMOS
High Speed Differential Inputs for Maximum Flexibility
Ultrasmall 20-Lead SOP Package with Built-In Heat Sink
DRIVER
OUT
INH
LDCPL
V
L
TV
CC
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
THERM
AD53040
1.0A/K
GND GND GND GND GND
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTION
The AD53040 transition from HI/LO or to inhibit is controlled
through the data and inhibit inputs. The input circuitry uses
high speed differential inputs with a common-mode range of
±3 V. This allows for direct interface to precision differential
ECL timing or the simplicity of stimulating the pin driver from a
single ended TTL or CMOS logic source. The analog logic HI/LO
inputs are equally easy to interface. Typically requiring 10 µA of
bias current, the AD53040 can be directly coupled to the
output of a digital-to-analog converter.
The AD53040 is a complete high speed pin driver designed for
use in digital or mixed-signal test systems. Combining a high
speed monolithic process with a unique surface mount package,
this product attains superb electrical performance while preserv-
ing optimum packaging densities and long-term reliability in an
ultrasmall 20-lead, SOP package with built-in heat sink.
Featuring unity gain programmable output levels of –3 V to
+8 V, with output swing capability of less than 100 mV to 9 V,
the AD53040 is designed to stimulate ECL, TTL and CMOS
logic families. The 500 MHz data rate capacity and matched
output impedance allows for real-time stimulation of these
digital logic families. To test I/O devices, the pin driver can
be switched into a high impedance state (Inhibit Mode), electri-
cally removing the driver from the path. The pin driver leakage
current inhibit is typically 100 nA and output charge transfer
entering inhibit is typically less than 20 pC.
The AD53040 is available in a 20-lead, SOP package with a
built-in heat sink and is specified to operate over the ambient
commercial temperature range of –25°C to +85°C.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(All specifications are at TJ = +85؇C ؎ 5؇C, +VS = +12 V ؎ 3%, –VS = –7 V ؎
3% unless otherwise noted. All temperature coefficients are measured at TJ = +75؇C–95؇C). (A 39 nF capacitor must be connected between
AD53040–SPECIFICATIONS
VCC and VHDCPL and between VEE and VLDCPL.)
Parameter
Min
Typ
Max Units
Test Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
Input Swing (Data to DATA, INH to INH)
Max (DATA, DATA) to Min (INH, INH)
Max (INH, INH) to Min (Data, DATA)
Bias Current
ECL
2
2
Volts
Volts
µA
±10
VIN = –2 V, 0.0 V
REFERENCE INPUTS
Bias Currents
–50
–2
+50
+8
µA
VL, VH = 5 V
OUTPUT CHARACTERISTICS
Logic High Range
Volts
DATA = H, VH = –2 V to +8 V
V
V
L = –3 V (VH = –2 V to +6 V)
L = –1 V (VH = +6 V to +8 V)
Logic Low Range
Amplitude (VH and VL)
–3
0.1
+5
9
Volts
Volts
DATA = L, VL = –3 V to +5 V, VH = +6 V
VL = –0.05 V, VH = +0.05 V and
V
L = –2 V, VH = +7 V
Absolute Accuracy
V
V
H Offset
H Gain + Linearity Error
–100
–100
+100 mV
% of VH + mV
+100 mV
% of VL + mV
DATA = H, VH = –2 V to +8 V, VL = –3 V
DATA = H, VH = –2 V to +8 V, VL = –3 V
DATA = L, VL = –3 V to +5 V, VH = +6 V
DATA = L, VL = –3 V to +5 V, VH = +6 V
VL, VH = 0 V, +5 V and –3 V, 0 V
DATA = H, VH = +3 V, VL = 0 V,
IOUT = 30 mA
±0.3 ±5
VL Offset
L Gain + Linearity Error
V
±0.3 ±5
0.5
47
Offset TC, VH or VL
Output Resistance
mV/°C
45
49
Ω
Output Leakage
Dynamic Current Limit
Static Current Limit
–1.0
+1.0 µA
mA
VOUT = –3 V to +8 V
150
±65
CBYP = 39 nF, VH = +7 V, VL = –2 V
Output to –3 V, VH = +8 V, VL = –1 V,
DATA = H and Output to +8 V, VH = +6 V,
mA
V
L = –3 V, DATA = L
PSRR, Drive Mode
35
dB
VS = VS ± 3%
DYNAMIC PERFORMANCE, DRIVE
(VH and VL)
Propagation Delay Time
1.5
2
ns
Measured at 50%, VH = +400 mV,
V
L = –400 mV
Measured at 50%, VH = +400 mV,
L = –400 mV
Measured at 50%, VH = +400 mV,
L = –400 mV
Propagation Delay TC
ps/°C
V
Delay Matching, Edge to Edge
100
ps
V
Rise and Fall Time
1 V Swing
3 V Swing
0.8
1.7
2.4
ns
ns
ns
Measured 20%–80%, VL = 0 V, VH = 1 V
Measured 10%–90%, VL = 0 V, VH = 3 V
Measured 10%–90%, VL = 0 V, VH = 5 V
5 V Swing
Rise and Fall Time TC
1 V Swing
3 V Swing
±1
±2
±3
ps/°C
ps/°C
ps/°C
Measured 20%–80%, VL = 0 V, VH = 1 V
Measured 10%–90%, VL = 0 V, VH = 3 V
Measured 10%–90%, VL = 0 V, VH = 5 V
5 V Swing
Overshoot, Undershoot and Preshoot
±(1% +50 mV)
% of Step + mV a. VL, VH = 0.0 V, 1.0 V
b. VL, VH = 0.0 V, 3.0 V
c. VL, VH = 0.0 V, 5.0 V
Settling Time
to 15 mV
to 4 mV
Delay Change vs. Pulsewidth
40
8
50
ns
µs
ps
VL = 0 V, VH = 0.5 V
L = 0 V, VH = 0.5 V
VL = 0 V, VH = 2 V,
V
Pulsewidth = 2.5 ns/7.5 ns, 30 ns/100 ns
REV. B
–2–
AD53040
Parameter
Min
Typ
Max
Units
Test Conditions
DYNAMIC PERFORMANCE, DRIVE
(VH and VL) (Continued)
Minimum Pulsewidth
3 V Swing
1.7
2.6
500
ns
4.0 ns Input, 10%/90% Output,
L = 0 V, VH = 3 V
6.0 ns Input, 10%/90% Output,
VL = 0 V, VH = 5 V
V
5 V Swing
ns
Toggle Rate
MHz
VL = –1.8 V, VH = –0.8 V,
VOUT > 600 mV p-p
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit
2
2
5
5
ns
ns
Measured at 50%, VH = +2 V,
V
L = –2 V
Delay Time, Inhibit to Active
Measured at 50%, VH = +2 V,
V
V
L = –2 V
H = 0 V, VL = 0 V
I/O Spike
Output Capacitance
<200
5
mV, p-p
pF
Driver Inhibited
POWER SUPPLIES
Total Supply Range
19
V
Positive Supply
Negative Supply
+12
–7
V
V
Positive Supply Current
Negative Supply Current
Total Power Dissipation
Temperature Sensor Gain Factor
75
75
1.43
mA
mA
W
1.15
1.0
µA/K
RLOAD = 10 K, VSOURCE = +12 V
NOTES
Connecting or shorting the decoupling capacitors to ground will result in the destruction of the device.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Power Supply Voltage
+VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V
–VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 V
Inputs
2Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3To ensure lead coplanarity (±0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24°C
± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.
DATA, DATA, INH, INH . . . . . . . . . . . . . . . . +5 V, –3 V
DATA to DATA, INH to INH . . . . . . . . . . . . . . . . . . ±3 V
VH, VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . +9 V, –4 V
VH to VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V, 0 V
Outputs
V
OUT Short Circuit Duration . . . . . . . . . . . . . . . .Indefinite2
ORDERING GUIDE
Shipment Method,
VOUT Range in Inhibit Mode
VHDCPL . . . . . Do Not Connect Except for Capacitor to VCC
VLDCPL . . . . . Do Not Connect Except for Capacitor to VEE
THERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V, 0 V
Environmental
Operating Temperature (Junction) . . . . . . . . . . . . . .+175°C
Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec)3 . . . . . . . . . .+260°C
Package
Quantity Per
Package
Model
Description
Shipping Container Option
AD53040KRP 20-Lead Power SOIC Tube, 38 Pieces
RP-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53040 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD53040
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Pin
Name
Pin
1
2
V
V
20 THERM
CC
Number Pin Functional Description
19 TV
CC
CC
VCC
1, 2
Positive Power Supply. Both pins
should be connected to minimize in-
ductance and allow maximum speed of
operation. VCC should be decoupled to
GND with a low inductance 0.1 µF
capacitor.
Negative Power Supply. Both pins
should be connected to keep the induc-
tance down and allow maximum speed
of operation. VEE should be decoupled
to GND with a low inductance 0.1 µF
capacitor.
3
18
V
V
V
H
HDCPL
4
17 GND
GND
AD53040
5
16
15
14
13
12
11
GND
V
TOP VIEW
OUT
(Not to Scale)
6
GND
V
L
7
GND
DATA
DATA
INH
COPPER
SLUG UP
LDCPL
8
V
EE
VEE
8, 9
9
V
EE
10
INH
Table I. Pin Driver Truth Table
GND
4, 6, 14,
16, 17
Output
State
Device Ground. These pins should be
connected to the circuit board’s ground
plane at the pins.
Analog Input that sets the voltage level
of a Logic 0 of the driver. Determines
the driver output for DATA > DATA.
Analog input that sets the voltage level
of a Logic 1 of the driver. Determines
the driver output for DATA > DATA.
The Driver Output. The nominal out-
put impedance is 50 Ω.
Internal supply decoupling for the
output stage. This pin is connected
to VCC through a 39 nF minimum
capacitors.
DATA
DATA
INH
INH
0
1
0
1
1
0
1
0
0
0
1
1
1
1
0
0
VL
VH
Hi-Z
Hi-Z
VL
15
18
VH
Table II. Package Thermal Characteristics
Air Flow, FM
JC, ؇C/W
JA, ؇C/W
VOUT
5
3
0
50
400
4
4
4
50
49
34
VHDCPL
VLDCPL
7
Internal supply decoupling for the
output stage. This pin is connected
to VEE through a 39 nF minimum
capacitors.
INH, INH 10, 11
ECL compatible input that control the
high impedance state of the driver.
When INH > INH, the driver goes into
a high impedance state.
DATA,
DATA
13, 12
ECL compatible inputs that determines
the high and low state of the driver.
Driver output is high for DATA >
DATA.
TVCC
19
20
Temperature Sensor Start-Up Pin. This
pin should be connected to VCC
.
THERM
Temperature Sensor Output Pin. A
resistor (10K) should be connected
between THERM and VCC. The ap-
proximate die temperature can be de-
termined by measuring the current
through the resistor. The typical scale
factor is 1 µA/K.
REV. B
–4–
AD53040
APPLICATION INFORMATION
Several points about the current-limit circuitry should be noted.
First, the limiting currents are not tightly controlled, as they are
functions of both absolute transistor VBES and junction tem-
perature; higher dc output current is available at lower junction
temperatures. Second, it is essential to connect the VHDCPL
capacitor to the positive supply (and the VLDCPL capacitor to
the negative supply)—failure to do so causes considerable ther-
mal stress in the current-limiting resistor(s) during normal sup-
ply sequencing and may ultimately cause them to fail, rendering
the part nonfunctional. Finally, the AD53040 may appear to
function normally for small output steps (less than 3 V or so) if
one or both of these capacitors is absent, but it will exhibit
excessive rise or fall times for steps of larger amplitude.
Power Supply Distribution, Bypassing and Sequencing
The AD53040 draws substantial transient currents from its
power supplies when switching between states and careful design
of the power distribution and bypassing is key to obtaining speci-
fied performance. Supplies should be distributed using broad,
low inductance traces or (preferably) planes in a multilayered
board with a dedicated ground-plane layer. All of the device’s
power supply pins should be used to minimize the internal in-
ductance presented by the part’s bond wires. Each supply must
be bypassed to ground with at least one 0.1 µF capacitor; chip-
style capacitors are preferable as they minimize inductance. One
or more 10 µF (or greater) Tantalum capacitors per board are
also advisable to provide additional local energy storage.
The AD53040 does not require special power-supply sequencing.
However, good design practice dictates that digital and analog
control signals not be applied to the part before the supplies are
stable. Violating this guideline will not normally destroy the
part, but the active inputs can draw considerable current until
the main supplies are applied.
The AD53040’s current-limit circuitry also requires external
bypass capacitors. Figure 1 shows a simplified schematic of the
positive current-limit circuit. Excessive collector current in out-
put transistor Q49 creates a voltage drop across the 10 Ω resis-
tor, which turns on PNP transistor Q48. Q48 diverts the rising-
edge slew current, shutting down the current mirror and remov-
ing the output stage’s base drive. The VHDCPL pin should be
bypassed to the positive supply with a 0.039 µF capacitor, while
the VLDCPL pin (not shown) requires a similar capacitor to the
negative supply- these capacitors ensure that the AD53040
doesn’t current limit during normal output transitions up the its
full 9 V rated step size. Both capacitors must have minimum-
length connections to the AD53040. Here again, chip capacitors
are ideal.
Digital Input Range Restrictions
Total range amongst all digital signals (DATA, DATA, INH,
and INH) has to be less than or equal to 2 V to meet specified
timing. The device will function above 2 V with reduced perfor-
mance up to the absolute maximum limit. This performance
degradation might not be noticed in all modes of operation. Of
all the six possible transitions (VH v VL, VL v VH, VH v INH,
INH v VH, VL v INH and INH v VL), there may be only one
that would show a degradation, usually in delay time. Taken to
the extreme, the driver may fail to achieve a proper output volt-
age, output impedance or may fail to fully inhibit.
VPOS
10⍀؎10%
An example of a scenario that would not work for the AD53040
is if the part is driven using 5 V single-ended CMOS. One pin of
each differential input would be tied to a +2.5 V reference level
and the logic voltages would be applied to the other. This would
meet the Absolute Maximum Rating of ±3 V because the max
differential is ±2.5 V. It is however possible, for example for
0.0 V to be applied to the INH input and +5 V to be applied to
the DATA input. This 5 V difference far exceeds the 2.0 V
limitation given above. Even using 3 V CMOS or TTL the
difference between logic high and logic low is greater than or
equal to 3 V which will not properly work. The only solution is
to use resistive dividers or equivalent to reduce the voltage levels.
V
Q48
HDCPL
RISING-EDGE SLEW
CONTROL CURRENT
LEVEL-SHIFTED
LOGIC DRIVE
V
H
VNEG
Q49
Q50
OUT
5.12V
550mV
/DIV
Figure 1. Simplified Schematic of the AD53040 Output
Stage and Positive Current Limit Circuitry
–380mV
66.25ns
500ps/DIV
71.25ns
Figure 2. 5 V Output Swing
REV. B
–5–
AD53040
NOTE:
1. 50⍀ TERMINATION TO BE AS CLOSE TO RECEIVER
AS POSSIBLE. (END OF TRACE MARKED BY *). THROUGH
SMA CONNECTS BETWEEN MC10EL16 OUTPUTS AND DUT.
2. NO VIAS ALLOWED ON VOUT LINE.
3. SMA ON V
IMPEDANCE MATCH.
TO BE MOUNTED ON ITS SIDE FOR BEST
OUT
4. ONE DIMENSION OF BOARD TO BE 4-1/2 INCHES.
5. DUT PACKAGE IS TO BE CENTERED ON BOARD.
6. ALL RESISTORS AND NONELECTROLYTIC CAPS ARE
0805-SIZE SURFACE MOUNT.
7. SEE DATA SHEET FOR HIDDEN POWER AND GROUND PINS
ON LOGIC GATES.
8. ALL 100nF BYPASS CAPACITORS TO BE LOCATED CLOSE
TO PACKAGE.
V
LOW
9. PCB IS TO BE 4-LAYER WITH POWER GND ( ) AND –2V AS
INNER PLANES.
V
HIGH
50⍀
50⍀
DATA
J1
SMB
SMB
C1
0.1F
+V
S
C2
0.1F
U1
MC10EL16
J4
1
8
50⍀
R6
2
3
7
C19
0.1F
6
50⍀
J8
5
SIDESMB
–5.2V
SMB
R4
R3
J3
C12
0.01F
C21
0.1F
TEST_LD
50⍀ 50⍀
R7
50⍀
C18
5pF
THERM
TV
CC
C16
0.039F
HQG1
+V
–2V
C14
0.1F
S
TH
50⍀
IL+
VH
VL
J7
G2H
G2L
INH
J2
SMB
SMB
U2
MC10EL16
SIDESMB
V
OUT
J5
U 3
50⍀
1
8
V
AD53040
OUT
50⍀
2
3
7
DATA
R5
50⍀
6
50⍀
IL–
5
–5.2V
SMB
INH
–V
S
R1
50⍀ 50⍀
R2
J6
C13
0.01F
JP1
1
C22
0.1F
C17
0.039F
GND
TP
–2V
JP2
C15
0.1F
PWR
GND
+V
S
1
C3
0.1F
TP
JP3
1
–V
S
P1
TP
–V
1
S
V
LOW
9
2
10
–2V
V
–5.2V
V
EE
HIGH
3
11
4
12
5
13
6
–V
V
S
CC
THERM
–5.2V
C9
0.1F
C10
0.1F
C11
0.1F
GND
+V
S
+
C5
1F
C4
1F
C7
1F
C6
1F
C8
0.1F
14
7
15
8
DB15
Figure 3. Evaluation Board Schematic
REV. B
–6–
AD53040
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Thermally Enhanced Small Outline Package (PSOP)
(RP-20)
0.5118 (13.00)
0.4961 (12.60)
20
11
0.1890 (4.80) 0.4193 (10.65)
0.1791 (4.55) 0.3937 (10.00)
HEAT
SINK
0.2992 (7.60)
0.2914 (7.40)
1
10
PIN 1
0.3340 (8.61)
0.3287 (8.35)
0.1043 (2.65)
0.0926 (2.35)
8°
0°
0.0500
(1.27)
BSC
0.0201 (0.51)
0.0118 (0.30)
0.0295 (0.75)
0.0098 (0.25)
SEATING
PLANE
0.0500 (1.27)
0.0057 (0.40)
x 45°
0.0130 (0.33)
0.0040 (0.10)
STANDOFF
REV. B
–7–
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