AD5317BRUZ_技术文档

2.5 V to 5.5 V, 400 μA, Quad Voltage Output,

8-/10-/12-Bit DACs in 16-Lead TSSOP

AD5307/AD5317/AD5327

GENERAꢀ DESCRIPTION

FEATURES

AD5307: 4 buffered 8-bit DACs in 16-lead TSSOP

A version: 1 ꢀSB INꢀ; B version: 0.625 ꢀSB INꢀ

AD5317: 4 buffered 10-bit DACs in 16-lead TSSOP

A version: 4 ꢀSB INꢀ; B version: 2.5 ꢀSB INꢀ

AD5327: 4 buffered 12-bit DACs in 16-lead TSSOP

A version: 16 ꢀSB INꢀ; B version: 10 ꢀSB INꢀ

ꢀow power operation: 400 μA @ 3 V, 500 μA @ 5 V

2.5 V to 5.5 V power supply

The AD5307/AD5317/AD5327¹are quad 8-,10-,12-bit buffered

voltage-output DACs in 16-lead TSSOP that operate from single

2.5 V to 5.5 V supplies and consume 400 μA at 3 V. Their on-

chip output amplifiers allow the outputs to swing rail-to-rail with

a slew rate of 0.7 V/μs. The AD5307/AD5317/AD5327 utilize

versatile 3-wire serial interfaces that operate at clock rates up to

30 MHz; these parts are compatible with standard SPI, QSPI,

MICROWIRE, and DSP interface standards.

Guaranteed monotonic by design over all codes

ꢀDAC

Power down to 90 nA @ 3 V, 300 nA @ 5 V (

Double-buffered input logic

pin)

The references for the four DACs are derived from two reference

pins (one per DAC pair). These reference inputs can be configured

as buffered or unbuffered inputs. Each part incorporates a power-

on reset circuit, ensuring that the DAC outputs power up to 0 V

and remain there until a valid write to the device takes place.

Buffered/unbuffered reference input options

Output range: 0 V to V_REFor 0 V to 2 V_REF

Power-on reset to 0 V

ꢀDAC

Simultaneous update of outputs (

CꢀR

pin)

CLR

Asynchronous clear facility (

pin)

There is also an asynchronous active low

DACs to 0 V. The outputs of all DACs can be updated simul-

LDAC

pin that clears all

ꢀow power, SPI®-, QSPI™-, MICROWIRE™-, and DSP-

compatible 3-wire serial interface

SDO daisy-chaining option

On-chip rail-to-rail output buffer amplifiers

Temperature range of −40°C to +105°C

taneously using the asynchronous

input. Each part

contains a power-down feature that reduces the current

consumption of the device to 300 nA @ 5 V (90 nA @ 3 V). The

parts can also be used in daisy-chaining applications using the

SDO pin.

APPꢀICATIONS

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

All three parts are offered in the same pinout, allowing users to

select the amount of resolution appropriate for their application

without redesigning their circuit board.

Industrial process control

FUNCTIONAꢀ BꢀOCK DIAGRAM

V

AB

DD

REF

GAIN-SELECT

LOGIC

AD5307/AD5317/AD5327

LDAC

INPUT

REGISTER

DAC

REGISTER

STRING

DAC A

V

A

B

BUFFER

OUT

SCLK

SYNC

INPUT

REGISTER

DAC

REGISTER

STRING

DAC B

BUFFER

OUT

INTERFACE

LOGIC

INPUT

REGISTER

DAC

REGISTER

STRING

DAC C

C

D

OUT

DIN

INPUT

REGISTER

DAC

REGISTER

STRING

DAC D

V

OUT

SDO

POWER-ON

RESET

POWER-DOWN

LOGIC

DCEN

LDAC CLR

V

CD

PD GND

REF

Figure 1.

¹Protected by U.S. Patent No. 5,969,657; other patents pending.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5307/AD5317/AD5327

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Shift Register .................................................................... 17

Control Bits ................................................................................. 17

Low Power Serial Interface ....................................................... 18

Daisy Chaining ........................................................................... 18

Double-Buffered Interface ........................................................ 18

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 13

Transfer Function ........................................................................... 14

Functional Description.................................................................. 15

Digital-to-Analog Section ......................................................... 15

Resistor String............................................................................. 15

DAC Reference Inputs ............................................................... 15

Output Amplifier........................................................................ 16

Power-On Reset .......................................................................... 16

Serial Interface ................................................................................ 17

LDAC

Load DAC Input (

).......................................................... 18

Power-Down Mode.................................................................... 18

Microprocessor Interfacing....................................................... 19

Applications..................................................................................... 20

Typical Application Circuit ....................................................... 20

Driving V_DDfrom the Reference Voltage ................................ 20

Bipolar Operation....................................................................... 20

Opto-Isolated Interface for Process-Control Applications... 21

Decoding Multiple AD5307/AD5317/AD5327 Devices....... 21

AD5307/AD5317/AD5327 as Digitally Programmable

Window Detectors ..................................................................... 21

Daisy Chaining ........................................................................... 22

Power Supply Bypassing and Grounding................................ 22

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 25

REVISION HISTORY

3/06—Rev. B to Rev. C

8/03—Rev. 0 to Rev. A

Changes to Table 3............................................................................ 5

Changes to Ordering Guide .......................................................... 25

Added A Version ................................................................Universal

Changes to Features ..........................................................................1

Changes to Specifications.................................................................2

Changes to Absolute Maximum Ratings........................................6

Changes to Ordering Guide.............................................................6

Changes to TPC 21......................................................................... 12

Added Octals section to Table II .................................................. 20

Updated Outline Dimensions....................................................... 21

10/05—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Bipolar Operation Section ........................................ 21

Changes to Ordering Guide .......................................................... 25

Rev. C | Page 2 of 28

AD5307/AD5317/AD5327

SPECIFICATIONS

V_DD= 2.5 V to 5.5 V, V_REF= 2 V, R_L= 2 kΩ to GND, C_L= 200 pF to GND. All specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

A Version¹

Typ

B Version

Typ

Parameter²

DC PERFORMANCE^{3, 4}

Min

Max

Min

Max

Unit

Conditions/Comments

AD5307

Resolution

8

Bits

LSB

Relative Accuracy

Differential Nonlinearity

0.15

0.02

1

0.15

0.02

0.625

0.25

Guaranteed monotonic by design

over all codes

AD5317

Resolution

10

Bits

LSB

Relative Accuracy

Differential Nonlinearity

0.5

0.05

4

0.5

0.05

2.5

0.5

Guaranteed monotonic by design

over all codes

AD5327

Resolution

12

2

12

2

Bits

LSB

Relative Accuracy

Differential Nonlinearity

16

1

10

1

0.2

Guaranteed monotonic by design

over all codes

Offset Error

5

0.3

10

60

5

0.3

10

60

mV

V_DD= 4.5 V, gain = 2; see Figure 29

and Figure 30

Gain Error

1.25

% FSR

mV

V_DD= 4.5 V, gain = 2; see Figure 29

and Figure 30

Lower Dead Band⁵

Upper Dead Band

60

See Figure 29, lower dead band

exists only if offset error is negative

60

mV

See Figure 30, upper dead band

exists only if V_REF= V_DDand offset

plus gain error is positive

Offset Error Drift⁶

Gain Error Drift

−12

−5

−12

−5

ppm of

FSR/°C

ppm of

FSR/°C

DC Power Supply Rejection Ratio

DC Crosstalk

−60

200

−60

200

dB

∆V_DD= 10%

mV

R_L= 2 kΩ to GND or V_DD

DAC REFERENCE INPUTS

V_REFInput Range

1

V_DD

1

V_DD

V

Buffered reference mode

0.25

V

Unbuffered reference mode

V_REFInput Impedance (R_DAC

)

>10

90

>10

90

MΩ

Buffered reference mode and

power-down mode

74

37

74

37

kΩ

Unbuffered reference mode,

0 V to V_REFoutput range

45

Unbuffered reference mode,

0 V to 2 V_REFoutput range

Reference Feedthrough

−90

−75

−90

−75

dB

Frequency = 10 kHz

Channel-to-Channel Isolation

OUTPUT CHARACTERISTICS

Minimum Output Voltage⁷

0.001

V

A measure of the minimum drive

capability of the output amplifier

Maximum Output Voltage

V_DD

−

V_DD

−

A measure of the maximum drive

capability of the output amplifier

0.001

0.5

25

0.001

0.5

25

DC Output Impedance

Short-Circuit Current

Ω

mA

μs

V_DD= 5 V

16

V_DD= 3 V

Power-Up Time

2.5

Coming out of power-down mode,

V

_DD= 5 V

Coming out of power-down mode,

_DD= 3 V

5

μs

V

Rev. C | Page 3 of 28

AD5307/AD5317/AD5327

A Version¹

Typ

B Version

Typ

Parameter²

Min

Max

Min

Max

Unit

Conditions/Comments

LOGIC INPUTS

Input Current

1

0.8

0.6

0.5

1

0.8

0.6

0.5

mA

V

Input Low Voltage, V_IL

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

V

Input High Voltage, V_IH

(Excluding DCEN)

1.7

2.4

1.7

2.4

V

V_DD= 2.5 V to 5.5 V; TTL and

1.8 V CMOS compatible

Input High Voltage, V_IH

(DCEN)

V_DD= 5 V 10%

2.1

2.0

2.1

2.0

V

V_DD= 3 V 10%

V_DD= 2.5 V

V

Pin Capacitance

3

pF

LOGIC OUTPUT (SDO)

V_DD= 4.5 V to 5.5 V

Output Low Voltage, V_OL

Output High Voltage, V_OH

V_DD= 2.5 V to 3.6 V

0.4

V

I_SINK= 2 mA

V_DD− 1

0.4

I_SOURCE= 2 mA

Output Low Voltage, V_OL

Output High Voltage, V_OH

V

I_SINK= 2 mA

V_DD

0.5

−

V_DD

0.5

−

I_SOURCE= 2 mA

Floating State Leakage Current

Floating State Output Capacitance

POWER REQUIREMENTS

V_DD

1

μA

pF

DCEN = GND

3

2.5

5.5

2.5

5.5

V

I_DD(Normal Mode)⁸

V_IH= V_DDand V_IL= GND

V_DD= 4.5 V to 5.5 V

500

400

900

750

500

400

900

750

μA

All DACs in unbuffered mode; in

buffered mode, extra current is

typically x mA per DAC, where

x = 5 mA + V_REF/R_DAC

V_DD= 2.5 V to 3.6 V

I_DD(Power-Down Mode)

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

V_IH= V_DDand V_IL= GND

0.3

1

0.3

1

μA

0.09

¹Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.

²See the Terminology section.

³DC specifications tested with the outputs unloaded, unless otherwise noted.

⁴Linearity is tested using a reduced code range: AD5307 (Code 8 to Code 255); AD5317 (Code 28 to Code 1023); AD5327 (Code 115 to Code 4095).

⁵This corresponds to x codes, where x = deadband voltage/LSB size.

⁶Guaranteed by design and characterization; not production tested.

⁷For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V_REF= V_DDand offset plus

gain error must be positive.

⁸Interface inactive. All DACs active. DAC outputs unloaded.

Rev. C | Page 4 of 28

AD5307/AD5317/AD5327

AC CHARACTERISTICS

V_DD= 2.5 V to 5.5 V, R_L= 2 kΩ to GND, C_L= 200 pF to GND. All specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

A, B Versions¹

Parameter^{2, 3}

Min

Typ

Max

Unit

Conditions/Comments

Output Voltage Settling Time

AD5307

AD5317

V_REF= V_DD= 5 V

6

7

8

9

10

μs

1/4 scale to 3/4 scale change (0x40 to 0xC0)

1/4 scale to 3/4 scale change (0x100 to 0x300)

1/4 scale to 3/4 scale change (0x400 to 0xC00)

AD5327

Slew Rate

0.7

12

0.5

4

0.5

1

3

200

−70

V/μs

nV-s

kHz

dB

Major-Code Change Glitch Energy

Digital Feedthrough

SDO Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

1 LSB change around major carry

Daisy-chain mode; SDO load is 10 pF

V_REF= 2 V 0.1 V p-p; unbuffered mode

V_REF= 2.5 V 0.1 V p-p; frequency = 10 kHz

¹Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.

²Guaranteed by design and characterization; not production tested.

³See the Terminology section.

TIMING CHARACTERISTICS

V_DD= 2.5 V to 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

A, B Versions

ꢀimit at T_MIN, T_MAX

Parameter^{1, 2,}

Unit

Conditions/Comments

3

t₁

t₂

t₃

t₄

33

13

5

ns min

ns max

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge set-up time

Data set-up time

Data hold time

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

t₅

t₆

t₇

4.5

5

t₈

50

20

0

t₉

LDAC pulse width

t₁₀

t₁₁

t₁₂

SCLK falling edge to LDAC rising edge

CLR pulse width

SCLK falling edge to LDAC falling edge

SCLK rising edge to SDO valid (V_DD= 3.6 V to 5.5 V)

SCLK rising edge to SDO valid (V_DD= 2.5 V to 3.5 V)

SCLK falling edge to SYNC rising edge

SYNC rising edge to SCLK rising edge

SYNC rising edge to LDAC falling edge

4, 5

t₁₃

20

25

5

t₁₄

t₁₅

t₁₆

8

0

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_R= t_F= 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 3 and Figure 4.

⁴This is measured with the load circuit of Figure 2. t₁₃determines maximum SCLK frequency in daisy-chain mode.

⁵Daisy-chain mode only.

Rev. C | Page 5 of 28

AD5307/AD5317/AD5327

2mA

I

OL

TO OUTPUT

V

OH (MIN)

C

L

50pF

2mA

I

OH

Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications

t₁

SCLK

t₂

t₄

t₃

t₇

t₈

SYNC

DIN

t₆

t₅

DB15

DB0

t₁₂

t₉

1

LDAC

t₁₀

2

LDAC

t₁₁

CLR

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE.

SYNCHRONOUS LDAC UPDATE MODE.

2

Figure 3. Serial Interface Timing Diagram

t₁

SCLK

t₁₄

t₂

t₃

t₈

t₄

SYNC

t₁₅

t₁₆

t₉

LDAC

DIN

t₆

t₅

DB0

DB15'

DB15

DB0'

DB0

DB15

INPUT WORD FOR DAC N

INPUT WORD FOR DAC (N+1)

INPUT WORD FOR DAC N

t₁₃

SDO

UNDEFINED

Figure 4. Daisy-Chaining Timing Diagram

Rev. C | Page 6 of 28

AD5307/AD5317/AD5327

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 4.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter¹

Ratings

V_DDto GND

−0.3 V to +7 V

Digital Input Voltage to GND

Digital Output Voltage to GND

Reference Input Voltage to GND

V_OUTA − V_OUTD to GND

Operating Temperature Range

Industrial (A, B Versions)

Storage Temperature Range

Junction Temperature (T_Jmax)

16-Lead TSSOP

−0.3 V to V_DD+ 0.3 V

−40°C to +105°C

−65°C to +150°C

150°C

Power Dissipation

θ_JAThermal Impedance

Reflow Soldering

(T_Jmax − T_A)/θ_JA

150.4°C/W

Peak Temperature

220°C

Time at Peak Temperature

10 sec to 40 sec

¹Transient currents of up to 100 mA do not cause SCR latch-up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page 7 of 28

AD5307/AD5317/AD5327

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

SDO

CLR

SYNC

15

LDAC

AD5307/

AD5317/ 14 SCLK

AD5327

V

DD

13

12

11

10

9

DIN

V

A

B

C

OUT

TOP VIEW

(Not to Scale)

GND

V

D

OUT

V

AB

CD

PD

REF

DCEN

V

REF

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

No.

Mnemonic Description

1

CLR

Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.

2

LDAC

Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this

pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous

update of all DAC outputs. Alternatively, this pin can be tied permanently low.

3

V_DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF

capacitor in parallel with a 0.1 μF capacitor to GND.

4

5

6

7

V_OUT

A

B

C

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of

the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range

of 0.25 V to V_DDin unbuffered mode and 1 V to V_DDin buffered mode.

V_REFAB

8

V_REFCD

Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of

the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range

of 0.25 V to V_DDin unbuffered mode and 1 V to V_DDin buffered mode.

9

DCEN

PD

Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is

being used in standalone mode.

Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this

pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to

300 nA @ 5 V (90 nA @ 3 V).

10

11

12

13

V_OUT

GND

DIN

D

Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of

the serial clock input. The DIN input buffer is powered down after each write cycle.

14

15

SCLK

SYNC

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be

transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers

on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the

following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and

the write sequence is ignored by the device.

16

SDO

Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in

the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the

falling edge of the clock.

Rev. C | Page 8 of 28

AD5307/AD5317/AD5327

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.3

0.2

T

= 25°C

A

T

= 25°C

V

= 5V

A

DD

V

= 5V

DD

0.5

0

0.1

0

–0.1

–0.5

–1.0

–0.2

–0.3

0

50

100

150

200

250

0

50

100

150

200

250

CODE

Figure 6. AD5307 INL

Figure 9. AD5307 DNL

3

2

0.6

0.4

T

V

= 25°C

T = 25°C

A

= 5V

V

= 5V

DD

1

0.2

0

–0.2

–1

–2

–3

–0.4

–0.6

200

400

600

900

1000

200

400

600

800

1000

CODE

Figure 7. AD5317 INL

Figure 10. AD5317 DNL

1.0

0.5

12

8

T

V

= 25°C

= 5V

A

T

V

= 25°C

= 5V

A

DD

4

0

–4

–8

–12

–0.5

–1.0

1000

2000

3000

4000

1000

2000

3000

4000

CODE

Figure 11. AD5327 DNL

Figure 8. AD5327 INL

Rev. C | Page 9 of 28

AD5307/AD5317/AD5327

0.2

0.1

0.50

T

V

= 25°C

A

T

V

= 25°C

MAX INL

A

= 5V

DD

= 2V

REF

0

0.25

0

GAIN ERROR

MAX DNL

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

MIN INL

OFFSET ERROR

–0.25

–0.50

0

1

2

3

4

5

0

1

2

3

4

5

6

V

(V)

V

(V)

DD

REF

Figure 12. AD5307 INL Error and DNL Error vs. V_REF

Figure 15. Offset Error and Gain Error vs. V_DD

0.5

0.4

5

4

3

2

1

0

V

= 5V

DD

= 3V

REF

MAX INL

5V SOURCE

3V SOURCE

0.3

0.2

MAX DNL

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

MIN DNL

3V SINK

5V SINK

MIN INL

80

–40

0

40

120

0

1

2

3

4

5

6

TEMPERATURE (°C)

SINK/SOURCE CURRENT (mA)

Figure 13. AD5307 INL Error and DNL Error vs. Temperature

Figure 16. V_OUTSource and Sink Current Capability

600

500

400

300

200

100

0

1.0

V

= 5V

= 2V

DD

REF

0.5

0

T

V

= 25°C

A

= 5V

= 2V

DD

V

REF

GAIN ERROR

OFFSET ERROR

–0.5

–1.0

–40

ZERO SCALE

FULL SCALE

120

0

40

80

CODE

TEMPERATURE (°C)

Figure 17. Supply Current vs. DAC Code

Figure 14. AD5307 Offset Error and Gain Error vs. Temperature

Rev. C | Page 10 of 28

AD5307/AD5317/AD5327

600

500

400

300

200

100

0

–40°C

+25°C

T

V

= 25°C

A

= 5V

DD

= 5V

REF

CH1

+105°C

V

A

OUT

SCLK

CH2

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

V

CH1 1V, CH2 5V, TIME BASE = 1µs/DIV

DD

Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change)

Figure 18. Supply Current vs. Supply Voltage

0.5

T

V

= 25°C

A

0.4

0.3

= 5V

DD

= 2V

REF

CH1

V

DD

–40°C

+25°C

0.2

0.1

CH2

V

A

OUT

+105°C

0

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

V

CH1 2.00V, CH2 200mV, TIME BASE = 200µs/DIV

DD

Figure 22. Power-On Reset to 0 V

Figure 19. Power-Down Current vs. Supply Voltage

800

700

600

500

400

300

DECREASING

T

= 25°C

A

T

V

= 25°C

A

= 5V

DD

= 2V

REF

INCREASING

CH1

V

= 5V

DD

V

A

OUT

INCREASING

DECREASING

CH2

V

= 3V

DD

PD

0

1

2

3

4

5

V

(V)

LOGIC

CH1 500MV, CH2 5.00V, TIME BASE = 1µs/DIV

Figure 20. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing

and Decreasing

Figure 23. Exiting Power-Down to Midscale

Rev. C | Page 11 of 28

AD5307/AD5317/AD5327

0.02

0.01

0

V

= 5V

DD

= 25°C

T

A

V

= 3V

V

= 5V

DD

–0.01

–0.02

0

1

2

3

4

5

6

350

400

450

I

500

(µA)

550

600

V

(V)

REF

DD

Figure 27. Full-Scale Error vs. V_REF

Figure 24. I_DDHistogram with V_DD= 3 V and V_DD= 5 V

2.50

2.49

2.48

2.47

1µs/DIV

150ns/DIV

Figure 25. AD5327 Major-Code Transition Glitch Energy

Figure 28. DAC-to-DAC Crosstalk

10

0

–10

–20

–30

–40

–50

–60

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response)

Rev. C | Page 12 of 28

AD5307/AD5317/AD5327

TERMINOLOGY

Relative Accuracy

Major-Code Transition Glitch Energy

For the DAC, relative accuracy, or integral nonlinearity (INL), is

a measure of the maximum deviation in LSB from a straight line

passing through the endpoints of the DAC transfer function.

Figure 6 through Figure 8 show plots of typical INL vs. code.

Major-code transition glitch energy is the energy of the impulse

injected into the analog output when the code in the DAC

register changes state. It is normally specified as the area of the

glitch in nV-s and is measured when the digital code is changed

by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00

or 100 . . . 00 to 011 . . . 11).

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. Figure 9 through Figure 11 show plots of

typical DNL vs. code.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device, but it is measured when the DAC is not being written to

SYNC

(

held high). It is specified in nV-s and is measured with a

full-scale change on the digital input pins, that is, from all 0s to

all 1s or vice versa.

Offset Error

Offset error is a measure of the deviation in the output voltage

from 0 V when zero-code is loaded to the DAC (see Figure 29

and Figure 30.) It can be negative or positive. It is expressed in

millivolts.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s or vice versa) in the input register of another DAC.

It is measured in standalone mode and is expressed in nV-s.

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the actual DAC transfer characteristic from

the ideal expressed as a percentage of the full-scale range.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

Offset Error Drift

Offset error drift is a measure of the change in offset error

with changes in temperature. It is expressed in (ppm of full-

scale range)/°C.

LDAC

code change (all 0s to all 1s or vice versa) while keeping

LDAC

high, and then pulsing

low and monitoring the output of

the DAC whose digital code has not changed. The area of the

glitch is expressed in nV-s.

Gain Error Drift

Gain error drift is a measure of the change in gain error

with changes in temperature. It is expressed in (ppm of full-

scale range)/°C.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs

with a full-scale code change (all 0s to all 1s or vice versa) with

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by

changes in the supply voltage. It is the ratio of the change in

LDAC

low while monitoring the output of another DAC. The

V_OUTto a change in V_DDfor full-scale output of the DAC. It is

measured in decibels. V_REFis held at 2 V, and V_DDis varied 10%.

energy of the glitch is expressed in nV-s.

DC Crosstalk

Multiplying Bandwidth

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is measured

with a full-scale output change on one DAC while monitoring

another DAC. It is expressed in microvolts.

The amplifiers within the DAC have a finite bandwidth, and the

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal at

the DAC output to the reference input when the DAC output is not

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its attenuated

version using the DAC. The sine wave is used as the reference for

the DAC, and the THD is a measure of the harmonics present

on the DAC output. It is measured in decibels.

LDAC

being updated (that is,

is high). It is expressed in decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is the ratio of the amplitude of the

signal at the output of one DAC to a sine wave on the reference

input of another DAC. It is measured in decibels.

Rev. C | Page 13 of 28

AD5307/AD5317/AD5327

TRANSFER FUNCTION

GAIN ERROR

+

OFFSET ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

DAC CODE

ACTUAL

IDEAL

LOWER

DEAD BAND

CODES

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

Figure 29. Transfer Function with Negative Offset

GAIN ERROR

+

OFFSET ERROR

UPPER

DEADBAND

CODES

OUTPUT

VOLTAGE

ACTUAL

IDEAL

POSITIVE

OFFSET

ERROR

FULL SCALE

DAC CODE

Figure 30. Transfer Function with Positive Offset (V_REF= V_DD

)

Rev. C | Page 14 of 28

AD5307/AD5317/AD5327

FUNCTIONAL DESCRIPTION

The AD5307/AD5317/AD5327 are quad resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10, and 12

bits respectively. Each contains four output buffer amplifiers

and is written to via a 3-wire serial interface. They operate from

single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers

provide rail-to-rail output swing with a slew rate of 0.7 V/ꢀs.

DAC A and DAC B share a common reference input, V_REFAB.

DAC C and DAC D share a common reference input, V_REFCD.

Each reference input can be buffered to draw virtually no

current from the reference source, or can be unbuffered to give

a reference input range of 0.25 V to V_DD. The devices have a

power-down mode in which all DACs can be completely turned

off with a high impedance output.

RESISTOR STRING

The resistor string section is shown in Figure 32. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

DAC REFERENCE INPUTS

There is a reference pin for each pair of DACs. The reference

inputs are buffered but can also be individually configured as

unbuffered. The advantage with the buffered input is the high

impedance it presents to the voltage source driving it. However,

if the unbuffered mode is used, the user can have a reference

voltage as low as 0.25 V and as high as V_DD, because there is no

restriction due to headroom and footroom of the reference

amplifier.

DIGITAꢀ-TO-ANAꢀOG SECTION

The architecture of one DAC channel consists of a resistor-

string DAC followed by an output buffer amplifier. The voltage

at the V_REFpin provides the reference voltage for the

corresponding DAC. Figure 31 shows a block diagram of the

DAC architecture. Because the input coding to the DAC is

straight binary, the ideal output voltage is given by

R

TO OUTPUT

R

V_REF× D

AMPLIFIER

V_OUT

=

2^N

R

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register:

Figure 32. Resistor String

0 to 255 for AD5307 (8 bits).

0 to 1023 for AD5317 (10 bits).

0 to 4095 for AD5327 (12 bits).

N is the DAC resolution.

If there is a buffered reference in the circuit (for example, REF192),

there is no need to use the on-chip buffers of the AD5307/AD5317/

AD5327. In unbuffered mode, the input impedance is still large

at typically 90 kΩ per reference input for 0 V to V_REFmode and

45 kΩ or 0 V to 2 V_REFmode.

V

AB

REF

REFERENCE

BUFFER

BUF

The buffered/unbuffered option is controlled by the BUF bit in

the data-word. The BUF bit setting applies to whichever DAC is

selected.

GAIN MODE

(GAIN = 1 OR 2)

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

V

A

OUT

OUTPUT

BUFFER AMPLIFIER

Figure 31. Single DAC Channel Architecture

Rev. C | Page 15 of 28

AD5307/AD5317/AD5327

OUTPUT AMPꢀIFIER

POWER-ON RESET

The output buffer amplifier is capable of generating output

voltages to within 1 mV of either rail. Its actual range depends

on the value of V_REF, GAIN, offset error, and gain error.

The AD5307/AD5317/AD5327 are each provided with a power-

on reset function so that they power up in a defined state. The

power-on state is

If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V

•

Normal operation

to V_REF

.

Reference inputs unbuffered

0 V to V_REFoutput range

Output voltage set to 0 V

If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V

to 2 V_REF. Because of clamping, however, the maximum output

is limited to V_DD− 0.001 V.

The output amplifier is capable of driving a load of 2 kΩ to GND

or V_DDin parallel with 500 pF to GND or V_DD. The source and

sink capabilities of the output amplifier can be seen in Figure 16.

Both input and DAC registers are filled with 0s until a valid

write sequence is made to the device. This is particularly useful

in applications where it is important to know the state of the

DAC outputs while the device is powering up.

The slew rate is 0.7 V/μs, with a half-scale settling time to

0.5 LSB (at eight bits) of 6 μs.

Rev. C | Page 16 of 28

AD5307/AD5317/AD5327

SERIAL INTERFACE

The AD5307/AD5317/AD5327 are controlled over versatile 3-wire

serial interfaces that operate at clock rates of up to 30 MHz and

are compatible with SPI, QSPI, MICROWIRE, and DSP

interface standards.

The AD5327 uses all 12 bits of DAC data; the AD5317 uses

10 bits and ignores the 2 LSBs. The AD5307 uses eight bits and

ignores the last four bits. The data format is straight binary, with

all 0s corresponding to 0 V output and all 1s corresponding to

full-scale output (V_REF− 1 LSB).

INPUT SHIFT REGISTER

SYNC

The

synchronization signal and chip enable. Data can be transferred

SYNC

input is a level-triggered input that acts as a frame

The input shift register is 16 bits wide. Data is loaded into the

device as a 16-bit word under the control of a serial clock input,

SCLK. The timing diagram for this operation is shown in

Figure 3. The 16-bit word consists of four control bits followed

by 8, 10, or 12 bits of DAC data, depending on the device type.

Data is loaded MSB first (Bit 15), and the first two bits

determine whether the data is for DAC A, DAC B, DAC C, or

DAC D. Bit 13 and Bit 12 control the operating mode of the

DAC. Bit 13 is GAIN, which determines the output range of the

part. Bit 12 is BUF, which controls whether the reference inputs

are buffered or unbuffered.

into the device only while

is low. To start the serial data

SYNC

transfer,

SYNC

should be taken low, observing the minimum

SYNC

to SCLK falling edge set-up time, t₄. After

goes

low, serial data is shifted into the device’s input shift register on

the falling edges of SCLK for 16 clock pulses. In standalone

mode (DCEN = 0), any data and clock pulses after the 16th

falling edge of SCLK are ignored, and no further serial data

SYNC

transfer can occur until

is taken high and low again.

SYNC

can be taken high after the falling edge of the 16th SCLK

Table 6. Address Bits for the AD53x7

SYNC

pulse, observing the minimum SCLK falling edge to

rising edge time, t₇.

A1 (Bit 15)

A0 (Bit 14)

DAC Addressed

DAC A

DAC B

DAC C

DAC D

0

1

0

1

0

1

After the end of serial data transfer, data is automatically trans-

ferred from the input shift register to the input register of the

selected DAC. If

SYNC

is taken high before the 16th falling

edge of SCLK, the data transfer is aborted and the DAC input

registers are not updated.

CONTROꢀ BITS

GAIN controls the output range of the addressed DAC.

When data has been transferred into the input register of a DAC,

the corresponding DAC register and DAC output can be updated

0: output range of 0 V to V_REF

1: output range of 0 V to 2 V_REF

.

LDAC

CLR

by taking

low.

is an active low, asynchronous clear

BUF controls whether reference of the addressed DAC is

buffered or unbuffered.

that clears the input registers and DAC registers to all 0s.

0: unbuffered reference.

1: buffered reference.

BIT 15

(MSB)

BIT 0

(LSB)

A1

A0 GAIN BUF D7

D6

D5

D4

D3

D2

D1

D0

X

D0

D2

X

DATA BITS

Figure 33. AD5307 Input Shift Register Contents

BIT 15

(MSB)

BIT 0

(LSB)

A1

A0 GAIN BUF D9

D8

D7

D6

D5

D4

D3

D2

D1

X

DATA BITS

Figure 34. AD5317 Input Shift Register Contents

BIT 15

(MSB)

BIT 0

(LSB)

A1

A0 GAIN BUF D11 D10 D9

D8

D7

D6

D5

D4

D3

D1

D0

DATA BITS

Figure 35. AD5327 Input Shift Register Contents

Rev. C | Page 17 of 28

AD5307/AD5317/AD5327

The double-buffered interface is useful if the user requires

simultaneous updating of all DAC outputs. The user can write

to three of the input registers individually and then, by bringing

ꢀOW POWER SERIAꢀ INTERFACE

To minimize the power consumption of the device, the interface

powers up fully only when the device is being written to, that is,

LDAC

low when writing to the remaining DAC input register,

SYNC

on the falling edge of

. The SCLK and DIN input buffers

all outputs update simultaneously.

SYNC

are powered down on the rising edge of

.

These parts each contain an extra feature whereby a DAC

register is not updated unless its input register has been updated

DAISY CHAINING

For systems that contain several DACs, or where the user

wishes to read back the DAC contents for diagnostic purposes,

the SDO pin can be used to daisy-chain several devices together

and provide serial readback.

LDAC

since the last time

was brought low. Normally, when

is brought low, the DAC registers are filled with the contents of

the input registers. In the case of the AD5307/AD5317/AD5327,

the DAC register updates only if the input register has changed

since the last time the DAC register was updated, thereby removing

unnecessary digital crosstalk.

By connecting the DCEN (daisy-chain enable) pin high, the

daisy-chain mode is enabled. It is tied low in the case of

standalone mode. In daisy-chain mode, the internal gating on

SCLK is disabled. The SCLK is continuously applied to the

ꢀOAD DAC INPUT (ꢀDAC)

LDAC

transfers data from the input registers to the DAC

LDAC

SYNC

input shift register when

is low. If more than 16 clock

registers and therefore updates the outputs. Use of the

function enables double buffering of the DAC data, GAIN, and

LDAC

pulses are applied, the data ripples out of the shift register and

appears on the SDO line. This data is clocked out on the rising

edge of SCLK and is valid on the falling edge. By connecting

this line to the DIN input on the next DAC in the chain, a

multi-DAC interface is constructed. Each DAC in the system

requires 16 clock pulses; therefore, the total number of clock

cycles must equal 16N, where N is the total number of devices

in the chain. When the serial transfer to all devices is complete,

BUF. There are two

Synchronous Mode

In this mode, the DAC registers are updated after new data is

modes: synchronous and asynchronous.

LDAC

read from on the falling edge of the 16th SCLK pulse.

can be tied permanently low or pulsed as in Figure 3.

SYNC

should be taken high. This prevents any further data

from being clocked into the input shift register.

Asynchronous Mode

In this mode, the outputs are not updated at the same time that

LDAC

goes low, the DAC

SYNC

A continuous SCLK source can be used if

is held low for

the input registers are written to. When

registers are updated with the contents of the input register.

the correct number of clock cycles. Alternatively, a burst clock

containing the exact number of clock cycles can be used and

POWER-DOWN MODE

SYNC

can be taken high some time later.

The AD5307/AD5317/AD5327 have low power consumption,

typically dissipating 1.2 mW with a 3 V supply and 2.5 mW with

a 5 V supply. Power consumption can be further reduced when

the DACs are not in use by putting them into power-down mode,

When the transfer to all input registers is complete, a common

LDAC

signal updates all DAC registers and all analog outputs

are updated simultaneously.

PD

which is selected by taking the

pin low.

DOUBꢀE-BUFFERED INTERFACE

PD

When the

pin is high, all DACs work normally with a typical

The AD5307/AD5317/AD5327 DACs have double-buffered

interfaces consisting of two banks of registers: input registers

and DAC registers. The input registers are connected directly to

the input shift register and the digital code is transferred to the

relevant input register on completion of a valid write sequence.

The DAC registers contain the digital code used by the resistor

strings.

power consumption of 500 μA at 5 V (400 μA at 3 V). However,

in power-down mode, the supply current falls to 300 nA at 5 V

(90 nA at 3 V) when all DACs are powered down. Not only does

the supply current drop, but the output stage is also internally

switched from the output of the amplifier, making it an open

circuit. This has the advantage that the output is three-state

while the part is in power-down mode and provides a defined

input condition for whatever is connected to the output of the

DAC amplifier. The output stage is illustrated in Figure 36.

LDAC

Access to the DAC registers is controlled by the

pin.

pin is high, the DAC registers are latched and

the input registers can change state without affecting the

LDAC

When the

The bias generator, output amplifiers, resistor string, and all

other associated linear circuitry are shut down when the power-

down mode is activated. However, the contents of the registers

are unaffected when in power-down. In fact, it is possible to

load new data to the input registers and DAC registers during

contents of the DAC registers. When

is brought low,

however, the DAC registers become transparent and the

contents of the input registers are transferred to them.

PD

power-down. The DAC outputs update as soon as

goes high.

Rev. C | Page 18 of 28

AD5307/AD5317/AD5327

68HC11/68L11¹

The time to exit power-down is typically 2.5 μs for V_DD= 5 V

and 5 μs when V_DD= 3 V. This is the time from the rising edge

AD5307/

AD5317/

AD5327¹

PD

of

to when the output voltage deviates from its power-down

SYNC

PC7

SCK

voltage. See Figure 23 for a plot.

SCLK

DIN

AMPLIFIER

MOSI

RESISTOR

STRING DAC

V

OUT

1

ADDITIONAL PINS OMITTED FOR CLARITY.

POWER-DOWN

CIRCUITRY

Figure 38. 68HC11/68L11-to-AD5307/AD5317/AD5327 Interface

80C51/80L51-to-AD5307/AD5317/AD5327 Interface

Figure 36. Output Stage During Power-Down

Figure 39 shows a serial interface between the AD5307/AD5317/

AD5327 and the 80C51/80L51 microcontroller. The setup for

the interface is as follows: TxD of the 80C51/80L51 drives SCLK

of the AD5307/AD5317/AD5327, and RxD drives the serial data

MICROPROCESSOR INTERFACING

ADSP-2101/ADSP-2103-to-

AD5307/AD5317/AD5327 Interface

SYNC

Figure 37 shows a serial interface between the AD5307/AD5317/

AD5327 and the ADSP-2101/ADSP-2103. The ADSP-2101/

ADSP-2103 should be set up to operate in the SPORT transmit

alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is

programmed through the SPORT control register and should be

configured as follows: internal clock operation, active low framing,

16-bit word length. Transmission is initiated by writing a word

to the Tx register after SPORT is enabled. The data is clocked

out on each rising edge of the DSP’s serial clock and clocked

into the AD5307/AD5317/AD5327 on the falling edge of the

DAC’s SCLK.

line of the part. The

signal is again derived from a bit-

programmable pin on the port. In this case, Port Line P3.3 is

used. When data is to be transmitted to the AD5307/AD5317/

AD5327, P3.3 is taken low. The 80C51/80L51 transmits data only

in 8-bit bytes; therefore, only eight falling clock edges occur in

the transmit cycle. To load data to the DAC, P3.3 is left low after

the first eight bits are transmitted, and a second write cycle is

initiated to transmit the second byte of data. P3.3 is taken high

following the completion of this cycle. The 80C51/80L51 outputs

the serial data LSB first. The AD5307/AD5317/AD5327 require

their data with the MSB as the first bit received. The

80C51/80L51 transmit routine should take this into account.

ADSP-2101/

ADSP-2103¹

AD5307/

AD5317/

AD5327¹

80C51/80L51¹

AD5307/

AD5317/

AD5327¹

SYNC

TFS

DT

SYNC

DIN

P3.3

TxD

SCLK

DIN

RxD

1

ADDITIONAL PINS OMITTED FOR CLARITY.

1

Figure 37. ADSP-2101/ADSP-2103-to-AD5307/AD5317/AD5327 Interface

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 39. 80C51/80L51-to-AD5307/AD5317/AD5327 Interface

68HC11/68L11-to-AD5307/AD5317/AD5327 Interface

MICROWIRE-to-AD5307/AD5317/AD5327 Interface

Figure 38 shows a serial interface between the AD5307/AD5317/

AD5327 and the 68HC11/68L11 microcontroller. SCK of the

68HC11/68L11 drives the SCLK of the AD5307/AD5317/

AD5327, and the MOSI output drives the serial data line (DIN)

Figure 40 shows an interface between the AD5307/AD5317/

AD5327 and a MICROWIRE-compatible device. Serial data is

shifted out on the falling edge of the serial clock, SK, and is

clocked into the AD5307/AD5317/AD5327 on the rising edge

of SK, which corresponds to the falling edge of the DAC’s SCLK.

SYNC

of the DAC. The

signal is derived from a port line (PC7).

The set-up conditions for correct operation of this interface are as

follows: The 68HC11/68L11 should be configured so that its CPOL

bit is 0 and its CPHA bit is 1. When data is being transmitted to the

1

MICROWIRE

AD5307/

AD5317/

AD5327¹

SYNC

DAC, the

line is taken low (PC7). With this configuration,

CS

SK

SO

SYNC

data appearing on the MOSI output is valid on the falling edge

of SCK. Serial data from the 68HC11/68L11 is transmitted in

8-bit bytes, with only eight falling clock edges occurring in the

transmit cycle. Data is transmitted MSB first. To load data to

the AD5307/AD5317/AD5327, PC7 is left low after the first

eight bits are transferred and a second serial write operation

is performed to the DAC. PC7 is taken high at the end of this

procedure.

SCLK

DIN

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 40. MICROWIRE-to-AD5307/AD5317/AD5327 Interface

Rev. C | Page 19 of 28

AD5307/AD5317/AD5327

APPLICATIONS

TYPICAꢀ APPꢀICATION CIRCUIT

BIPOꢀAR OPERATION

The AD5307/AD5317/AD5327 can be used with a wide range

of reference voltages and offer full, one-quadrant multiplying

capability over a reference range of 0.25 V to V_DD. More typically,

these devices are used with a fixed precision reference voltage.

Suitable references for 5 V operation are the AD780 and REF192

(2.5 V references). For 2.5 V operation, a suitable external refer-

ence would be the AD589, a 1.23 V band gap reference. Figure 41

shows a typical setup for the AD5307/AD5317/AD5327 when

using an external reference.

The AD5307/AD5317/AD5327 are designed for single-supply

operation, but a bipolar output range is also possible using the

circuit shown in Figure 42. This circuit provides an output

voltage range of 5 V. Rail-to-rail operation at the amplifier

output is achievable by using an AD820 or an OP295 as the

output amplifier.

The output voltage for any input code can be calculated as

follows:

⎡

⎢

⎤

⎥

(

REFIN × D /2^N

R1

)

×(R1+ R2)

V

= 2.5V TO 5.5V

DD

V_OUT

=

− REFIN ×(R2/ R1)

⎢

⎥

⎣

⎦

10µF

0.1µF

V

IN

where:

V

OUT

V

AB

CD

V

A

B

REF

OUT

1µF

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

REFIN is the reference voltage input.

EXT

REF

V

OUT

AD5307/AD5317/

AD5327

AD780/REF192

WITH V = 5V

OR AD589 WITH

DD

SCLK

V

C

D

OUT

DIN

V

= 2.5V

DD

When REFIN = 5 V, R1 = R2 = 10 kΩ,

OUT

SYNC

GND

V

_OUT= (10 × D/2^N) − 5 V

SERIAL

INTERFACE

R2

10kΩ

+5V

Figure 41. AD5307/AD5317/AD5327 Using a 2.5 V External Reference

+5V

R1

+6V TO +16V

10kΩ

DRIVING V_DDFROM THE REFERENCE VOꢀTAGE

10µF

0.1µF

±5V

If an output range of 0 V to V_DDis required when the reference

inputs are configured as unbuffered, the simplest solution is to

connect the reference input to V_DD. Because this supply can be

noisy and not very accurate, the AD5307/AD5317/AD5327 can

be powered from the reference voltage, for example, from a 5 V

reference such as the REF195, which outputs a steady supply

voltage. The typical current required from the REF195 with no

load on the DAC outputs is 500 μA supply current and ≈112 μA

into the reference inputs (if unbuffered). When the DAC

outputs are loaded, the REF195 also needs to supply the current

to the loads. The total current required with a 10 kΩ load on

each output is

V

A

AD820/

OP295

DD OUT

V

AD5307/AD5317/

AD5327

IN

–5V

REF195

V

AB

OUT

REF

V

B

C

D

OUT

1µF

V

CD

REF

GND

DIN SCLK SYNC

SERIAL

INTERFACE

Figure 42. Bipolar Operation with the AD5307/AD5317/AD5327

612 μA + 4 (5 V/10 kΩ) = 2.6 mA

The load regulation of the REF195 is typically 2 ppm/mA,

which results in an error of 5.2 ppm (26 μV) for the 2.6 mA

current drawn from it. This corresponds to a 0.0013 LSB error

at eight bits and a 0.021 LSB error at 12 bits.

Rev. C | Page 20 of 28

AD5307/AD5317/AD5327

AD5307

OPTO-ISOꢀATED INTERFACE FOR

PROCESS-CONTROꢀ APPꢀICATIONS

V

A

B

C

D

OUT

SCLK

DIN

SYNC

DIN

SCLK

The AD5307/AD5317/AD5327 each have a versatile 3-wire serial

interface, making them ideal for generating accurate voltages in

process-control and industrial applications. Due to noise, safety

requirements, or distance, it may be necessary to isolate the

AD5307/AD5317/AD5327 from the controller. This can easily

be achieved by using opto-isolators capable of providing isolation

in excess of 3 kV. The actual data rate achieved can be limited

by the type of optocouplers chosen. The serial loading structure

of the AD5307/AD5317/AD5327 makes them ideally suited for

use in opto-isolated applications. Figure 43 shows an opto-isolated

interface to the AD5307/AD5317/AD5327 where DIN, SCLK,

V

DD

CC

AD5307

74HC139

1G

1A

1B

ENABLE

V

A

B

C

D

1Y0

1Y1

1Y2

1Y3

OUT

V

OUT

SYNC

DIN

SCLK

CODED

ADDRESS

DGND

AD5307

V

A

B

C

D

OUT

SYNC

DIN

SCLK

AD5307

SYNC

and

are driven from optocouplers. The power supply to

V

A

B

C

D

OUT

V

SYNC

DIN

SCLK

OUT

the part should also be isolated. This is done by using a trans-

former. On the DAC side of the transformer, a 5 V regulator

provides the 5 V supply required for the AD5307/AD5317/

AD5327.

Figure 44. Decoding Multiple AD5307 Devices in a System

AD5307/AD5317/AD5327 AS DIGITAꢀꢀY

PROGRAMMABꢀE WINDOW DETECTORS

5V

REGULATOR

0.1µF

10µF

POWER

A digitally programmable upper/lower limit detector using two of

the DACs in the AD5307/AD5317/AD5327 is shown in Figure 45.

The upper and lower limits for the test are loaded to DAC A

and DAC B, which, in turn, set the limits on the CMP04. If the

signal at the V_INinput is not within the programmed window,

an LED indicates the fail condition. Similarly, DAC C and DAC D

can be used for window detection on a second V_INsignal.

V

DD

10kΩ

V

DD

SCLK

V

AB

SCLK

REF

CD

REF

AD5307

V

DD

10kΩ

V

A

B

C

D

OUT

5V

SYNC

0.1µF

10µF

SYNC

V

1kΩ

FAIL

1kΩ

PASS

V

IN

V

DD

V

AB

CD

REF

V

A

DD

OUT

V

REF

10kΩ

AD5307/

AD5317/

AD5327

PASS/FAIL

1/6 74HC05

1/2

CMP04

DIN

DCEN GND

DIN

SYNC

DIN

SYNC

DIN

SCLK

V

B

OUT

GND

Figure 43. AD5307 in an Opto-Isolated Interface

Figure 45. Window Detection

DECODING MUꢀTIPꢀE

AD5307/AD5317/AD5327 DEVICES

SYNC

The

pin on the AD5307/AD5317/AD5327 can be used in

applications to decode a number of DACs. In this application,

all DACs in the system receive the same serial clock and serial

SYNC

data, but the

to only one of the devices is active at any

given time, allowing access to four channels in this 16-channel

system. The 74HC139 is used as a 2-to-4 line decoder to address

any of the DACs in the system. To prevent timing errors, the

enable input should be brought to its inactive state while the

coded address inputs are changing state. Figure 44 shows a

diagram of a typical setup for decoding multiple AD5307

devices in a system.

Rev. C | Page 21 of 28

AD5307/AD5317/AD5327

DAISY CHAINING

POWER SUPPꢀY BYPASSING AND GROUNDING

For systems that contain several DACs, or where the user

wishes to read back the DAC contents for diagnostic purposes,

the SDO pin can be used to daisy-chain several devices together

and provide serial readback. Figure 4 shows the timing diagram

for daisy-chain applications. The daisy-chain mode is enabled

by connecting DCEN high (see Figure 46).

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5307/AD5317/AD5327 are mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the AD5307/AD5317/AD5327

are in a system where multiple devices require an AGND-to-

DGND connection, the connection should be made at one

point only. The star ground point should be established as close

as possible to the device. The AD5307/AD5317/AD5327 should

have ample supply bypassing of 10 μF in parallel with 0.1 μF on

the supply located as close to the package as possible, ideally right

up against the device. The 10 μF capacitors are the tantalum bead

type. The 0.1 μF capacitor should have low effective series

resistance (ESR) and low effective series inductance (ESI), such

as is typical of the common ceramic types that provide a low

impedance path to ground at high frequencies to handle

transient currents due to internal logic switching.

1

68HC11

AD5307¹

DIN

MOSI

SCK

PC7

PC6

SCLK

SYNC

LDAC

DCEN

SDO

MISO

DIN

AD5307¹

SCLK

SYNC

LDAC

The power supply lines of the AD5307/AD5317/AD5327 should

use as large a trace as possible to provide low impedance paths

and reduce the effects of glitches on the power supply line. Com-

ponents, such as clocks, with fast switching signals should be

shielded with digital ground to avoid radiating noise to other

parts of the board, and they should never be run near the refer-

ence inputs. Avoid crossover of digital and analog signals. Traces

on opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough on the board. A

microstrip technique is by far the best, but it is not always

possible with a double-sided board. In this technique, the com-

ponent side of the board is dedicated to ground plane, and signal

traces are placed on the solder side.

DCEN

SDO

DIN

AD5307¹

SCLK

SYNC

LDAC

DCEN

SDO

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. AD5307 in Daisy-Chain Mode

Rev. C | Page 22 of 28

AD5307/AD5317/AD5327

Table 7. Overview of AD53xx Serial Devices¹

Part No.

Resolution

No. of DACs

DNꢀ

0.25

0.5

1.0

0.25

0.5

1.0

Interface

Settling Time (μs)

Package

SINGLES

AD5300

8

1

SPI

2-Wire

4

6

8

6

7

8

SOT-23, MSOP

6, 8

AD5310

AD5320

AD5301

AD5311

AD5321

10

12

8

10

12

DUALS

AD5302

AD5312

AD5322

AD5303

AD5313

AD5323

8

2

0.25

0.5

1.0

0.25

0.5

1.0

SPI

6

7

8

6

7

8

MSOP

TSSOP

8

16

10

12

8

10

12

QUADS

AD5304

AD5314

AD5324

AD5305

AD5315

AD5325

AD5306

AD5316

AD5326

AD5307

AD5317

AD5327

8

4

0.25

0.5

1.0

0.25

0.5

1.0

0.25

0.5

1.0

0.25

0.5

1.0

SPI

2-Wire

SPI

6

7

8

6

7

8

6

7

8

6

7

8

MSOP

TSSOP

10

16

10

12

8

10

12

8

10

12

8

10

12

SPI

OCTALS

AD5308

AD5318

AD5328

8

10

12

8

0.25

0.5

1.0

SPI

6

7

8

TSSOP

16

¹Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information.

Table 8. Overview of AD53xx Parallel Devices

Additional Pin Functions

Part No.

Resolution

DNꢀ

V_REFPin

Settling Time (μs)

BUF

GAIN

HBEN

CꢀR

Package

SINGLES

AD5330

8

0.25

1

6

7

8

•

TSSOP

20

24

20

AD5331

AD5340

AD5341

10

12

0.5

1.0

•

DUALS

AD5332

AD5333

AD5342

AD5343

8

0.25

0.5

1.0

2

1

6

7

8

•

TSSOP

20

24

28

20

10

12

•

1.0

•

QUADS

AD5334

AD5335

AD5336

AD5344

8

0.25

0.5

2

4

6

7

8

•

TSSOP

24

28

10

12

1.0

Rev. C | Page 23 of 28

AD5307/AD5317/AD5327

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Rev. C | Page 24 of 28

AD5307/AD5317/AD5327

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD5307ARU

−40°C to +105°C

16-Lead Thin Shrink Small Outline Package [TSSOP]

RU-16

AD5307ARU-REEL7

AD5307ARUZ¹

AD5307ARUZ-REEL7¹

AD5307BRU

AD5307BRU-REEL

AD5307BRU-REEL7

AD5307BRUZ¹

AD5307BRUZ-REEL¹

AD5307BRUZ-REEL7¹

AD5317ARU

AD5317ARU-REEL7

AD5317ARUZ¹

AD5317BRU

AD5317BRU-REEL

AD5317BRU-REEL7

AD5317BRUZ¹

AD5317BRUZ-REEL¹

AD5317BRUZ-REEL7¹

AD5327ARU

AD5327ARU-REEL7

AD5327ARUZ¹

AD5327BRU

AD5327BRU-REEL

AD5327BRU-REEL7

AD5327BRUZ¹

AD5327BRUZ-REEL¹

AD5327BRUZ-REEL7¹

¹Z = Pb-free part.

Rev. C | Page 25 of 28

AD5307/AD5317/AD5327

NOTES

Rev. C | Page 26 of 28

AD5307/AD5317/AD5327

NOTES

Rev. C | Page 27 of 28

AD5307/AD5317/AD5327

NOTES

registered trademarks are the property of their respective owners.

C02067–0–3/06(C)

Rev. C | Page 28 of 28


型号：	AD5317BRUZ
厂家：	ADI
描述：	2.5 V to 5.5 V, 400 muA, Quad Voltage Output 2.5 V至5.5 V ， 400 MUA ，四路电压输出
文件：	总28页 (文件大小：585K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5317BRUZ [ADI]

相关型号：

AD5317BRUZ-REEL

AD5317BRUZ-REEL7

AD5317RBCPZ-RL7

AD5317RBRUZ

AD5317RBRUZ-RL7

AD5318

AD5318ARU

AD5318ARU-REEL7

AD5318ARUZ

AD5318ARUZ-REEL7

AD5318BRU

AD5318BRU-REEL