AD5341BRU_技术文档

2.5 V to 5.5 V, 115 ␮A, Parallel Interface

Single Voltage-Output 8-/10-/12-Bit DACs

a

AD5330/AD5331/AD5340/AD5341*

FEATURES

GENERAL DESCRIPTION

AD5330: Single 8-Bit DAC in 20-Lead TSSOP

The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and

AD5331: Single 10-Bit DAC in 20-Lead TSSOP

AD5340: Single 12-Bit DAC in 24-Lead TSSOP

AD5341: Single 12-Bit DAC in 20-Lead TSSOP

Low Power Operation: 115 ␮A @ 3 V, 140 ␮A @ 5 V

Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin

2.5 V to 5.5 V Power Supply

12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-

suming just 115 µA at 3 V, and feature a power-down mode that

further reduces the current to 80 nA. These devices incorporate

an on-chip output buffer that can drive the output to both

supply rails, while the AD5330, AD5340, and AD5341 allow a

choice of buffered or unbuffered reference input.

Double-Buffered Input Logic

The AD5330/AD5331/AD5340/AD5341 have a parallel interface.

CS selects the device and data is loaded into the input registers

on the rising edge of WR.

Guaranteed Monotonic by Design Over All Codes

Buffered/Unbuffered Reference Input Options

Output Range: 0–V_REFor 0–2 V_REF

Power-On Reset to Zero Volts

Simultaneous Update of DAC Outputs via LDAC Pin

Asynchronous CLR Facility

Low Power Parallel Data Interface

On-Chip Rail-to-Rail Output Buffer Ampliﬁers

Temperature Range: –40؇C to +105؇C

The GAIN pin allows the output range to be set at 0 V to V_REF

or 0 V to 2 × V_REF

.

Input data to the DACs is double-buffered, allowing simultaneous

update of multiple DACs in a system using the LDAC pin.

An asynchronous CLR input is also provided, which resets the

contents of the Input Register and the DAC Register to all zeros.

These devices also incorporate a power-on reset circuit that ensures

that the DAC output powers on to 0 V and remains there until

valid data is written to the device.

APPLICATIONS

Portable Battery-Powered Instruments

Digital Gain and Offset Adjustment

Programmable Voltage and Current Sources

Programmable Attenuators

The AD5330/AD5331/AD5340/AD5341 are available in Thin

Shrink Small Outline Packages (TSSOP).

Industrial Process Control

AD5330 FUNCTIONAL BLOCK DIAGRAM

(Other Diagrams Inside)

V

DD

REF

POWER-ON

RESET

AD5330

BUF

DAC

REGISTER

INPUT

REGISTER

GAIN

8-BIT

DAC

DB

V

BUFFER

7

.

OUT

.

INTER-

FACE

LOGIC

DB

0

CS

WR

CLR

RESET

POWER-DOWN

LOGIC

LDAC

GND

PD

*Protected by U.S. Patent Number 5,969,657; other patents pending.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD5330/AD5331/AD5340/AD5341–SPECIFICATIONS

(V_DD= 2.5 V to 5.5 V, V_REF= 2 V. R_L= 2 k⍀ to GND; C_L= 200 pF to GND; all speciﬁcations T_MINto T_MAXunless otherwise noted.)

B Version²

Parameter¹

Min

Typ

Max

Unit

Conditions/Comments

DC PERFORMANCE^{3, 4}

AD5330

Resolution

8

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5331

0.15

0.02

1

0.25

Guaranteed Monotonic By Design Over All Codes

Resolution

10

0.5

0.05

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5340/AD5341

Resolution

Relative Accuracy

Differential Nonlinearity

Offset Error

4

0.5

12

2

0.2

0.4

0.15

10

–12

–5

–60

Bits

LSB

% of FSR

mV

16

1

3

1

60

Gain Error

Lower Deadband⁵

Upper Deadband

Offset Error Drift⁶

Gain Error Drift⁶

DC Power Supply Rejection Ratio⁶

Lower Deadband Exists Only if Offset Error Is Negative

V_DD= 5 V. Upper Deadband Exists Only if V_{REF =}V_DD

60

mV

ppm of FSR/°C

dB

∆V_DD= 10%

DAC REFERENCE INPUT⁶

V_REFInput Range

1

0.25

V_DD

V

Buffered Reference (AD5330, AD5340, and AD5341)

Unbuffered Reference

V_REFInput Impedance

>10

180

90

MΩ

kΩ

dB

Buffered Reference (AD5330, AD5340, and AD5341)

Unbuffered Reference. Gain = 1, Input Impedance = R_DAC

Unbuffered Reference. Gain = 2, Input Impedance = R_DAC

Frequency = 10 kHz

Reference Feedthrough

–90

OUTPUT CHARACTERISTICS⁶

Minimum Output Voltage^{4, 7}

Maximum Output Voltage^{4, 7}

DC Output Impedance

0.001

V_DD–0.001

V min

V max

Ω

Rail-to-Rail Operation

0.5

25

15

2.5

5

Short Circuit Current

mA

µs

V_DD= 5 V

V_DD= 3 V

Power-Up Time

Coming Out of Power-Down Mode. V_DD= 5 V

Coming Out of Power-Down Mode. V_DD= 3 V

µs

LOGIC INPUTS⁶

Input Current

V_IL, Input Low Voltage

1

µA

V

0.8

0.6

0.5

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

V

V_IH, Input High Voltage

2.4

2.1

2.0

V

V_DD= 5 V 10%

V_DD= 3 V 10%

V_DD= 2.5 V

Pin Capacitance

3

pF

POWER REQUIREMENTS

V_DD

2.5

5.5

V

I_DD(Normal Mode)

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

DACs active and excluding load currents. Unbuffered

Reference. V_IH= V_DD, V_IL= GND.

I_DDincreases by 50 µA at V_REF> V_DD– 100 mV.

In Buffered Mode extra current is (5 + V_REF/R_DAC) µA,

where R_DACis the resistance of the resistor string.

140

115

250

200

µA

I_DD(Power-Down Mode)

V_DD= 4.5 V to 5.5 V

V_DD= 2.5 V to 3.6 V

0.2

0.08

1

µA

NOTES

¹See Terminology section.

²Temperature range: B Version: –40°C to +105°C; typical speciﬁcations are at 25°C.

³Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095).

⁴DC speciﬁcations tested with output unloaded.

⁵This corresponds to x codes. x = Deadband voltage/LSB size.

⁶Guaranteed by design and characterization, not production tested.

⁷In order for the ampliﬁer output to reach its minimum voltage, Offset Error must be negative. In order for the ampliﬁer output to reach its maximum voltage, V_REF= V_DDand

“Offset plus Gain” Error must be positive.

Speciﬁcations subject to change without notice.

–2–

REV. 0

AD5330/AD5331/AD5340/AD5341

(V_DD= 2.5 V to 5.5 V. R_L= 2 k⍀ to GND; C_L= 200 pF to GND; all speciﬁcations T_MINto T_MAX

unless otherwise noted.)

AC CHARACTERISTICS¹

B Version³

Parameter²

Min

Typ

Max

Unit

Conditions/Comments

_REF= 2 V. See Figure 20

Output Voltage Settling Time

AD5330

AD5331

AD5340

AD5341

V

6

7

8

0.7

6

0.5

200

–70

8

9

10

µs

1/4 Scale to 3/4 Scale Change (40 H to C0 H)

1/4 Scale to 3/4 Scale Change (100 H to 300 H)

1/4 Scale to 3/4 Scale Change (400 H to C00 H)

µs

V/µs

nV-s

kHz

dB

Slew Rate

Major Code Transition Glitch Energy

Digital Feedthrough

Multiplying Bandwidth

Total Harmonic Distortion

1 LSB Change Around Major Carry

V_REF= 2 V 0.1 V p-p. Unbuffered Mode

V_REF= 2.5 V 0.1 V p-p. Frequency = 10 kHz

NOTES

¹Guaranteed by design and characterization, not production tested.

²See Terminology section.

³Temperature range: B Version: –40°C to +105°C; typical speciﬁcations are at 25°C.

Speciﬁcations subject to change without notice.

TIMING CHARACTERISTICS^{1, 2, 3}(V_DD= 2.5 V to 5.5 V, All speciﬁcations T_MINto T_MAXunless otherwise noted.)

Parameter

Limit at T_MIN, T_MAX

Unit

Condition/Comments

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

0

20

5

4.5

5

4.5

5

4.5

20

50

ns min

CS to WR Setup Time

CS to WR Hold Time

WR Pulsewidth

Data, GAIN, BUF, HBEN Setup Time

Data, GAIN, BUF, HBEN Hold Time

Synchronous Mode. WR Falling to LDAC Falling.

Synchronous Mode. LDAC Falling to WR Rising.

Synchronous Mode. WR Rising to LDAC Rising.

Asynchronous Mode. LDAC Rising to WR Rising.

Asynchronous Mode. WR Rising to LDAC Falling.

LDAC Pulsewidth

t₉

t₁₀

t₁₁

t₁₂

t₁₃

CLR Pulsewidth

Time Between WR Cycles

NOTES

¹Guaranteed by design and characterization, not production tested.

²All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

³See Figure 1.

t₂

t₁

CS

t₁₃

t₃

WR

t₅

t₄

DATA,

GAIN,

BUF,

HBEN

t₈

t₆

t₇

t₉

1

LDAC

t₁₀

t₁₁

2

LDAC

t₁₂

CLR

NOTES:

1

SYNCHRONOUS LDAC UPDATE MODE

ASYNCHRONOUS LDAC UPDATE MODE

2

Figure 1. Parallel Interface Timing Diagram

–3–

REV. 0

AD5330/AD5331/AD5340/AD5341

ABSOLUTE MAXIMUM RATINGS*

(T_A= 25°C unless otherwise noted)

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V_DD+ 0.3 V

Digital Output Voltage to GND . . . . . –0.3 V to V_DD+ 0.3 V

Reference Input Voltage to GND . . . . –0.3 V to V_DD+ 0.3 V

V_OUTto GND . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

TSSOP Package

Power Dissipation . . . . . . . . . . . . . . . (T_Jmax – T_A)/θ_JAmW

θ

_JAThermal Impedance (20-Lead TSSOP) . . . . . 143°C/W

_JAThermal Impedance (24-Lead TSSOP) . . . . . 128°C/W

θ

_JAThermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W

_JCThermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W

ORDERING GUIDE

Package

Option

Model

Temperature Range

Package Description

AD5330BRU

AD5331BRU

AD5340BRU

AD5341BRU

–40°C to +105°C

TSSOP (Thin Shrink Small Outline Package)

RU-20

RU-24

RU-20

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD5330/AD5331/AD5340/AD5341 features proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. 0

AD5330/AD5331/AD5340/AD5341

AD5330 FUNCTIONAL BLOCK DIAGRAM

AD5330 PIN CONFIGURATION

V

DD

REF

1

2

20

19

18

DB

BUF

NC

7

DB

POWER-ON

RESET

6

AD5330

3

V

REF

OUT

5

4

3

4

17 DB

16 DB

V

BUF

8-BIT

5

GND

CS

DAC

REGISTER

INPUT

REGISTER

AD5330

GAIN

TOP VIEW

8-BIT

DAC

6

15

DB

V

2

BUFFER

7

.

OUT

(Not to Scale)

.

INTER-

FACE

LOGIC

DB

0

7

14 DB

13 DB

WR

1

8

GAIN

CLR

LDAC

0

CS

9

12

11

V

DD

WR

CLR

10

PD

RESET

POWER-DOWN

LOGIC

NC = NO CONNECT

LDAC

GND

PD

AD5330 PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

1

2

BUF

NC

Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.

No Connect.

3

4

5

6

7

8

9

10

11

12

V_REF

V_OUT

GND

CS

Reference Input.

Output of DAC. Buffered output with rail-to-rail operation.

Ground reference point for all circuitry on the part.

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

Gain Control Pin. This controls whether the output range from the DAC is 0–V_REFor 0–2 V_REF.

Asynchronous active low control input that clears all input registers and DAC registers to zero.

Active low control input that updates the DAC registers with the contents of the input registers.

Power-Down Pin. This active low control pin puts the DAC into power-down mode.

WR

GAIN

CLR

LDAC

PD

V_DD

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

13–20

DB₀–DB₇

Eight Parallel Data Inputs. DB₇is the MSB of these eight bits.

–5–

REV. 0

AD5330/AD5331/AD5340/AD5341

AD5331 FUNCTIONAL BLOCK DIAGRAM

AD5331 PIN CONFIGURATION

V

DD

REF

1

2

20

19

18

DB

7

8

DB

POWER-ON

RESET

6

5

9

AD5331

3

V

REF

OUT

4

17 DB

V

4

BUF

10-BIT

5

16 DB

GND

CS

DAC

REGISTER

INPUT

REGISTER

3

AD5331

TOP VIEW

10-BIT

DAC

6

15

DB

V

9

.

2

BUFFER

OUT

(Not to Scale)

.

INTER-

FACE

LOGIC

DB

0

7

14 DB

WR

1

8

13 DB

GAIN

CLR

LDAC

0

CS

9

12

11

V

DD

WR

CLR

10

PD

RESET

POWER-DOWN

LOGIC

LDAC

PD GND

AD5331 PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

1

2

3

4

5

6

7

DB₈

DB₉

V_REF

V_OUT

GND

CS

Parallel Data Input.

Most Significant Bit of Parallel Data Input.

Unbuffered Reference Input.

Output of DAC. Buffered output with rail-to-rail operation.

Ground reference point for all circuitry on the part.

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR

8

9

10

11

12

GAIN

CLR

LDAC

PD

Gain Control Pin. This controls whether the output range from the DAC is 0–V_REFor 0–2 V_REF

Active low control input that clears all input registers and DAC registers to zero.

Active low control input that updates the DAC registers with the contents of the input registers.

Power-Down Pin. This active low control pin puts the DAC into power-down mode.

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled

.

V_DD

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

13–20

DB₀–DB₇

Eight Parallel Data Inputs.

–6–

REV. 0

AD5330/AD5331/AD5340/AD5341

AD5340 PIN CONFIGURATION

AD5340 FUNCTIONAL BLOCK DIAGRAM

V

DD

REF

1

2

24

23

22

21

20

19

18

DB

9

8

7

6

5

4

10

11

POWER-ON

RESET

3

AD5340

BUF

4

V

REF

OUT

NC

12-BIT

AD5340

TOP VIEW

(Not to Scale)

V

5

BUF

DAC

REGISTER

INPUT

REGISTER

GAIN

6

12-BIT

DAC

DB

11

.

V

7

BUFFER

OUT

GND

CS

3

2

1

0

.

INTER-

FACE

LOGIC

DB

0

8

17 DB

16 DB

15 DB

14

9

WR

CS

10

11

12

GAIN

CLR

LDAC

WR

CLR

V

DD

RESET

POWER-DOWN

LOGIC

13

PD

NC = NO CONNECT

LDAC

GND

PD

AD5340 PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

1

2

3

4

5

6

DB₁₀

DB₁₁

BUF

V_REF

V_OUT

NC

Parallel Data Input.

Most Significant Bit of Parallel Data Input.

Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.

Reference Input.

Output of DAC. Buffered output with rail-to-rail operation.

No Connect.

7

8

9

10

11

12

13

14

GND

CS

Ground reference point for all circuitry on the part.

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

Gain Control Pin. This controls whether the output range from the DAC is 0–V_REFor 0–2 V_REF.

Asynchronous active low control input that clears all input registers and DAC registers to zero.

Active low control input that updates the DAC registers with the contents of the input registers.

Power-Down Pin. This active low control pin puts the DAC into power-down mode.

WR

GAIN

CLR

LDAC

PD

V_DD

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

15–24

DB₀–DB₉

10 Parallel Data Inputs.

–7–

REV. 0

AD5330/AD5331/AD5340/AD5341

AD5341 PIN CONFIGURATION

AD5341 FUNCTIONAL BLOCK DIAGRAM

V

DD

REF

1

2

20

19

18

DB

HBEN

BUF

7

BUF

POWER-ON

RESET

AD5341

DB

6

5

GAIN

V

3

REF

DB

7

.

HIGH BYTE

REGISTER

4

17 DB

V

DAC

REGISTER

4

DB

OUT

0

12-BIT

5

16 DB

GND

CS

3

AD5341

INTER-

FACE

LOGIC

HBEN

CS

TOP VIEW

6

15

DB

LOW BYTE

REGISTER

2

12-BIT

DAC

(Not to Scale)

BUFFER

V

OUT

7

14 DB

WR

1

WR

8

13 DB

GAIN

CLR

LDAC

0

RESET

9

12

11

CLR

LDAC

V

DD

POWER-DOWN

LOGIC

10

PD

GND

PD

AD5341 PIN FUNCTION DESCRIPTIONS

No.

Mnemonic

Function

1

HBEN

High Byte Enable Pin. This pin is used when writing to the device to determine if data is written

to the high byte register or the low byte register.

2

3

4

5

6

7

8

9

BUF

V_REF

V_OUT

GND

CS

Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.

Reference Input.

Output of DAC. Buffered output with rail-to-rail operation.

Ground reference point for all circuitry on the part.

Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

Gain Control Pin. This controls whether the output range from the DAC is 0–V_REFor 0–2 V_REF.

Asynchronous active low control input that clears all input registers and DAC registers to zero.

Active low control input that updates the DAC registers with the contents of the input registers.

Power-Down Pin. This active low control pin puts the DAC into power-down mode.

WR

GAIN

CLR

LDAC

PD

10

11

12

V_DD

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

13–20

DB₀–DB₇

Eight Parallel Data Inputs. DB₇is the MSB of these eight bits.

–8–

REV. 0

AD5330/AD5331/AD5340/AD5341

TERMINOLOGY

RELATIVE ACCURACY

For the DAC, Relative Accuracy or Integral Nonlinearity (INL)

is a measure of the maximum deviation, in LSBs, from a straight

line passing through the actual endpoints of the DAC transfer

function. Typical INL versus Code plot can be seen in Figures

5, 6, and 7.

GAIN ERROR

AND

OFFSET ERROR

OUTPUT

VOLTAGE

ACTUAL

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A speciﬁed differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed mono-

tonic by design. Typical DNL versus Code plot can be seen in

Figures 8, 9, and 10.

IDEAL

POSITIVE

OFFSET

DAC CODE

GAIN ERROR

This is a measure of the span error of the DAC (including any

error in the gain of the buffer ampliﬁer). It is the deviation in

slope of the actual DAC transfer characteristic from the ideal

expressed as a percentage of the full-scale range. This is illus-

trated in Figure 2.

Figure 3. Positive Offset Error and Gain Error

GAIN ERROR

AND

OFFSET ERROR

This is a measure of the offset error of the DAC and the output

ampliﬁer. It is expressed as a percentage of the full-scale range.

OUTPUT

VOLTAGE

ACTUAL

IDEAL

If the offset voltage is positive, the output voltage will still be

positive at zero input code. This is shown in Figure 3. Because

the DACs operate from a single supply, a negative offset cannot

appear at the output of the buffer ampliﬁer. Instead, there will

be a code close to zero at which the ampliﬁer output saturates

(ampliﬁer footroom). Below this code there will be a deadband

over which the output voltage will not change. This is illustrated

in Figure 4.

NEGATIVE

OFFSET

DAC CODE

POSITIVE

GAIN ERROR

DEADBAND CODES

AMPLIFIER

FOOTROOM

(~1mV)

NEGATIVE

GAIN

ERROR

OUTPUT

VOLTAGE

ACTUAL

NEGATIVE

OFFSET

IDEAL

Figure 4. Negative Offset Error and Gain Error

DAC CODE

Figure 2. Gain Error

–9–

REV. 0

AD5330/AD5331/AD5340/AD5341

OFFSET ERROR DRIFT

DIGITAL FEEDTHROUGH

This is a measure of the change in Offset Error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Digital Feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital input pins of the

device, but is measured when the DAC is not being written to

(CS held high). It is speciﬁed in nV secs and is measured with a

full-scale change on the digital input pins, i.e., from all 0s to all

1s and vice versa.

GAIN ERROR DRIFT

This is a measure of the change in Gain Error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

POWER-SUPPLY REJECTION RATIO (PSRR)

MULTIPLYING BANDWIDTH

This indicates how the output of the DAC is affected by changes in

the supply voltage. PSRR is the ratio of the change in V_OUTto a

change in V_DDfor full-scale output of the DAC. It is measured

in dBs. V_REFis held at 2 V and V_DDis varied 10%.

The ampliﬁers within the DAC have a ﬁnite bandwidth. The

Multiplying Bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The Multiplying Bandwidth is the frequency at which

the output amplitude falls to 3 dB below the input.

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the DAC output

to the reference input when the DAC output is not being updated

(i.e., LDAC is high). It is expressed in dBs.

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated

version using the DAC. The sine wave is used as the reference

for the DAC and the THD is a measure of the harmonics present

on the DAC output. It is measured in dBs.

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-Code Transition Glitch Energy is the energy of the

impulse injected into the analog output when the DAC changes

state. It is normally speciﬁed as the area of the glitch in nV secs

and is measured when the digital code is changed by 1 LSB at

the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00

to 011 . . . 11).

–10–

REV. 0

Typical Performance Characteristics–

AD5330/AD5331/AD5340/AD5341

12

3

1.0

0.5

T

= 25؇C

A

T

= 25؇C

T

V

= 25؇C

A

V

DD

= 5V

V

= 5V

8

DD

2

1

4

0

–0.5

–1.0

0

–1

–2

–3

–4

–8

–12

0

4000

1000

2000

3000

0

50

100

150

CODE

200

250

200

400

CODE

600

800

1000

0

CODE

Figure 5. AD5330 Typical INL Plot

Figure 6. AD5331 Typical INL Plot

Figure 7. AD5340 Typical INL Plot

0.3

1.0

0.6

T

= 25؇C

T

V

= 25؇C

T

V

= 25؇C

A

V = 5V

= 5V

DD

0.4

0.2

0.5

0

0.1

0

–0.1

–0.2

–0.4

–0.6

–0.5

–1.0

–0.2

–0.3

0

50

100

150

200

250

0

1000

2000

CODE

3000

4000

200

400

600

CODE

800

1000

CODE

Figure 8. AD5330 Typical DNL Plot

Figure 9. AD5331 Typical DNL Plot

Figure 10. AD5340 Typical DNL Plot

1.00

1.0

1.00

V

= 5V

= 3V

V

T

= 5V

= 25؇C

DD

V

= 5V

DD

0.75

0.50

0.25

0

0.75

0.50

REF

A

= 2V

REF

0.5

0.0

MAX DNL MAX INL

GAIN ERROR

0.25

MAX INL

MAX DNL

0.00

MIN DNL

MIN INL

–0.25

–0.50

–0.75

–1.00

–0.25

–0.50

–0.75

MIN INL MIN DNL

OFFSET ERROR

–0.5

–1.0

–1.00

–40

0

40

80

120

2

3

4

5

–40

0

40

80

120

V

– V

TEMPERATURE – ؇C

REF

TEMPERATURE – ؇C

Figure 11. AD5330 INL and DNL

Error vs. V_REF

Figure 12. AD5330 INL Error and

DNL Error vs. Temperature

Figure 13. AD5330 Offset Error

and Gain Error vs. Temperature

–11–

REV. 0

AD5330/AD5331/AD5340/AD5341

300

250

200

150

100

0.2

5

T

= 25؇C

A

ؠ

T

V

= 25 C

A

0.1

V

= 2V

5V SOURCE

3V SOURCE

REF

= 2V

REF

4

V

= 5.5V

= 3.6V

DD

GAIN ERROR

0

–0.1

–0.2

–0.3

–0.4

3

2

1

0

DD

OFFSET ERROR

3V SINK

50

0

5V SINK

–0.5

–0.6

ZERO-SCALE

FULL-SCALE

0

1

2

3

4

5

6

0

1

2

3

4

5

6

DAC CODE

V

– Volts

SINK/SOURCE CURRENT – mA

DD

Figure 16. Supply Current vs. DAC

Code

Figure 15. V_OUTSource and Sink

Current Capability

Figure 14. Offset Error and Gain

Error vs. V_DD

1800

0.5

300

T

= 25؇C

A

T

= 25؇C

T

= 25؇C

A

1600

1400

1200

1000

800

600

400

200

0

A

0.4

0.3

0.2

0.1

0

200

100

0

V

= 5V

DD

V

= 3V

DD

0

1

2

3

4

5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

V – Volts

LOGIC

V

– Volts

V

– Volts

DD

Figure 19. Supply Current vs. Logic

Input Voltage

Figure 18. Power-Down Current vs.

Supply Voltage

Figure 17. Supply Current vs. Supply

Voltage

ؠ

V

T

= 5V

= 25؇C

T

V

= 25 C

= 5V

T

V

= 25 C

= 5V

DD

A

DD

CH2

CH1

CLK

= 2V

REF

CH1

CH2

CH1

CH2

V

DD

V

A

OUT

V

OUT

V

A

PD

OUT

CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV

CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV

CH1 1V, CH2 5V, TIME BASE = 5␮s/DIV

Figure 21. Power-On Reset to 0 V

Figure 22. Exiting Power-Down to

Midscale

Figure 20. Half-Scale Settling (1/4 to

3/4 Scale Code Change)

–12–

REV. 0

AD5330/AD5331/AD5340/AD5341

10

0.917

0.916

0.915

0.914

0.913

0.912

0.911

0.910

0.909

0.908

0.907

0.906

0.905

0.904

0.903

0

–10

–20

–30

V

= 3V

DD

V

= 5V

DD

–40

–50

–60

80 90 100 110 120 130 140 150 160 170 180 190 200

0.01

0.1

1

10

100

1k

10k

250ns/DIV

I

– ␮A

DD

FREQUENCY – kHz

Figure 23. I_DDHistogram with V _DD

3 V and V_DD= 5 V

=

Figure 24. AD5340 Major-Code Tran-

sition Glitch Energy

Figure 25. Multiplying Bandwidth

(Small-Signal Frequency Response)

0.4

V

= 5V

DD

T

= 25؇C

A

0.2

0

–0.2

0

1

2

3

4

5

V

– Volts

REF

Figure 26. Full-Scale Error vs. V_REF

FUNCTIONAL DESCRIPTION

where:

The AD5330/AD5331/AD5340/AD5341 are single resistor-string

DACs fabricated on a CMOS process with resolutions of 8, 10,

12, and 12 bits, respectively. They are written to using a parallel

interface. They operate from single supplies of 2.5 V to 5.5 V and

the output buffer amplifiers offer rail-to-rail output swing. The

AD5330, AD5340, and AD5341 have a reference input that may

be buffered to draw virtually no current from the reference

source. The reference input of the AD5331 is unbuffered. The

devices have a power-down feature that reduces current con-

sumption to only 80 nA @ 3 V.

D = decimal equivalent of the binary code which is loaded to the

DAC register:

0–255 for AD5330 (8 Bits)

0–1023 for AD5331 (10 Bits)

0–4095 for AD5340/AD5341 (12 Bits)

N = DAC resolution

Gain = Output Ampliﬁer Gain (1 or 2)

V

REF

Digital-to-Analog Section

The architecture of one DAC channel consists of a reference

buffer and a resistor-string DAC followed by an output buffer

ampliﬁer. The voltage at the V_REFpin provides the reference

voltage for the DAC. Figure 27 shows a block diagram of the

DAC architecture. Since the input coding to the DAC is straight

binary, the ideal output voltage is given by:

REFERENCE

BUFFER

BUF

GAIN

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

V

OUT

OUTPUT

BUFFER AMPLIFIER

D

2^N

V_OUT= V_REF

×

× Gain

Figure 27. Single DAC Channel Architecture

–13–

REV. 0

AD5330/AD5331/AD5340/AD5341

Resistor String

PARALLEL INTERFACE

The resistor string section is shown in Figure 28. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines at what node on the string the

voltage is tapped off to be fed into the output ampliﬁer. The

voltage is tapped off by closing one of the switches connecting

the string to the ampliﬁer. Because it is a string of resistors, it

is guaranteed monotonic.

The AD5330, AD5331, and AD5340 load their data as a single

8-, 10-, or 12-bit word, while the AD5341 loads data as a low

byte of eight bits and a high byte containing four bits.

Double-Buffered Interface

The AD5330/AD5331/AD5340/AD5341 DACs all have double-

buffered interfaces consisting of an input register and a DAC

register. DAC data, BUF, and GAIN inputs are written to the input

register under control of the Chip Select (CS) and Write (WR).

V

REF

Access to the DAC register is controlled by the LDAC function.

When LDAC is high, the DAC register is latched and the input

register may change state without affecting the contents of the

DAC register. However, when LDAC is brought low, the DAC

register becomes transparent and the contents of the input register

are transferred to it. The gain and buffer control signals are also

double-buffered and are only updated when LDAC is taken low.

R

TO OUTPUT

AMPLIFIER

Double-buffering is also useful where the DAC data is loaded in

two bytes, as in the AD5341, because it allows the whole data

word to be assembled in parallel before updating the DAC register.

This prevents spurious outputs that could occur if the DAC

register were updated with only the high byte or the low byte.

R

These parts contain an extra feature whereby the DAC regis-

ter is not updated unless its input register has been updated

since the last time that LDAC was brought low. Normally,

when LDAC is brought low, the DAC register is filled with the

contents of the input register. In the case of the AD5330/AD5331/

AD5340/AD5341, the part will only update the DAC register if

the input register has been changed since the last time the DAC

register was updated. This removes unnecessary crosstalk.

Figure 28. Resistor String

DAC Reference Input

There is a reference input pin for the DAC. The reference input

is buffered on the AD5330/AD5340/AD5341 but can be config-

ured as unbuffered also. The reference input of the AD5331 is

unbuffered. The buffered/unbuffered option is controlled by the

BUF pin.

Clear Input (CLR)

CLR is an active low, asynchronous clear that resets the input and

DAC registers.

In buffered mode (BUF = 1), the current drawn from an external

reference voltage is virtually zero as the impedance is at least

10 MΩ. The reference input range is 1 V to 5 V with a 5 V supply.

Chip Select Input (CS)

CS is an active low input that selects the device.

In unbuffered mode (BUF = 0), the user can have a reference

voltage as low as 0.25 V and as high as V_DDsince there is no

restriction due to headroom and footroom of the reference ampli-

fier. The impedance is still large at typically 180 kΩ for 0–V_REF

mode and 90 kΩ for 0–2 V_REFmode. If there is an external

buffered reference (e.g., REF192) there is no need to use the

on-chip buffer.

Write Input (WR)

WR is an active low input that controls writing of data to the

device. Data is latched into the input register on the rising edge

of WR.

Load DAC Input (LDAC)

LDAC transfers data from the input register to the DAC register

(and hence updates the outputs). Use of the LDAC function enables

double-buffering of the DAC data, GAIN, and BUF. There

are two LDAC modes:

Output Ampliﬁer

The output buffer ampliﬁer is capable of generating output

voltages to within 1 mV of either rail. Its actual range depends

on V_REF, GAIN, the load on V_OUT, and offset error.

Synchronous Mode: In this mode the DAC register is updated

after new data is read in on the rising edge of the WR input.

LDAC can be tied permanently low or pulsed as in Figure 1.

If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V

to V_REF

.

If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V

to 2 V_REF. However, because of clamping, the maximum output

is limited to V_DD– 0.001 V.

Asynchronous Mode: In this mode the outputs are not updated

at the same time that the input register is written to. When LDAC

goes low, the DAC register is updated with the contents of the

input register.

The output ampliﬁer is capable of driving a load of 2 kΩ to

GND or V_DD, in parallel with 500 pF to GND or V_DD. The

source and sink capabilities of the output ampliﬁer can be seen

in Figure 15.

High-Byte Enable Input (HBEN)

High-Byte Enable is a control input on the AD5341 only that

determines if data is written to the high-byte input register or

the low-byte input register.

The slew rate is 0.7 V/µs with a half-scale settling time to

0.5 LSB (at eight bits) of 6 µs with the output unloaded. See

Figure 20.

–14–

REV. 0

AD5330/AD5331/AD5340/AD5341

The low data byte of the AD5341 consists of data bits 0 to 7 at

data inputs DB₀to DB₇, while the high byte consists of data

bits 8 to 11 at data inputs DB₀to DB₃as shown in Figure 29.

DB₄to DB₇are ignored during a high-byte write, but they may

be used for data to set up the reference input as buffered/

unbuffered, and buffer amplifier gain. See Figure 33.

reduced when the DAC is not in use by putting it into power-

down mode, which is selected by taking pin PD low.

When the PD pin is high, the DAC works normally with a

typical power consumption of 140 µA at 5 V (115 µA at 3 V).

In power-down mode, however, the supply current falls to

200 nA at 5 V (80 nA at 3 V) when the DAC is powered-down.

Not only does the supply current drop, but the output stage is

also internally switched from the output of the amplifier mak-

ing it open-circuit. This has the advantage that the output is

three-state while the part is in power-down mode and pro-

vides a defined input condition for whatever is connected to

the output of the DAC amplifier. The output stage is illus-

trated in Figure 30.

HIGH BYTE

X

DB11 DB10 DB9 DB8

LOW BYTE

DB5 DB4

DB2

DB1 DB0

DB7 DB6

X = UNUSED BIT

DB3

Figure 29. Data Format for AD5341

POWER-ON RESET

The AD5330/AD5331/AD5340/AD5341 are provided with a

power-on reset function, so that they power up in a deﬁned state.

The power-on state is:

RESISTOR

STRING DAC

AMPLIFIER

V

OUT

POWER-DOWN

CIRCUITRY

• Normal Operation

• Reference Input Unbuffered

• 0 – V_REFOutput Range

• Output Voltage Set to 0 V

Figure 30. Output Stage During Power-Down

The bias generator, the output ampliﬁer, the resistor string,

and all other associated linear circuitry are shut down when

the power-down mode is activated. However, the contents

of the registers are unaffected when in power-down. The time

to exit power-down is typically 2.5 µs for V_DD= 5 V and 5 µs

when V_DD= 3 V. This is the time from a rising edge on the

PD pin to when the output voltage deviates from its power-

down voltage. See Figure 22.

Both input and DAC registers are ﬁlled with zeros and remain so

until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

POWER-DOWN MODE

The AD5330/AD5331/AD5340/AD5341 have low power con-

sumption, dissipating only 0.35 mW with a 3 V supply and

0.7 mW with a 5 V supply. Power consumption can be further

Table I. AD5330/AD5331/AD5340 Truth Table

CLR

LDAC

CS

WR

Function

1

0

1

X

1

0

1

X

1

X

0➝1

X

No Data Transfer

Clear All Registers

Load Input Register

Load Input Register and DAC Register

Update DAC Register

X

0

X

X = don’t care.

Table II. AD5341 Truth Table

CLR

LDAC

CS

WR

HBEN

Function

1

0

1

X

1

0

1

X

1

X

0➝1

X

0

1

0

No Data Transfer

Clear All Registers

Load Low-Byte Input Register

Load High-Byte Input Register

Load Low-Byte Input Register and DAC Register

Load High-Byte Input Register and DAC Register

Update DAC Register

X

0

X

1

X

X = don’t care.

–15–

REV. 0

AD5330/AD5331/AD5340/AD5341

SUGGESTED DATABUS FORMATS

APPLICATIONS INFORMATION

In most applications GAIN and BUF are hard-wired. However,

if more flexibility is required, they can be included in a databus.

This enables you to software program GAIN, giving the option

of doubling the resolution in the lower half of the DAC range.

In a bused system, GAIN and BUF may be treated as data inputs

since they are written to the device during a write operation and

take effect when LDAC is taken low. This means that the refer-

ence buffers and the output amplifier gain of multiple DAC

devices can be controlled using common GAIN and BUF lines.

Typical Application Circuits

The AD5330/AD5331/AD5340/AD5341 can be used with a

wide range of reference voltages, especially if the reference inputs

are configured to be unbuffered, in which case the devices offer

full, one-quadrant multiplying capability over a reference range

of 0.25 V to V_DD. More typically, these devices may be used with a

fixed, precision reference voltage. Figure 34 shows a typical

setup for the devices when using an external reference connected to

the unbuffered reference inputs. If the reference inputs are unbuf-

fered, the reference input range is from 0.25 V to V_DD, but if the

on-chip reference buffers are used, the reference range is reduced.

Suitable references for 5 V operation are the AD780 and REF192.

For 2.5 V operation, a suitable external reference would be the

AD589, a 1.23 V bandgap reference.

In the case of the AD5330 this means that the databus must be

wider than eight bits. The AD5331 and AD5340 databuses must

be at least 10 and 12 bits wide respectively and are best suited

to a 16-bit databus system.

Examples of data formats for putting GAIN and BUF on a 16-

bit databus are shown in Figure 31. Note that any unused bits

above the actual DAC data may be used for BUF and GAIN.

DAC devices can be controlled using common GAIN and

BUF lines.

V

= 2.5V TO 5.5V

DD

10␮F

0.1␮F

AD5330

V

IN

X

DB6

DB7

DB5

BUF GAIN

X

DB4 DB3 DB2 DB1 DB0

V

DD

EXT

REF

V

REF

OUT

AD5331

V

OUT

DB9 DB8 DB7 DB6 DB5

DB0

DB4 DB3 DB2 DB1

GND

AD5330/AD5331/

AD5340/AD5341

AD5340

DB10 DB9 DB8 DB7 DB6 DB5 DB3 DB2 DB1

DB4

BUF GAIN

X

DB11

AD780/REF192

WITH V = 5V

DD

X = UNUSED BIT

GND

OR

Figure 31. GAIN and BUF Data on a 16-Bit Bus

AD589 WITH V = 2.5V

DD

The AD5341 is a 12-bit device that uses byte load, so only four

bits of the high byte are actually used as data. Two of the unused

bits can be used for GAIN and BUF data by connecting them

to the GAIN and BUF inputs; e.g., Bits 6 and 7, as shown in

Figures 32 and 33.

Figure34. AD5330/AD5331/AD5340/AD5341Using

External Reference

Driving V_DDFrom the Reference Voltage

If an output range of zero to V_DDis required, the simplest solu-

tion is to connect the reference inputs to V_DD. As this supply may

not be very accurate, and may be noisy, the devices may be

powered from the reference voltage, for example using a 5 V

reference such as the ADM663 or ADM666, as shown in

Figure 35.

8-BIT

DATA BUS

DATA

INPUTS

DB DB

6

7

BUF

AD5341

GAIN

LDAC

CLR

CS

6V TO 16V

WR

10␮F

0.1␮F

HBEN

V

IN

Figure 32. AD5341 Data Format for Byte Load with GAIN

and BUF Data on 8-Bit Bus

ADM663/ADM666

SENSE

V

DD

In this case, the low byte is written first in a write operation

with HBEN = 0. Bits 6 and 7 of DAC data will be written into

GAIN and BUF registers but will have no effect. The high byte

is then written. Only the lower four bits of data are written into the

DAC high byte register, so Bits 6 and 7 can be GAIN and BUF

data.

V

OUT(2)

REF

V

OUT

VSET

SHDN

GND

0.1␮F

AD5330/AD5331/

AD5340/AD5341

GND

LDAC is used to update the DAC, GAIN and BUF values.

HIGH BYTE

Figure 35. Using an ADM663/ADM666 as Power and Refer-

encetoAD5330/AD5331/AD5340/AD5341

BUF GAIN

X

DB11 DB10 DB9 DB8

LOW BYTE

DB5 DB4

DB2

DB7 DB6

DB3

DB1 DB0

X = UNUSED BIT

Figure 33. AD5341 with GAIN and BUF Data on 8-Bit Bus

–16–

REV. 0

AD5330/AD5331/AD5340/AD5341

Bipolar Operation Using the AD5330/AD5331/AD5340/AD5341

The AD5330/AD5331/AD5340/AD5341 have been designed

for single supply operation, but bipolar operation is achievable

using the circuit shown in Figure 36. The circuit shown has been

conﬁgured to achieve an output voltage range of –5 V < V_O<

+5 V. Rail-to-rail operation at the ampliﬁer output is achievable

using an AD820 or OP295 as the output ampliﬁer.

The 74HC139 is used as a 2- to 4-line decoder to address any

of the DACs in the system. To prevent timing errors, the enable

input should be brought to its inactive state while the coded

address inputs are changing state. Figure 37 shows a diagram of a

typical setup for decoding multiple devices in a system. Once

data has been written sequentially to all DACs in a system, all the

DACs can be updated simultaneously using a common LDAC

line. A common CLR line can also be used to reset all DAC

outputs to zero.

The output voltage for any input code can be calculated as

follows:

V_O= [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V_REF× D/2^N)] – R4 × V_REF/R3

AD5330/AD5331/

AD5340/AD5341

where:

D is the decimal equivalent of the code loaded to the DAC, N is

DAC resolution and V_REFis the reference voltage input.

HBEN*

WR

LDAC

CLR

CS

HBEN

WR

LDAC

CLR

DATA

INPUTS

With:

V_REF= 2.5 V

R1 = R3 = 10 kΩ

AD5330/AD5331/

AD5340/AD5341

R2 = R4 = 20 kΩ and V_DD= 5 V.

V

_OUT= (10 × D/2^N) – 5

HBEN*

WR

DATA

INPUTS

LDAC

CLR

CS

V

= 5V

V

DD

R4

20k⍀

V

CC

1G

1A

1B

10␮F

0.1␮F

ENABLE

1Y0

1Y1

1Y2

+5V

AD5330/AD5331/

AD5340/AD5341

R3

10k⍀

CODED

ADDRESS

74HC139

DGND

HBEN*

V

؎5V

IN

WR

DATA

INPUTS

V

DD

EXT

V

LDAC

CLR

CS

V

1Y3

REF

OUT

–5V

0.1␮F

AD5330/AD5331/

AD5340/AD5341

GND

R1

10k⍀

V

OUT

AD5330/AD5331/

AD5340/AD5341

AD780/REF192

WITH V = 5V

R2

20k⍀

DD

OR

HBEN*

WR

GND

AD589 WITH V = 2.5V

DD

DATA

INPUTS

LDAC

CLR

CS

Figure 36. Bipolar Operation using the AD5330/AD5331/

AD5340/AD5341

*AD5341 ONLY

Figure 37. Decoding Multiple DAC Devices

Decoding Multiple AD5330/AD5331/AD5340/AD5341

The CS pin on these devices can be used in applications to decode

a number of DACs. In this application, all DACs in the system

receive the same data and WR pulses, but only the CS to one of

the DACs will be active at any one time, so data will only be

written to the DAC whose CS is low. If multiple AD5341s are

being used, a common HBEN line will also be required to

determine if the data is written to the high-byte or low-byte

register of the selected DAC.

–17–

REV. 0

AD5330/AD5331/AD5340/AD5341

Programmable Current Source

Power Supply Bypassing and Grounding

Figure 38 shows the AD5330/AD5331/AD5340/AD5341 used

as the control element of a programmable current source. In this

example, the full-scale current is set to 1 mA. The output volt-

age from the DAC is applied across the current setting resistor

of 4.7 kΩ in series with the 470 Ω adjustment potentiometer,

which gives an adjustment of about 5%. Suitable transistors to

place in the feedback loop of the amplifier include the BC107

and the 2N3904, which enable the current source to operate

from a minimum V_SOURCEof 6 V. The operating range is deter-

mined by the operating characteristics of the transistor. Suitable

amplifiers include the AD820 and the OP295, both having rail-

to-rail operation on their outputs. The current for any digital

input code and resistor value can be calculated as follows:

In any circuit where accuracy is important, careful consideration

of the power supply and ground return layout helps to ensure

the rated performance. The printed circuit board on which the

AD5330/AD5331/AD5340/AD5341 is mounted should be

designed so that the analog and digital sections are separated,

and conﬁned to certain areas of the board. If the device is in a

system where multiple devices require an AGND-to-DGND

connection, the connection should be made at one point only.

The star ground point should be established as closely as pos-

sible to the device. The AD5330/AD5331/AD5340/AD5341

should have ample supply bypassing of 10 µF in parallel with

0.1 µF on the supply located as close to the package as pos-

sible, ideally right up against the device. The 10 µF capacitors

are the tantalum bead type. The 0.1 µF capacitor should have

low Effective Series Resistance (ESR) and Effective Series Induc-

tance (ESI), like the common ceramic types that provide a low

impedance path to ground at high frequencies to handle tran-

sient currents due to internal logic switching.

D

I = G × V_REF

×

mA

(2^N× R)

Where:

G is the gain of the buffer ampliﬁer (1 or 2)

The power supply lines of the device should use as large a trace

as possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals such

as clocks should be shielded with digital ground to avoid radiat-

ing noise to other parts of the board, and should never be run

near the reference inputs. Avoid crossover of digital and ana-

log signals. Traces on opposite sides of the board should run

at right angles to each other. This reduces the effects of feed-

through through the board. A microstrip technique is by far

the best, but not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground plane while signal traces are placed on the solder side.

D is the digital equivalent of the digital input code

N is the DAC resolution (8, 10, or 12 bits)

R is the sum of the resistor plus adjustment potentiometer in kΩ

V

= 5V

DD

10␮F

0.1␮F

V

SOURCE

V

IN

LOAD

5V

V

DD

EXT

REF

V

REF

OUT

AD820/

OP295

AD5330/AD5331/

AD5340/AD5341

GND

AD780/REF192

WITH V = 5V

4.7k⍀

470⍀

DD

GND

Figure 38. Programmable Current Source

–18–

REV. 0

AD5330/AD5331/AD5340/AD5341

Table III. Overview of AD53xx Parallel Devices

Part No.

Resolution DNL

V_REFPins

Settling Time

Additional Pin Functions

Package

Pins

SINGLES

AD5330

AD5331

AD5340

AD5341

BUF

ꢀ

GAIN

HBEN

CLR

ꢀ

8

0.25

0.5

1.0

1

6 µs

7 µs

8 µs

ꢀ

TSSOP

20

24

20

10

12

ꢀ

DUALS

AD5332

AD5333

AD5342

AD5343

8

0.25

0.5

1.0

2

1

6 µs

7 µs

8 µs

ꢀ

TSSOP

20

24

28

20

10

12

ꢀ

QUADS

AD5334

AD5335

AD5336

AD5344

8

0.25

0.5

1.0

2

4

6 µs

7 µs

8 µs

ꢀ

TSSOP

24

28

10

12

Table IV. Overview of AD53xx Serial Devices

Part No.

Resolution

No. of DACs

DNL

Interface

Settling Time

Package

Pins

SINGLES

AD5300

AD5310

AD5320

8

10

12

1

0.25

0.5

1.0

SPI

4 µs

6 µs

8 µs

SOT-23, MicroSOIC

6, 8

AD5301

AD5311

AD5321

8

10

12

1

0.25

0.5

1.0

2-Wire

6 µs

7 µs

8 µs

SOT-23, MicroSOIC

6, 8

DUALS

AD5302

AD5312

AD5322

8

10

12

2

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

MicroSOIC

8

AD5303

AD5313

AD5323

8

10

12

2

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

TSSOP

16

QUADS

AD5304

AD5314

AD5324

8

10

12

4

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

MicroSOIC

10

AD5305

AD5315

AD5325

8

10

12

4

0.25

0.5

1.0

2-Wire

6 µs

7 µs

8 µs

MicroSOIC

10

AD5306

AD5316

AD5326

8

10

12

4

0.25

0.5

1.0

2-Wire

6 µs

7 µs

8 µs

TSSOP

16

AD5307

AD5317

AD5327

8

10

12

4

0.25

0.5

1.0

SPI

6 µs

7 µs

8 µs

TSSOP

16

Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html

–19–

REV. 0

AD5330/AD5331/AD5340/AD5341

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

20-Lead Thin Shrink Small Outline Package TSSOP

(RU-20)

0.260 (6.60)

0.252 (6.40)

20

11

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

0.246 (6.25)

1

10

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0433 (1.10)

MAX

8؇

0؇

0.0256 (0.65)

BSC

0.0118 (0.30)

0.0075 (0.19)

0.028 (0.70)

0.020 (0.50)

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

24-Lead Thin Shrink Small Outline Package TSSOP

(RU-24)

0.311 (7.90)

0.303 (7.70)

24

13

0.177 (4.50)

0.169 (4.30)

0.256 (6.50)

0.246 (6.25)

1

12

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0433 (1.10)

MAX

8؇

0؇

0.0256 (0.65) 0.0118 (0.30)

0.028 (0.70)

0.020 (0.50)

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

BSC

0.0075 (0.19)

–20–

REV. 0


型号：	AD5341BRU
厂家：	ADI
描述：	2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs 2.5 V至5.5 V ， 115微安，并行接口单电压输出8位/ 10位/ 12位DAC
文件：	总20页 (文件大小：352K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD5341BRU [ADI]

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